LED chip structure and preparation method thereof

Abstract

The invention relates to the technical field of LED chips, in particular to an LED chip structure and a preparation method thereof. The invention provides an LED chip structure and a preparation method thereof, and the structure comprises a substrate, and a nucleating layer, a buffer layer and an n-type GaN layer which are located on the substrate and are stacked in sequence. The isolation layer is positioned on the n-type GaN layer; the nano-column array penetrates through the isolation layer, the nano-column array comprises a plurality of nano-column units which are arranged in an array, and each nano-column unit comprises a plurality of nano-columns with different diameters. According to the invention, the nanorod array is formed on the LED chip, and the nanorod array comprises a plurality of nanorods with different diameters, so that the emission of light with different wavelengths can be realized, and therefore, the high-pixel and high-luminous-efficiency panchromatic display of the LED chip can be realized; and the full-color display is integrated on the LED chip, so that a huge transfer and bonding technology used for manufacturing the traditional LED display is avoided, the yield of the LED chip is greatly improved, and the manufacturing cost is remarkably reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of LED chips, and in particular to an LED chip structure and a preparation method thereof. Background Art

[0002] The size of Micro-LED (micro light-emitting diode) chips is usually less than 50 microns. It has the advantages of low power consumption, high contrast, high responsiveness, long life and high reliability. It is known as the "new generation of display technology" and has received widespread attention from academia and industry at home and abroad.

[0003] The key to realizing the mass commercialization of Micro-LED chips lies in the epitaxial growth of high-quality materials, high-precision and high-yield chip mass transfer, and full-color technology based on the three primary colors of red, green and blue. One of the most critical challenges restricting the application of full-color Micro-LED display is the mass transfer technology, that is, how to transfer and integrate the full-color Micro-LED chips of the three primary colors of red, green and blue into the drive circuit substrate in batches. Existing transfer technologies such as roller transfer and self-assembly transfer still have certain shortcomings in achieving batch and high-precision selective transfer. Therefore, it is urgent to develop a method for preparing full-color Micro-LED chips with large batches, controllable processes and low costs.

[0004] Since Micro-LED full-color display usually requires red, green and blue primary color Micro-LED chips with high yield and high luminous efficiency, blue light III-nitride Micro-LED is generally used for actual production and preparation. As the emission wavelength gradually shifts to green and red light, the wavelength uniformity and spectrum broadening caused by quantum well components and structural fluctuations ultimately lead to reduced luminous efficiency and deterioration of photoelectric performance of green and red Micro-LEDs, which hinders the application of III-nitride Micro-LED full-color display. Therefore, how to achieve high-light-efficiency full-color Micro-LED is one of the problems that technicians in this field need to solve. Summary of the invention

[0005] The present disclosure provides an LED chip structure and a preparation method thereof, so as to at least solve the above technical problems existing in the prior art.

[0006] According to a first aspect of the present disclosure, there is provided an LED chip structure, wherein the structure comprises: A substrate, and a nucleation layer, a buffer layer and an n-type GaN layer stacked in sequence on the substrate; an isolation layer located on the n-type GaN layer; A nanocolumn array penetrating the isolation layer, wherein the nanocolumn array comprises a plurality of nanocolumn units arranged in an array, and each of the nanocolumn units comprises a plurality of nanocolumns with different diameters.

[0007] In one possible implementation, in each of the nanocolumn units, a plurality of nanocolumns with different diameters are arranged in order of diameter size along a first direction, wherein the first direction is a direction parallel to the substrate plane; or, In each of the nanocolumn units, a plurality of nanocolumns with different diameters are arranged in a polygonal shape.

[0008] In one possible implementation manner, a plurality of the nano-column units are arranged in an array along a row direction and a column direction, wherein the nano-column units in adjacent rows and adjacent columns are respectively aligned with each other.

[0009] In one possible implementation, a plurality of the nanocolumn units are arranged in an array along row and column directions, wherein the nanocolumn units in adjacent rows and adjacent columns are arranged alternately, and the nanocolumn units in alternate rows and alternate columns are aligned with each other.

[0010] In one embodiment, the material of the isolation layer includes at least one of silicon dioxide or aluminum oxide.

[0011] In one embodiment, the diameter of the nanocolumns is in the range of 0.05-50 μm, and the distance between two adjacent nanocolumns is in the range of 0.1-10 μm.

[0012] In one possible implementation, the height of the nanocolumn is equal to or lower than the height of the isolation layer, wherein the difference between the height of the nanocolumn and the height of the isolation layer is less than or equal to 30 nm.

[0013] In one embodiment, the shape of the projection of the nanorod along a direction perpendicular to the substrate plane includes any one of a circle, a triangle, a quadrilateral and a pentagon.

[0014] In one possible implementation, the nanocolumn includes a stress buffer layer, an active region light-emitting layer, an electron blocking layer, and a p-type GaN layer stacked in sequence.

[0015] In one possible implementation, the structure further includes: a transparent conductive layer located on the isolation layer; a first electrode located on the transparent conductive layer and a second electrode located on the n-type GaN layer; a passivation layer covering the transparent conductive layer, the n-type GaN layer, the first electrode and the second electrode; a distributed Bragg reflector layer on the passivation layer; A first pad and a second pad are located on the distributed Bragg reflector layer, wherein the first pad is connected to the first electrode, and the second pad is connected to the second electrode.

[0016] According to a second aspect of the present disclosure, a method for preparing an LED chip structure is provided, wherein the method comprises: providing a substrate; forming a nucleation layer, a buffer layer and an n-type GaN layer stacked in sequence on the substrate; forming an isolation layer on the n-type GaN layer; forming a plurality of through holes penetrating the isolation layer; A nanocolumn is formed in each of the through holes, and a plurality of the nanocolumns form a nanocolumn array, wherein the nanocolumn array includes a plurality of nanocolumn units arranged in an array, and each of the nanocolumn units includes a plurality of nanocolumns with different diameters.

[0017] In one possible implementation manner, the forming of a plurality of through holes penetrating the isolation layer; and the forming of a nanocolumn in each of the through holes include: forming a photoresist layer on the isolation layer; Photolithography the photoresist layer using a photolithography process to form a plurality of through-hole positions in the photoresist layer, wherein the through-holes include a plurality of different diameters; Etching and removing the isolation layer not covered by the photoresist layer through the through hole position, and stopping the etching at the upper surface of the n-type GaN layer to form the through hole; A nano-column is formed in each of the through holes.

[0018] In one possible implementation manner, the forming of a plurality of through holes penetrating the isolation layer; and the forming of a nanocolumn in each of the through holes include: forming a first photoresist layer on the isolation layer; Photolithography the first photoresist layer using a photolithography process to form a plurality of first through hole locations in the first photoresist layer, wherein the first through holes have a first diameter; Etching and removing the isolation layer not covered by the first photoresist layer through the first through hole position, and stopping the etching at the upper surface of the n-type GaN layer to form the first through hole; forming a nanorod having a first diameter in each of the first through holes; removing the first photoresist layer; forming a second photoresist layer on the isolation layer; Photolithography the second photoresist layer using a photolithography process to form a plurality of second through hole locations in the second photoresist layer, wherein the second through holes have a second diameter; Etching and removing the isolation layer not covered by the second photoresist layer through the second through hole position, and stopping the etching at the upper surface of the n-type GaN layer to form the second through hole; forming a nanorod having a second diameter in each of the second through holes; And so on, until the preparation of all nanocolumns is completed.

[0019] In one embodiment, forming a nanocolumn in each of the through holes includes: A stress buffer layer, an active area light-emitting layer, an electron blocking layer and a p-type GaN layer stacked in sequence are formed in the through hole.

[0020] In one possible implementation, in each of the nanocolumn units, a plurality of nanocolumns with different diameters are arranged in order of diameter size along a first direction, wherein the first direction is a direction parallel to the substrate plane; or, In each of the nanocolumn units, a plurality of nanocolumns with different diameters are arranged in a polygonal shape.

[0021] In one possible implementation manner, a plurality of the nano-column units are arranged in an array along a row direction and a column direction, wherein the nano-column units in adjacent rows and adjacent columns are respectively aligned with each other.

[0022] In one possible implementation, a plurality of the nanocolumn units are arranged in an array along row and column directions, wherein the nanocolumn units in adjacent rows and adjacent columns are arranged alternately, and the nanocolumn units in alternate rows and alternate columns are aligned with each other.

[0023] In one embodiment, the diameter of the nanocolumns is in the range of 0.05-50 μm, and the distance between two adjacent nanocolumns is in the range of 0.1-10 μm.

[0024] In one possible implementation, the height of the nanocolumn is equal to or lower than the height of the isolation layer, wherein the difference between the height of the nanocolumn and the height of the isolation layer is less than or equal to 30 nm.

[0025] In one embodiment, the shape of the projection of the nanorod along a direction perpendicular to the substrate plane includes any one of a circle, a triangle, a quadrilateral and a pentagon.

[0026] In one embodiment, the method further comprises: forming a transparent conductive layer on the isolation layer; forming a first electrode on the transparent conductive layer, and forming a second electrode on the n-type GaN layer; forming a passivation layer covering the transparent conductive layer, the n-type GaN layer, the first electrode and the second electrode; forming a distributed Bragg reflector layer on the passivation layer; forming a first window and a second window through the distributed Bragg reflector layer and the passivation layer, wherein the first window exposes the first electrode and the second window exposes the second electrode; forming a first pad on the first window, wherein the first pad is connected to the first electrode; A second pad is formed on the second window, and the second pad is connected to the second electrode.

[0027] The LED chip structure and preparation method disclosed herein form a nanocolumn array on the LED chip. Since the nanocolumn array includes nanocolumns of various different diameters, nanocolumns of different diameters can emit light of different wavelengths, thereby enabling high-pixel, high-light-efficiency full-color display of the LED chip. Furthermore, since the full-color display is integrated on the LED chip, the massive transfer and bonding technology used in traditional LED display manufacturing is avoided, thereby greatly improving the LED chip yield and significantly reducing the manufacturing cost.

[0028] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, in which: In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0030] Figure 1 A schematic diagram of the structure of an LED chip provided by the present disclosure; Figure 2 A perspective view of a nanopillar array provided for the present disclosure; Figure 3 A schematic diagram of the structure of a nanocolumn provided in an embodiment of the present disclosure; Figures 4 to 6 are different arrangements of nanorod arrays, where Figure 4 This is the arrangement mode 1 of the nanorod array; Figure 5 This is the second arrangement of the nanorod array; Figure 6 The third arrangement mode of the nanopillar array; Figure 7A flow chart of a method for preparing an LED chip structure provided in an embodiment of the present disclosure; Figures 8 to 15 This is a schematic diagram of the LED chip structure provided in the embodiment of the present disclosure during the preparation process, wherein: Figure 8 The LED chip structure in the embodiment of the present disclosure is schematically shown in the manufacturing process. Figure 1 ; Fig. 9 The LED chip structure in the embodiment of the present disclosure is schematically shown in the manufacturing process. Figure 2 ; Fig.10 The LED chip structure in the embodiment of the present disclosure is schematically shown in the manufacturing process. Figure 3 ; Fig.11 The LED chip structure in the embodiment of the present disclosure is schematically shown in the manufacturing process. Figure 4 ; Fig.12 The LED chip structure in the embodiment of the present disclosure is schematically shown in the manufacturing process. Figure 5 ; Fig.13 The LED chip structure in the embodiment of the present disclosure is schematically shown in the manufacturing process. Figure 6 ; Fig.14 The LED chip structure in the embodiment of the present disclosure is schematically shown in the manufacturing process. Figure 7 ; Fig.15 The LED chip structure in the embodiment of the present disclosure is schematically shown in the manufacturing process. Figure 8 ; Figures 16 to 21 Another embodiment of the present disclosure provides a method for preparing a nanocolumn, wherein: Fig.16 Schematic diagram of the preparation process of a nanocolumn in another embodiment of the present disclosure Figure 1 ; Fig.17 Schematic diagram of the preparation process of a nanocolumn in another embodiment of the present disclosure Figure 2 ; Fig.18 Schematic diagram of the preparation process of a nanocolumn in another embodiment of the present disclosure Figure 3 ; Fig.19 Schematic diagram of the preparation process of a nanocolumn in another embodiment of the present disclosure Figure 4 ; Fig. 20 Schematic diagram of the preparation process of a nanocolumn in another embodiment of the present disclosure Figure 5 ; Fig.21Schematic diagram of the preparation process of a nanocolumn in another embodiment of the present disclosure Figure 6 .

[0031] Reference numerals: 11. substrate; 12. nucleation layer; 13. buffer layer; 14. n-type GaN layer; 20, isolation layer; 200, through hole; 201, first through hole; 202, second through hole; 203, third through hole; 30. Nanocolumn array; 31. Nanocolumn unit; 311. Nanocolumn; 3111. Stress buffer layer; 3112. Active region light emitting layer; 3113. Electron blocking layer; 3114. P-type GaN layer; 40. Transparent conductive layer; 51. a first electrode; 52. a second electrode; 60. Passivation layer; 70. Distributed Bragg reflector layer; 81. First solder pad; 82. Second solder pad. DETAILED DESCRIPTION

[0032] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0033] Traditional full-color display requires the batch transfer and integration of red, green and blue Micro-LEDs onto the drive circuit substrate, and the precise and rapid interconnection of different Micro-LED chips corresponding to different colors with the drive backplane through bonding technology. As the size of Micro-LED chips shrinks, the number of Micro-LED chips in the same display area grows exponentially, which puts higher requirements on the transfer accuracy, transfer efficiency, bonding yield and reliability of the manufacturing process. There is still much room for improvement in the existing mass transfer and bonding technologies.

[0034] Based on this, the present disclosure provides an LED chip structure. Figure 1 This is a schematic diagram of the structure of the LED chip provided by the present disclosure. Figure 2 A three-dimensional image of a nanopillar array provided by the present disclosure, such as Figure 1 and Figure 2 As shown, the structure includes: A substrate 11, and a nucleation layer 12, a buffer layer 13 and an n-type GaN layer 14 stacked in sequence on the substrate 11; An isolation layer 20 located on the n-type GaN layer 14; The nano-column array 30 penetrates the isolation layer 20 , wherein the nano-column array 30 includes a plurality of nano-column units 31 arranged in an array, and each of the nano-column units 31 includes a plurality of nano-columns 311 with different diameters.

[0035] In one embodiment, the substrate 11 may be a single semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (e.g., a germanium silicon substrate, etc.), or a silicon on insulator substrate (SOI), a germanium on insulator (GOI) substrate, or a sapphire substrate, etc. In a preferred embodiment, the substrate 11 may be a sapphire substrate or a silicon substrate, etc.

[0036] In one embodiment, the nucleation layer 12 includes at least one of an AlN layer or a GaN layer.

[0037] When the nucleation layer 12 is an AlN layer, the thickness of the AlN layer is 5 to 15 nm; when the nucleation layer 12 is a GaN layer, the thickness of the GaN layer is 5 to 15 nm; when the nucleation layer 12 is a mixed nucleation layer of the AlN layer and the GaN layer, the thickness of the AlN layer is 5 to 10 nm, and the thickness of the GaN layer is 5 to 10 nm.

[0038] The nucleation layer 12 can alleviate the lattice mismatch and thermal mismatch between the substrate and the epitaxial layer, promote the transformation of the epitaxial material growth from a three-dimensional mode to a two-dimensional mode, obtain high-quality epitaxial materials, and improve the crystal quality of the epitaxial materials of the Micro-LED chip.

[0039] In one embodiment, the buffer layer 13 may be a GaN buffer layer, and the thickness of the GaN buffer layer is 1.5-3 μm.

[0040] In one embodiment, the n-type GaN layer 14 is an n-type doped GaN layer, and the thickness of the n-type doped GaN layer is 1-2 μm.

[0041] In one embodiment, the material of the isolation layer 20 includes at least one of silicon dioxide and aluminum oxide. The isolation layer 20 can provide insulation isolation for adjacent nano-pillars to prevent crosstalk between adjacent nano-pillars.

[0042] The role of these materials in the LED chip structure is to provide effective isolation and protection, improve the performance and reliability of the chip. By selecting the appropriate isolation layer material, the electrical performance and thermal stability of the LED chip can be improved.

[0043] When selecting the isolation layer material, one or a combination of two materials, silicon dioxide or aluminum oxide, can be chosen according to specific application requirements. Silicon dioxide has good electrical insulation performance and thermal stability, and is suitable for applications in high-temperature environments. Aluminum oxide, on the other hand, has excellent mechanical strength and corrosion resistance, and is suitable for applications that require high strength and durability. In addition, the performance of the isolation layer can be optimized by adjusting the ratio of silicon dioxide and aluminum oxide to meet the requirements of different application scenarios.

[0044] As Figure 2 shown, the nanocolumn array 30 in the present disclosure includes a plurality of nanocolumn units 31 arranged in an array, and each of the nanocolumn units 31 includes a plurality of nanocolumns 311 with different diameters.

[0045] In the embodiment of the present disclosure, as Figure 2 shown, the nanocolumn unit 31 includes three kinds of nanocolumns 311 with different diameters. It can be understood that the nanocolumn unit can also include more than three kinds of nanocolumns with different diameters, which can be specifically set according to actual needs.

[0046] Figure 3 is a schematic structural diagram of the nanocolumn provided in the embodiment of the present disclosure.

[0047] As Figure 3 shown, the nanocolumn 311 includes a stress buffer layer 3111, an active region light-emitting layer 3112, an electron blocking layer 3113, and a p-type GaN layer 3114 stacked in sequence.

[0048] The stress buffer layer 3111 can be an n-type doped In x Ga 1-x N layer (0 < x < 0.05) or an In x Ga 1-x N / GaN (0 < x < 0.05) superlattice layer, where the thickness of the n-type doped In x Ga 1-x N layer is 10 - 20 nm, and the number of periods of the In x Ga 1-x N / GaN superlattice layer is 1 - 7.

[0049] The stress buffer layer 3111 can relieve the lattice mismatch between different epitaxial layers, further improve the crystal quality of the epitaxial material, and obtain a high-performance and high-light-efficiency Micro-LED chip.

[0050] The active region light-emitting layer 3112 is the key part for the Micro-LED chip to emit light, responsible for generating light, and is composed of periodically arranged In x Ga 1-x N quantum well layers and GaN quantum barrier layers, and the In x Ga 1-xThe thickness of the N quantum well layer is 1.5~3.5nm, the thickness of the GaN quantum barrier layer is 9~15nm, and the thickness of the In x Ga 1-x The period number of N quantum wells and GaN quantum barriers is 3~7.

[0051] The electron blocking layer 3113 is used to prevent electron leakage and improve the luminous efficiency. The electron blocking layer 3113 is made of Al x Ga 1-x N, with a thickness of about 15~30nm.

[0052] The p-type GaN layer 3114 is a P-type doped GaN layer, which is the upper layer of the nanocolumn layer and provides charge carriers. The thickness of the p-type GaN layer 3114 is about 20-50 nm.

[0053] By stacking these layers in sequence, the nanopillars can achieve efficient light emission and maintain structural stability.

[0054] In one embodiment, the height of the nanocolumn 311 composed of the stress buffer layer 3111, the active region light emitting layer 3112, the electron blocking layer 3113 and the p-type GaN layer 3114 is equal to or lower than the height of the isolation layer 20, wherein the difference between the height of the nanocolumn 311 and the height of the isolation layer 20 is less than or equal to 30 nm. The height of the nanocolumn is equal to or lower than the height of the isolation layer, so that the nanocolumn is supported and fixed by the isolation layer around it, and the stability is improved, which is conducive to enhancing the stability of the process and the performance of the device.

[0055] In one embodiment, the ratios of indium atoms in the nanorods 311 of different diameters are different.

[0056] Specifically, the proportion of indium atomic components in the active region light-emitting layer 3112 can be adjusted according to the diameter of the nanocolumn, so as to design different proportions of indium atomic components for nanocolumns of different diameters. The emission wavelength of the Micro-LED chip is related to the nanocolumn array. By reducing the diameter of the nanocolumn, the stress of epitaxial growth can be reduced, which is conducive to incorporating more indium atomic components into the epitaxial layer, thereby obtaining a longer emission wavelength, so that nanocolumns with different emission wavelengths can be integrated in the nanocolumn array.

[0057] Figures 4 to 6 Different arrangements of nanorod arrays.

[0058] In one embodiment, in each of the nanocolumn units 31, a plurality of nanocolumns 311 with different diameters are arranged in order of diameter size along a first direction, wherein the first direction is a direction parallel to the plane of the substrate 11; or, In each of the nano-column units 31 , a plurality of nano-columns 311 with different diameters are arranged in a polygonal shape.

[0059] Specifically, Figure 4 As shown, three nanorods 311 of different diameters are arranged along the first direction in the order from small to large diameters. It is understandable that they can also be arranged along the first direction in the order from large to small diameters.

[0060] like Figure 5 and Figure 6 As shown, three nanopillars 311 with different diameters are arranged in a triangle. It is understood that the nanopillar unit may include nanopillars with more than three different diameters. For example, when the nanopillar unit includes nanopillars with four different diameters, they may be arranged in a quadrilateral.

[0061] In the present disclosure, the performance of the LED chip structure is improved by optimizing the arrangement of the nanocolumn array. By arranging in order of diameter size or in a polygonal shape, the uniform distribution and reasonable spacing of the nanocolumns in the LED chip structure can be ensured, thereby reducing light scattering and reflection losses, thereby improving photoelectric performance and luminous efficiency.

[0062] In one embodiment, the plurality of nano-column units 31 are arranged in an array along the row direction and the column direction, wherein the nano-column units 31 in adjacent rows and adjacent columns are aligned with each other.

[0063] Specifically, Figure 4 and Figure 5 As shown, the nano-column units 31 in two adjacent rows are aligned with each other, and the nano-column units 31 in two adjacent columns are aligned with each other.

[0064] In one embodiment, the plurality of nanocolumn units 31 are arranged in an array along the row direction and the column direction, wherein the nanocolumn units 31 in adjacent rows and adjacent columns are arranged alternately, and the nanocolumn units 31 in alternate rows and alternate columns are aligned with each other.

[0065] Specifically, Figure 6 As shown, the nanocolumn units 31 in two adjacent rows are arranged in a staggered manner, and the nanocolumn units 31 in the alternate row are aligned with each other; the nanocolumn units 31 in two adjacent columns are arranged in a staggered manner, and the nanocolumn units 31 in the alternate column are aligned with each other.

[0066] This staggered arrangement can not only increase the arrangement density of the nanocolumn units, but also reduce the mutual interference between the nanocolumns, and improve the luminous efficiency and uniformity of the LED chip. In this way, the arrangement problem of the nanocolumn units in the row and column directions can be effectively solved, ensuring the efficiency and stability of the LED chip in practical applications.

[0067] Understandably, Figures 4 to 6 Only several possible arrangements are shown; the nanorod array may also have other arrangements.

[0068] In one embodiment, the diameter of the nanorods 311 ranges from 0.05 to 50 μm, and the distance between two adjacent nanorods 311 ranges from 0.1 to 10 μm.

[0069] In a specific embodiment, for example, the nanocolumn unit 31 includes three nanocolumns 311 of different diameters, wherein the diameter of the nanocolumn 311 with the smallest diameter is, for example, 0.05-10 μm, the diameter of the nanocolumn 311 with the medium diameter is, for example, 10-30 μm, and the diameter of the nanocolumn with the largest diameter is, for example, 30-50 μm.

[0070] As the diameter of the nanopillars continues to decrease, the stress in the heteroepitaxial growth process can be effectively released. On the one hand, it is conducive to reducing the density of structural defects such as dislocations, which is conducive to obtaining high-quality III-nitride Micro-LEDs. On the other hand, the reduction of stress is conducive to the incorporation of more indium atoms into the epitaxial layer, ultimately achieving longer wavelength emission and covering a wider band of light. In addition, reducing stress helps to reduce the influence of the in-plane polarization electric field, which can confine electrons and holes to the center of the quantum well, reduce the spatial separation of wave functions, and improve the probability of radiative recombination and luminous efficiency.

[0071] In the present disclosure, nanocolumns 311 of different diameters emit light of different wavelengths. The smaller the diameter, the longer the wavelength of the emitted light. Therefore, red light can be emitted by the nanocolumn 311 with the smallest diameter, green light can be emitted by the nanocolumn 311 with a medium diameter, and blue light can be emitted by the nanocolumn 311 with the largest diameter.

[0072] Because the nanocolumn array contains nanocolumns of various different diameters, nanocolumns of different diameters can emit light of different wavelengths. Therefore, red, green and blue primary color Micro-LED chips can be integrated on a single epitaxial wafer, thereby achieving high-pixel, high-light-efficiency full-color display. And because the full-color display is integrated on the LED chip, the massive transfer and bonding technology used in traditional LED display manufacturing is avoided, which greatly improves the LED chip yield and significantly reduces manufacturing costs.

[0073] By selecting nanocolumns of specific diameters in specific areas of the chip, it is possible to emit light of a specific wavelength in the selected area. The area of ​​the selected area is related to the area occupied by nanocolumns of the corresponding diameter.

[0074] In one embodiment, the shape of the projection of the nanorod 311 along a direction perpendicular to the plane of the substrate 11 includes any one of a circle, a triangle, a quadrilateral and a pentagon.

[0075] like Figures 4 to 6As shown, the projection shape of the nanorod 311 is a circle. In some other embodiments, the projection shape of the nanorod may also be any one of a triangle, a quadrilateral and a pentagon. It is understood that the projection shape of the nanorod is not limited to this, and may also be other shape structures.

[0076] In one embodiment, if Figure 1 As shown, the structure further includes: a transparent conductive layer 40 located on the isolation layer 20; A first electrode 51 located on the transparent conductive layer 40 and a second electrode 52 located on the n-type GaN layer 14; a passivation layer 60 covering the transparent conductive layer 40, the n-type GaN layer 14, the first electrode 51 and the second electrode 52; a distributed Bragg reflector layer 70 located on the passivation layer 60; A first pad 81 and a second pad 82 are located on the distributed Bragg reflector layer 70 , wherein the first pad 81 passes through the distributed Bragg reflector layer 70 and the passivation layer 60 to be connected to the first electrode 51 , and the second pad 82 passes through the distributed Bragg reflector layer 70 and the passivation layer 60 to be connected to the second electrode 52 .

[0077] The material of the transparent conductive layer 40 includes but is not limited to indium tin oxide (ITO). A low-resistance ohmic contact is formed between the transparent conductive layer 40 and the P-type GaN layer 3114 .

[0078] like Figure 1 As shown, the isolation layer 20 does not completely cover the n-type GaN layer 14 , but exposes a portion of the n-type GaN layer 14 , so that the second electrode 52 can be formed on the n-type GaN layer 14 .

[0079] The first electrode 51 includes not only a portion located on the transparent conductive layer 40 , but also a portion passing through a distributed Bragg reflector (DBR) 70 and a passivation layer 60 ; the second electrode includes not only a portion located on the n-type GaN layer, but also a portion passing through a distributed Bragg reflector (DBR) 70 and a passivation layer 60 .

[0080] The first electrode 51 and the second electrode 52 have different conductivity types. For example, the first electrode 51 is a p-electrode, and the second electrode 52 is an n-electrode.

[0081] The material of the first electrode 51 and the second electrode 52 may include at least one of Cr, Au, Ti, Ag, and Pt.

[0082] In the present disclosure, the Micro-LEDs based on the nanorod array 30 share a first electrode, which simplifies the electrode preparation process and reduces the manufacturing cost.

[0083] The passivation layer 60 may be made of Al 2 O 3 、SiO 2 、SiN x The dielectric layer.

[0084] The distributed Bragg reflector layer 70 is an optical distributed Bragg reflector layer.

[0085] The distributed Bragg reflector layer 70 may be made of SiO 2 and Ti 2 O 5 It can also be composed of SiO 2 、Ti 2 O 5 and Al 2 O 3 composition.

[0086] The first pad 81 and the second pad 82 have different conductivity types, corresponding to the conductivity types of the first electrode 51 and the second electrode 52. For example, when the first electrode 51 is a p-electrode, the first pad 81 is a p-pad, and when the second electrode 52 is an n-electrode, the second pad 82 is an n-pad.

[0087] The present invention forms a nanocolumn array on an LED chip. Since the nanocolumn array includes nanocolumns of various different diameters, nanocolumns of different diameters can emit light of different wavelengths. Therefore, it is possible to achieve a high-pixel, high-light-efficiency full-color display of the LED chip. Furthermore, since the full-color display is integrated on the LED chip, the massive transfer and bonding technology used in traditional LED display manufacturing is avoided, thereby greatly improving the LED chip yield and significantly reducing the manufacturing cost.

[0088] The disclosed embodiment also provides a method for preparing an LED chip structure. Figure 7 A flow chart of a method for preparing an LED chip structure provided in an embodiment of the present disclosure, such as Figure 7 As shown, the method includes: Step 701: providing a substrate; Step 702: forming a nucleation layer, a buffer layer and an n-type GaN layer stacked in sequence on the substrate; Step 703: forming an isolation layer on the n-type GaN layer; Step 704: forming a plurality of through holes penetrating the isolation layer; Step 705: forming a nanocolumn in each of the through holes, wherein a plurality of the nanocolumns form a nanocolumn array, wherein the nanocolumn array includes a plurality of nanocolumn units arranged in an array, and each of the nanocolumn units includes a plurality of nanocolumns with different diameters.

[0089] The preparation method of the LED chip structure provided by the embodiment of the present disclosure is further described in detail below in conjunction with specific embodiments. Figures 8 to 15 A schematic diagram of the LED chip structure during the preparation process provided in an embodiment of the present disclosure.

[0090] First, see Figure 8 , execute step 701 and provide a substrate 11.

[0091] In one embodiment, the substrate 11 may be a single semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (e.g., a germanium silicon substrate, etc.), or a silicon on insulator substrate (SOI), a germanium on insulator (GOI) substrate, or a sapphire substrate, etc. In a preferred embodiment, the substrate 11 may be a sapphire substrate or a silicon substrate, etc.

[0092] Next, continue to see Figure 8 , executing step 702 , forming a nucleation layer 12 , a buffer layer 13 and an n-type GaN layer 14 stacked in sequence on the substrate 11 .

[0093] The nucleation layer 12 , the buffer layer 13 and the n-type GaN layer 14 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods.

[0094] In a preferred embodiment, the nucleation layer 12 , the buffer layer 13 and the n-type GaN layer 14 may be deposited by metal-organic chemical vapor deposition (MOCVD) technology.

[0095] The nucleation layer 12 includes at least one of an AlN layer or a GaN layer.

[0096] Specifically, when the nucleation layer 12 is an AlN layer, the AlN layer is a sputtered AlN layer. The AlN layer can be sputtered on the substrate 11 with a thickness of 5 to 15 nm using a magnetron sputtering device with a high-purity aluminum target as an aluminum source for magnetron sputtering.

[0097] When the nucleation layer 12 is a GaN layer, the GaN layer is a low-temperature GaN layer, and the GaN layer is grown on the substrate 11 by a metal organic chemical vapor deposition (MOCVD) device to have a thickness of 5 to 15 nm.

[0098] When the nucleation layer 12 is a mixed nucleation layer of an AlN layer and a GaN layer, the mixed nucleation layer is composed of a sputtered AlN layer and a low-temperature GaN layer, wherein the sputtered AlN layer has a thickness of 5-10 nm and the low-temperature GaN layer has a growth thickness of 5-10 nm.

[0099] The nucleation layer 12 can alleviate the lattice mismatch and thermal mismatch between the substrate and the epitaxial layer, promote the transformation of the epitaxial material growth from a three-dimensional mode to a two-dimensional mode, obtain high-quality epitaxial materials, and improve the crystal quality of the epitaxial materials of the Micro-LED chip.

[0100] In one embodiment, the buffer layer 13 may be a GaN buffer layer, and the thickness of the GaN buffer layer is 1.5-3 μm.

[0101] In one embodiment, the n-type GaN layer 14 is an n-type doped GaN layer, and the thickness of the n-type doped GaN layer is 1-2 μm.

[0102] Next, see Fig. 9 , execute step 703 to form an isolation layer 20 on the n-type GaN layer 14.

[0103] The isolation layer 20 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods. In a preferred embodiment, the isolation layer 20 may be formed on the n-type GaN layer 14 by using plasma enhanced chemical vapor deposition (PECVD).

[0104] After the isolation layer 20 is deposited, the surface of the entire epitaxial wafer is modified to convert the hydrophilicity of the surface of the isolation layer 20 into hydrophobicity, so that the subsequently formed photoresist can adhere better to the isolation layer 20 .

[0105] In one embodiment, the material of the isolation layer 20 includes at least one of silicon dioxide and aluminum oxide. The isolation layer 20 can provide insulation isolation for the subsequently formed nano-pillars to prevent crosstalk between adjacent nano-pillars.

[0106] Next, see Fig.10 and Fig.11 , executing step 704 to form a plurality of through holes 200 penetrating the isolation layer 20, and executing step 705 to form a nanocolumn 311 in each of the through holes 200, wherein the plurality of nanocolumns 311 form a nanocolumn array 30, wherein the nanocolumn array 30 includes a plurality of nanocolumn units 31 arranged in an array, and each of the nanocolumn units 31 includes a plurality of nanocolumns 311 with different diameters.

[0107] Here, there are two implementation methods for forming the nanorods 311 in the isolation layer 20. One implementation method is as follows: Fig.10 and Fig.11 As shown, another Figures 16 to 21 Next, Fig.10 and Fig.11 The illustrated embodiment will be described in detail.

[0108] like Fig.10 and Fig.11 As shown, the forming of a plurality of through holes 200 penetrating the isolation layer 20; forming a nanocolumn 311 in each of the through holes 200, comprises: forming a photoresist layer (not shown in the figure) on the isolation layer 20; Photolithography the photoresist layer using a photolithography process to form a plurality of through-hole positions in the photoresist layer, wherein the through-holes include a plurality of different diameters; Through the through hole position, the isolation layer 20 not covered by the photoresist layer is removed by etching, and the etching stops at the upper surface of the n-type GaN layer 14 to form the through hole 200; A nano-rod 311 is formed in each of the through holes 200 .

[0109] In actual operation, a layer of photoresist is evenly spin-coated on the surface of the epitaxial wafer with the isolation layer 20 deposited, and then placed on a hot plate for pre-baking to evaporate the water inside the photoresist and complete the shaping. After the photoresist is evenly coated, it is exposed to ultraviolet light and developed. After the development is completed, the epitaxial wafer is cleaned with deionized water, and after the film is hardened, it is cleaned with a plasma stripper. The above epitaxial wafer is placed in an inductively coupled plasma (ICP) etcher, and successively passes through SF 6 and Cl 2 / BCl 3 The gas performs dry etching on the epitaxial wafer to completely etch the isolation layer 20 without photoresist protection until the upper surface of the n-type GaN layer 14 is exposed, thereby forming through holes 200 with various diameters.

[0110] The remaining photoresist layer is removed, and the surface moisture is dried in a spin dryer, thereby fabricating the nanorods 311 in the through holes 200 .

[0111] Next, Figures 16 to 21 The illustrated embodiment will be described in detail.

[0112] like Figures 16 to 21 As shown, the forming of a plurality of through holes penetrating the isolation layer 20; forming a nanocolumn 311 in each of the through holes, comprises: forming a first photoresist layer (not shown in the figure) on the isolation layer 20; Photolithography the first photoresist layer using a photolithography process to form a plurality of first through hole locations in the first photoresist layer, wherein the first through holes have a first diameter; Through the first through hole position, the isolation layer 20 not covered by the first photoresist layer is removed by etching, and the etching stops at the upper surface of the n-type GaN layer 14 to form the first through hole 201; forming a nanorod 311 having a first diameter in each of the first through holes 201; removing the first photoresist layer; forming a second photoresist layer (not shown in the figure) on the isolation layer 20; Photolithography the second photoresist layer using a photolithography process to form a plurality of second through hole locations in the second photoresist layer, wherein the second through holes have a second diameter; Through the second through hole position, the isolation layer 20 not covered by the second photoresist layer is removed by etching, and the etching stops at the upper surface of the n-type GaN layer 14 to form the second through hole 202; forming a nanorod 311 having a second diameter in each of the second through holes 202; And so on, until the preparation of all nanorods 311 is completed.

[0113] In actual operation, taking the formation of nanocolumns with three diameters as an example, masks with three diameters are designed to prepare nanocolumns with three diameters.

[0114] First, a mask having a first diameter is used to form a first through hole. Specifically, first, see Fig.16 , a first photoresist layer (not shown in the figure) is evenly spin-coated on the surface of the epitaxial wafer with the deposited isolation layer 20, and placed on a hot plate for pre-baking to evaporate the water inside the first photoresist layer and complete the shaping. After the photoresist is evenly coated, it is exposed to ultraviolet light and developed. After the development is completed, the epitaxial wafer is cleaned with deionized water, and after the film is hardened, it is cleaned with a plasma stripper. The above epitaxial wafer is placed in an inductively coupled plasma etcher, and successively passes through SF 6 and Cl 2 / BCl 3The gas performs dry etching on the epitaxial wafer to completely etch the isolation layer 20 that is not protected by the first photoresist layer until the upper surface of the n-type GaN layer 14 is exposed, thereby forming a first through hole 201 with a first diameter.

[0115] Next, see Fig.17 , removing the remaining first photoresist layer, and drying the surface moisture in a spin dryer, thereby preparing the nanorods 311 with the first diameter in the first through holes 201 .

[0116] Next, a second through hole is formed using a mask having a second diameter. Specifically, first refer to Fig.18 , a second photoresist layer (not shown in the figure) is evenly spin-coated on the surface of the epitaxial wafer with the deposited isolation layer 20, and placed on a hot plate for pre-baking to evaporate the water inside the second photoresist layer and complete the shaping. After the coating is evenly coated, ultraviolet exposure and development are performed. After the development is completed, the epitaxial wafer is cleaned with deionized water, and after the film is hardened, it is cleaned with a plasma stripper. The above epitaxial wafer is placed in an inductively coupled plasma etcher, and successively passes through SF 6 and Cl 2 / BCl 3 The gas performs dry etching on the epitaxial wafer to completely etch the isolation layer 20 that is not protected by the second photoresist layer until the upper surface of the n-type GaN layer 14 is exposed, thereby forming a second through hole 202 with a second diameter.

[0117] Next, see Fig.19 , removing the remaining second photoresist layer, and drying the surface moisture in a spin dryer, thereby fabricating the nanorods 311 having the second diameter in the second through holes 202 .

[0118] Next, a third through hole is formed using a mask having a third diameter. Specifically, first refer to Fig. 20 , a third photoresist layer (not shown in the figure) is evenly spin-coated on the surface of the epitaxial wafer with the deposited isolation layer 20, and placed on a hot plate for pre-baking to evaporate the water inside the third photoresist layer and complete the shaping. After the coating is evenly coated, ultraviolet exposure and development are performed. After the development is completed, the epitaxial wafer is cleaned with deionized water, and after the film is hardened, it is cleaned with a plasma stripper. The above epitaxial wafer is placed in an inductively coupled plasma etcher, and successively passes through SF 6 and Cl 2 / BCl 3 The gas performs dry etching on the epitaxial wafer to completely etch the isolation layer 20 that is not protected by the third photoresist layer, until the upper surface of the n-type GaN layer 14 is exposed, thereby forming a third through hole 203 with a third diameter.

[0119] Next, see Fig.21, removing the remaining third photoresist layer, and drying the surface moisture in a spin dryer, thereby preparing the nanorods 311 with the third diameter in the third through holes 203 .

[0120] Since the full-color display effect based on Micro-LED is mainly affected by pixel density, the higher the pixel density per unit area, the better the display effect and the clearer the image. However, as the density increases, the size of the Micro-LED chip becomes smaller, and the perimeter-area ratio of the device increases accordingly, thereby causing the small size effect. In the process of preparing nanocolumns in the prior art, a stacked structure containing nanocolumn materials is first formed, and then the stacked structure is dry-etched using plasma to form an isolation layer. The traditional preparation method causes the smaller the size, the more serious the sidewall damage, and the greater the impact on the optoelectronic performance of the device, which ultimately leads to a significant decrease in the luminous efficiency of the Micro-LED chip under low current density injection conditions, seriously affecting the full-color display brightness, resolution and color uniformity.

[0121] In the present disclosure, an isolation layer is formed first, and then the isolation layer is etched to form a through hole, and then a nanocolumn is formed in the through hole. This avoids the sidewall damage caused by the process of defining each Micro-LED by etching the epitaxial wafer in the traditional Micro-LED preparation process, and avoids the negative impact of defects caused by the sidewall damage on the luminous efficiency and service life of the Micro-LED.

[0122] In the embodiment of the present disclosure, the nanocolumn unit 31 includes three nanocolumns 311 with different diameters. It is understandable that the nanocolumn unit may also include more than three nanocolumns with different diameters, which may be specifically configured according to actual needs.

[0123] In one embodiment, if Figure 3 As shown, the nanorod 311 is formed in each of the through holes 200, including: A stress buffer layer 3111 , an active region light emitting layer 3112 , an electron blocking layer 3113 and a p-type GaN layer 3114 stacked in sequence are formed in the through hole 200 .

[0124] The stress buffer layer 3111 , the active region light emitting layer 3112 , the electron blocking layer 3113 and the p-type GaN layer 3114 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods.

[0125] In a preferred embodiment, a metal organic chemical vapor deposition (MOCVD) process can be used to form a stress buffer layer 3111, an active region light-emitting layer 3112, an electron blocking layer 3113, and a p-type GaN layer 3114.

[0126] The stress buffer layer 3111 can be an n-type doped In x Ga 1-x N layer (0 < x < 0.05) or an In x Ga 1-x N / GaN (0 < x < 0.05) superlattice layer, where the thickness of the n-type doped In x Ga 1-x N layer is 10 - 20 nm, and the number of periods of the In x Ga 1-x N / GaN superlattice layer is 1 - 7.

[0127] The stress buffer layer 3111 can relieve the lattice mismatch between different epitaxial layers, further improve the crystal quality of the epitaxial material, and obtain a high-performance and high-light-efficiency Micro-LED chip.

[0128] The active region light-emitting layer 3112 is the key part for the Micro-LED chip to emit light, and is composed of periodically arranged In x Ga 1-x N quantum well layers and GaN quantum barrier layers. The thickness of the In x Ga 1-x N quantum well layer is 1.5 - 3.5 nm, the thickness of the GaN quantum barrier layer is 9 - 15 nm, and the number of periods of the In x Ga 1-x N quantum well and the GaN quantum barrier is 3 - 7.

[0129] The electron blocking layer 3113 is composed of Al x Ga 1-x N, and its thickness is about 15 - 30 nm.

[0130] The p-type GaN layer 3114 is a P-type doped GaN layer, and the thickness of the p-type GaN layer 3114 is about 20 - 50 nm.

[0131] In Figures 16 to 21 the illustrated embodiment, since the nanocolumns with different diameters are formed separately, the proportion of indium atom components in the active region light-emitting layer 3112 can be adjusted according to the diameter of the nanocolumns and synergistically, so as to design different proportions of indium atom components for nanocolumns with different diameters. The emission wavelength of the Micro-LED chip is related to the nanocolumn array. By reducing the diameter of the nanocolumns, the stress of epitaxial growth can be reduced, which is beneficial to incorporating more indium atom components in the epitaxial layer, obtaining a longer emission wavelength, and thus enabling nanocolumns with different emission wavelengths to be integrated in the nanocolumn array.

[0132] In one embodiment, the smaller the diameter of the nanorod, the higher the proportion of the indium atomic component. However, the proportion of the indium atomic component can also be adjusted according to the requirements of the wavelength of specific light and the diameter of the nanorod.

[0133] The light-emitting wavelength of the Micro-LED chip disclosed in the present invention can be continuously controlled in the entire visible light range only by adjusting the nanocolumns accordingly, such as the shape, diameter, period or thickness of the quantum well, the proportion of indium atomic components, etc. of the nanocolumns. The quantum well epitaxial growth conditions of Micro-LED chips of different wavelengths are completely consistent, and there is no need to change the growth temperature, gas flow rate and other conditions, which simplifies the setting of growth condition parameters during the epitaxial growth process. The Micro-LED based on the nanocolumn array can achieve long-wavelength emission and integration of different wavelengths only by changing the nanocolumn structure, avoiding the problem of material deterioration and Micro-LED chip performance degradation caused by lowering the epitaxial growth temperature.

[0134] In one embodiment, the height of the nanocolumn 311 composed of the stress buffer layer 3111, the active region light emitting layer 3112, the electron blocking layer 3113 and the p-type GaN layer 3114 is equal to or lower than the height of the isolation layer 20, wherein the difference between the height of the nanocolumn 311 and the height of the isolation layer 20 is less than or equal to 30 nm. The height of the nanocolumn is equal to or lower than the height of the isolation layer, so that the nanocolumn is supported and fixed by the isolation layer around it, and the stability is improved, which is conducive to enhancing the stability of the process and the performance of the device.

[0135] In one embodiment, in each of the nanocolumn units 31, a plurality of nanocolumns 311 with different diameters are arranged in order of diameter size along a first direction, wherein the first direction is a direction parallel to the plane of the substrate 11; or, In each of the nano-column units 31 , a plurality of nano-columns 311 with different diameters are arranged in a polygonal shape.

[0136] Specifically, Figure 4 As shown, three nanorods 311 of different diameters are arranged along the first direction in the order from small to large diameters. It is understandable that they can also be arranged along the first direction in the order from large to small diameters.

[0137] like Figure 5 and Figure 6 As shown, three nanopillars 311 of different diameters are arranged in a triangle. It is understood that the nanopillar unit may include more than three nanopillars of different diameters, for example, when the nanopillar unit includes four nanopillars of different diameters, it may be arranged in a quadrilateral, and when the nanopillar unit includes five nanopillars of different diameters, it may be arranged in a pentagon.

[0138] In one embodiment, the plurality of nano-column units 31 are arranged in an array along the row direction and the column direction, wherein the nano-column units 31 in adjacent rows and adjacent columns are aligned with each other.

[0139] Specifically, Figure 4 and Figure 5 As shown, the nano-column units 31 in two adjacent rows are aligned with each other, and the nano-column units 31 in two adjacent columns are aligned with each other.

[0140] In one embodiment, the plurality of nanocolumn units 31 are arranged in an array along the row direction and the column direction, wherein the nanocolumn units 31 in adjacent rows and adjacent columns are arranged alternately, and the nanocolumn units 31 in alternate rows and alternate columns are aligned with each other.

[0141] Specifically, Figure 6 As shown, the nanocolumn units 31 in two adjacent rows are arranged in a staggered manner, and the nanocolumn units 31 in the alternate row are aligned with each other; the nanocolumn units 31 in two adjacent columns are arranged in a staggered manner, and the nanocolumn units 31 in the alternate column are aligned with each other.

[0142] Understandably, Figures 4 to 6 Only several possible arrangements are shown; the nanorod array may also have other arrangements.

[0143] In one embodiment, the diameter of the nanorods 311 ranges from 0.05 to 50 μm, and the distance between two adjacent nanorods 311 ranges from 0.1 to 10 μm.

[0144] In a specific embodiment, for example, when the nanocolumn unit 31 includes three nanocolumns 311 of different diameters, the diameter of the nanocolumn 311 with the smallest diameter is, for example, 0.05-10 μm, the diameter of the nanocolumn 311 with the medium diameter is, for example, 10-30 μm, and the diameter of the nanocolumn with the largest diameter is, for example, 30-50 μm. When the nanocolumn unit 31 includes four nanocolumns 311 of different diameters, the diameter of each nanocolumn can be, for example, 0.05-5 μm, 5-20 μm, 20-35 μm, and 35-50 μm, respectively, from small to large diameters.

[0145] As the diameter of the nanopillars continues to decrease, the stress in the heteroepitaxial growth process can be effectively released. On the one hand, it is conducive to reducing the density of structural defects such as dislocations, which is conducive to obtaining high-quality III-nitride Micro-LEDs. On the other hand, the reduction of stress is conducive to the incorporation of more indium atoms into the epitaxial layer, ultimately achieving longer wavelength emission and covering a wider band of light. In addition, reducing stress helps to reduce the influence of the in-plane polarization electric field, which can confine electrons and holes to the center of the quantum well, reduce the spatial separation of wave functions, and improve the probability of radiative recombination and luminous efficiency.

[0146] In the present disclosure, nanocolumns 311 of different diameters emit light of different wavelengths. The smaller the diameter, the longer the wavelength of the emitted light. Therefore, red light can be emitted by the nanocolumn 311 with the smallest diameter, green light can be emitted by the nanocolumn 311 with a medium diameter, and blue light can be emitted by the nanocolumn 311 with the largest diameter.

[0147] Because the nanocolumn array contains nanocolumns of various different diameters, nanocolumns of different diameters can emit light of different wavelengths. Therefore, red, green and blue primary color Micro-LED chips can be integrated on a single epitaxial wafer, thereby achieving high-pixel, high-light-efficiency full-color display. And because the full-color display is integrated on the LED chip, the massive transfer and bonding technology used in traditional LED display manufacturing is avoided, which greatly improves the LED chip yield and significantly reduces manufacturing costs.

[0148] By selecting nanocolumns of specific diameters in specific areas of the chip, it is possible to emit light of a specific wavelength in the selected area. The area of ​​the selected area is related to the area occupied by nanocolumns of the corresponding diameter.

[0149] In one embodiment, the shape of the projection of the nanorod 311 along a direction perpendicular to the plane of the substrate 11 includes any one of a circle, a triangle, a quadrilateral and a pentagon.

[0150] like Figures 4 to 6 As shown, the projection shape of the nanorod 311 is a circle. In some other embodiments, the projection shape of the nanorod may also be any one of a triangle, a quadrilateral and a pentagon. It is understood that the projection shape of the nanorod is not limited to this, and may also be other shape structures.

[0151] Next, see Figures 12 to 15 , the method further comprises: forming a transparent conductive layer 40 on the isolation layer 20; forming a first electrode 51 on the transparent conductive layer 40 and forming a second electrode 52 on the n-type GaN layer 14; forming a passivation layer 60 covering the transparent conductive layer 40, the n-type GaN layer 14, the first electrode 51 and the second electrode 52; forming a distributed Bragg reflector layer 70 on the passivation layer 60; forming a first window (not shown in the figure) and a second window (not shown in the figure) passing through the distributed Bragg reflector layer 70 and the passivation layer 60, wherein the first window exposes the first electrode 51, and the second window exposes the second electrode 52; forming a first pad 81 on the first window, wherein the first pad 81 is connected to the first electrode 51; A second pad 82 is formed on the second window, and the second pad 82 is connected to the second electrode 52 .

[0152] In actual operation, see Fig.12 , a transparent conductive layer 40 is evaporated on the isolation layer 20 and the p-type GaN layer 3114, and annealed in a nitrogen atmosphere to form a low-resistance ohmic contact between the transparent conductive layer 40 and the p-type GaN layer 3114, The material of the transparent conductive layer 40 includes, but is not limited to, indium tin oxide (ITO).

[0153] Next, see Fig.13 , a portion of the transparent conductive layer 40 and the isolation layer 20 are removed by etching using an inductively coupled plasma (ICP) process to expose the n-type GaN layer 14 , thereby forming a mesa structure.

[0154] Specifically, a layer of photoresist can be evenly spin-coated on the surface of the epitaxial wafer on which the transparent conductive layer 40 is deposited, and then placed on a hot plate for pre-baking to evaporate the water inside the photoresist and complete the shaping. After the photoresist is evenly coated, it is exposed to ultraviolet light and developed. After the development is completed, the epitaxial wafer is cleaned with deionized water, and after the film is hardened, it is cleaned with a plasma stripper. The above epitaxial wafer is placed in an inductively coupled plasma (ICP) etcher, and successively passes through SF 6 and Cl 2 / BCl 3 The gas performs dry etching on the epitaxial wafer to completely etch the transparent conductive layer 40 without photoresist protection until the upper surface of the n-type GaN layer 14 is exposed, thereby forming a mesa structure.

[0155] Continue to see Fig.13 , metal electrodes are sputtered on the transparent conductive layer 40 and the n-type GaN layer 14 using electron beam evaporation technology to form the first electrode 51 and the second electrode 52 respectively.

[0156] The first electrode 51 and the second electrode 52 have different conductivity types. For example, the first electrode 51 is a p-electrode, and the second electrode 52 is an n-electrode.

[0157] The material of the first electrode 51 and the second electrode 52 may include at least one of Cr, Au, Ti, Ag, and Pt.

[0158] In the present disclosure, the Micro-LEDs based on the nanorod array 30 share a first electrode, which simplifies the electrode preparation process and reduces the manufacturing cost.

[0159] Next, see Fig.14 , forming a passivation layer 60 covering the transparent conductive layer 40 , the n-type GaN layer 14 , the first electrode 51 and the second electrode 52 .

[0160] The passivation layer 60 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods.

[0161] In a preferred embodiment, the passivation layer 60 is formed by deposition using a plasma enhanced chemical vapor deposition (PECVD) process, and the passivation layer 60 covers the entire epitaxial layer.

[0162] The passivation layer 60 may be made of Al 2 O 3 、SiO 2 、SiN x The dielectric layer.

[0163] Next, continue to see Fig.14 , and further deposited to form a distributed Bragg reflector layer 70 .

[0164] The distributed Bragg reflector layer 70 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other deposition methods.

[0165] In a preferred embodiment, the distributed Bragg reflector layer 70 is deposited by a plasma enhanced chemical vapor deposition (PECVD) process.

[0166] The distributed Bragg reflector (DBR) 70 is an optical distributed Bragg reflector. The distributed Bragg reflector 70 may be made of SiO 2 and Ti 2 O 5 It can also be composed of SiO 2 、Ti 2 O 5 and Al 2 O 3 composition.

[0167] Next, see Fig.15A first window (not shown in the figure) and a second window (not shown in the figure) are formed through the distributed Bragg reflector layer 70 and the passivation layer 60 by dry etching, wherein the first window exposes the first electrode 51 and the second window exposes the second electrode 52; a metal electrode is then deposited in the first window, which can serve as a part of the first electrode 51, and a metal electrode is also deposited in the second window, which can serve as a part of the second electrode 52; a first pad 81 and a second pad 82 are then formed on the distributed Bragg reflector layer 70, wherein the first pad 81 is connected to the first electrode 51 and the second pad 82 is connected to the second electrode 52.

[0168] The first pad 81 and the second pad 82 have different conductivity types, corresponding to the conductivity types of the first electrode 51 and the second electrode 52. For example, when the first electrode 51 is a p-electrode, the first pad 81 is a p-pad, and when the second electrode 52 is an n-electrode, the second pad 82 is an n-pad.

[0169] In the present disclosure, a nanocolumn array for achieving emission of different wavelengths is integrated into the chip structure. By changing the nanocolumns in the array, the stress caused by lattice mismatch during the epitaxial growth of the III-nitride material can be regulated. On the one hand, it can improve the crystal quality of the epitaxial material and reduce the defect density in the material, thereby obtaining a high-brightness, high-efficiency, and high-performance Micro-LED chip. On the other hand, the emission wavelength of the Micro-LED chip is closely related to the nanocolumns in the array. Reducing the diameter of the nanocolumns is conducive to stress release, so that more indium atoms can be incorporated into the quantum well layer, ultimately achieving long-wavelength emission.

[0170] It is understandable that the present disclosure forms a Micro-LED chip of the InGaN material system, but the LED chip structure and preparation method provided in the embodiments of the present disclosure can also be applied to the AlInGaP material system, except that the epitaxial material and the material of the stacked structure used are different.

[0171] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0172] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0173] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An LED chip structure, characterized in that: The structure comprises: A substrate, and a nucleation layer, a buffer layer and an n-type GaN layer stacked in sequence on the substrate; an isolation layer located on the n-type GaN layer; A nanocolumn array penetrating the isolation layer, wherein the nanocolumn array comprises a plurality of nanocolumn units arranged in an array, and each of the nanocolumn units comprises a plurality of nanocolumns with different diameters.

2. The LED chip structure according to claim 1, characterized in that: In each of the nanocolumn units, a plurality of nanocolumns with different diameters are arranged in order of diameter size along a first direction, wherein the first direction is a direction parallel to the substrate plane; or In each of the nanocolumn units, a plurality of nanocolumns with different diameters are arranged in a polygonal shape.

3. The LED chip structure according to claim 1 or 2, characterized in that: The plurality of nanocolumn units are arranged in an array along the row direction and the column direction, wherein the nanocolumn units in adjacent rows and adjacent columns are aligned with each other.

4. The LED chip structure according to claim 1 or 2, characterized in that: The plurality of nanocolumn units are arranged in an array along the row direction and the column direction, wherein the nanocolumn units in adjacent rows and adjacent columns are arranged alternately, and the nanocolumn units in alternate rows and alternate columns are aligned with each other.

5. The LED chip structure according to claim 1, characterized in that: The material of the isolation layer includes at least one of silicon dioxide and aluminum oxide.

6. The LED chip structure according to claim 1, characterized in that: The diameter of the nanocolumns ranges from 0.05 to 50 μm, and the distance between two adjacent nanocolumns ranges from 0.1 to 10 μm.

7. The LED chip structure according to claim 1, characterized in that: The height of the nanocolumn is equal to or lower than the height of the isolation layer, wherein the difference between the height of the nanocolumn and the height of the isolation layer is less than or equal to 30 nm.

8. The LED chip structure according to claim 1, characterized in that: The shape of the projection of the nanorod along a direction perpendicular to the substrate plane includes any one of a circle, a triangle, a quadrilateral and a pentagon.

9. The LED chip structure according to claim 1, characterized in that: The nanocolumn comprises a stress buffer layer, an active region light-emitting layer, an electron blocking layer and a p-type GaN layer which are stacked in sequence.

10. The LED chip structure according to claim 1, characterized in that: The structure also includes: a transparent conductive layer located on the isolation layer; a first electrode located on the transparent conductive layer and a second electrode located on the n-type GaN layer; a passivation layer covering the transparent conductive layer, the n-type GaN layer, the first electrode and the second electrode; a distributed Bragg reflector layer on the passivation layer; A first pad and a second pad are located on the distributed Bragg reflector layer, wherein the first pad is connected to the first electrode, and the second pad is connected to the second electrode.

11. A method for preparing an LED chip structure, characterized in that: The method comprises: providing a substrate; forming a nucleation layer, a buffer layer and an n-type GaN layer stacked in sequence on the substrate; forming an isolation layer on the n-type GaN layer; forming a plurality of through holes penetrating the isolation layer; A nanocolumn is formed in each of the through holes, and a plurality of the nanocolumns form a nanocolumn array, wherein the nanocolumn array includes a plurality of nanocolumn units arranged in an array, and each of the nanocolumn units includes a plurality of nanocolumns with different diameters.

12. The method according to claim 11, characterized in that The step of forming a plurality of through holes penetrating the isolation layer and forming a nanocolumn in each of the through holes comprises: forming a photoresist layer on the isolation layer; Photolithography the photoresist layer using a photolithography process to form a plurality of through-hole positions in the photoresist layer, wherein the through-holes include a plurality of different diameters; Etching and removing the isolation layer not covered by the photoresist layer through the through hole position, and stopping the etching at the upper surface of the n-type GaN layer to form the through hole; A nano-column is formed in each of the through holes.

13. The method according to claim 11, characterized in that The step of forming a plurality of through holes penetrating the isolation layer and forming a nanocolumn in each of the through holes comprises: forming a first photoresist layer on the isolation layer; Photolithography the first photoresist layer using a photolithography process to form a plurality of first through hole locations in the first photoresist layer, wherein the first through holes have a first diameter; Etching and removing the isolation layer not covered by the first photoresist layer through the first through hole position, and stopping the etching at the upper surface of the n-type GaN layer to form the first through hole; forming a nanorod having a first diameter in each of the first through holes; removing the first photoresist layer; forming a second photoresist layer on the isolation layer; Photolithography the second photoresist layer using a photolithography process to form a plurality of second through hole locations in the second photoresist layer, wherein the second through holes have a second diameter; Etching and removing the isolation layer not covered by the second photoresist layer through the second through hole position, and stopping the etching at the upper surface of the n-type GaN layer to form the second through hole; forming a nanorod having a second diameter in each of the second through holes; And so on, until the preparation of all nanocolumns is completed.

14. The method according to any one of claims 11 to 13, characterized in that The forming of a nanocolumn in each of the through holes comprises: A stress buffer layer, an active area light-emitting layer, an electron blocking layer and a p-type GaN layer stacked in sequence are formed in the through hole.

15. The method according to claim 11, characterized in that In each of the nanocolumn units, a plurality of nanocolumns with different diameters are arranged in order of diameter size along a first direction, wherein the first direction is a direction parallel to the substrate plane; or In each of the nanocolumn units, a plurality of nanocolumns with different diameters are arranged in a polygonal shape.

16. The method according to claim 11 or 15, characterized in that The plurality of nanocolumn units are arranged in an array along the row direction and the column direction, wherein the nanocolumn units in adjacent rows and adjacent columns are aligned with each other.

17. The method according to claim 11 or 15, characterized in that: The plurality of nanocolumn units are arranged in an array along the row direction and the column direction, wherein the nanocolumn units in adjacent rows and adjacent columns are arranged alternately, and the nanocolumn units in alternate rows and alternate columns are aligned with each other.

18. The method according to claim 11, characterized in that The diameter of the nanocolumns ranges from 0.05 to 50 μm, and the distance between two adjacent nanocolumns ranges from 0.1 to 10 μm.

19. The method according to claim 11, characterized in that The height of the nanocolumn is equal to or lower than the height of the isolation layer, wherein the difference between the height of the nanocolumn and the height of the isolation layer is less than or equal to 30 nm.

20. The method according to claim 11, characterized in that The shape of the projection of the nanorod along a direction perpendicular to the substrate plane includes any one of a circle, a triangle, a quadrilateral and a pentagon.

21. The method according to claim 11, characterized in that The method further comprises: forming a transparent conductive layer on the isolation layer; forming a first electrode on the transparent conductive layer, and forming a second electrode on the n-type GaN layer; forming a passivation layer covering the transparent conductive layer, the n-type GaN layer, the first electrode and the second electrode; forming a distributed Bragg reflector layer on the passivation layer; forming a first window and a second window through the distributed Bragg reflector layer and the passivation layer, wherein the first window exposes the first electrode and the second window exposes the second electrode; forming a first pad on the first window, wherein the first pad is connected to the first electrode; A second pad is formed on the second window, and the second pad is connected to the second electrode.

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