Light emitting diode for improving bonding quality and preparation method thereof

Abstract

The invention provides a light-emitting diode for improving bonding quality and a preparation method thereof, and belongs to the technical field of photoelectron manufacturing. The light-emitting diode comprises an epitaxial layer and an insulating layer, the epitaxial layer is provided with a first surface and a second surface which are opposite, the first surface is provided with an electrode groove and an isolation groove, the isolation groove is located on the peripheral edge of the first surface and surrounds the electrode groove, and the depth of the electrode groove is different from that of the isolation groove; the insulating layer is located on the first surface, in the electrode groove and in the isolation groove, and the surface, away from the second surface, of the insulating layer located in the electrode groove is flush with the surface, away from the second surface, of the insulating layer located in the isolation groove. According to the embodiment of the invention, the adhesiveness between the insulating layer and the substrate can be improved, and the bonding reliability of the light-emitting diode is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technologies, and particularly relates to a light-emitting diode for improving bonding quality and a preparation method thereof. Background Art

[0002] A light-emitting diode (English: Light Emitting Diode, abbreviated as: LED) is a common product. An LED is usually formed by fabricating various film layers on a substrate, performing patterning processing, and then cutting.

[0003] In related technologies, during the preparation of a light-emitting diode, multiple grooves are usually formed on the surface of an epitaxial layer. The grooves include electrode grooves for connecting with electrodes and scribe grooves for scribing LED chips. To avoid leakage or short circuit of the light-emitting diode, an insulating layer is usually further formed in the grooves and on the surface of the epitaxial layer.

[0004] Since the insulating layer is mainly prepared by chemical vapor deposition, evaporation, or magnetron sputtering processes, the thickness of the prepared insulating layer is uniform. However, the depths of different grooves are usually inconsistent. Therefore, after the insulating layer is formed in the grooves, some grooves are difficult to be filled. That is, height differences are formed in different regions of the formed insulating layer, and after metal is evaporated thereon, very large height differences are also formed. When bonding the substrate to the light-emitting diode, air holes and voids are formed between the positions where the unfilled grooves are located and the substrate, resulting in poor adhesion between this position and the substrate and affecting the bonding stability of the light-emitting diode. Summary of the Invention

[0005] Embodiments of the present disclosure provide a light-emitting diode for improving bonding quality and a preparation method thereof, which can improve the adhesion between the insulating layer and the substrate and enhance the bonding reliability of the light-emitting diode. The technical solutions are as follows:

[0006] On the one hand, embodiments of the present disclosure provide a light-emitting diode, which includes an epitaxial layer and an insulating layer. The epitaxial layer has opposite first and second surfaces. The first surface has an electrode groove and an isolation groove. The isolation groove is located at the peripheral edge of the first surface and surrounds the electrode groove. The groove depth of the electrode groove is different from the groove depth of the isolation groove. The insulating layer is located on the first surface, in the electrode groove, and in the isolation groove. The surface of the insulating layer in the electrode groove away from the second surface is flush with the surface of the insulating layer in the isolation groove away from the second surface.

[0007] In one implementation manner of the present disclosure, the groove depth of the electrode groove is less than the groove depth of the isolation groove.

[0008] In another implementation of the present disclosure, the ratio of the depth of the isolation groove to the thickness of the epitaxial layer is 0.5 to 0.98.

[0009] In another implementation of the present disclosure, the ratio of the depth of the electrode groove to the thickness of the epitaxial layer is 0.1 to 0.5.

[0010] In another implementation of the present disclosure, the width of the isolation groove is 1.5 μm to 5 μm.

[0011] In another implementation of the present disclosure, the angle between the groove wall of the isolation groove and the second surface is 25° to 70°.

[0012] The embodiments of the present disclosure provide a method for manufacturing a light-emitting diode. The manufacturing method includes: preparing an epitaxial layer on a substrate, the epitaxial layer having opposite first and second surfaces, and the second surface being connected to the substrate; forming an electrode groove and an isolation groove on the first surface, the isolation groove being located at the peripheral edge of the epitaxial layer and surrounding the electrode groove, and the etching depth of the electrode groove being different from the etching depth of the isolation groove; forming an insulating layer on the first surface, in the electrode groove, and in the isolation groove, and the surface of the insulating layer in the electrode groove away from the second surface being flush with the surface of the insulating layer in the isolation groove away from the second surface.

[0013] Optionally, forming an insulating layer on the first surface, in the electrode groove, and in the isolation groove includes: spin-coating an insulating material on the first surface to make the insulating material flow into the electrode groove and the isolation groove; baking the insulating material to cure the insulating material to obtain an insulating layer.

[0014] Optionally, forming an electrode groove and an isolation groove on the first surface includes: forming an electrode groove on the first surface; forming an isolation groove surrounding the electrode groove on the first surface, and the etching depth of the electrode groove being less than the etching depth of the isolation groove.

[0015] Optionally, the ratio of the depth of the isolation groove to the thickness of the epitaxial layer is 0.5 to 0.98, and the ratio of the depth of the electrode groove to the thickness of the epitaxial layer is 0.1 to 0.5.

[0016] The beneficial effects brought by the technical solutions provided by the embodiments of the present disclosure at least include:

[0017] The first surface of the epitaxial layer of the light-emitting diode provided by the embodiment of the present disclosure has an electrode groove and an isolation groove. Among them, the isolation grooves are distributed on the peripheral edge of the first surface, the electrode grooves are distributed in the middle of the first surface, and the isolation grooves surround the electrode grooves. The insulating layer is laminated on the first surface and extends into the electrode grooves and the isolation grooves. Among them, the surfaces of the insulating layer in the electrode grooves and the isolation grooves away from the second surface are flush. That is, when the groove depths of the electrode grooves and the isolation grooves are different, the surfaces of the insulating layer in each area are flush and there is no large height difference. In this way, when bonding the substrate to the surface of the insulating layer, it is not easy to have air holes between the insulating layer and the substrate, which will not affect the adhesion between the insulating layer and the substrate, and can effectively improve the bonding stability of the light-emitting diode. Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0019] Figure 1 is a top view of a light-emitting diode provided by an embodiment of the present disclosure;

[0020] Figure 2 is a structural schematic diagram of a light-emitting diode provided by an embodiment of the present disclosure;

[0021] Figure 3 is a stress comparison diagram of an epitaxial layer provided with isolation grooves in an embodiment of the present disclosure;

[0022] Figure 4 is a hierarchical schematic diagram of an epitaxial layer provided by an embodiment of the present disclosure;

[0023] Figure 5 is a preparation flow chart of a light-emitting diode provided by an embodiment of the present disclosure;

[0024] Figure 6 is a preparation state diagram of a light-emitting diode provided by the present disclosure;

[0025] Figure 7 is a preparation state diagram of a light-emitting diode provided by the present disclosure.

[0026] The descriptions of the marks in the drawings are as follows:

[0027] 10. Substrate;

[0028] 20. Epitaxial layer; 201. First surface; 202. Second surface; 203. Electrode groove; 204. Isolation groove;

[0029] 21. first semiconductor layer; 22. multi-quantum well layer; 23. second semiconductor layer;

[0030] 30. Insulation layer;

[0031] 41. Transparent conductive layer; 42. Metal reflective layer; 43. Metal protective layer;

[0032] 51. bonding metal layer; 52. conductive substrate;

[0033] 60. Connect the electrodes. DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0035] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0036] Figure 1 It is a top view of a light emitting diode provided by an embodiment of the present disclosure. Figure 2 It is a structural schematic diagram of a light emitting diode provided in an embodiment of the present disclosure. Figure 2 The indication is along Figure 1 The layered diagram obtained by cutting along the AA section line.

[0037] like Figure 2 As shown, the light emitting diode comprises an epitaxial layer 20 and an insulating layer 30. The epitaxial layer 20 has a first surface 201 and a second surface 202 opposite to each other. The first surface 201 has an electrode groove 203 and an isolation groove 204. The groove depth of the electrode groove 203 is different from the groove depth of the isolation groove 204.

[0038] like Figure 1As shown, the isolation groove 204 is located at the peripheral edge of the first surface 201, and the isolation groove 204 surrounds the electrode groove 203.

[0039] As Figure 2 shown, the insulating layer 30 is located on the first surface 201, inside the electrode groove 203 and inside the isolation groove 204. The surface of the insulating layer 30 inside the electrode groove 203 that is away from the second surface 202 is flush with the surface of the insulating layer 30 inside the isolation groove 204 that is away from the second surface 202.

[0040] The first surface 201 of the epitaxial layer 20 of the light-emitting diode provided by the embodiment of the present disclosure has an electrode groove 203 and an isolation groove 204. Among them, the isolation groove 204 is distributed at the peripheral edge of the first surface 201, the electrode groove 203 is distributed in the middle of the first surface 201, and the isolation groove 204 surrounds the electrode groove 203. The insulating layer 30 is laminated on the first surface 201 and extends into the electrode groove 203 and the isolation groove 204. Among them, the surfaces of the insulating layer 30 in the electrode groove 203 and the isolation groove 204 that are away from the second surface 202 are flush. That is, when the groove depths of the electrode groove 203 and the isolation groove 204 are different, the surfaces of the insulating layer 30 in each region are flush, and there is no large height difference. In this way, when bonding the substrate to the surface of the insulating layer 30, it is not easy to have air holes between the insulating layer 30 and the substrate, which will not affect the adhesion between the insulating layer 30 and the substrate, and can effectively improve the bonding stability of the light-emitting diode.

[0041] Figure 3 is a stress comparison diagram of the epitaxial layer 20 provided with the isolation groove 204 in the embodiment of the present disclosure. As Figure 3 shown, on the left side of the vertical line in the figure is the light-emitting diode without the isolation groove 204 opened on the epitaxial layer 20, and on the right side of the vertical line in the figure is the light-emitting diode with the isolation groove 204 provided on the epitaxial layer 20. According to the attached drawings, the stress of the epitaxial layer 20 without the isolation groove 204 is higher than 0.39, while the stress of the epitaxial layer 20 with the isolation groove 204 is lower than 0.4. Therefore, by providing the isolation groove 204, the stress generated in the epitaxial layer 20 can be effectively reduced. This is because when the stress inside the epitaxial layer 20 is transmitted to the isolation groove 204, the epitaxial layer 20 in the area where the isolation groove 204 is located is not continuous, and the stress cannot continue to be transmitted when it reaches the isolation groove 204, so it is released at the isolation groove 204, thereby reducing the stress generated inside the epitaxial layer 20 and avoiding the warping of the light-emitting diode and improving the problem of peeling of the epitaxial layer 20.

[0042] Optionally, as Figure 2As shown, the groove depth of the electrode groove 203 is less than that of the isolation groove 204. Since the greater the groove depth of the isolation groove 204, the better the stress isolation effect of the isolation groove 204, and most of the stress can be released at the isolation groove 204. Therefore, by defining that the groove depth of the isolation groove 204 is greater than that of the electrode groove 203, it can be ensured that the groove depth of the isolation groove 204 formed on the epitaxial layer 20 is large enough to minimize the stress generated inside the epitaxial layer 20 as much as possible.

[0043] Optionally, the ratio of the groove depth of the isolation groove 204 to the thickness of the epitaxial layer 20 is 0.5 to 0.98. Controlling the groove depth of the isolation groove 204 to exceed half of the thickness of the epitaxial layer 20 can ensure that the groove depth of the isolation groove 204 formed on the epitaxial layer 20 is large enough to minimize the stress generated inside the epitaxial layer 20 as much as possible.

[0044] Exemplarily, when the thickness of the epitaxial layer 20 is 6μm, the groove depth of the isolation groove 204 can be 3μm to 5.9μm.

[0045] Optionally, the ratio of the groove depth of the electrode groove 203 to the thickness of the epitaxial layer 20 is 0.1 to 0.5. Controlling the groove depth of the electrode groove 203 not to exceed half of the thickness of the epitaxial layer 20 can prevent the electrode groove 203 from completely penetrating the epitaxial layer 20 and failing to electrically connect the electrode to the semiconductor layer exposed by the electrode groove 203.

[0046] Exemplarily, when the thickness of the epitaxial layer 20 is 6μm, the groove depth of the electrode groove 203 can be 0.6μm to 3μm.

[0047] Optionally, the width of the isolation groove 204 is 1.5μm to 5μm.

[0048] In the embodiments of the present disclosure, by setting the width of the isolation groove 204 within the above range, it is possible to prevent the width of the isolation groove 204 from being too large and removing too much of the epitaxial layer 20, which affects the light-emitting effect of the epitaxial layer 20; it can also prevent the width of the isolation groove 204 from being too small and failing to achieve the purpose of interrupting stress transmission.

[0049] As an example, in the embodiments of the present disclosure, the width of the isolation groove 204 can be 5μm.

[0050] Figure 4 It is a hierarchical schematic diagram of an epitaxial layer 20 provided by the embodiments of the present disclosure. As Figure 4 shown, the angle α between the groove wall of the isolation groove 204 and the second surface 202 is 25° to 70°.

[0051] By setting the groove wall of the isolation groove 204 as an inclined wall surface, the insulating layer 30 formed in the isolation groove 204 can be more easily attached to the inner wall of the isolation groove 204, enabling the insulating layer 30 to better fill the isolation groove 204, avoiding the situation of air holes or voids when the insulating layer 30 fills the isolation groove 204, preventing the insulating layer 30 located in the isolation groove 204 from collapsing during bonding to form air holes, and ensuring the adhesion between the insulating layer 30 and the substrate.

[0052] As an example, in the embodiments of the present disclosure, the included angle between the groove wall of the isolation groove 204 and the second surface 202 is 60°.

[0053] Optionally, the insulating layer 30 can be at least one of a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0054] Exemplarily, the insulating layer 30 can be a silicon oxide layer.

[0055] By forming the insulating layer 30 on the surface of the epitaxial layer 20 to wrap the epitaxial layer 20, it can avoid the epitaxial layer 20 from contacting other film layers and short - circuiting, and can effectively protect the epitaxial layer 20.

[0056] In the embodiments of the present disclosure, the electrode groove 203 exposes the semiconductor layer in the epitaxial layer 20, and the electrode groove 203 is used for depositing an electrode, so as to facilitate energizing the semiconductor layer exposed by the electrode groove 203 through the electrode.

[0057] Exemplarily, as Figure 2 shown, the orthographic projection of the electrode groove 203 on the second surface 202 does not overlap with the orthographic projection of the isolation groove 204 on the second surface 202.

[0058] In the embodiments of the present disclosure, the electrode groove 203 and the isolation groove 204 are formed by different etching processes respectively. In this way, it can be avoided that the area where the electrode groove 203 is located is etched when etching the isolation groove 204. Since the etched groove depth of the isolation groove 204 is greater than the etched groove depth of the electrode groove 203, therefore, etching the electrode groove 203 and the isolation groove 204 separately can avoid the over - etching of the electrode groove 203.

[0059] Optionally, as Figure 2 shown, from the first surface 201 to the second surface 202, the epitaxial layer 20 includes a first semiconductor layer 21, a multi - quantum well layer 22, and a second semiconductor layer 23 stacked in sequence.

[0060] Optionally, one of the first semiconductor layer 21 and the second semiconductor layer 23 is an n - type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is a p - type layer.

[0061] Exemplarily, the first semiconductor layer 21 is a p - type layer, and the second semiconductor layer 23 is an n - type layer.

[0062] Optionally, the n-type layer is an n-type GaN layer doped with silicon. The thickness of the n-type GaN layer can be 0.5 μm to 3 μm.

[0063] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. Among them, the multi-quantum well layer 22 can include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0064] As an example, in the embodiments of the present disclosure, the multi-quantum well layer 22 includes 5 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0065] Optionally, the thickness of the multi-quantum well layer 22 can be 150 nm to 200 nm.

[0066] Optionally, the p-type layer is a p-type GaN layer doped with magnesium. The thickness of the p-type GaN layer can be 0.5 μm to 3 μm.

[0067] Optionally, as Figure 2 shown, both the isolation groove 204 and the electrode groove 203 are located on the surface of the first semiconductor layer 21 away from the second semiconductor layer 23.

[0068] Optionally, as Figure 2 shown, the light-emitting diode further includes: a transparent conductive layer 41, a metal reflection layer 42, and a metal protection layer 43.

[0069] As Figure 2 shown, the transparent conductive layer 41 is located on the first surface 201. The insulating layer 30 also covers the transparent conductive layer 41. The insulating layer 30 has a through hole exposing the transparent conductive layer 41. The metal reflection layer 42 is located on the surface of the insulating layer 30 away from the second surface 202 and is connected to the transparent conductive layer 41 through the through hole. The metal protection layer 43 is located on the surface of the insulating layer 30 away from the second surface 202, and the metal protection layer 43 covers the metal reflection layer 42.

[0070] Exemplarily, the transparent conductive layer 41 can be an Indium Tin Oxide (ITO) layer. The ITO layer has good transmittance and low resistivity.

[0071] Exemplarily, the transparent conductive layer 41 can be an Indium Zinc Oxide (IZO) layer. The IZO layer has good transmittance and low resistivity.

[0072] Among them, using an ITO layer or an IZO layer as the transparent conductive layer 41 can allow more light to transmit through the transparent conductive layer 41, thus ensuring the light output effect; at the same time, due to the low resistivity, the metal reflective layer 42 is stacked on the transparent conductive layer 41, so that carriers can be more efficiently conducted from the metal reflective layer 42 to the epitaxial layer 20, improving the injection efficiency.

[0073] Exemplarily, the thickness of the transparent conductive layer 41 can be 600 angstroms to 2000 angstroms. For example, the thickness of the transparent conductive layer 41 is 1500 angstroms.

[0074] In the embodiments of the present disclosure, by providing the metal reflective layer 42, it can be used to reflect the light emitted from the epitaxial layer 20, allowing more light to be emitted from the light output surface of the epitaxial layer 20, and improving the luminous intensity of the light-emitting diode.

[0075] At the same time, a metal protection layer 43 is further covered on the reflective layer, which can prevent the metal in the metal reflective layer 42 from migrating upward.

[0076] Optionally, the metal reflective layer 42 includes a sequentially stacked Ag layer.

[0077] Since Ag has a good reflection effect, setting an Ag layer in the metal reflective layer 42 can enhance the reflection of light by the metal reflective layer 42 and improve the light emission brightness of the light output surface of the light-emitting diode.

[0078] Optionally, the metal protection layer 43 includes a Ni layer or a TiW layer.

[0079] Among them, the Ni layer has good corrosion resistance and wear resistance. The TiW layer can be successfully deposited on other thin films as an adhesion layer without peeling or cracking. The alternately stacked Ni layer and TiW layer can act as a barrier layer to protect the silver mirror.

[0080] Exemplarily, the thickness of the Ag layer is 1400 angstroms to 1700 angstroms. For example, the thickness of the Ag layer is 1500 angstroms.

[0081] Exemplarily, the thickness of the Ni layer is 100 angstroms to 300 angstroms. For example, the thickness of the Ni layer is 200 angstroms.

[0082] Exemplarily, the thickness of the TiW layer is 700 angstroms to 1000 angstroms. For example, the thickness of the TiW layer is 800 angstroms.

[0083] Figure 5 It is a flowchart of the preparation of a light-emitting diode provided by the embodiments of the present disclosure. As Figure 5 shown, the preparation method includes:

[0084] Step S11: Prepare an epitaxial layer on a substrate.

[0085] Exemplarily, the substrate may be a sapphire substrate. The sapphire substrate has a relatively high light transmittance, that is, the substrate is a transparent substrate. Moreover, the sapphire material is relatively hard and has relatively stable chemical properties, enabling the LED to have good luminous effects and stability.

[0086] The process of preparing the epitaxial layer 20 may include the following steps:

[0087] First, as Figure 6 shown, the epitaxial layer 20 grown on the sapphire substrate 10 includes a second semiconductor layer 23, a multi-quantum well layer 22, and a first semiconductor layer 21 stacked in sequence.

[0088] Among them, the sapphire substrate can be pre-treated by placing the sapphire substrate in an MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking the sapphire substrate for 12 to 18 minutes. As an example, in the embodiments of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0089] Specifically, the baking temperature can be 1000°C to 1200°C, and the pressure in the MOCVD reaction chamber during baking can be 100 mbar to 200 mbar.

[0090] Exemplarily, the first semiconductor layer 21 can be a p-type layer, and the second semiconductor layer 23 can be an n-type layer.

[0091] Optionally, the n-type layer is an n-type GaN layer doped with silicon. The thickness of the n-type GaN layer can be 0.5 μm to 3 μm.

[0092] The growth temperature of the n-type GaN layer can be 1000°C to 1100°C, and the growth pressure of the n-type GaN layer can be 100 torr to 300 torr.

[0093] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. Among them, the multi-quantum well layer 22 can include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0094] When growing the multi-quantum well layer 22, the pressure in the MOCVD reaction chamber is controlled at 200 torr. When growing the InGaN quantum well layer, the reaction chamber temperature is 760°C to 780°C. When growing the GaN quantum barrier layer, the reaction chamber temperature is 860°C to 890°C.

[0095] As an example, in the embodiments of the present disclosure, the multi-quantum well layer 22 includes 5 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0096] Optionally, the thickness of the multi-quantum well layer 22 can be from 150 nm to 200 nm.

[0097] Optionally, the p-type layer is a p-type GaN layer doped with magnesium. The thickness of the p-type GaN layer can be from 0.5 μm to 3 μm.

[0098] When growing the p-type GaN layer, the growth pressure of the p-type GaN layer can be from 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer can be from 800 °C to 1000 °C.

[0099] Then, the epitaxial layer 20 is etched to form a second groove 211 exposing the second semiconductor layer 23 on the surface of the first semiconductor layer 21.

[0100] Step S12: Form an electrode groove 203 and an isolation groove 204 on the first surface 201.

[0101] As Figure 6 shown, the isolation groove 204 is located at the peripheral edge of the epitaxial layer 20 and surrounds the electrode groove 203, and the groove depth of the electrode groove 203 is different from that of the isolation groove 204.

[0102] Specifically, it can include: etching to form the electrode groove 203 on the first surface 201; etching to form the isolation groove 204 surrounding the electrode groove 203 on the first surface 201, and the etching depth of the electrode groove 203 is less than that of the isolation groove 204.

[0103] Etching to form the electrode groove 203 and the isolation groove 204 separately in this way can form the electrode groove 203 and the isolation groove 204 with different groove depths respectively, and also avoid the etching depth of the electrode groove 203 being too large and penetrating the epitaxial layer 20.

[0104] Optionally, as Figure 1 shown, the width L of the isolation groove 204 is from 1.5 μm to 5 μm.

[0105] As an example, in the embodiment of the present disclosure, the width of the isolation groove 204 can be 5 μm.

[0106] Optionally, the groove depth of the electrode groove 203 is less than that of the isolation groove 204. Exemplarily, the ratio of the groove depth of the isolation groove 204 to the thickness of the epitaxial layer 20 is from 0.5 to 0.98. The ratio of the groove depth of the electrode groove 203 to the thickness of the epitaxial layer 20 is from 0.1 to 0.5.

[0107] As an example, when the thickness of the epitaxial layer 20 is 6 μm, the groove depth of the isolation groove 204 can be from 3 μm to 5.9 μm, and the groove depth of the electrode groove 203 can be from 0.6 μm to 3 μm.

[0108] Optionally, the included angle between the groove wall of the isolation groove 204 and the second surface 202 is from 25° to 70°.

[0109] After step S12, the following steps may further be included:

[0110] First step, as Figure 6 shown, a transparent conductive layer 41 is formed on the surface of the first semiconductor layer 21.

[0111] Among them, the transparent conductive layer 41 is located outside the electrode groove 203.

[0112] Exemplarily, the transparent conductive layer 41 is an indium tin oxide layer or an indium zinc oxide layer.

[0113] Exemplarily, the thickness of the transparent conductive layer 41 is 100 Å to 300 Å. For example, the thickness of the transparent conductive layer 41 is 200 Å.

[0114] Second step, a passivation layer is formed on the first surface 201 to cover the transparent conductive layer 41.

[0115] Among them, the passivation layer has a through hole exposing the transparent conductive layer 41.

[0116] Optionally, the passivation layer may be at least one of a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0117] Exemplarily, the passivation layer may be a silicon oxide layer.

[0118] Third step, as Figure 6 shown, a metal reflective layer 42 is formed on the surface of the passivation layer, and the metal reflective layer 42 is connected to the transparent conductive layer 41 through the through hole.

[0119] Fourth step, as Figure 6 shown, a metal protection layer 43 is formed on the surface of the passivation layer to cover the metal reflective layer 42.

[0120] Step S13: An insulating layer 30 is formed on the first surface 201, inside the electrode groove 203, and inside the isolation groove 204.

[0121] As Figure 6 shown, the surface of the insulating layer 30 located inside the electrode groove 203 away from the second surface 202 is flush with the surface of the insulating layer 30 located inside the isolation groove 204 away from the second surface 202.

[0122] The specific process of preparing the insulating layer 30 may include: spin-coating an insulating material on the first surface 201 to make the insulating material flow into the electrode groove 203 and the isolation groove 204. Bake the insulating material to cure the insulating material to obtain the insulating layer 30.

[0123] Exemplarily, the insulating material may be silicon oxide.

[0124] Since the groove depth of the isolation groove formed at the edge of the epitaxial layer is set to be large enough to reduce stress, this will result in a relatively large distance from the bottom of the isolation groove to the first surface of the epitaxial layer, that is, a groove with a large height difference is formed on the surface of the epitaxial layer. In the related art, the thickness of the insulating layer prepared by chemical vapor deposition, evaporation or magnetron sputtering process is the same. Therefore, when bonding the substrate to the surface of the insulating layer, air holes are likely to appear between the insulating layer and the substrate, affecting the adhesion between the insulating layer and the substrate.

[0125] In the embodiment of the present disclosure, the insulating material formed on the first surface 201 by spin coating is in a liquid state, and the liquid insulating material will preferentially flow into the electrode groove 203 and the isolation groove 204 until the electrode groove 203 and the isolation groove 204 are filled. That is, the thickness of the insulating layer 30 formed by spin coating is also thicker in the area with a larger groove depth and relatively thinner in the area with a smaller groove depth. Therefore, by spin coating, it can be ensured that the insulating material fills the electrode groove 203 and the isolation groove 204, making the surface of the insulating layer far from the second surface in the electrode groove and the isolation groove flatter, eliminating the problem that a large height difference exists on the surface of the insulating layer due to different groove depths of the electrode groove and the isolation groove. Moreover, it can reduce the problem of bubbles or holes appearing between the insulating layer 30 and the substrate when bonding the light-emitting diode to the substrate, and improve the bonding stability.

[0126] After step S13, the following steps may further be included:

[0127] The first step, as Figure 6 shown, etch the insulating layer 30 to form a through hole exposing the bottom of the electrode groove 203, and form a bonding metal layer 51 in the through hole, so that the bonding metal layer 51 is electrically connected to the second semiconductor layer 23.

[0128] Exemplarily, the bonding metal layer 51 may be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer and an Au layer stacked in sequence.

[0129] Among them, the thickness of the first Al layer is 8000 Å to 12000 Å, the thickness of the first Ti layer is 100 Å to 500 Å, the thickness of the second Al layer is 8000 Å to 12000 Å, the thickness of the second Ti layer is 500 Å to 1500 Å, and the thickness of the Au layer is 2000 Å to 5000 Å.

[0130] For example, the thickness of the first Al layer is 10000 Å, the thickness of the first Ti layer is 200 Å, the thickness of the second Al layer is 10000 Å, the thickness of the second Ti layer is 1000 Å, and the thickness of the Au layer is 3000 Å.

[0131] The second step, as Figure 7As shown, the side of the light-emitting diode having the insulating layer 30 is bonded to the conductive substrate 52, and the substrate is removed to expose the second surface 202 of the epitaxial layer 20.

[0132] Specifically, it may include: forming a bonding metal layer 51 on the conductive substrate 52, bonding the bonding metal layer 51 of the conductive substrate 52 to the bonding metal layer 51 on the epitaxial layer 20, and removing the sapphire substrate by laser lift-off to expose the second semiconductor layer 23.

[0133] Exemplarily, the conductive substrate 52 may be a silicon substrate.

[0134] The third step is as Figure 7 shown, forming a connection groove on the second surface 202 of the epitaxial layer 20 and forming a connection electrode 60 in the connection groove.

[0135] Exemplarily, the connection electrode 60 includes a Cr layer, an Al layer, a Ti layer, an Al layer, a Ti layer, an Al layer, a Cr layer, a Pt layer, and a Ti layer stacked in sequence. And the thicknesses of the respective metal layers are 30 Å, 2000 Å, 1000 Å, 2000 Å, 1000 Å, 2000 Å, 500 Å, 2000 Å, and 500 Å respectively.

[0136] The above are only optional embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light emitting diode comprises an epitaxial layer (20) and an insulating layer (30), the epitaxial layer (20) having a first surface (201) and a second surface (202) opposite to each other, the first surface (201) having an electrode groove (203) and an isolation groove (204), the isolation groove (204) being located at the peripheral edge of the first surface (201) and surrounding the electrode groove (203), the groove depth of the electrode groove (203) being different from the groove depth of the isolation groove (204); The insulating layer (30) is located on the first surface (201), in the electrode groove (203) and in the isolation groove (204), and the surface of the insulating layer (30) in the electrode groove (203) away from the second surface (202) is flush with the surface of the insulating layer (30) in the isolation groove (204) away from the second surface (202).

2. The light emitting diode according to claim 1, characterized in that: The groove depth of the electrode groove (203) is smaller than the groove depth of the isolation groove (204).

3. The light emitting diode according to claim 2, characterized in that: The ratio of the depth of the isolation trench (204) to the thickness of the epitaxial layer (20) is 0.5 to 0.

98.

4. The light emitting diode according to claim 2, characterized in that: The ratio of the depth of the electrode groove (203) to the thickness of the epitaxial layer (20) is 0.1 to 0.

5.

5. The light emitting diode according to claim 1, characterized in that: The width (L) of the isolation groove (204) is 1.5 μm to 5 μm.

6. The light emitting diode according to any one of claims 1 to 5, characterized in that: The included angle (α) between the groove wall of the isolation groove (204) and the second surface (202) is 25° to 70°.

7. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: Preparing an epitaxial layer on a substrate, wherein the epitaxial layer has a first surface and a second surface opposite to each other, wherein the second surface is connected to the substrate; forming an electrode groove and an isolation groove on the first surface, wherein the isolation groove is located at the peripheral edge of the epitaxial layer and surrounds the electrode groove, and the groove depth of the electrode groove is different from the groove depth of the isolation groove; An insulating layer is formed on the first surface, in the electrode groove and in the isolation groove, and a surface of the insulating layer in the electrode groove away from the second surface is flush with a surface of the insulating layer in the isolation groove away from the second surface.

8. The preparation method according to claim 7, characterized in that: Forming an insulating layer on the first surface, in the electrode groove and in the isolation groove comprises: Spin-coating an insulating material on the first surface so that the insulating material flows into the electrode groove and the isolation groove; The insulating material is baked to solidify the insulating material, thereby obtaining an insulating layer.

9. The preparation method according to claim 7 or 8, characterized in that: Forming the electrode groove and the isolation groove on the first surface includes: forming an electrode groove on the first surface; An isolation groove surrounding the electrode groove is formed on the first surface, and an etching depth of the electrode groove is smaller than an etching depth of the isolation groove.

10. The preparation method according to claim 9, characterized in that: The ratio of the trench depth of the isolation trench to the thickness of the epitaxial layer is 0.5 to 0.98, and the ratio of the trench depth of the electrode trench to the thickness of the epitaxial layer is 0.1 to 0.5.

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