Mini-LED chip and manufacturing method thereof

Abstract

The embodiment of the invention provides a Mini-LED chip and a manufacturing method thereof, and the method comprises the steps: obtaining a to-be-bonded structure which comprises an epitaxial structure layer and a bonding layer with a first target thickness, and bonding the to-be-bonded structure and a transparent substrate in a direction from the bonding layer with the first target thickness to the transparent substrate, the first type layer, the active layer and the bonding layer with the second target thickness located in the cutting channel area are etched, a step structure is formed, the step structure comprises a first step and a second step, the first step comprises the first type layer and the active layer, and the second step comprises the second type layer and the bonding layer with the first target thickness; forming a distributed Bragg reflection layer and an electrode; according to the method, the transparent substrate exposed in the cutting channel region is cut to form a plurality of sub-millimeter light-emitting diode Mini-LED chips, and because no thick bonding layer exists in the cutting channel region, the edge breakage probability when the Mini-LED chips are formed through cutting can be greatly reduced only by cutting the transparent substrate, so that the cutting yield of the Mini-LED chips is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and particularly to a Mini-LED chip and a manufacturing method thereof. Background Art

[0002] With the rapid development of display-related technologies and semiconductor devices, color displays can be achieved using submillimeter light-emitting diode (Mini-LED) chips.

[0003] As the size of Mini-LED chips becomes smaller and smaller, the color display effect becomes finer, but the difficulty of manufacturing Mini-LED chips becomes greater. The current manufacturing process steps for Mini-LED chips include cutting a plurality of Mini-LED chips to form independent Mini-LED chips.

[0004] However, after the current cutting process, there is a problem of chipping on the Mini-LED chips, which affects the cutting yield of the Mini-LED chips. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a Mini-LED chip and a manufacturing method thereof, which reduce the chipping probability of the Mini-LED chip and improve the cutting yield of the Mini-LED chip.

[0006] To achieve the above purpose, this application has the following technical solutions:

[0007] This application provides a manufacturing method for a Mini-LED chip, including:

[0008] Obtaining a structure to be bonded, the structure to be bonded including an epitaxial structure layer and a bonding layer, the epitaxial structure layer including a first type layer, an active layer, and a second type layer stacked in sequence, and the bonding layer being located on a surface of the second type layer away from the first type layer;

[0009] Removing a part of the thickness of the bonding layer using a grinding process to obtain a bonding layer with a first target thickness;

[0010] Bonding the structure to be bonded and the transparent substrate with the bonding layer having the first target thickness facing the direction of the transparent substrate;

[0011] Etching the first type layer, the active layer, and the bonding layer with a second target thickness located in the cutting channel area to form a stepped structure, the stepped structure including a first stepped layer and a second stepped layer, the first stepped layer including the first type layer and the active layer, and the second stepped layer including the second type layer and the bonding layer with the first target thickness;

[0012] Form a distributed Bragg reflector layer and electrodes;

[0013] Cut the transparent substrate exposed in the scribing lane region to form a plurality of sub - millimeter light - emitting diode (Mini - LED) chips.

[0014] Optionally, etching the first - type layer, the active layer, and the bonding layer with a second target thickness located in the scribing lane region to form a stepped structure including:

[0015] Using the same mesa etching process to etch the first - type layer and the active layer located in the chip region and to etch the bonding layer with a second target thickness located in the scribing lane region to form a stepped structure.

[0016] Optionally, the forming of the distributed Bragg reflector layer and electrodes includes:

[0017] Deposit the material of the distributed Bragg reflector layer, etch the material of the distributed Bragg reflector layer located on the stepped structure and in the scribing lane region to form a first groove, a second groove, and a distributed Bragg reflector layer, where the distributed Bragg reflector layer covers the sidewalls of the stepped structure, the first groove exposes the surface of the first - layer step, and the second groove exposes the surface of the second - layer step;

[0018] Form electrodes in the first groove and the second groove.

[0019] Optionally, the cutting of the transparent substrate exposed in the scribing lane region includes:

[0020] Use laser scribing to cut the transparent substrate exposed in the scribing lane region;

[0021] Use laser dicing to continue cutting the transparent substrate exposed in the scribing lane region.

[0022] Optionally, the first target thickness is less than or equal to 2 microns.

[0023] Optionally, the obtaining of the bonding structure to be bonded includes:

[0024] Use chemical - mechanical polishing to remove part of the thickness of the bonding layer, reduce the surface roughness of the bonding layer, and obtain a bonding layer with a first target thickness.

[0025] Optionally, the transparent substrate is a sapphire substrate.

[0026] Optionally, the obtaining of the structure to be bonded includes:

[0027] Form an epitaxial structure layer on a temporary substrate;

[0028] A bonding layer is formed on a surface of the epitaxial structure layer away from the temporary substrate to obtain a structure to be bonded;

[0029] Before etching the second type layer, the active layer, and the bonding layer with the second target thickness in the dicing channel region, the method further includes:

[0030] Removing the temporary substrate.

[0031] An embodiment of the present application provides a Mini-LED chip, including:

[0032] A transparent substrate and a bonding layer on one side of the transparent substrate;

[0033] On a surface of the bonding layer away from the transparent substrate, an epitaxial structure layer is provided. The epitaxial structure layer includes a second type layer, an active layer, and a first type layer stacked in sequence. The bonding layer and the epitaxial structure layer form a stepped structure. The stepped structure includes a first stepped portion and a second stepped portion. The first stepped portion includes the first type layer and the active layer, and the second stepped portion includes the second type layer and the bonding layer with the first target thickness;

[0034] A distributed Bragg reflector covers the surface and the sidewall of the stepped structure. The distributed Bragg reflector includes a first groove and a second groove. The first groove exposes the surface of the first stepped portion, and the second groove exposes the surface of the second stepped portion;

[0035] Electrodes are provided in the first groove and the second groove.

[0036] Optionally, the first target thickness is less than or equal to 2 micrometers.

[0037] The present application provides a method for manufacturing a Mini-LED chip. The method includes: obtaining a structure to be bonded, which includes an epitaxial structure layer and a bonding layer. The epitaxial structure layer includes a first-type layer, an active layer, and a second-type layer that are sequentially stacked, and the bonding layer is located on a surface of the second-type layer away from the first-type layer; using a grinding process to remove a part of the thickness of the bonding layer to obtain a bonding layer with a first target thickness, and reducing the thickness of the bonding layer to reduce the probability of chipping during subsequent cutting of the Mini-LED chip; bonding the structure to be bonded and a transparent substrate with the bonding layer having the first target thickness facing the transparent substrate, etching the first-type layer, the active layer, and the bonding layer with a second target thickness in the scribe lane area, where the second target thickness is less than or equal to the first target thickness, to form a stepped structure. The stepped structure includes a first stepped layer and a second stepped layer. The first stepped layer includes the first-type layer and the active layer, and the second stepped layer includes the second-type layer and the bonding layer with the first target thickness. That is to say, during the process of etching the first-type layer and the active layer to form the stepped structure, the bonding layer with the second target thickness in the scribe lane area is etched to avoid a relatively thick bonding layer in the scribe lane area, further reducing the probability of chipping during subsequent cutting of the Mini-LED chip; forming a distributed Bragg reflector layer and electrodes; cutting the transparent substrate exposed in the scribe lane area to form a plurality of sub-millimeter light-emitting diode Mini-LED chips. Since there is no relatively thick bonding layer in the scribe lane area, only cutting the transparent substrate can greatly reduce the probability of chipping when cutting to form Mini-LED chips, thereby improving the cutting yield of Mini-LED chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0039] Figure 1 FIG. shows a flowchart of a method for manufacturing a Mini-LED chip provided by an embodiment of the present application;

[0040] Figures 2 - 6 FIG. shows a schematic structural diagram of a Mini-LED chip manufactured by the method for manufacturing a Mini-LED chip provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] In order to make the above objects, features, and advantages of the present application more obvious and understandable, the following will provide a detailed description of the specific embodiments of the present application in conjunction with the drawings.

[0042] In the following description, numerous specific details are set forth to provide a thorough understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Persons skilled in the art can make similar generalizations without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0043] Secondly, the present application will be described in detail in conjunction with schematic diagrams. When detailing the embodiments of the present application, for ease of explanation, the cross-sectional views showing the device structure will be enlarged locally out of proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present application herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0044] As the size of Mini-LED chips becomes smaller and smaller, the color display effect becomes more refined, but the difficulty of manufacturing Mini-LED chips becomes greater and greater. The current process steps for manufacturing Mini-LED chips include cutting a plurality of Mini-LED chips to form independent Mini-LED chips.

[0045] However, after the current cutting process, there is a problem of chipping on the edges of Mini-LED chips, which affects the cutting yield of Mini-LED chips.

[0046] Currently, Mini-LED chips are obtained by bonding an epitaxial structure layer with silicon oxide and a substrate and then cutting at least the silicon oxide and the substrate. Therefore, the cutting process of Mini-LED chips is mainly the cutting of silicon oxide and the substrate. Since the current thickness of the silicon oxide is relatively thick, about 5 micrometers, positive chipping of the silicon oxide occurs when cutting the silicon oxide and the substrate, resulting in the chipping problem of Mini-LED chips.

[0047] Based on the above technical problems, the present application provides a method for manufacturing a Mini-LED chip. The method includes: obtaining a bonding structure to be bonded, the bonding structure to be bonded including an epitaxial structure layer and a bonding layer, the epitaxial structure layer including a first type layer, an active layer, and a second type layer stacked in sequence, and the bonding layer being located on a surface of the second type layer away from the first type layer; using a grinding process to remove a part of the thickness of the bonding layer to obtain a bonding layer with a first target thickness, and reducing the probability of chipping during subsequent cutting of the Mini-LED chip by reducing the thickness of the bonding layer; bonding the bonding structure to be bonded and a transparent substrate with the bonding layer having the first target thickness facing the transparent substrate, etching the first type layer, the active layer, and a second target thickness of the bonding layer located in the scribe lane region, the second target thickness being less than or equal to the first target thickness, to form a step structure, the step structure including a first layer step and a second layer step, the first layer step including the first type layer and the active layer, and the second layer step including the second type layer and the bonding layer with the first target thickness, that is, by etching the second target thickness of the bonding layer located in the scribe lane region during the process of etching the first type layer and the active layer to form the step structure, avoiding a relatively thick bonding layer in the scribe lane region, and further reducing the probability of chipping during subsequent cutting of the Mini-LED chip; forming a distributed Bragg reflector layer and electrodes; cutting the transparent substrate exposed in the scribe lane region to form a plurality of submillimeter light-emitting diode Mini-LED chips. Since there is no relatively thick bonding layer in the scribe lane region, only cutting the transparent substrate can greatly reduce the probability of chipping during cutting to form Mini-LED chips, thereby improving the cutting yield of Mini-LED chips.

[0048] To better understand the technical solutions and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0049] Reference Figure 1 As shown, it is a flowchart of a method for manufacturing a Mini-LED chip provided by an embodiment of the present application. The method includes the following steps:

[0050] S101, obtain a bonding structure to be bonded, the bonding structure to be bonded including an epitaxial structure layer and a bonding layer, the epitaxial structure layer including a first type layer, an active layer, and a second type layer stacked in sequence, and the bonding layer being located on a surface of the second type layer away from the first type layer.

[0051] In an embodiment of the present application, since manufacturing a Mini-LED chip requires bonding with a transparent substrate, a bonding structure to be bonded can be obtained. The bonding structure to be bonded includes an epitaxial structure layer 100 and a bonding layer 200. Reference Figure 2 As shown.

[0052] The epitaxial structure layer 100 includes a first-type layer 110, an active layer 120, and a second-type layer 130 that are sequentially stacked. With the first-type layer 110 as the bottom layer and the second-type layer 130 as the top layer, the active layer 120 covers the first-type layer 110, and the second-type layer 130 covers the active layer 120.

[0053] Specifically, the first-type layer 110 is an N-type layer, and the second-type layer 130 is a P-type layer. The P-type layer includes a P-type confinement layer and a P-type window layer. The materials of the N-type layer and the P-type confinement layer can be AlGaInP, and the material of the P-type window layer is GaP. The active layer 120 is a multi-quantum well (MQW).

[0054] The bonding layer 200 is located on the surface of the second-type layer 130 away from the first-type layer 110, that is, the bonding layer 200 is in direct contact with the second-type layer 130.

[0055] Specifically, the material of the bonding layer 200 is silicon oxide. The initial thickness of the bonding layer 200 can be 3 micrometers.

[0056] As a possible implementation, the epitaxial structure layer 100 further includes an ohmic contact layer, an etch stop layer, and a buffer layer that are sequentially stacked. The ohmic contact layer is disposed on the surface of the first-type layer 110 away from the second-type layer 130, that is, the ohmic contact layer is in direct contact with the first-type layer 110. With the first-type layer 110 as the bottom layer and the second-type layer 130 as the top layer, the ohmic contact layer covers the etch stop layer, and the etch stop layer covers the buffer layer.

[0057] Specifically, the materials of the buffer layer and the ohmic contact layer can be GaAs.

[0058] In the embodiment of the present application, to form the structure to be bonded, a temporary substrate 201 can be obtained, the epitaxial structure layer 100 is formed on the temporary substrate 201, and then the bonding layer 200 is continuously formed on the surface of the epitaxial structure layer 100 away from the temporary substrate 201, so as to obtain the structure to be bonded, as shown in Figure 2 shown.

[0059] Specifically, the material of the temporary substrate 201 can be GaAs, and the epitaxial structure layer 100 is formed on the temporary substrate 201 by using the Metal-organic Chemical Vapor Deposition (MOCVD) process.

[0060] The specific process of forming the bonding layer 200 on the epitaxial structure layer 100 is as follows: cleaning the surface of the epitaxial structure layer 100 by means of acetone, isopropyl alcohol, deionized water, etc., roughening the surface of the P-type window layer with a GaP roughening solution, and then depositing the bonding layer on the epitaxial structure layer 100. The roughened P-type window layer and the bonding layer 200 have better adhesion.

[0061] S102, removing a part of the thickness of the bonding layer by a grinding process to obtain a bonding layer with a first target thickness.

[0062] In an embodiment of the present application, after forming the bonding layer 200 on the epitaxial structure layer 100 to obtain the structure to be bonded, a part of the thickness of the bonding layer 200 can be removed by a grinding process to obtain a bonding layer 200 with a first target thickness, as shown in Figure 3 That is to say, the bonding layer 200 is polished and thinned by a grinding process, so as to reduce the thickness of the bonding layer 200, and the probability of chipping during subsequent cutting of the Mini-LED chip is reduced by reducing the thickness of the bonding layer.

[0063] As a possible implementation manner, a part of the thickness of the bonding layer 200 is removed by a chemical mechanical polishing (CMP) process to reduce the surface roughness of the bonding layer 200 and obtain a bonding layer 200 with a first target thickness. Reducing the surface roughness of the bonding layer 200 can achieve better bonding with the transparent substrate subsequently. The first target thickness is the thickness that is relatively easy to etch and remove when etching the bonding layer 200 subsequently.

[0064] As an example, the first target thickness is less than or equal to 2 μm. That is to say, the bonding layer 200 is polished by the CMP process, the thickness of the bonding layer 200 is reduced to less than or equal to 2 μm, and the surface roughness of the bonding layer 200 is adjusted to 70-90 pm, that is, the surface roughness range of the bonding layer 200 is 70-90 pm.

[0065] S103, bonding the structure to be bonded and the transparent substrate with the bonding layer having the first target thickness facing the direction of the transparent substrate.

[0066] In an embodiment of the present application, a transparent substrate 300 is obtained, and the structure to be bonded and the transparent substrate 300 are bonded with the bonding layer 200 having the first target thickness facing the direction of the transparent substrate 300. As shown in Figure 4 That is, the bonding layer 200 is in direct contact with the transparent substrate 300.

[0067] The transparent substrate 300 can be used as the light-emitting side of the subsequent Mini-LED chip, so a material with better light transmittance can be selected. Specifically, the transparent substrate 300 can be a sapphire substrate.

[0068] In practical applications, before bonding, the surfaces of the bonding layer 200 and the transparent substrate 300 can also be subjected to activation treatment.

[0069] In the embodiments of the present application, after bonding the structure to be bonded and the transparent substrate 300, the temporary substrate 201 can be removed to facilitate subsequent other processes.

[0070] S104, etching the first type layer, the active layer, and the bonding layer with a second target thickness located in the dicing channel area to form a stepped structure. The stepped structure includes a first stepped layer and a second stepped layer. The first stepped layer includes the first type layer and the active layer, and the second stepped layer includes the second type layer and the bonding layer with a first target thickness. The second target thickness is less than or equal to the first target thickness.

[0071] In the embodiments of the present application, considering that when manufacturing Mini-LED chips, it is necessary to perform dicing to obtain independent Mini-LED chips. Therefore, the structure to be bonded and the transparent substrate after bonding include a dicing channel area 1000 and a chip area 2000. The dicing channel area 1000 surrounds the chip area 2000. After bonding the structure to be bonded and the transparent substrate 300, the first type layer 110, the active layer 120 located in the chip area 2000 and the dicing channel area 1000, and the bonding layer 200 with a second target thickness located in the dicing channel area 1000 can be etched to form a stepped structure. The second target thickness is less than or equal to the first target thickness. Refer to Figure 5 As shown, taking the second target thickness equal to the first target thickness as an example, the bonding layer 200 located in the dicing channel area 1000 is etched for illustration, that is, the entire bonding layer 200 located in the dicing channel area 1000 is etched. That is to say, when etching the first type layer 110 and the active layer 120, the bonding layer 200 with a first target thickness located in the dicing channel area 1000 is also etched, avoiding the relatively thick bonding layer 200 in the dicing channel area 1000. Preferably, the bonding layer 200 in the dicing channel area 1000 is completely removed. When subsequently dicing the Mini-LED chip, there is no need to cut the bonding layer 200, and only the transparent substrate 300 needs to be cut in the dicing channel area 1000, greatly reducing the dicing difficulty and further reducing the probability of chipping when subsequently dicing the Mini-LED chip.

[0072] In practical applications, etching the bonding layer 200 with a thickness less than the first target thickness can reduce the difficulty of etching and removing the bonding layer 200, and can also achieve the purpose of reducing the dicing difficulty.

[0073] The step structure is located in the chip region 2000 and is composed of a first-type layer 110, an active layer 120, a second-type layer 130, and a bonding layer 200. The step structure includes two layers of steps, namely a first layer of steps and a second layer of steps. The first layer of steps includes the first-type layer 110 and the active layer 120, and the second layer of steps includes the second-type layer 130 and the bonding layer 200.

[0074] Reference Figure 5 As shown, in the direction perpendicular to the surface of the transparent substrate 300, the side walls of the bonding layer 200 and the second-type layer 130 are flush, thereby forming the second layer of steps to ensure that the bonding layer 200 is not located in the dicing channel region 1000.

[0075] As a possible implementation, mesa etching can be performed, that is, etching the first-type layer 110 and the active layer 120, so as to form electrodes subsequently. When performing mesa etching, the bonding layer 200 with a second target thickness located in the dicing channel region 1000 can also be etched. That is to say, the first-type layer 110 and the active layer 120 located in the chip region 2000 and the bonding layer 200 with a second target thickness located in the dicing channel region 1000 can be etched using the same mesa etching process to form a step structure. During the process of etching the bonding layer 200 with a second target thickness located in the dicing channel region 1000 using the mesa etching process, the second-type layer 130 located in the dicing channel region 1000 is also etched away, so that only the transparent substrate 300 remains in the dicing channel region 1000.

[0076] In the embodiment of the present application, when etching the first-type layer 110, the active layer 120, and the bonding layer 200 with a second target thickness located in the dicing channel region 1000 to form a step structure, the first-type layer 110 and the active layer 120 located in the chip region 2000 can be asymmetrically etched, so as to obtain a step structure presenting an asymmetric structure.

[0077] As a possible implementation, when etching the first-type layer 110 and the active layer 120 located in the chip region 2000, the etched area of one side of the subsequent formed step structure can be set to be larger, and the etched area of the opposite side can be set to be smaller. Reference Figure 5 As shown, the second layer of steps of the etched step structure includes a first side step and a second side step. The first side step and the second side step are oppositely arranged, and the surface area of the first side step is larger than the surface area of the second side step, so as to have sufficient area to form electrodes on the first side step subsequently.

[0078] S105, forming a distributed Bragg reflector layer and electrodes.

[0079] In an embodiment of the present application, after forming the stepped structure, a distributed Bragg reflector layer 400 and an electrode 500 can be formed on the stepped structure, so that the distributed Bragg reflector layer 400 is used to realize the emission of light from the Mini-LED chip in the direction of the transparent substrate 300 during light emission, and the electrode 500 realizes the electrical lead-out of the Mini-LED chip.

[0080] Specifically, the electrode 500 may include a first electrode electrically connected to the first type layer 110 and a second electrode electrically connected to the second type layer 130. The first electrode is located on the surface of the first type layer 110 away from the transparent substrate 300, and the second electrode is located on the surface of the second type layer 120 away from the transparent substrate 300. Refer to Figure 6 as shown.

[0081] As a possible implementation manner, the material of the distributed Bragg reflector layer can be deposited on the stepped structure first, and the material of the distributed Bragg reflector layer located on the stepped structure and in the dicing channel region 1000 is etched, so as to avoid the dicing channel region 1000 having the material of the distributed Bragg reflector layer, avoid affecting the subsequent dicing process in the dicing channel region 1000 due to the deposition of the material of the distributed Bragg reflector layer, avoid increasing the dicing difficulty, and avoid the problem of chipping, to form a first groove, a second groove and a distributed Bragg reflector layer 400. At this time, the distributed Bragg reflector layer 400 covers the side wall of the stepped structure, which not only realizes the light reflection using the distributed Bragg reflector layer 400, but also realizes the electrical isolation of the Mini-LED chip. The first groove exposes the surface of the first layer of the step, and the second groove exposes the surface of the second layer of the step; then the electrode 500 is formed in the first groove and the second groove, so as to realize the electrical lead-out.

[0082] Specifically, the forming process of the electrode 500 can be an evaporation process, and the first electrode and the second electrode can be formed simultaneously.

[0083] S106, dicing the transparent substrate exposed in the dicing channel region to form a plurality of sub-millimeter light-emitting diode Mini-LED chips.

[0084] In an embodiment of the present application, after forming the Bragg reflector layer 400 and the electrode 500, the transparent substrate 300 exposed in the dicing channel region 1000 can also be diced to form a plurality of sub-millimeter light-emitting diode Mini-LED chips. Since there is no thick bonding layer 200 in the dicing channel region 1000, only dicing the transparent substrate 300 can greatly reduce the probability of chipping when forming Mini-LED chips, thereby improving the dicing yield of Mini-LED chips.

[0085] As a possible implementation, when cutting the transparent substrate 300 exposed in the cutting channel area 1000, the transparent substrate 300 exposed in the cutting channel area 1000 can be first cut by laser surface cutting, and then the transparent substrate 300 exposed in the cutting channel area 1000 can be continuously cut by laser stealth cutting. That is to say, the transparent substrate 300 is grooved by laser surface cutting, and then stealth cutting and chip breaking are carried out, so as to further reduce the probability of chipping when forming Mini-LED chips by cutting, and further improve the cutting yield of Mini-LED chips.

[0086] It can be seen that in the manufacturing method of the Mini-LED chip provided by the embodiment of the present application, during the process of etching the first type layer and the active layer to form a step structure, the bonding layer with the second target thickness located in the cutting channel area is etched to avoid the bonding layer being located in the cutting channel area, and further reduce the probability of chipping when cutting the Mini-LED chip subsequently; when forming multiple sub-millimeter light-emitting diode Mini-LED chips, since there is no thick bonding layer in the cutting channel area, only cutting the transparent substrate can greatly reduce the probability of chipping when cutting to form Mini-LED chips, thereby improving the cutting yield of Mini-LED chips.

[0087] Based on the manufacturing method of the Mini-LED chip provided in the above embodiments, the embodiment of the present application also provides a Mini-LED chip. Refer to Figure 6 As shown, it is a schematic structural diagram of a Mini-LED chip provided by the embodiment of the present application. The Mini-LED chip includes a transparent substrate 300 and a bonding layer 200 located on one side of the transparent substrate 300.

[0088] On the surface of the bonding layer 200 away from the transparent substrate 300, an epitaxial structure layer 100 is provided. The epitaxial structure layer 100 includes a second type layer 130, an active layer 120, and a first type layer 110 that are sequentially stacked; the bonding layer 200 and the epitaxial structure layer 100 form a step structure, and the step structure includes a first layer step and a second layer step. The first layer step includes the first type layer 110 and the active layer 120, and the second layer step includes the second type layer 130 and the bonding layer with the first target thickness.

[0089] The distributed Bragg reflector layer 400 covers the surface and the side wall of the step structure. The distributed Bragg reflector layer 400 includes a first groove and a second groove. The first groove exposes the surface of the first layer step, and the second groove exposes the surface of the second layer step; electrodes 500 are provided in the first groove and the second groove.

[0090] In an embodiment of the present application, the epitaxial structure layer 100 includes a second-type layer 130, an active layer 120, and a first-type layer 110 that are sequentially stacked. With the first-type layer 110 as the top layer and the second-type layer 130 as the bottom layer, the active layer 120 covers the second-type layer 130, and the first-type layer 110 covers the active layer 120.

[0091] Specifically, the first-type layer 110 is an N-type layer, and the second-type layer 130 is a P-type layer. The P-type layer includes a P-type confinement layer and a P-type window layer. The P-type window layer is disposed on a side of the P-type confinement layer away from the active layer 120, that is, the P-type window layer is in direct contact with the bonding layer 200, and the P-type confinement layer is in direct contact with the active layer 120. The materials of the N-type layer and the P-type confinement layer can be AlGaInP, and the material of the P-type window layer is GaP. The active layer 120 is a multi-quantum well (MQW).

[0092] The bonding layer 200 is located on a surface of the second-type layer 130 away from the first-type layer 110, that is, the bonding layer 200 is in direct contact with the second-type layer 130.

[0093] Specifically, the material of the bonding layer 200 is silicon oxide. The initial thickness of the bonding layer 200 can be 3 microns.

[0094] As a possible implementation, the epitaxial structure layer 100 further includes an ohmic contact layer, an etch stop layer, and a buffer layer that are sequentially stacked. The ohmic contact layer is disposed on a surface of the first-type layer 110 away from the second-type layer 130, that is, the ohmic contact layer is in direct contact with the first-type layer 110. With the first-type layer 110 as the top layer and the second-type layer 130 as the bottom layer, the etch stop layer covers the ohmic contact layer, and the buffer layer covers the etch stop layer.

[0095] Specifically, the materials of the buffer layer and the ohmic contact layer can be GaAs.

[0096] In an embodiment of the present application, the thickness of the bonding layer 200 is a first target thickness.

[0097] Specifically, the first target thickness is less than or equal to 2 microns.

[0098] Specifically, the roughness range of the surface of the bonding layer 200 in contact with the transparent substrate 300 is 70 - 90 pm, that is, the roughness range of the surface of the bonding layer 200 is 70 - 90 pm.

[0099] In an embodiment of the present application, the transparent substrate 300 can be used as the light-emitting side of a subsequent Mini-LED chip, so a material with better light transmittance can be selected. Specifically, the transparent substrate 300 can be a sapphire substrate.

[0100] In an embodiment of the present application, the stepped structure is composed of a first type layer 110, an active layer 120, a second type layer 130, and a bonding layer 200. The stepped structure includes two layers of steps, namely a first layer of step and a second layer of step. The first layer of step includes the first type layer 110 and the active layer 120, and the second layer of step includes the second type layer 130 and the bonding layer 200.

[0101] As shown in Figure 6 the figure, in the direction perpendicular to the surface of the transparent substrate 300, the side walls of the bonding layer 200 and the second type layer 130 are flush, thereby forming the second layer of step.

[0102] In an embodiment of the present application, the stepped structure is an asymmetric structure.

[0103] As a possible implementation manner, the second layer of step of the stepped structure includes a first side step and a second side step. The first side step and the second side step are oppositely arranged, and the surface area of the first side step is larger than that of the second side step, so as to have sufficient area on the first side step to arrange the electrode 500.

[0104] In an embodiment of the present application, a distributed Bragg reflector layer 400 and an electrode 500 are arranged on the stepped structure, so as to use the distributed Bragg reflector layer 400 to realize the light emitted by the Mini-LED chip in the direction of the transparent substrate 300, and the electrode 500 realizes the electrical lead-out of the Mini-LED chip.

[0105] Specifically, the electrode 500 may include a first electrode electrically connected to the first type layer 110 and a second electrode electrically connected to the second type layer 130. The first electrode is located on the surface of the first type layer 110 away from the transparent substrate 300, and the second electrode is located on the surface of the second type layer 120 away from the transparent substrate 300. As shown in Figure 6 the figure.

[0106] As a possible implementation manner, the distributed Bragg reflector layer 400 covers the side walls of the stepped structure, which not only realizes the light reflection by using the distributed Bragg reflector layer 400, but also realizes the electrical isolation of the Mini-LED chip. The distributed Bragg reflector layer 400 has a first groove and a second groove. The first groove exposes the surface of the first layer of step, and the second groove exposes the surface of the second layer of step; then the electrode 500 is formed in the first groove and the second groove, thereby realizing the electrical lead-out.

[0107] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the structural embodiments, since they are basically similar to the method embodiments, they are described relatively simply, and the relevant parts can refer to the partial description of the method embodiments.

[0108] The above description is only a preferred embodiment of the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the protection of the technical solution of the present application.

Claims

1. A method for manufacturing a Mini-LED chip, characterized in that: include: Acquire a structure to be bonded, the structure to be bonded comprising an epitaxial structure layer and a bonding layer, the epitaxial structure layer comprising a first type layer, an active layer and a second type layer stacked in sequence, the bonding layer being located on a side surface of the second type layer away from the first type layer; Using a grinding process to remove a portion of the bonding layer thickness to obtain a bonding layer of a first target thickness; Bonding the structure to be bonded and the transparent substrate with the bonding layer having the first target thickness facing the transparent substrate; Etching the first type layer and the active layer and the bonding layer of the second target thickness located in the cutting road area to form a step structure, wherein the step structure includes a first step and a second step, the first step includes the first type layer and the active layer, the second step includes the second type layer and the bonding layer of the first target thickness, and the second target thickness is less than or equal to the first target thickness; forming a distributed Bragg reflection layer and an electrode; The transparent substrate exposed in the dicing line area is cut to form a plurality of sub-millimeter light emitting diode Mini-LED chips.

2. The method according to claim 1, characterized in that The etching of the first type layer, the active layer, and the bonding layer of the second target thickness located in the cutting road area to form a step structure includes: The first type layer and the active layer located in the chip area are etched by the same mesa etching process, and the bonding layer of the second target thickness located in the saw road area is etched to form a step structure.

3. The method according to claim 1, characterized in that The forming of the distributed Bragg reflection layer and the electrode comprises: Depositing material for a distributed Bragg reflector layer, and etching the material of the distributed Bragg reflector layer located in the step structure and in the cutting road area to form a first groove, a second groove, and a distributed Bragg reflector layer, wherein the distributed Bragg reflector layer covers the sidewall of the step structure, the first groove exposes a surface of a first step, and the second groove exposes a surface of a second step; Electrodes are formed in the first groove and the second groove.

4. The method according to claim 1, characterized in that: The cutting of the transparent substrate exposed in the scribe line area comprises: Cutting the transparent substrate exposed in the cutting path area by laser surface cutting; The transparent substrate exposed in the scribe line area is continuously cut by laser stealth cutting.

5. The method according to claim 4, characterized in that The first target thickness is less than or equal to 2 micrometers.

6. The method according to claim 1, characterized in that The method of removing a portion of the bonding layer by a grinding process to obtain a bonding layer of a first target thickness includes: A chemical mechanical polishing process is used to remove a portion of the thickness of the bonding layer, reduce the roughness of the surface of the bonding layer, and obtain a bonding layer of a first target thickness.

7. The method according to claim 1, characterized in that The transparent substrate is a sapphire substrate.

8. The method according to claim 2, characterized in that: The obtaining of the structure to be bonded comprises: forming an epitaxial structure layer on a temporary substrate; forming a bonding layer on a surface of the epitaxial structure layer away from the temporary substrate to obtain a structure to be bonded; Before etching the second type layer and the active layer and the bonding layer of the second target thickness located in the scribe line area, the method further includes: The temporary substrate is removed.

9. A Mini-LED chip, characterized in that: include: A transparent substrate and a bonding layer located on one side of the transparent substrate; An epitaxial structure layer is arranged on a surface of the bonding layer away from the transparent substrate, and the epitaxial structure layer includes a second type layer, an active layer and a first type layer stacked in sequence; the bonding layer and the epitaxial structure layer form a step structure, and the step structure includes a first step layer and a second step layer, the first step layer includes the first type layer and the active layer, and the second step layer includes the second type layer and the bonding layer of the first target thickness; The distributed Bragg reflector covers the surface of the step structure and the sidewall of the step structure, and the distributed Bragg reflector includes a first groove and a second groove, wherein the first groove exposes the surface of the first step and the second groove exposes the surface of the second step; Electrodes are disposed in the first groove and the second groove.

10. The Mini-LED chip according to claim 9, characterized in that: The first target thickness is less than or equal to 2 micrometers.

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