Connecting a chip to an interposer die and package interface using spacer interconnects coupled to a portion of the chip

Abstract

The invention discloses a semiconductor package assembly. The semiconductor package assembly comprises a package interface. An interposer die has a first surface and a second surface opposite the first surface, wherein the first surface of the interposer die is a die positioned on the package interface. The interposer die includes a plurality of electrically conductive connectors between the first surface and the second surface. The chiplet includes a connectivity region having a conductive path, where a first portion of the connectivity region is coupled to a conductive connection of the interposer die, and a second portion of the connectivity region cantilevered from the interposer die.

Description

BACKGROUND OF THE INVENTION

[0001] An increasing number of components are interconnected in semiconductor components. To connect different components, some semiconductor components include conductive traces parallel to a substrate, to which the components are coupled. In some variations, such conductive traces are located above the surface of the substrate itself. While this elevation of the conductive traces above the substrate simplifies manufacturing, the use of such elevated conductive traces impedes power delivery to portions of a system-on-chip or die coupled to the elevated conductive traces. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 is a cross-sectional view of a semiconductor component including dies, according to some embodiments, the dies being coupled to a portion of an interposer die and to spacer interconnects.

[0003] Figure 2 is a cross-sectional view of another semiconductor component including dies, according to some embodiments, the dies being coupled to an interposer die and to spacer interconnects.

[0004] Figure 3 is a comparison of cross-sections of configurations for coupling dies to an interposer die, according to some embodiments.

[0005] Figure 4 is a cross-sectional view of an exemplary integrated circuit device including dies, according to some embodiments, the dies being coupled to a portion of an interposer die and to spacer interconnects.

[0006] Figure 5 is an exemplary computing device, according to some embodiments.

[0007] Figure 6 is a flow chart illustrating an exemplary method for manufacturing an integrated circuit device including dies, according to some embodiments, the dies being coupled to a portion of an interposer die and to spacer interconnects. DETAILED DESCRIPTION

[0008] As semiconductor technology has further advanced, stacked semiconductor devices (e.g., three-dimensional integrated circuits (3DICs)) have emerged as an effective alternative for further reducing the physical size of semiconductor devices. In a stacked semiconductor device, active circuits (such as logic circuits, memory circuits, processor circuits, etc.) are fabricated on different semiconductor dies. Two or more semiconductor dies can be mounted or stacked on top of each other to further reduce the form factor of the semiconductor device. To provide certain types of functionality, a stacked semiconductor device includes one or more function-specific dies. For example, a stacked semiconductor device includes input / output dies to provide input signals to and output signals from the stacked semiconductor device.

[0009] Various types of function-specific dies receive signals from the package interface of the stacked semiconductor device. This prevents those function-specific dies from being stacked on top of another die because such stacking would involve including through-silicon vias in the other die to allow such function-specific dies to receive signals from the package interface of the stacked semiconductor device. Such through-silicon vias would adversely affect the active portion of the die on which the function-specific die is stacked. Similarly, including the functionality of a function-specific die in a die on which another die is stacked would lead to through-silicon vias in a portion of the die that performs the functionality of the function-specific die to allow the die to communicate with the other die, thereby preventing the execution of the functionality of the function-specific die. Conventional methods place the function-specific die side by side with another die, which increases the overall area of the stacked semiconductor device and, by increasing the distance between the function-specific die and the other die, increases the latency for the function-specific die to communicate with other dies.

[0010] To reduce the overall area of the stacked semiconductor device while reducing the latency for a die coupled to an interposer die to communicate with other dies, this specification describes coupling a portion of a die to a first surface of an interposer die. The first surface of the interposer die is opposite a second surface of the interposer die positioned on a package substrate. This lifts the die above the package substrate and causes a portion of the die to cantilever out from the interposer die. To support the cantilevered portion of the die, spacer interconnects are positioned between the die and the package substrate. Such a configuration reduces the overall area of the semiconductor device by repositioning the die from adjacent to the interposer die to partially overlapping the interposer die. Additionally, the above configuration allows the die to receive signals or power via the spacer interconnects rather than from through-silicon vias formed in the interposer die.

[0011] To this end, this specification describes various embodiments of a semiconductor package assembly, which includes: a package interface and an interposer die having a first surface and a second surface opposite the first surface, wherein the first surface of the interposer die is positioned on the package interface, and the interposer die includes a plurality of conductive connections between the first surface and the second surface. The semiconductor package assembly further includes a die, the die includes a connectivity region having a conductive path, wherein a first portion of the connectivity region is coupled to the conductive connections of the interposer die, and a second portion of the connectivity region is not coupled to the interposer die. In various embodiments, the first portion of the connectivity region of the die is configured to communicate with the interposer die, and the second portion of the connectivity region of the die is configured to communicate with the package substrate.

[0012] In some embodiments, the semiconductor package assembly further includes a spacer interconnect of a spacer device disposed between the second portion of the connectivity region of the die and the package interface, wherein the spacer device includes spacer conductive connections that couple the conductive path of the second portion of the connectivity region to one or more connections within the package interface. In various embodiments, the spacer interconnect includes a passive die. In some embodiments, the diameter of the spacer conductive connections is different from the diameter of the connectors included in the package interface. In some embodiments, the diameter of the spacer conductive connections is less than the diameter of the connectors included in the package interface. In some embodiments, a plurality of spacer conductive connections are coupled to the connectors included in the package interface. In various embodiments, the diameter of the spacer conductive connections is equal to the diameter of the connectors included in the package interface. In some embodiments, the spacer interconnect includes a molding compound that fills the distance between the second portion of the connectivity region of the die and the surface of the package interface, and fills the regions between and around one or more other dies included in the semiconductor package assembly. In some embodiments, the spacer interconnect has a thickness based on the distance between the second portion of the connectivity region of the die and the surface of the package interface.

[0013] In some embodiments, the interposer die includes an active interposer die. In various embodiments, the die is configured to perform one or more input / output functions.

[0014] This specification also describes a method that includes coupling a first portion of a connectivity region of a dielet to a conductive connection of an interposer die, a second surface of the interposer die, the conductive connection being between the second surface and a first surface of the interposer die, the connectivity region having one or more conductive paths, and a second portion of the connectivity region cantilevering out from the interposer die. In some embodiments, the method also couples a spacer interconnect to the second portion of the connectivity region of the dielet and to a package interface that is coupled to the first surface of the interposer die, the spacer interconnect including one or more conductive paths of the conductive paths that are coupled to the second portion of the connectivity region and one or more spacer conductive connections to a connector within the package interface to which the interposer die is coupled. In some embodiments, the spacer interconnect includes a passive die. In some embodiments, a diameter of the spacer conductive connection is less than a diameter of a connector included in the package interface. In some embodiments, a plurality of spacer conductive connections are coupled to the connector included in the package interface. In various embodiments, the diameter of the spacer conductive connection is equal to the diameter of the connector included in the package interface. In various embodiments, the spacer interconnect has a thickness based on a distance between the second portion of the connectivity region of the dielet and a surface of the package interface. In some embodiments, the interposer die is an active interposer die.

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description includes embodiments in which the first and second features are formed in direct contact, and includes embodiments in which additional features are formed between the first and second features such that the first and second features are in direct contact. Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," "front," "back," "top," "bottom," etc., are used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Similarly, terms such as "front surface" and "rear surface" or "top surface" and "bottom surface" are used herein to more readily identify various components and to identify those components, for example, as being on opposite sides of another component. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

[0016] Figure 1is a cross-sectional view of a semiconductor assembly including a die 100 coupled to an interposer die 105 and a spacer interconnect 120. In various embodiments, die 100 implements one or more specific functions of a system-on-chip (SoC). For example, die 100 performs one or more input / output functions of the SoC, allowing communication between one or more other dies in the semiconductor assembly and components external to the semiconductor assembly. In other embodiments, die 100 performs one or more direct memory access (DMA) functions for the semiconductor assembly, performs one or more address translation functions for the semiconductor assembly, performs one or more input-output memory management functions for the semiconductor assembly, performs one or more security functions for the semiconductor assembly, or performs one or more compression functions for the semiconductor assembly. However, in other embodiments, die 100 performs any suitable function or combination of functions for the semiconductor assembly.

[0017] Interposer die 105 receives power or other signals and routes the power to other components of the semiconductor assembly, such as other dies or dies included in the semiconductor assembly. Interposer die 105 has a first surface 104 and a second surface 106 opposite and parallel to the first surface 104, with a plurality of conductive connectors 107 therebetween. In some embodiments, interposer die 105 is an active interposer that includes logic for routing signals, power, etc. received by interposer die 105 to one or more conductive paths. Such routing logic allows interposer die 105 to direct signals, power, etc. received by interposer die 105 to other components. In some embodiments, the first surface 104 of interposer die 105 is the front surface of interposer die 105, and the second surface 106 of interposer die 105 is the back surface of interposer die 105. Alternatively, in other embodiments, the first surface 104 of interposer die 105 is the back surface of interposer die 105, and the second surface 106 of interposer die 105 is the front surface of interposer die 105.

[0018] In various embodiments, interposer die 105 receives power and ground through a package interface 110, at Figure 1In the specific implementation shown, the package interface also couples the interposer die 105 to a substrate (not shown). In various specific implementations, the package interface 110 includes connectors 140, such as copper pillars, solder bumps (e.g., C4 bumps), or other types of package interconnects. One or more of the connectors 140 are coupled to the conductive connections 107 of the interposer die 105, allowing the interposer die 105 to be coupled to components external to the semiconductor assembly through the connectors 140 and conductive connections 107 of the interposer die 105. In various specific implementations, one or more of the connectors 140 are coupled to a power source and to the conductive connections 107 of the interposer die 105, allowing the interposer die 107 to receive power from the power source.

[0019] Additionally, the interposer die 105 includes one or more connection layers 135. In some examples, the connection layer 135 includes a metallization layer and an interlayer dielectric material layer, as well as conductive structures such as vias, traces, and pads. In these examples, one or more of the connection layers 135 form connections between circuit components formed in the die substrate to implement the functional circuit blocks of the interposer die 105. For example, one or more of the connection layers 135 implement a die-level redistribution layer structure formed during the die manufacturing process, such as a back-end-of-line (BEOL) structure. In another example, one or more of the connection layers 135 are implemented with bond pads or bond pad vias. In other examples, one or more of the connection layers 135 are redistribution layers (RDLs) included in the interposer die 105. In other examples, one or more of the connection layers 135 are implemented with more than one structure (e.g., BEOL and bond pad vias). During the manufacturing process, the interconnects can be formed with a very fine line / space pitch of less than 1 μm, allowing for high-density connections. In these examples, one or more of the connection layers also include bond sites to which metal connectors (e.g., die pads, micro-bumps, controlled collapse chip connection (C4) bumps) can be attached during the manufacturing process or during a post-manufacturing process such as die packaging. In various specific implementations, one or more of the connection layers 135 in the connection layer 135 are coupled to one or more of the conductive connections in the conductive connections 107 of the interposer die 105. Coupling the conductive connections 107 of the interposer die 105 to the connection layer 135 allows the interposer die 105 to distribute signals or power received via the conductive connections 107 to other components of the semiconductor assembly through the connection layer 135 of the interposer die 105. For illustrative purposes, Figure 1 one or more of the connection layers 135 closest to the second surface 106 of the interposer die 105 are shown, while the interposer die 105 includes one or more connection layers near the first surface 104 of the interposer die 105, which include bond sites to which metal connectors (e.g., die pads, micro-bumps, controlled collapse chip connection (C4) bumps) can be attached in various specific implementations.

[0020] In Figure 1 the example shown, a first portion of the die 100 is positioned on a portion of a second surface 106 of the interposer die 105. In various embodiments, a first portion of a first surface of the die 100 is coupled to a portion of the second surface 106 of the interposer die 105. In various embodiments, the first surface of the die 100 is closest to the package interface 110. The die 100 includes a connectivity region 115 proximate to the first surface of the die 100. The connectivity region 115 includes conductive paths generally parallel to the second surface 106 of the interposer die 105. In various embodiments, the conductive paths include metallization layers and interlayer dielectric material layers, as well as conductive structures such as vias, traces, and pads. In some examples, as Figure 1 shown, by various bonding techniques such as hybrid bonding, thermocompression bonding, solder reflow, and other techniques, a first portion of the die 100 is face-to-back (F2B) bonded to a portion of the second surface 106 of the interposer die 105. However, it is also contemplated that the die 100 can be face-to-face (F2F) bonded to the interposer die 105 by various bonding techniques (such as hybrid bonding, thermocompression bonding, solder reflow, and other techniques).

[0021] A first portion of the connectivity region 115 within the first portion of the die 100 is coupled to one or more conductive connectors 107 of the interposer die 105. However, a second portion of the connectivity region 115 is not coupled to the die 100. Thus, the second portion of the connectivity region 115 extends cantilevered from the die 100 and is located above the surface of the package interface 110. In some embodiments, one or more conductive connectors 107 of the interposer die 105 are directly coupled to one or more conductive paths of the first portion of the connectivity region 115. In other embodiments, one or more conductive paths of the first portion of the connectivity region 115 are coupled to one or more connection layers 135 of the interposer die 105, where one or more connection layers 135 are coupled to one or more conductive connectors 107 of the interposer die 105. For example, a first portion of the connectivity region 115 within the first portion of the die 100 is coupled to one or more conductive connectors 107 through the second surface 106 of the interposer die 105. As Figure 1 shown, the conductive connectors 107 of the interposer die 105 provide a connection from one or more connection layers 135 of the interposer die 105, or from the second surface 106 of the die, to the first surface 104 of the interposer die 105. Thus, the conductive connectors 107 provide signals (as well as power and ground) on one surface of the interposer die 105 to the opposite surface of the interposer die 105 for interconnection with another component. In Figure 1In the example shown, the second surface 106 of the interpolator die 105 includes one or more connection layers 135, the one or more connection layers including a metallization layer or multiple metallization layers and dielectric layers formed on the second surface 106 of the die for connecting the conductive connectors 107 to another component. In various embodiments, the conductive connectors 107 are die vias. In some examples, the conductive connectors 107 are fabricated before the device layers (transistors, capacitors, resistors, etc.) are patterned onto the interpolator die 105. In some examples, the conductive connectors 107 are fabricated after the respective devices are patterned but before one or more connection layers are formed on the interpolator die 105. In some examples, the conductive connectors 107 are fabricated after (or during) the fabrication of one or more connection layers. After formation, the conductive connectors 107 may be selectively filled or plated with a conductive material (e.g., copper) to form interconnects. In some examples, the diameter of the conductive connectors 107 is less than 10 μm. In some examples, the conductive connectors 107 are buried such that the body of the substrate will be ground or etched away to expose the conductive connectors 107. The conductive connectors 107 provide high-density, short-channel, wide interconnects that can be used for die partitioning and die stacking. In some embodiments, one or more of the conductive connections in the conductive connectors 107 are coupled to one or more of the connection layers 135 of the interpolator die 105.

[0022] As Figure 1As shown, the spacer interconnect 120 is placed between the second portion of the first surface of the die 100 and the package interface 110, and this second portion includes the second portion of the connectivity region 115 of the die 100. In some embodiments, the spacer interconnect 120 is a passive die, while in other embodiments. In various embodiments, the passive die includes silicon that does not include active components, but includes spacer conductive connectors 125 described further below. In another embodiment, the spacer interconnect 120 is a dielectric material. In other embodiments, the spacer interconnect 120 is a die that includes one or more active components. In various embodiments, the spacer interconnect 120 is coupled to the end 130 of the first surface of the die 100, and this end is opposite to the end of the die 100 to which the interposer die 105 is coupled. For example, the spacer interconnect 120 is coupled to the second portion of the connectivity region 115 of the die 100. Additionally, the spacer interconnect 120 includes spacer conductive connectors 125 that couple one or more conductive paths of the connectivity region 115 within the second portion of the die 100 to one or more connectors 140 within the package interface 110. For example, one or more of the spacer conductive connectors 125 of the spacer interconnect 120 are coupled to one or more connectors 140 within the package interface 110 and to one or more of the conductive paths of the connectivity region 115 of the second portion of the die 100. In various embodiments, the spacer conductive connectors 125 of the spacer interconnect 120 are vias within the spacer interconnect 120, such as through-silicon vias within the spacer interconnect 120. In some embodiments, the vias are selectively filled or plated with a conductive material (e.g., copper) to form the interconnects.

[0023] The spacer conductive connectors 125 extend through the thickness 145 of the spacer interconnect 120. The thickness 145 of the spacer interconnect 120 is based on the vertical distance between the first surface of the die 100 and the surface of the package interface 110. Thus, the spacer conductive connectors 125 allow the die 100 to be coupled to the connectors 140 included in the package interface 110 for coupling components external to the semiconductor component to components within the semiconductor component. Additionally, the spacer interconnect 120 offsets the height difference between the surface of the package interface 110 and the first surface of the die 100. In Figure 1In the example shown, the thickness 145 of the spacer interconnect 120 is based on the distance between the first surface of the die 100 and the upper surface of the package interface 110. For example, the spacer interconnect 120 has a thickness 145 equal to the distance between the topmost surface of the package interface 110 parallel to the die 100 and the first surface of the die 100. As another example, the spacer interconnect 120 has a thickness 145 within a threshold amount of the distance between the topmost surface of the package interface 110 parallel to the first surface of the die 100 and the first surface of the die 100. Thus, the thickness 145 of the spacer interconnect 120 can be customized for different embodiments to address different distances between the first surface of the die 100 and the surface of the package interface 110 of the semiconductor component.

[0024] In different embodiments, the diameter of the spacer conductive connectors 125 included in the spacer interconnect 120 is different from the diameter of the conductive connectors 107 within the interposer die 105. In some embodiments, the spacer conductive connectors 125 in the spacer interconnect 120 have a diameter less than the diameter of the connectors 140 in the package interface 110, such that multiple spacer conductive connectors 125 are grouped together to reduce the impedance of delivering signals from the connectors 140 of the package interface 110 to the die 100. For example, for a manufacturing method for forming a semiconductor component, the spacer conductive connectors 125 have a minimum diameter. In other embodiments, the diameter of the spacer conductive connectors 125 is determined based on the diameter of the connectors 140 of the package interface 110. As an example, the diameter of the spacer conductive connectors 210 is equal to the diameter of the connectors of the package interface 110. In another example, the diameter of the spacer conductive connectors 125 is within a threshold amount of the diameter of the connectors 140 of the package interface 110, resulting in relatively wide spacer conductive connectors 125 that increase resilience to long-term wear related to electromigration.

[0025] One or more of the spacer conductive connectors 125 in the spacer interconnect 120 are coupled to one or more of the connectors 140 of the package interface 110. This electrically couples one or more of the spacer conductive connectors 125 to components external to the semiconductor component via one or more of the connectors 140 of the package interface 110. Thus, the spacer conductive connectors 125 and the connectors 140 of the package interface 110 allow the die 100 to be coupled to one or more components external to the semiconductor component that includes the die 100.

[0026] As Figure 1As shown, compared to techniques where the die 100 and the interposer die 105 are adjacent to each other in a common plane, positioning a first portion of the die 100 on a portion of the second surface of the interposer die 105 reduces the overall area of the semiconductor component. Positioning the spacer interconnect 120 between a second portion of the die 100 and the package interface 110 also simplifies providing power or other signals from the package interface 110 to the die 100. Additionally, this configuration prevents vias from penetrating the die 100 while keeping a majority of the first surface of the die 100 exposed for connection to the connector 140 within the package interface 110. Further, positioning the first portion of the die 100 on the second surface 106 of the interposer die 105 raises the die 100 above the package interface 110, thereby reducing the overall semiconductor component size and allowing for an increase in the yield of semiconductor components per wafer.

[0027] Figure 2 is a cross-sectional view of a semiconductor component including the die 100, which is coupled to the interposer die 105 and the spacer interconnect. In Figure 2 the example shown, additional die 200 are stacked on top of the interposer die 105. In various embodiments, the additional die 200 are coupled to one or more connection layers 135 closest to the second surface 106 of the interposer die 105. The additional die 200 implement one or more additional component functions of a system-on-chip (SoC). For example, the interposer die 105 is an active interposer die configured to direct signals or power to other components of the semiconductor component, such as to the additional die 200, while the additional die 200 perform one or more computing functions of the semiconductor component.

[0028] As described above in connection with Figure 1 further, a first portion of the die 100 is positioned on a portion of the second surface of the interposer die 105. In various embodiments, a first portion of the first surface of the die 100 is positioned on this portion of the second surface 106 of the interposer die 105. In Figure 2 the example shown, when manufacturing the semiconductor component, molding compound 205 (or other material) is used to fill the regions between different dies or components included in the semiconductor component. As Figure 2 shown, a portion 207 of the molding compound 205 fills the region between the package interface 110 and the first surface of the die 100. Additionally, other portions of the molding compound 205 fill the regions between the dies or other components of the semiconductor component. In Figure 2In the example shown, the molding compound 205 fills the region between the die 100 and the additional die 200, as well as the regions surrounding the additional die 200 and the regions surrounding the interposer die 105. Thus, the portion 207 of the molding compound 205 between the first surface of the die 100 and the package interface 110 is used as Figure 2 the spacer interconnect 120 in

[0029] One or more of the spacer conductive connections in the spacer conductive connector 210 are coupled to one or more of the connectors 140 of the package interface 110. This electrically couples one or more of the spacer conductive connectors 210 to components external to the semiconductor component through one or more of the connectors 140 of the package interface 110. Thus, the spacer conductive connectors 210 and the connectors 140 of the package interface 110 allow the die 100 to be coupled to one or more components external to the semiconductor component including the die 100.

[0030] Thus, in Figure 2 the example of, the spacer interconnect 120 includes the molding compound 205, wherein the spacer conductive connector 210 is included in the molding compound 205 to couple one or more paths of the connectivity region 115 of the die 100 to one or more of the connectors 140 within the package interface. Thus, one or more of the spacer conductive connectors 210 of the spacer interconnect 120 are coupled to one or more conductive paths of the connectivity region 115 of the die 100 and to one or more of the connectors 140 of the package interface 110. In various embodiments, when the molding compound 205 is used as the spacer interconnect 120, the spacer conductive connector 210 of the spacer interconnect 120 is a molded through hole in the molding compound 205. In some embodiments, the molded through hole is selectively filled or plated with a conductive material (e.g., copper) to form the interconnect.

[0031] Figure 1 and Figure 2 show different embodiments for forming the spacer interconnect 120, which is used to fill the region between the package interface 110 and the first surface of the die 100. In Figure 1 the example of, the spacer interconnect 120 can be independently constructed and included in the semiconductor component. In Figure 2 the example of, the spacer interconnect 120 is formed during the assembly of the semiconductor component by constructing molded through holes for the spacer conductive connectors 210 of the spacer interconnect 120 during the manufacture of the semiconductor component.

[0032] Figure 3 is a comparison of cross-sections of configurations for coupling the die 100 to the interposer die 105. For illustrative purposes, Figure 3Shows a conventional configuration 300, where the die 100 and the interposer die 105 are positioned side by side. In the conventional configuration 300, the function - specific die is coupled to the interposer die 105 through the interconnect die 305. Thus, in the conventional configuration 300, the die 100 and the interposer die 105 are side by side in a common plane, where the interconnect die 305 is coupled to the first surface of the die 100 and coupled to the first surface of the interposer die 105. For example, in the conventional configuration 300, the first surface 105 of the interposer die 105 and the first surface of the die 100 are in a common plane, and portions of both are coupled to the interconnect die 305. A portion of the interconnect die 305 is coupled to a portion of the first surface of the die 100 and coupled to a portion of the first surface of the interposer die 105.

[0033] In contrast, configuration 310 couples the die 100 to the interposer die 105, as described above in connection with Figure 1 and Figure 2 and further described. In configuration 210, the first portion of the die 100 is coupled to the interposer die 105, as described above in connection with Figure 1 and Figure 2 and further described. For example, the first portion of the first surface of the die 100 is coupled to a portion of the second surface 106 of the interposer die 105, where the second surface 106 of the interposer die 106 is opposite the first surface 104 and closest to the package interface (not shown). In configuration 310, the spacer interconnect 120, described above in connection with Figure 1 and Figure 2 and further described, is coupled to the first surface of the die 100. As described above in connection with Figure 1 and Figure 2 and further described, the spacer interconnect 120 offsets the height difference between the first surface of the die 100 coupled to the second surface of the interposer die 105 and the plane including the first surface of the interposer die 105.

[0034] As Figure 3 shown, coupling the first portion of the die 100 to the interposer die 105 in configuration 310, rather than positioning the die 100 and the interposer die 105 side by side in configuration 300, reduces the total width of the combination of the interposer die 105 and the die 100. In Figure 3 , relative to configuration 300, configuration 310 reduces the width of the combination of the interposer die 105 and the die 100 by the distance 315. As Figure 3As shown, by coupling a first portion of a first surface of die 100 to a portion of a second surface 106 of interposer die 105, configuration 300 shortens the area used to couple die 100 to interposer die 105 relative to a conventional configuration 300 in which interposer die 105 and die 100 are positioned adjacent to each other and coupled together via interconnect die 305 at a distance 315.

[0035] Figure 4 FIG. 4 is a cross-sectional view of an exemplary integrated circuit device 400 including die 100 in accordance with some embodiments of the present disclosure, the die being coupled to interposer die 105 and to spacer interconnects 120. The exemplary integrated circuit device 400 may be implemented in various computing devices, including mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, smart phones, etc. (as Figure 6 shown). Figure 4 The exemplary integrated circuit device 400 of FIG. 4 includes a semiconductor assembly 405 that includes die 100 and interposer die 105, as further described above in connection with Figures 1 to 3 FIG. 4. Interposer die 105 has a first surface 104 and a second surface 106 that is parallel and opposite to the first surface 104. A first portion of die 100 is coupled to interposer die 105. In various embodiments, a first portion of a first surface of die 100 is coupled to a portion of a second surface 106 of interposer die 105. Spacer interconnects 120 are coupled to a second portion of a first surface of die 100. In some embodiments, spacer interconnects 120 are silicon, while in other embodiments, spacer interconnects 120 are a dielectric material. In various embodiments, spacer interconnects 120 are coupled to an end of a first surface of die 100 that is opposite the end of die 100 to which interposer die 105 is coupled. Additionally, spacer interconnects 120 include conductive connectors 125 that are generally perpendicular to the connectivity region 115 of die 100.

[0036] As an example, semiconductor assembly 405 includes one or more processors 505 of a computing device 500 as Figure 5 shown in FIG. 5. Computing device 500 is implemented, for example, as a desktop computer, laptop computer, server, gaming machine, smart phone, tablet computer, etc. In addition to one or more processors 505, computing device 500 further includes a memory 510. Memory 510 includes random access memory (RAM) or other volatile memory. Memory 510 further includes non-volatile memory, such as disk memory, solid state memory, etc.

[0037] In some specific implementations, the computing device 500 further includes one or more network interfaces 515. In some specific implementations, the network interface 515 includes a wired network interface 515, such as Ethernet or another wired network connection as may be understood. In some specific implementations, the network interface 515 includes a wireless network interface 515, such as WiFi, cellular or other wireless network interfaces 515 as may be understood. In some specific implementations, the computing device 500 includes one or more input devices 520 that accept user input. Exemplary input devices 520 include keyboards, touchpads, touchscreen interfaces, etc. Those skilled in the art should understand that in some specific implementations, the input device 520 includes peripheral devices such as external keyboards, mice, etc.

[0038] In some specific implementations, the computing device 500 includes a display 525. In some specific implementations, the display 525 includes an external display connected via a video or display port. In some specific implementations, the display 525 is disposed within the housing of the computing device 500. For example, the display 525 includes the screen of a tablet computer, laptop, smartphone, or other mobile device. In a specific implementation where the display 525 includes a touchscreen, the display 525 also serves as the input device 520.

[0039] The semiconductor component 405 is coupled to the substrate 410. The substrate 410 is a part of the material that mechanically supports the coupled components, such as the semiconductor component 405. In some specific implementations, the substrate 410 also electrically couples various components mounted to the substrate 410 via conductive traces, tracks, pads, etc. For example, the substrate 410 electrically couples the components of the semiconductor component 405 to one or more other components via connection traces and solder joints formed by solder balls coupled to conductive pads, such as through the connector 140 in the package interface 110 of the semiconductor component 405. In various specific implementations, one or more spacer conductive connectors in the spacer conductive connectors 125 are coupled to the connector 140 to connect the die 100 to one or more components external to the semiconductor component 405.

[0040] In some specific implementations, the substrate 410 includes a printed circuit board (PCB), while in other specific implementations, the substrate 410 is another semiconductor device, such as the semiconductor component 405 (which may include active components). In some specific implementations, the connector 140 that couples the semiconductor component 405 to the substrate 410 is included in a socket (not shown), where the semiconductor component 405 is soldered or otherwise mounted in the socket. In other specific implementations, such as Figure 4As shown, a connector 140 that directly couples to the package interface 110 of the direct-coupled semiconductor component 405 is directly coupled to the substrate 410 via a direct solder connection or other connection as may be understood. In some specific embodiments, the semiconductor component 405 is coupled to the substrate 410 using a land grid array (LGA), a pin grid array (PGA), or other packaging technology as may be understood.

[0041] For further explanation, Figure 6 A flowchart illustrating an exemplary method for fabricating a die 100 that is coupled to an interposer die 105 and coupled to a spacer interconnect 120 is presented. Figure 6 The method shown includes coupling 605 a first portion of the connectivity region 115 of the die 100 to one or more conductive connectors 107 on a second surface of the interposer die 105, the second surface being opposite and parallel to the first surface of the interposer die 105. A second portion of the connectivity region 115 of the die 100 extends cantilevered from the interposer die 105. Thus, the first portion of the connectivity region 115 of the die is coupled to the conductive connector 107 of the die, while the second portion of the connectivity region 115 is not coupled to the interposer die 105, resulting in a portion of the die 100 other than the first portion of the connectivity region 115 being suspended above the interposer die 105. One or more conductive connectors 107 are interposed between the first surface and the second surface of the interposer die 105. The connectivity region 115 includes at least one conductive path coupled to at least one conductive connector 107, as further described above in connection with Figure 1 As described. In some specific embodiments, the die is configured to perform one or more input / output functions. Additionally, in some specific embodiments, the interposer die 105 is an active interposer die.

[0042] In some specific implementations, the method further includes a coupling 610 that couples the spacer interconnect 120 to a second portion of the connectivity region 115 of the die 100. The spacer interconnect 120 is coupled to the package interface 110 that is opposite the second portion of the connectivity region 115. Thus, the spacer interconnect 120 fills the distance between the second portion of the connectivity region 115 and the package interface 110, and the connectivity region projects cantilevered from the interposer die 105. The spacer interconnect 120 includes one or more spacer conductive connectors 125 that are coupled to one or more conductive paths of the connectivity region 115 within the second portion of the connectivity region 115 of the die 100. The one or more spacer conductive connectors 125 are also coupled to the connectors 140 included in the package interface 110. In various specific implementations, the spacer interconnect 120 is a passive die (i.e., a die that does not include any active components). In other specific implementations, the spacer interconnect 120 is a molding compound that fills the distance between the first surface of the die and the package interface. The molding compound also fills the regions between and around one or more other dies included in the semiconductor package assembly including the die 100 and the interposer die 105, as further described above in connection with Figure 2 as described. In some specific implementations, the spacer conductive connectors 125 are molded vias.

[0043] In various specific implementations, the diameter of the spacer conductive connectors 125 is equal to the diameter of the connectors 140 included in the package interface 110. In other specific implementations, the diameter of the spacer conductive connectors 125 is less than the diameter of the connectors 140 included in the package interface 110. If the diameter of the spacer conductive connectors 125 is less than the diameter of the connectors 140 included in the package interface 110, then a plurality of spacer conductive connectors 125 are coupled to the connectors 140 included in the package interface 110. In various specific implementations, the spacer interconnect 120 has a thickness based on the distance between the first surface of the die 100 including the connectivity region 115 and the surface of the package interface 110, and this thickness determines the thickness of the spacer interconnect 120.

[0044] In view of the explanations set forth above, the reader will recognize that fabricating a semiconductor assembly that includes a die coupled to an interconnect die, which is coupled to a spacer interconnect, allows the die to be coupled to another component having a different height than the die, or to another component having different temperature constraints than the die. Additionally, when the semiconductor assembly is a stacked semiconductor assembly, including the interconnect die during the fabrication of the semiconductor assembly simplifies the connection of the die to other components by coupling the die to the interconnect die that is coupled to the spacer interconnect. Further, coupling a second surface of the die to the interconnect die that is coupled to the spacer interconnect allows the first surface of the die to remain unobstructed, thus simplifying the delivery of power, ground, or other signals to the first surface of the die.

[0045] It will be understood from the foregoing description that modifications and variations can be made in the various specific embodiments of the present disclosure. The description in this specification is for illustrative purposes only and should not be construed in a limiting sense. The scope of the present disclosure is defined only by the language of the appended claims.

Claims

1. A semiconductor package assembly, the semiconductor package assembly comprising: a package interface; an interposer die having a first surface and a second surface opposite the first surface, the first surface of the interposer die being positioned on the package interface, the interposer die including a plurality of conductive connections between the first surface and the second surface; and a dielet, the dielet including a connectivity region having a conductive path, wherein a first portion of the connectivity region is coupled to the conductive connection of the interposer die, and a second portion of the connectivity region extends cantilevered from the interposer die.

2. The semiconductor package assembly according to claim 1, the semiconductor package assembly further comprising: a spacer interconnect placed between the second portion of the connectivity region of the dielet and the package interface, the spacer interconnect including spacer conductive connections coupling the conductive path of the second portion of the connectivity region to one or more connections within the package interface.

3. The semiconductor package assembly according to claim 2, wherein the spacer interconnect includes a passive die.

4. The semiconductor package assembly according to claim 2, wherein the diameter of the spacer conductive connection is different from the diameter of a connector included in the package interface.

5. The semiconductor package assembly according to claim 4, wherein the diameter of the spacer conductive connection is less than the diameter of the connector included in the package interface.

6. The semiconductor package assembly according to claim 5, wherein a plurality of spacer conductive connections are coupled to the connector included in the package interface.

7. The semiconductor package assembly according to claim 2, wherein the diameter of the spacer conductive connection is equal to the diameter of a connector included in the package interface.

8. The semiconductor package assembly according to claim 2, wherein the spacer interconnect includes a molding compound that fills the distance between the second portion of the connectivity region and the surface of the package interface, and fills the regions between and around one or more other dielets included in the semiconductor package assembly.

9. The semiconductor package assembly according to claim 2, wherein the spacer interconnect has a thickness based on the distance between the second portion of the connectivity region of the dielet and the surface of the package interface.

10. The semiconductor package assembly according to claim 1, wherein the interposer die includes an active interposer die.

11. The semiconductor package assembly according to claim 1, wherein the dielet is configured to perform one or more input / output functions.

12. The semiconductor package assembly according to claim 1, wherein the first portion of the connectivity region of the dielet is configured to communicate with the interposer die, and the second portion of the connectivity region of the dielet is configured to communicate with a package substrate to which the interposer die is coupled.

13. A method, the method comprising: Couple a first portion of a connectivity region of the dielet to a conductive interconnect of the interposer die, the second surface of the interposer die, the conductive interconnect being between the second surface and the first surface of the interposer die, the connectivity region having one or more conductive paths, and a second portion of the connectivity region extending cantilevered from the interposer die.

14. The method of claim 13, the method further comprising: Couple a spacer interconnect to the second portion of the connectivity region of the dielet and to a package interface, the package interface being coupled to the first surface of the interposer die, the spacer interconnect including one or more of the conductive paths of the conductive paths of the second portion of the connectivity region and one or more spacer conductive interconnects coupled to a connector within the package interface to which the interposer die is coupled.

15. The method of claim 14, wherein the spacer interconnect includes a passive die.

16. The method of claim 14, wherein the diameter of the spacer conductive interconnect is less than the diameter of the connector included in the package interface.

17. The method of claim 14, wherein a plurality of spacer conductive interconnects are coupled to the connector included in the package interface.

18. The method of claim 14, wherein the diameter of the spacer conductive interconnect is equal to the diameter of the connector included in the package interface.

19. The method of claim 14, wherein the spacer interconnect has a thickness based on the distance between the second portion of the connectivity region of the dielet and the surface of the package interface.

20. The method of claim 13, wherein the interposer die includes an active interposer die.

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