Override mechanism for PWM operation

Abstract

An apparatus (100) includes a pulse width modulation (PWM) generator circuit (102) to generate a generally complementary PWM signal (PWMH, PWML). The signal is used to prevent both of the two complementary switches receiving the complementary PWM signal from being activated simultaneously. The PWM signals are typically complementary with respect to their active portions. The apparatus includes an override circuit (104) to override at least one of the complementary PWM signals to generate an adjusted PWM signal (APWMH, APWML). When the adjusted PWM signal is received at the two complementary switches, the adjusted PWM signal is used to cause the two complementary switches to be simultaneously activated.

Description

[0001] Priority

[0002] This application claims priority to U.S. Provisional Patent No. 63 / 444,505, filed on February 9, 2023, the content of which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to pulse-width modulation (PWM) generation, and more particularly to an override mechanism for PWM operation in complementary mode. Background Art

[0004] Complementary-mode PWM signal generation is commonly used to operate circuits of transistors connected in series between a positive level and a negative level of a voltage rail. The most common transistor circuit configuration is two transistors connected in series (in a so-called half-bridge configuration). Thus, the PWM generators of control devices such as PWM controllers, microcontrollers, and switching regulators typically provide a pair of signal generator outputs, where one signal generator output provides a control signal for an upper transistor (PWMH) and a complementary signal output for a lower transistor (PWML). If all of the transistors connected in series in such a circuit are turned on simultaneously, this circuit configuration will short-circuit the voltage rails to which they are connected, resulting in an undesirable circuit condition such as a short circuit, which may cause severe damage to the circuit. Thus, complementary-mode PWM signal generation typically includes a protection circuit that prevents the PWM logic components from generating overlapping PWMH and PWML signals.

[0005] The inventors of examples of the present disclosure have found that such safety features used in complementary-mode PWM signal generation can limit certain applications, such as when complementary-mode PWM generation is needed to drive a transistor circuit configuration where the transistors do not directly connect a power supply rail to ground but are used to apply a voltage across a storage device such as an inductor or a capacitor. Thus, in these applications, overlapping PWMH or PWML control signals or control signals that simultaneously transition their respective signal levels (critical complementary mode) will not, therefore, imply a critical or unsafe operating condition, but can actually be used to ensure proper circuit functionality. Thus, the built-in protection against overlapping control signals limits the availability of protected complementary PWM generation.

[0006] Examples of the present disclosure can solve one or more of these problems. Brief Description of the Drawings

[0007] Figure 1A and Figure 1B are diagrams of an example apparatus for overriding PWM operation in complementary mode according to an example of the present disclosure.

[0008] Figure 2is a more detailed illustration of the operation of a PWM generator circuit according to an example of the present disclosure.

[0009] Figure 3 is a more detailed illustration of an apparatus for overriding PWM operation in complementary mode according to an example of the present disclosure.

[0010] Figure 4 is an illustration of an example application circuit to which an apparatus according to an example of the present disclosure may provide a PWM signal.

[0011] Figure 5 is an illustration of the operation of an example application circuit according to an example of the present disclosure.

[0012] Figure 6 is an illustration of an example application circuit to which an apparatus according to an example of the present disclosure may provide a PWM signal.

[0013] Figure 7 is an illustration of the operation of an example application circuit according to an example of the present disclosure.

[0014] Figure 8 is an illustration of the operation of an apparatus for providing an override signal to an example application circuit 600 according to an example of the present disclosure, where the apparatus 100 may provide a PWM signal to the example application circuit.

[0015] Figure 9 is an illustration of an example system for overriding PWM operation to generate generally complementary PWM signals according to an example of the present disclosure.

[0016] Figure 10A and Figure 10B is an illustration of an example method for overriding PWM operation in complementary mode according to an example of the present disclosure. DETAILED DESCRIPTION

[0017] The present disclosure includes for selectively allowing or preventing the generation of overlapping complementary PWM output signals without inadvertently compromising the security of the generation of non - overlapping signals in a common complementary mode or interfering with the proper functioning of overlapping or critical complementary mode signal generation. For simplicity and clarity, the examples and description relate to complementary mode PWM signal generation for N - type transistors that are enabled by a logic - high control signal and disabled by a logic - low control signal. However, the PWM generator also allows a configuration for selectively changing the polarity of the PWM output signals, thereby allowing each generated PWM output signal to be individually inverted. When not inverted, the active state may cause a logic - high signal to be generated at the output pin. When inverted, the active state may cause a logic - low to be generated relative to its signal level to allow the use of P - type transistors as well as N - type transistors at each PWM signal output.

[0018] Figure 1A and Figure 1B is an illustration of an example apparatus 100 for overriding PWM operation in complementary mode according to an example of the present disclosure.

[0019] Apparatus 100 may include a PWM generator circuit 102 and an override circuit 104. The PWM generator circuit 102 may output PWM signals for a complementary switch pair. In one example, the PWM generator circuit 102 may output a PWML signal and a PWMH signal that are complementary or nearly complementary to each other, with no overlap between the active portions of the PWMH signal and the PWML signal.

[0020] Specifically, the PWM generator circuit 102 may generate PWM signals such that PWMH and PWML do not cause the complementary switch pair receiving PWMH and PWML to be simultaneously active or transitioning. At least with respect to the active portions of the PWM signals, the PWM signals themselves may be complementary or nearly complementary to each other. Although described as complementary, these signals may be mostly complementary, with exceptions such as a forced deadtime when both signals would cause the corresponding complementary switches to be disabled.

[0021] The forced complementary nature of the PWMH signal and the PWML signal generated by the PWM generator circuit 102 with respect to the active portions of the PWM signals may be a safety feature, because in many applications, if two such switches are activated simultaneously, a breakdown condition from power to ground may occur, for example. Thus, the PWM generator circuit 102 may include forced complementary logic and forced deadtime logic. In addition, the PWM generator circuit 102 may enforce a deadtime during which both switches are to be off after receiving PWMH and PWML. The deadtime is understood to refer to the time between a first edge at which one signal changes from active to inactive and a second edge at which the complementary signal changes from inactive to active.

[0022] The override circuit 104 can override the forced complementary nature of the PWMH signal and the PWML signal relative to the active portion of the PWM signal before the PWM signal issued by the PWM generator circuit 102 is transmitted to the complementary switch pair. The override circuit 104 can override the PWMH signal and the PWML signal to generate an adjusted PWM signal. The adjusted PWM signal can be mostly complementary relative to the active portion of the PWM signal, with exceptions such as override operations or dead time. The adjusted PWM signal can be given as APWMH and APWML. The adjusted PWM signal can be applied to the complementary switch pair. After receiving the adjusted PWM signals APWMH and APWML, the complementary switch pair can be activated simultaneously within at least a portion of the PWM time-base clock cycle. When the override operation is enabled, the override circuit 104 can override the forced complementary nature of the PWMH signal and the PWML signal relative to the active portion of the PWM signal within at least a portion of the PWM time-base clock cycle. When the override operation is not enabled, the override circuit 104 can transmit the PWMH signal and the PWML signal unchanged as APWMH and APWML.

[0023] The override circuit 104 can include a special configuration procedure that requires a specific sequence of software instructions to unlock or lock a control register before an override enabled or disabled is accepted by the PWM control logic. This additional protection against accidental override of the forced complementary mode signal generation may be required only once, allowing for quick state modification during operation via software commands or hardware signals.

[0024] For example, in FIG. 1, the PWM generator circuit 102 can generate the PWMH signal and the PWML signal from any suitable input (not shown). Such inputs can be read from a memory (such as a register) or streamed from a random access memory, received at the device 100 as a function call, or received as an input signal from another element of the system in which the device 100 is implemented. As shown, the PWMH signal and the PWML signal can be mostly complementary relative to each other. Dead time can be added to the PWMH signal and the PWML signal to ensure that during the actual turn-on and turn-off of the complementary switch pair, the two switches are not activated simultaneously. Thus, as shown in FIG. 1, the PWMH signal and the PWML signal may not both be active at the same time (i.e., logic high for the n-type transistor or logic low for the p-type transistor).

[0025] After receiving the PWMH and PWML signals, if enabled, the override circuit 104 can selectively generate the APWMH and APWML signals. The input to the override circuit 104 (not shown) can specify whether the override operation is enabled and the specific times at which one or both of the PWMH and PWML signals are to be overridden. Additionally, the input can specify the value to be used to override the PWMH or PWML signal. The value can be a pre-determined value, such as logic 1, to activate the corresponding one of the complementary switches. For example, the input can be made from a software call to the device 100 via a register.

[0026] The override circuit 104 can override a portion of the PWMH or PWML signal such that the overridden portion causes both the PWMH and PWML signals to activate two of the complementary switches simultaneously. As shown in FIG. 1, between the enumerated times 2 and 3, the PWMH signal is inactive while the PWML signal is active. Based on the enabled override function and an indication to make both PWM signals active between the enumerated times 2 and 3, the override circuit 104 can selectively cause the PWMH signal to be overridden and active between the enumerated times 2 and 3 while maintaining the PWML signal active between the enumerated times 2 and 3. Thus, between the enumerated times 2 and 3, the resulting APWMH and APWML signals can both be active and provided to the complementary switches, thereby activating two of the complementary switches during that time period (i.e., between the enumerated times 2 and 3).

[0027] Multiple instances of the device 100 can be present in a given implementation or system. Additionally, the device 100 can be implemented using multiple instances of the PWM generator circuit 102 and the override circuit 104 to generate multiple pairs of PWM signals to be provided to multiple complementary switches.

[0028] Shown in FIG. 1 are example switches Q1 and Q2, which can be arranged in series between a voltage input terminal (VIN) and ground as shown. The midpoint of Q1 and Q2 can be connected to a first lead of an output inductor (LOUT), where a second lead of the output inductor (LOUT) is connected to a voltage output terminal (VOUT), and an output capacitor (COUT) can be connected across the voltage output terminal (VOUT) to ground. This is a simple example of a voltage regulator, where a constant regulated voltage can be provided at VOUT. The constant regulated voltage can be provided according to the duty cycle switching cycles of Q1 and Q2. Q1 and Q2 can be controlled by PWM signals that are typically complementary to each other. Even if both PWM signals are inactive simultaneously, if the time of such simultaneous inactivity is relatively small (such as less than 10% of the duty cycle of the PWM signal) or for purposes such as allowing reduction of jitter or other noise, the PWM signals can be considered to be typically complementary to each other. Generally, in other applications, it may be prevented that both Q1 and Q2 are turned on simultaneously to prevent a direct path for current between VIN and ground. In other words, a dead time is provided to prevent breakdown.

[0029] For example, if the PWMH signal and the PWML signal generated by the PWM generator circuit 102 are used to control Q1 and Q2, then between times 0 and 1, the PWMH signal will be inactive and Q1 will be turned off, while the PWML signal is active and Q2 will be turned on; between times 1 and 2, the PWMH signal will be active and Q1 will be turned on, while the PWML signal is inactive and Q2 will be turned off; between times 2 and 4, the PWMH signal will be inactive and Q1 will be turned off, while the PWML signal is active and Q2 will be turned on; between times 4 and 5, the PWMH signal will be active and Q1 will be turned on, while the PWML signal is inactive and Q2 will be turned off; and between times 5 and 6, the PWMH signal will be inactive and Q1 will be turned off, while the PWML signal is active and Q2 will be turned on. A required dead time may exist between states. Although the logic states and the switching of Q1 and Q2 occurring at times 1, 2, 4, and 5 have been described above, it should be understood that the PWM generator circuit 102 enforces a dead time between the falling edge of the PWMH or PWML signal and the immediately following rising edge of the PWML or PWMH signal, respectively. For simplicity, the dead time is not shown.

[0030] In contrast, if the APWMH signal and the APWML signal are applied to Q1 and Q2 at time 2 (e.g., in different voltage regulator topologies), the override circuit 104 may determine to override the PWMH signal using the effective value such that both PWM signals are used to activate the corresponding switches. Both Q1 and Q2 are activated by the effective signal values of the APWMH signal and the APWML signal in the time frame between time 2 and time 3. Similarly, the forced dead time can be overridden by the override circuit 104.

[0031] In the present disclosure, the switches are described as being activated by effective input values (i.e., the effective values on the corresponding signals). This may occur, for example, when using n-type field effect transistors (FETs) to implement the switches. However, one skilled in the art will recognize that switches can be implemented using, for example, p-type FETs, in which case an ineffective input value can activate the switch. The teachings of the present disclosure of the override circuit 104 can be suitably adapted for overriding in order to cause an effective or ineffective output for a given switch as needed to override the safety features of the signals generated by the PWM generator circuit 102.

[0032] The PWM generator circuit 102 and the override circuit 104 can be implemented in any suitable manner (such as by analog circuits, digital circuits, instructions for execution by a processor (not shown), application specific integrated circuits, field programmable gate arrays, programmable logic, programmable hardware, programmable logic devices, or any suitable combination thereof).

[0033] Figure 2 is a more detailed illustration of the operation of the PWM generator circuit 102 according to an example of the present disclosure.

[0034] Given a data input stream, such as for the PWMH signal: {1, 0, 0, 1, 0, 0} and for the PWML signal: {1, 0, 0, 1, 1, 0}, the PWM generator circuit 102 may not output the fourth such data element in the PWMH signal. This value may be removed to prevent both switches receiving the PWML signal and the PWMH signal from being activated simultaneously. As described in the present disclosure, this safety feature can be overridden by the override circuit 104.

[0035] Figure 3 is a more detailed illustration of the apparatus 100 for overriding PWM operation in complementary mode according to an example of the present disclosure.

[0036] The PWM generator circuit 102 may include an initial PWM signal circuit 302 to generate a PWM signal based on any suitable input. The initial PWM signal circuit 302 may generate complementary initial PWM signals given as IPWMH signals and IPWML signals that are implemented in a manner similar to the above-described PWMH signal and PWML signals.

[0037] In one example, the PWM generator circuit 102 may include any suitable number and type of dead time generator circuits 304, 306. In another example, the PWM generator circuit 102 may be configured to output the IPWMH signal and the IPWML signal to dead time generator circuits 304, 306 implemented externally relative to the PWM generator circuit 102. Although described as two circuits, the dead time generator circuits 304, 306 may be implemented in the same circuit. The dead time generator circuits 304, 306 may receive the IPWMH signal and the IPWML signal and output the PWMH signal and the PWML signal, respectively. The dead time generator circuits 304, 306 may delay or accelerate the transition between active and inactive in the PWMH signal or the PWML signal so as to enforce a dead time during which both the PWMH signal and the PWML signal are inactive, or otherwise cause two complementary switches to be deactivated simultaneously. The dead time may be used as a safety feature, for example, to allow a switch to fully transition from one state to another, because the physical limitations associated with a particular implementation of a given switch do not allow the switch to turn on or off completely instantaneously.

[0038] The dead time generator circuits 304, 306 may be selectively enabled. The dead time generator circuits 304, 306 may be selectively enabled by any suitable element, such as the override circuit 104. If enabled, the dead time generator circuits 304, 306 may cause a dead time to be added to the IPWMH signal and the IPWML signal and emitted as the PWMH signal and the PWML signal. If disabled, the dead time generator circuits 304, 306 may emit the IPWMH signal and the IPWML signal to be emitted as the PWMH signal and the PWML signal, respectively.

[0039] The override circuit 104 may include a control circuit 312. The control circuit 312 may control various operations of the override circuit 104, as well as the operations of overriding the dead time generator circuits 304, 306.

[0040] Override circuit 104 may include any suitable analog circuitry, digital circuitry, instructions for execution by a processor (not shown), application specific integrated circuit, field programmable gate array, programmable logic, programmable hardware, programmable logic device, or any suitable combination thereof, for causing override of one or more of the PWMH signal and the PWML signal. For example, override circuit 104 may include multiplexers 308, 310 to selectively override the PWMH signal and the PWML signal, respectively. Multiplexers 308, 310 may be controlled by control signals from control circuit 312. Multiplexer 308 may selectively switch between the PWMH signal and a control value from control circuit 312 to output an APWMH signal. Multiplexer 310 may selectively switch between the PWML signal and a control value from control circuit 312 to output an APWML signal. The control value from control circuit 312 to be output as the APWMH signal or the APWML signal may be a pre-determined value, shown as PRE 1 or PRE2. The pre-determined value may be one or valid to cause the corresponding switch to be activated. Additionally, control circuit 312 may issue control signals to multiplexers 308, 310 to operate based on software instructions to override one of the PWMH signal and the PWML signal, shown as control signals SW1 and SW2, respectively. Control signals SW1 and SW2 may be read from, for example, registers or other suitable mechanisms. Control signals SW 1 and SW2 may not only define whether to override one of the PWMH signal and the PWML signal, but also define how long and when to override. The control of the selective operation of multiplexers 308, 310 is illustrated as being based on control signals SW1 and SW2, respectively.

[0041] Control circuit 312 may selectively turn on or off dead time generator circuits 304, 306. When overriding one of the PWMH signal and the PWML signal, control circuit 312 may turn off the corresponding one of dead time generators 304, 306.

[0042] Control circuit 312, dead time generator circuits 304, 306, and initial PWM signal circuit 302 may be implemented in any suitable manner, such as by analog circuitry, digital circuitry, instructions for execution by a processor (not shown), application specific integrated circuit, field programmable gate array, programmable logic, programmable hardware, programmable logic device, or any suitable combination thereof.

[0043] Figure 4FIG. 400 is a diagram of an example application circuit 400 to which a PWM signal may be provided by apparatus 100 in accordance with an example of the present disclosure. Specifically, multiple examples of apparatus 100 may provide multiple instances of an APWMH signal and an APWML signal to control switches within example application circuit 400. Application circuit 400 may be a three-level voltage converter that utilizes a split half-bridge circuit.

[0044] In application circuit 400, a VIN input may be input into application circuit 400. A series of switches Q1, Q2, Q3, Q4 may be connected in series from top to bottom. Q1 may be controlled by a PWM signal APWMH1, and Q4 may be controlled by a corresponding PWM signal APWML1. Q2 may be controlled by a PWM signal APWMH2, and Q3 may be controlled by a corresponding PWM signal APWML2. A flyback capacitor CFLY may be connected across Q2 and Q3. An input or bus capacitor CBUS may be connected across Q1 and Q4. An output inductor LOUT may be connected from the midpoint between Q2 and Q3 to the output of application circuit 400. An output capacitor COUT may be connected between the output and ground.

[0045] The operation of outputting a voltage from application circuit 400 may be performed by charging and discharging a flying capacitor CFLY.

[0046] Figure 5 FIG. 400 is a diagram of the operation of an example application circuit 400 in accordance with an example of the present disclosure. Specifically, Figure 5 illustrates the timing of signals generated by an application that uses PWM signals from apparatus 100 that have not been overridden but may be overridden. During different phases of operation, different switches among Q1 to Q4 may be activated.

[0047] In a first phase, Q1 and Q3 may be activated while Q2 and Q4 are deactivated. During this first phase, the flyback capacitor C FLY may be charged to V IN .

[0048] In a second phase, Q4 and Q3 may be activated while Q1 and Q2 are deactivated.

[0049] In a third phase, Q4 and Q2 may be activated while Q1 and Q3 are deactivated. This may be the opposite of the first phase.

[0050] In a fourth phase, Q4 and Q3 may be activated while Q1 and Q2 are deactivated. This may be the same operation as in the second phase.

[0051] Figure 6FIG. 600 is a diagram of an example application circuit to which the apparatus 100 according to an example of the present disclosure may provide a PWM signal. Specifically, multiple examples of the apparatus 100 may include multiple instances of the APWMH signal and the APWML signal to control switches within the example application circuit 600. Specifically, multiple examples of the apparatus 100 may provide multiple instances of the APWMH signal and the APWML signal to control switches within the example application circuit 400. The application circuit 600 may be a four-level totem-pole power factor correction circuit.

[0052] In the application circuit 600, a series of six switches Q1, Q2, Q3, Q4, Q5, Q6 may be connected in series from top to bottom and may form a bridge. In parallel, two switches Q7 and Q8 may be connected in series with each other. The voltage source VIN may be connected between the midpoint of Q7 and Q8 at the first end of the voltage source VIN and the first end of the input inductor LIN at the second end of the voltage source VIN. The second end of the input inductor LIN may be connected to the midpoint of Q3 and Q4. These switches Q7, Q8, VIN, and LOUT may together form a rectifier. The flyback capacitor CF1 may be connected between the midpoint of Q1 and Q2 at the first end and the midpoint of Q5 and Q6 at the second end. The flyback capacitor CF2 may be connected between the midpoint of Q2 and Q3 at the first end and the midpoint of Q4 and Q5 at the second end. The output capacitor CDC may be connected between the output terminal and ground.

[0053] Q1 may be controlled by the PWM signal APWMH1, and Q6 may be controlled by the corresponding PWM signal APWML1. Q2 may be controlled by the PWM signal APWMH2, and Q5 may be controlled by the corresponding PWM signal APWML2. Q3 may be controlled by the PWM signal APWMH3, and Q4 may be controlled by the corresponding PWM signal APWML3.

[0054] Figure 7 FIG. 600 is a diagram of the operation of an example application circuit 600 according to an example of the present disclosure. Shown are VAC generated by VIN, VDC output from the application circuit 600, the current through LIN, and the switch voltage (VSW).

[0055] In the application circuit 600, in order to achieve a low total harmonic distortion (THD) of the input of the power supply, it may be important to appropriately balance the voltages of the flyback capacitors CF1 and CF2. During the level transition of the switch voltage VSW, where significantly different voltage levels may be generated as VOUT, the VFCAP representing the voltages of the flyback capacitors CF1 and CF2 across Figure 6 the flyback capacitors CF1 and CF2 in may become distorted through parasitic resistances. The distortion may cause oscillations in the voltage balance, which may otherwise require active compensation.

[0056] Figure 8FIG. 0 is a diagram of the operation of apparatus 100 for providing an override signal to example application circuit 600 in accordance with an example of the present disclosure. Apparatus 100 may provide a PWM signal to the example application circuit. Figure 8 Illustrated may be how two switches of a given complementary pair may be made active simultaneously via the action of override circuit 104. Figure 8 Shown therein is the control of switches Q2 and Q5. The PWMH2 signal is shown as the control of Q2 as a baseline without override. The APWML2 signal is shown as the control of Q5, although PWML2 would be the same signal. The override circuit 104 may enhance PWMH2 to include Figure 8 the shaded portion shown therein to produce an APWMH2 signal, where overlap may occur with the APWML2 signal such that both switches Q2 and Q5 may be activated simultaneously. When both Q2 and Q5 are activated simultaneously, there may be no risk of breakdown current because the capacitor may be charged rather than causing a short circuit. The overlapping switch times may shorten the time to reach the flying capacitor center starting voltage. The capacitor will produce a positive sine wave and a negative sine wave, so the capacitor needs to be fully discharged, or discharged to a known half charge, or at a deterministic starting point. The overlapping switch times may make the time to reach such a deterministic starting point shorter.

[0057] Figure 9 FIG. 10 is a diagram of an example system 900 for overriding PWM operation to generate generally complementary PWM signals in accordance with an example of the present disclosure. System 900 may include a PWM generator circuit 902, an override circuit 904, and an output circuit 908. The PWM generator circuit 902 and the override circuit 902 may be implemented in whole or in part by, or implement, the PWM generator circuit 102 and the override circuit 104. The PWM generator circuit 902, the override circuit 904, and the output circuit 908 may be implemented in any suitable manner, such as by analog circuitry, digital circuitry, instructions for execution by a processor (not shown), application specific integrated circuit, field programmable gate array, programmable logic, programmable hardware, programmable logic device, or any suitable combination thereof.

[0058] The PWM generator circuit 902 may generate a first PWM signal (such as PWMH) and a second PWM signal (such as PWML). The signals PWHM and PWML may generally be complementary to each other with respect to their active portions.

[0059] The override circuit 904 may receive the signals PWMH and PWML and output adjusted PWM signals, such as APWMH and APWML, to the output circuit 908 based on PWMH and PWML.

[0060] The output circuit 908 can output a first PWM output signal (such as OPWMH) and a second PWM output signal (such as OPWML). These signals can be provided to, for example, a complementary switch pair. The output circuit 908 can perform various signal regulations, such as adjusting the relative polarities of its input PWM signals.

[0061] The override circuit 904 can select between a first override value or a first PWM signal (such as PWMH) to provide the adjusted PWM signal as APWMH to the output circuit. The override circuit 904 can perform this operation by, for example, using the multiplexer 806 or any other suitable mechanism. Thus, the output circuit 908 can output a first output PWM signal (such as OPWMH) based on the first adjusted PWM signal (such as APWMH), which is based on either the first override value or the selected one of the first PWM signals (such as PWMH) from the PWM generator circuit 902.

[0062] Figure 10A and Figure 10B is an illustration of an example method 1000 for overriding PWM operation in complementary mode according to an example of the present disclosure. The method 1000 can be performed by any suitable element, such as those elements of the control circuit shown in FIGS. 1 to Figure 3 、 Figure 9 as shown. The method 1000 can be performed with more or fewer steps than those shown in FIG. 10, and the steps of the method 1000 can optionally be omitted, repeated, performed in a different order, performed in parallel, or performed recursively.

[0063] The method 1000 can start at any suitable point. Specifically, a determination to override a given PWM signal can be made on any appropriate basis. In FIG. 10, such a determination can be made by a suitable one of 1005, 1010, 1015, or 1020. These steps can be performed in parallel with each other, or in any suitable order.

[0064] At 1005, for example, it can be determined whether a software override of PWM generation has been received. If so, the method 1000 can proceed to 1030. Otherwise, the method 1000 can proceed to 1010.

[0065] At 1010, it can be determined whether the flying capacitor connected between two complementary switches receiving the PWM signal needs to be charged. If so, the method 1000 can proceed to 1030. Otherwise, the method 1000 can proceed to 1015.

[0066] At 1015, it can be determined whether the flying capacitor connected between two complementary switches receiving a PWM signal needs to be discharged. If so, method 1000 can proceed to 1030. Otherwise, method 1000 can proceed to 1020.

[0067] At 1020, it can be determined whether the time to reach the centered starting voltage of the flying capacitor connected between two complementary switches receiving a PWM signal needs to be shortened in order to compensate for the voltage of the flying capacitor. If so, method 1000 can proceed to 1030. Otherwise, method 1000 can proceed to 1025.

[0068] At 1025, the generated PWM signal can be output from the override circuit unchanged. The PWM signal can be output for transmission to the complementary switches. Method 1000 can proceed to 1050.

[0069] At 1030, it can be determined whether to override one or both of the complementary PWM signals. If both are overridden, method 1000 can proceed to 1035. If a single one is overridden, method 1000 can proceed to 1040.

[0070] At 1035, two of these PWM signals can be overridden. These signals can be overridden using a predefined value. The predefined value can cause the corresponding switch to be activated. This process can generate an adjusted PWM signal to activate the switches simultaneously. Method 1000 can proceed to 1045.

[0071] At 1040, a single PWM signal in the PWM signals can be overridden sufficiently to activate the two switches simultaneously. This signal can be overridden using a predefined value. The predefined value can cause the corresponding switch to be activated. This process can generate an adjusted PWM signal to activate the switches simultaneously. Method 1000 can proceed to 1045.

[0072] At 1045, dead-time compensation can be bypassed in the generation of the PWM signal for the overridden signals. Method 1000 can proceed to 1050.

[0073] At 1050, it can be determined whether method 1000 will repeat. If so, method 1000 can repeat, for example, at 1005. Otherwise, method 1000 can terminate.

[0074] Examples of the present disclosure may include an apparatus. The apparatus may include a PWM generator circuit for generating generally complementary PWM signals. These signals may be used to prevent both of two complementary switches receiving these complementary PWM signals from being activated simultaneously. The PWM signals may generally be complementary with respect to their active portions. The apparatus may include an override circuit for overriding at least one of the complementary PWM signals to produce an adjusted PWM signal. When the adjusted PWM signal is received at the two complementary switches, the adjusted PWM signal may cause the two complementary switches to be activated simultaneously.

[0075] In combination with any one of the above embodiments, the override circuit is configured to override the complementary PWM signals based on software override to produce an adjusted PWM signal.

[0076] In combination with any one of the above embodiments, the override circuit may be configured to override the complementary PWM signals to produce an adjusted PWM signal to activate both of two complementary switches to charge a flying capacitor connected between the two complementary switches.

[0077] In combination with any one of the above embodiments, the override circuit may be configured to override the complementary PWM signals to produce an adjusted PWM signal to activate both of two complementary switches to discharge a flying capacitor connected between the two complementary switches.

[0078] In combination with any one of the above embodiments, the override circuit may be configured to override the complementary PWM signals to produce an adjusted PWM signal to activate both of two complementary switches to actively compensate for the voltage of a flying capacitor connected between the two complementary switches.

[0079] In combination with any one of the above embodiments, the override circuit may be configured to actively compensate for the voltage of a flying capacitor connected between the two complementary switches by shortening the time to reach the center starting voltage of the flying capacitor.

[0080] In combination with any one of the above embodiments, the override circuit may be configured to bypass dead-time compensation to generate at least one of the complementary PWM signals.

[0081] In combination with any one of the above embodiments, the override circuit may be configured to override a single one of the complementary PWM signals to produce an adjusted PWM signal.

[0082] In combination with any one of the above embodiments, the override circuit may be configured to override one of the complementary PWM signals with a predefined value to produce an adjusted PWM signal.

[0083] Examples of the present disclosure may include a system. The system may include any one of the devices in the above examples. The PWM generator circuit may be used to generate a first PWM signal and a second PWM signal. The first PWM signal and the second PWM signal may generally be complementary to each other with respect to their active portions. The system may include an output circuit for outputting a first output PWM signal and a second output PWM signal. The system may include an override circuit for selecting between a first override value or a first adjusted PWM signal to be provided to the output circuit. The output circuit may be used to output the first output PWM signal based on the first adjusted PWM signal, which is based on a selected one of the first override value or the first adjusted PWM signal from the override circuit.

[0084] The PWM generator circuit, the override circuit, and the output circuit in any one of the above examples may be implemented in any suitable manner, such as by an analog circuit, a digital circuit, instructions for execution by a processor (not shown), an application specific integrated circuit, a field programmable gate array, programmable logic, programmable hardware, a programmable logic device, or any suitable combination thereof.

[0085] In combination with any one of the above embodiments, the override circuit may be used to turn off adding a dead time to the first PWM signal based on a determination of selecting the first override value to be provided to the output circuit.

[0086] Examples of the present disclosure may include a method performed by any one of the above examples.

[0087] Although the examples have been described above, the present disclosure may have other variations and examples without departing from the essence and scope of these examples.

Claims

1. A device, comprising: a pulse width modulation (PWM) generator circuit to generate a normally complementary PWM signal, the signal being used to prevent two complementary switches receiving the complementary PWM signal from both being activated at the same time, the PWM signals being normally complementary with respect to their active portions; and An override circuit is configured to override at least one of the complementary PWM signals to generate an adjusted PWM signal, the adjusted PWM signal being configured to cause the two complementary switches to be activated simultaneously when the adjusted PWM signal is received at the two complementary switches.

2. The device of claim 1, wherein the override circuit is to override the complementary PWM signal to generate the adjusted PWM signal based on a software override.

3. The apparatus according to any one of claims 1 to 2, wherein the override circuit is used to override the complementary PWM signal to generate the adjusted PWM signal to activate both of the two complementary switches to charge a flying capacitor connected between the two complementary switches.

4. The apparatus according to any one of claims 1 to 3, wherein the override circuit is used to override the complementary PWM signal to generate the adjusted PWM signal to activate both of the two complementary switches to discharge a flying capacitor connected between the two complementary switches.

5. The apparatus of any one of claims 1 to 4, wherein the override circuit is used to override the complementary PWM signal to generate the adjusted PWM signal to activate both of the two complementary switches to actively compensate for a voltage of a flying capacitor connected between the two complementary switches.

6. The apparatus of claim 5, wherein the override circuit is to actively compensate the voltage of the flying capacitor connected between the two complementary switches by shortening the time to reach a centered start-up voltage of the flying capacitor.

7. The apparatus of any one of claims 1 to 6, wherein the override circuit is configured to bypass dead time compensation to generate at least one of the complementary PWM signals.

8. The apparatus of any one of claims 1 to 7, wherein the override circuit is configured to override a single one of the complementary PWM signals to generate the adjusted PWM signal.

9. The apparatus of any one of claims 1 to 8, wherein the override circuit is configured to override one of the complementary PWM signals with a predefined value to generate the adjusted PWM signal.

10. A method comprising: generating generally complementary pulse width modulated (PWM) signals that are generally complementary with respect to their active portions, the complementary PWM signals being used to prevent two complementary switches receiving the complementary PWM signals from both being activated simultaneously; and At least one of the complementary PWM signals is overridden to generate an adjusted PWM signal, the second adjusted PWM signal being adapted to cause the two complementary switches to be activated simultaneously upon receiving the second adjusted PWM signal.

11. The method of claim 10, wherein overriding the complementary PWM signal to generate the adjusted PWM signal is based on software override.

12. The method of any one of claims 10 to 11, wherein the complementary PWM signal is overridden to generate the adjusted PWM signal to activate both of the two complementary switches to charge a flying capacitor connected between the two complementary switches.

13. The method of any one of claims 10 to 11, wherein the complementary PWM signal is overridden to generate the adjusted PWM signal to activate both of the two complementary switches to discharge a flying capacitor connected between the two complementary switches.

14. The method of any one of claims 10 to 13, wherein the complementary PWM signal is overridden to generate the adjusted PWM signal to activate both of the two complementary switches to actively compensate for a voltage of a flying capacitor connected between the two complementary switches.

15. The method of claim 14, comprising shortening the time to reach a centered start-up voltage of the flying capacitor to actively compensate for the voltage of the flying capacitor connected between the two complementary switches.

16. A method according to any one of claims 10 to 15, comprising bypassing dead time compensation to generate the complementary PWM signal to produce the adjusted PWM signal.

17. A method according to any one of claims 10 to 16, comprising overriding a single one of the complementary PWM signals to produce the adjusted PWM signal.

18. A method according to any one of claims 10 to 17, comprising overriding one of the complementary PWM signals by a predefined value to generate the adjusted PWM signal.

19. A system, comprising: a pulse width modulation (PWM) generator circuit, the PWM generator circuit being configured to generate a first PWM signal and a second PWM signal, the first PWM signal and the second PWM signal being generally complementary to each other with respect to their effective portions; An output circuit, the output circuit is used to output a first output PWM signal and a second output PWM signal; and an override circuit to select between a first override value or a first adjusted PWM signal to provide to the output circuit; The output circuit is configured to output the first output PWM signal based on the first adjusted PWM signal, the first adjusted PWM signal being based on a selected one of the first override value from the override circuit or the first adjusted PWM signal.

20. The system of claim 19, wherein the override circuit is to turn off adding dead time to the first PWM signal based on a determination to select the first override value to be provided to the output circuit.

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