Method and system for testing semiconductor device
By building the objective function and test allocation model and selecting the optimal combination of test resources, the problem of difficulty in effectively testing different types of semiconductor devices in the existing technology is solved, and more efficient and accurate testing is achieved.
Patent Information
- Application Number
- CN202510068594.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-16
- Publication Date
- 2025-05-30
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
It is difficult for the prior art to effectively select the best test machines and test tools for comprehensive testing for different types of semiconductor devices.
By obtaining the types of semiconductor devices to be tested, the types of test toolkits and the types of test components, an objective function that meets the test needs, and based on this, a test allocation model is built, and the optimal combination of test resources is selected for semiconductor device testing.
Maximize the testing needs of each type of semiconductor device and improve the applicability and accuracy of semiconductor device testing.
Smart Images
Figure CN120064914A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor test scheduling, and more particularly, to a method and system for testing semiconductor devices. Background Art
[0002] Testing semiconductor devices requires a process of comprehensively evaluating the electrical, physical, optoelectronic, thermal and other properties of the semiconductor devices after production and packaging in a test workstation. These tests are designed to verify whether the semiconductor devices meet the design requirements, whether the manufacturing process is stable and reliable, and how the devices perform in actual applications. However, there are various types of semiconductor devices, each type having different structures and functions, and different test methods and test instruments are required for different functional tests. At the same time, the test workstation includes multiple groups of test machines. Therefore, how to select the optimal test machines and test tools for different types of semiconductor devices for comprehensive testing is a technical problem that needs to be solved urgently in the prior art. Summary of the Invention
[0003] In view of this, the present invention proposes a method and system for testing semiconductor devices to solve the problems existing in the above prior art.
[0004] On the one hand, to achieve the above object, the present invention proposes a method for testing semiconductor devices, including:
[0005] Obtaining the types of semiconductor devices to be tested, the types of test toolkits and the types of test components of a semiconductor test workstation;
[0006] Constructing an objective function that meets the test requirements based on the types of semiconductor devices to be tested, the types of test toolkits, and the types of test components;
[0007] Constructing a test allocation model based on the objective function, and selecting an optimal test resource combination based on the test allocation model for semiconductor resource testing.
[0008] Further, the objective function is used to describe maximizing the satisfaction of the test requirements of all types of semiconductor devices, and the objective function is as follows:
[0009]
[0010] Wherein, W j (1 ≤ j ≤ n) represents the penalty coefficient of semiconductor device j, D j (1 ≤ j ≤ n) represents the test requirement of semiconductor device j, Y j represents the number of semiconductor devices whose tests are completed.
[0011] Further, the process of selecting the optimal test resource combination based on the test allocation model for semiconductor resource testing includes:
[0012] Represent the test allocation problem of semiconductor devices based on the system state vector of the semiconductor test workstation;
[0013] Obtain several test jobs and test resource combinations respectively based on the synchronous resource selection rule, the minimum input-output ratio rule, the minimum weighted total resource occupancy rule, the minimum relative total resource occupancy rule, and the minimum weighted load test set optimization rule;
[0014] Calculate the return rates of several said test resource combinations; Use the test resource combination with the highest return rate to test semiconductor devices.
[0015] Further, the representation form of the system state vector is as follows:
[0016]
[0017] Among them, represents the job type of the last test completed by tester i; T i (1 ≤ i ≤ m) represents the job type being processed by tester i. If the tester is in an idle state, it is represented by 0; represents the remaining processing time of the job being processed by tester i (if T i = 0, then ); H i (1 ≤ i ≤ m) represents the type of test tool kit being used in conjunction with tester i (if T i = 0, then Hi = 0); U i (1 ≤ i ≤ m) represents the type of enabler component being used in conjunction with tester i (if T i = 0, then U i = 0); z j，s represents the quantity of the j-th type of semiconductor device to be tested waiting for the s-th process; represents the unmet demand of semiconductor device j; represents the quantity of unoccupied enabler component u at the current moment; τ represents the current moment.
[0018] Further, the method for calculating the return rates of several said test resource combinations is as follows:
[0019]
[0020] Among them, r(τ) represents the return rate obtained between the (t - 1)-th moment and the t-th moment, τ t-1 < τ ≤ τt , Y j，t represents the number of tests completed for semiconductor j at time t, w j represents the penalty coefficient of semiconductor device j, D j represents the test requirements of semiconductor device,.
[0021] On the other hand, to achieve the above object, the present invention proposes a test system for semiconductor devices, including a test statistics module and a test allocation module connected to each other;
[0022] The test statistics module is used to obtain the types of semiconductor devices to be tested, the types of test toolkits and test component types of semiconductor test workstations;
[0023] The test allocation module is used to construct an objective function that meets the test requirements of all types of semiconductor devices according to the types of semiconductor devices to be tested, the types of test toolkits, and the types of test components, and construct a test allocation model according to the objective function, and select the optimal test resource combination according to the test allocation model for semiconductor resource testing.
[0024] Furthermore, the test allocation module obtains the test requirements and the number of tests completed for each type of semiconductor device, and constructs a test objective function for the corresponding type of semiconductor device according to the test requirements and the number of tests completed; the objective function is shown as follows:
[0025]
[0026] where, W j (1 ≤ j ≤ n) represents the penalty coefficient of semiconductor device j, D j (1 ≤ j ≤ n) represents the test requirements of semiconductor device j, Y j represents the number of tests completed for semiconductor devices
[0027] Furthermore, the test allocation module describes the system state by obtaining the type of the last job completed by the tester, the remaining processing time of the job being processed by the tester, the type of the test toolkit and the type of the enabler component used in conjunction with the tester, the number of a certain type of semiconductor device to be tested waiting for a certain process, the unmet test requirements of the semiconductor device to be tested, and the number of unoccupied enabler components at the current moment; and according to the system state, several test jobs and test resource combinations are obtained by combining the synchronous resource selection rule, the minimum input-output ratio rule, the minimum weighted total resource occupancy rule, the minimum relative total resource occupancy rule, and the minimum weighted load test set optimization rule, and the return rate is calculated for each of the several test resource combinations, and the test resource combination with the highest return rate is used for the test of the corresponding type of semiconductor device to be tested.
[0028] Furthermore, the description of the system state is as follows:
[0029]
[0030] Among them, represents the type of job that the test machine i has completed in the most recent test; T i (1 ≤ i ≤ m) represents the type of job that the test machine i is processing. If the test machine is in an idle state, it is represented by 0; represents the remaining processing time of the job that the test machine i is processing (if T i = 0, then ); H i (1 ≤ i ≤ m) represents the type of test tool kit that is being used in conjunction with the test machine i (if T i = 0, then Hi = 0); U i (1 ≤ i ≤ m) represents the type of enabler component that is being used in conjunction with the test machine i (if T i = 0, then U i = 0); z j，s represents the number of semiconductor devices of the jth type waiting to be tested for the sth process; represents the unmet demand of the semiconductor device j; represents the number of enabler components u that are not occupied at the current moment; τ represents the current moment.
[0031] Furthermore, the test allocation module calculates the rate of return for several combinations of test resources using the following formula:
[0032]
[0033] Among them, r(τ) represents the rate of return obtained between the (t - 1)th moment and the tth moment, τ t-1 < τ ≤ τ t , Y j，t represents the number of tests completed for semiconductor j at the tth moment, w j represents the penalty coefficient for semiconductor device j, D j represents the test requirement for semiconductor device j.
[0034] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0035] The present invention obtains different test requirements according to different types of semiconductor devices, selects a better resource combination corresponding to the test requirements according to the system state of the test workstation and different combination methods of test resources, and finally obtains the optimal test combination by calculating the rate of return, so as to maximize the satisfaction of the test requirements of each type of semiconductor device and improve the applicability and accuracy of semiconductor device testing. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. Moreover, throughout the drawings, the same reference numerals are used to denote the same components. In the drawings:
[0037] Figure 1 is a flowchart of a semiconductor device testing method in an embodiment of the present invention;
[0038] Figure 2 is a structural diagram of a semiconductor device testing system in an embodiment of the present invention. Detailed Embodiments
[0039] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art. It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. Hereinafter, the present invention will be described in detail with reference to the drawings and in conjunction with the embodiments.
[0040] Embodiment 1
[0041] This embodiment proposes a testing method for semiconductor devices, as Figure 1 shown, including the following steps:
[0042] Obtain the types of semiconductor devices to be tested, the types of test toolkits of the semiconductor test workstation, and the types of test components;
[0043] Construct an objective function that meets the test requirements based on the types of semiconductor devices to be tested, the types of test toolkits, and the types of test components;
[0044] Construct a test allocation model based on the objective function, and select the optimal test resource combination based on the test allocation model for semiconductor resource testing.
[0045] The semiconductor testing problem described in this embodiment considers the scheduling problem of the device changeover time, various supporting resource constraints, device test paths, and other constraint conditions. In this embodiment, the test workstation for testing includes m test machines, and n semiconductor devices need to be tested. Among them, device j needs to be processed in N j test processes on the test machine. Different processes of the same type of device can be processed discontinuously, but must be in the order of precedence, and the test processes of different test processes are different. Use Mj,s Denote the set of test machines for the s-th process of processing the j-th type of product. Use operation (j, s) to represent the s-th process of product j. Each test machine cannot process multiple operations simultaneously, and the processing of each type of operation cannot be interrupted. The processing time of each type of operation is known, denoted by p i,j,s Denote the operation processing time of the test machine. Use s j1 , s 1 , j 2 , s 2 Denote the setup time from operation (j 1 , s 1 ) to (j 2 , s 2 ). If the two consecutive operations have the same type (j 1 = j 2 , s 1 = s 2 ), then no setup time is required; otherwise, setup time is required.
[0046] Semiconductor testing requires the supporting use of resources such as test machines and enablers. An enabler consists of several test toolkits and enabler components. Each test toolkit consists of multiple different types of test components. Since an enabler can be decomposed into test toolkits and enabler components, and various test toolkits and enabler components can be recombined into different types of enablers, an enabler is decomposable and recombinable. During testing, one test machine and one or more test toolkits of the same type, as well as one or more enabler components of the same type, are required for supporting.
[0047] The requirements for various additional test resources supporting a test machine are related. That is, the types and quantities of test toolkits and enabler components required for test operation (j, s) are not only related to the operation type but also related to the type of the supporting test machine. One type of operation can be tested by one or more combinations of [test machine, test toolkit, enabler component], and one combination of [test machine, test toolkit, enabler component] can test one or more types of operations. Therefore, there is a many-to-many mapping relationship between operation types and resource combinations. Thus, the purpose of this embodiment is to screen out the most suitable test resource combination for each semiconductor device to meet its test requirements.
[0048] For the above reasons, the objective function constructed in this embodiment is used to maximize the test requirements of each device, as shown specifically below:
[0049]
[0050] Among them, W j (1 ≤ j ≤ n) represents the penalty coefficient of semiconductor device j, D j(1 ≤ j ≤ n) represents the test requirements of semiconductor device j, and Y j represents the number of semiconductor devices whose tests have been completed.
[0051] The system state of the tester workstation can be represented in the form of a vector. For the above objective function, the following vectors are constructed to describe the system state:
[0052]
[0053] Among them, represents the type of job that the last test of tester i has completed; T i (1 ≤ i ≤ m) represents the type of job that tester i is processing. If the tester is in an idle state, it is represented by 0; represents the remaining processing time of the job that tester i is processing (if T i = 0, then ); H i (1 ≤ i ≤ m) represents the type of test tool kit that is being used in conjunction with tester i (if T i = 0, then H i = 0); U i (1 ≤ i ≤ m) represents the type of enabler component that is being used in conjunction with tester i (if T i = 0, then U i = 0); z j，s represents the number of semiconductor devices of the jth type waiting to be tested for the s-th process; represents the unmet demand of semiconductor device j; represents the number of unoccupied enabler components u at the current moment; τ represents the current moment.
[0054] After describing the system operation state, various test resource combinations can be obtained according to different objectives. In this embodiment, the test operations and test resources are combined and allocated respectively according to five principles: the synchronous resource selection rule, the minimum input-output ratio rule, the minimum weighted total resource occupancy rule, the minimum relative total resource occupancy rule, and the minimum weighted load test set optimization rule
[0055] Furthermore, the synchronous resource selection rule uses the tendency factors of the tester and the test operation, the tendency factor of the test tool kit, and the tendency factor of the enabler component to represent the priority of the test resources. By estimating the remaining processing time of the tester, the above three tendency factors are calculated. The larger the value of the tendency factor, the higher the priority of the processing job.
[0056] The minimum input-output ratio rule calculates the priority of a test by computing the amount of input resources consumed by a test machine during a test operation, including the input amount of the test machine, the input amount of the semiconductor under test, and the input amount of the enabling component. The calculated result indicates to a certain extent the cost that the test operation needs to consume. Therefore, the higher the cost, the lower the test priority.
[0057] The minimum weighted total resource occupancy rule calculates the test efficiency of each test machine for each test operation. A resource combination with a higher test efficiency represents a test combination that occupies the least system resources. In this way, multiple test combinations with less resource occupancy are obtained.
[0058] The minimum relative total resource occupancy rule screens multiple test combinations by calculating the total resource occupancy of each test combination. The smaller the occupancy of the system's total resources, the higher the priority of the test combination.
[0059] The minimum weighted load test set optimization rule includes: the priority of downstream test operations is greater than that of upstream test operations, and by calculating the load of the test machine, the processing efficiency of the test machine, and the remaining available test time, a proportion is allocated to each test resource combination. The test resource combination with a higher proportion has a higher priority.
[0060] As a preferred implementation, after obtaining multiple test resource combinations through the above principles, it is necessary to screen out the best combination for the test operation of the corresponding semiconductor device. At this time, the return rates of several of the test resource combinations are calculated, and the combination with the highest return rate is used as the best test resource combination. The specific calculation method is as follows:
[0061]
[0062] Among them, r(τ) represents the return rate obtained between the (t - 1)th moment and the tth moment, τ t-1 <τ ≤ τ t ,Y j，t represents the number of tests completed for semiconductor j at the tth moment, w j represents the penalty coefficient of semiconductor device j, D j represents the test requirement of semiconductor device j.
[0063] Embodiment 2
[0064] As Figure 2 shown, this embodiment provides a test system for semiconductor devices, including a test statistics module and a test allocation module that are interconnected;
[0065] The test statistics module is used to obtain the types of semiconductor devices to be tested, the types of test toolkits, and the types of test components of the semiconductor test workstation;
[0066] The test allocation module is used to construct an objective function that meets the test requirements of all types of semiconductor devices according to the type of semiconductor device to be tested, the type of test tool kit, and the type of test component, and construct a test allocation model according to the objective function, and select the optimal test resource combination according to the test allocation model for semiconductor resource testing.
[0067] Further, the test allocation module obtains the test requirements of each type of semiconductor device and the number of tests completed, and constructs a test objective function for the corresponding type of semiconductor device according to the test requirements and the number of tests completed; the objective function is shown as follows:
[0068]
[0069] Among them, W j (1 ≤ j ≤ n) represents the penalty coefficient of semiconductor device j, D j (1 ≤ j ≤ n) represents the test requirement of semiconductor device j, Y j represents the number of tests completed for the semiconductor device.
[0070] Further, the test allocation module describes the system state by obtaining the type of the job last tested by the tester, the remaining processing time of the job being processed by the tester, the type of the test tool kit used in conjunction with the tester and the type of the enabler component, the number of a certain type of semiconductor device to be tested waiting for a certain process, the unmet test requirements of the semiconductor device to be tested, and the number of unoccupied enabler components at the current moment; and according to the system state, in combination with the synchronous resource selection rule, the minimum input-output ratio rule, the minimum weighted total resource occupancy rule, the minimum relative total resource occupancy rule, and the minimum weighted load test set optimization rule, several test jobs and test resource combinations are obtained, the rate of return is calculated for each of the several test resource combinations, and the test resource combination with the highest rate of return is used for testing the corresponding type of semiconductor device to be tested.
[0071] Further, the description of the system state is as follows:
[0072]
[0073] Among them, represents the type of the job last tested by tester i; T i (1 ≤ i ≤ m) represents the type of the job being processed by tester i, and if the tester is in an idle state, it is represented by 0; represents the remaining processing time of the job being processed by tester i (if Ti = 0, then ); H i(1 ≤ i ≤ m) represents the type of test tool kit being used in conjunction with test machine i (if T i = 0, then H i = 0); U i (1 ≤ i ≤ m) represents the type of enablement component being used in conjunction with test machine i (if T i = 0, then U i = 0); z j，s represents the number of semiconductor devices of the j-th type waiting to be tested in the s-th process; represents the unmet demand of semiconductor device j; represents the number of unoccupied enablement components u at the current moment; τ represents the current moment.
[0074] Furthermore, the test allocation module calculates the rate of return for several combinations of test resources using the following formula:
[0075]
[0076] where r(τ) represents the rate of return obtained between the (t - 1)-th moment and the t-th moment, τ t-1 < τ ≤ τ t , Y j，t represents the number of tests completed for semiconductor j at time t, w j represents the penalty coefficient for semiconductor device j, D j represents the test requirement of semiconductor device,.
[0077] In this specification, each embodiment is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For the system disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple. For related parts, reference can be made to the description in the method section.
[0078] Finally, it should be noted that the above embodiments are only specific implementation manners of the present invention, used to illustrate the technical solutions of the present invention, rather than to limit it. The protection scope of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: Any person skilled in the art within the technical scope disclosed by the present invention can still modify the technical solutions recorded in the foregoing embodiments, or can easily think of changes, or perform equivalent replacements for some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims
1. A method for testing a semiconductor device, characterized in that: The following steps are involved: Obtain the type of semiconductor device to be tested, the type of test tool kit and the type of test element of the semiconductor test workstation; Constructing an objective function that meets the test requirements based on the type of the semiconductor device to be tested, the type of the test tool kit, and the type of the test element; A test allocation model is constructed based on the objective function, and an optimal test resource combination is selected based on the test allocation model to perform semiconductor resource testing.
2. The method for testing a semiconductor device according to claim 1, wherein: The objective function is used to describe the maximum satisfaction of the test requirements of all types of semiconductor devices, and the objective function is as follows: Among them, W j (1≤j≤n) represents the penalty coefficient of semiconductor device j, D j (1≤j≤n) represents the test requirement of semiconductor device j, Y j Indicates the number of tests completed on semiconductor devices.
3. The method for testing a semiconductor device according to claim 1, wherein: The process of selecting the optimal test resource combination for semiconductor resource testing based on the test allocation model includes: A test allocation problem for semiconductor devices based on a system state vector representation of a semiconductor test workstation; Obtain several test jobs and test resource combinations based on the synchronization resource selection rule, the minimum input-output ratio rule, the minimum weighted total resource occupancy rule, the minimum relative total resource occupancy rule, and the minimum weighted load test set optimization rule; The payback rates of several test resource combinations are calculated; and the test resource combination with the highest payback rate is used to test the semiconductor device.
4. The method for testing a semiconductor device according to claim 3, wherein: The system state vector is represented as follows: in, Indicates the type of job that the test machine i has completed the most recent test; T i (1≤i≤m) indicates the type of job that the test machine i is processing. If the test machine is in an idle state, it is represented by 0; Indicates the remaining processing time of the test machine i during the processing operation (if T i =0, then );H i (1≤i≤m) represents the type of test kit being used with tester i (if T i =0, then H i =0); U i (1≤i≤m) indicates the type of enabler component being used with tester i (if T i =0, then U i =0); z j,s represents the number of semiconductor devices of the jth type waiting to be tested in the sth process; represents the unmet requirements of the semiconductor device j under test; represents the number of unoccupied enabler components u at the current moment; τ represents the current moment.
5. The method for testing a semiconductor device according to claim 3, wherein: The method for calculating the rate of return of several test resource combinations is as follows: Among them, r(τ) represents the rate of return obtained between the t-1th moment and the tth moment, τ t-1 <τ≤τ t , Y j,t represents the number of completed tests of semiconductor j at time t, w j represents the penalty coefficient of semiconductor device j, D j Represents the test requirements of semiconductor device j.
6. A semiconductor device testing system, characterized in that: including a test statistics module and a test allocation module connected to each other; The test statistics module is used to obtain the types of semiconductor devices to be tested and the types of test tool kits and test components of semiconductor test workstations; The test allocation module is used to construct an objective function that meets the testing requirements of all types of semiconductor devices according to the type of semiconductor device to be tested, the type of test tool kit, and the type of test element, and to construct a test allocation model according to the objective function, and to select the optimal test resource combination for semiconductor resource testing according to the test allocation model.
7. The method for testing a semiconductor device according to claim 6, wherein: The test allocation module obtains the test requirements and the number of completed tests for each type of semiconductor device, and constructs a test objective function for the corresponding type of semiconductor device according to the test requirements and the number of completed tests; the objective function is shown in the following formula: Among them, W j (1≤j≤n) represents the penalty coefficient of semiconductor device j, D j (1≤j≤n) represents the test requirement of semiconductor device j, Y j Indicates the number of tests completed on semiconductor devices.
8. The method for testing a semiconductor device according to claim 6, wherein: The test allocation module describes the system status by obtaining the type of job that the tester has tested most recently, the remaining processing time of the job that the tester is processing, the type of test toolkit and enabler component type used in conjunction with the tester, the number of a certain type of semiconductor devices to be tested waiting to test a certain process, unmet test requirements of the semiconductor devices to be tested, and the number of enabler components that are not occupied at the current moment; and based on the system status, combined with the synchronization resource selection rule, the minimum input-output ratio rule, the minimum weighted total resource occupancy rule, the minimum relative total resource occupancy rule, and the minimum weighted load test set optimization rule, obtains several test jobs and test resource combinations, calculates the rate of return for several test resource combinations, and uses the test resource combination with the highest rate of return to test the corresponding type of semiconductor devices to be tested.
9. The method for testing a semiconductor device according to claim 8, wherein: The description of the system status is as follows: in, Indicates the type of job that the test machine i has completed the most recent test; T i (1≤i≤m) indicates the type of job that the test machine i is processing. If the test machine is in an idle state, it is represented by 0; Indicates the remaining processing time of the test machine i during the processing operation (if T i =0, then );H i (1≤i≤m) represents the type of test kit being used with tester i (if T i =0, then H i =0); U i (1≤i≤m) indicates the type of enabler component being used with tester i (if T i =0, then U i =0); z j,s represents the number of semiconductor devices of the jth type waiting to be tested in the sth process; represents the unmet requirements of the semiconductor device j under test; represents the number of unoccupied enabler components u at the current moment; τ represents the current moment.
10. The method for testing a semiconductor device according to claim 8, wherein: The test allocation module uses the following formula to calculate the rate of return for several test resource combinations: Among them, r(τ) represents the rate of return obtained between the t-1th moment and the tth moment, τ t-1 <τ≤τ t , Y j,t represents the number of completed tests of semiconductor j at time t, w j represents the penalty coefficient of semiconductor device j, D j Represents the test requirements of semiconductor device j.