Test method of multi-layer stacked chip and storage medium

Abstract

The invention discloses a multi-layer stacked chip test method and a storage medium, the test method provided by the invention is applied to test the performance of each layer of chip in the multi-layer stacked chips, and the test method transmits first data through a first data transmission channel to activate the nth layer of chip, and transmits the first data through a second data transmission channel to activate the nth layer of chip; and then the second data is transmitted through the second data transmission channel to test the performance of the activated chip, so that the situation that in the prior art, each layer of chip of the multi-layer stacked chips cannot be independently controlled and tested, and the test efficiency of the multi-layer stacked chips is reduced is avoided. According to the test method provided by the invention, the performance of each layer of chip in the multiple layers of stacked chips can be tested independently, the test efficiency of the multiple layers of stacked chips is improved, and the user experience of the test method provided by the invention is improved.

Description

Technical Field

[0001] This application relates to the technical field of multi-layer stacked chip testing, and particularly to a testing method and storage medium for multi-layer stacked chips. Background Art

[0002] HBM (High Bandwidth Memory) is a high-performance DRAM (Dynamic Random Access Memory) memory based on 3D (3 Dimensions) stack technology. Compared with traditional memory technologies, HBM has higher bandwidth and smaller size, and can be widely used in the fields of computers and artificial intelligence. Currently, with the development of computer application technologies, the demand for HBM is increasing. In order to meet the requirements for miniaturization and high performance of HBM, higher integration and more chip stacking layers are required for HBM. In the HBM formed by multi-layer chip stacking, it is more difficult to test the performance of each layer of chips in the HBM. Summary of the Invention

[0003] To solve the above technical problems, this application provides a testing method for multi-layer stacked chips, which is applied to test the performance of each layer of chips in the multi-layer stacked chips. The multi-layer stacked chips include N layers of chips stacked in sequence, a first data transmission channel, and a second data transmission channel. The testing method includes:

[0004] Transmit first data through the first data transmission channel to activate the nth layer of chips in the multi-layer stacked chips, where n is less than or equal to N and n is an integer greater than or equal to 1;

[0005] Transmit second data through the second data transmission channel, and determine that the performance of the nth layer of chips is normal after receiving a feedback signal;

[0006] Wherein, the feedback signal is the signal fed back after the nth layer of chips receives the second data.

[0007] Wherein, the first data includes the characteristic information of the nth layer of chips. The step of transmitting the first data through the first data transmission channel to activate the first chips in the multi-layer stacked chips includes:

[0008] Transmit the first data through the first data transmission channel, so that the nth layer of chips receives the first data based on the characteristic information and activates the nth layer of chips.

[0009] Among them, the multi-layer stacked chip includes a plurality of second data transmission channels, each chip includes a plurality of switches, the plurality of switches correspond to the plurality of second data transmission channels one by one, and each switch is used to connect the corresponding second data transmission channel to the chip;

[0010] Among them, the first data further includes switch information. To enable the nth layer chip to receive the first data based on the feature information, the step of activating the nth layer chip further includes:

[0011] Controlling the first switch in the chip to close based on the first data, so that the second data transmission channel corresponding to the first switch is connected to the chip; where the first switch is one of the plurality of switches.

[0012] Among them, the step of transmitting the second data through the second data transmission channel and determining that the performance of the nth layer chip is normal after receiving the feedback signal includes:

[0013] Transmitting the second data to the nth layer chip through the second data transmission channel corresponding to the first switch, so that the nth layer chip receives the second data and sends a feedback signal.

[0014] Among them, the feature information includes the voltage information of the nth layer chip. The step of transmitting the first data through the first data transmission channel to activate the nth layer chip in the multi-layer stacked chip includes:

[0015] Transmitting the first data through the first data transmission channel, so that the nth layer chip corresponding to the activation voltage and the voltage information is activated.

[0016] Among them, the test method further includes:

[0017] If the feedback signal is not received within the preset time, it is determined that the performance of the nth layer chip is abnormal.

[0018] Among them, the test method further includes:

[0019] If the feedback signal is not received within the preset time, then after transmitting the first data through the first data transmission channel for the second time, transmit the second data through the second data transmission channel for the second time; where the first data includes the feature information of the (n + 1)th layer chip, and n + 1 is less than or equal to N;

[0020] In response to receiving the feedback signal, it is determined that the performance of the nth layer chip is abnormal.

[0021] Among them, the test method further includes:

[0022] In response to the feedback signal of the (n + 1)-th layer chip not being received within the preset time, after the first data is transmitted through the first data transmission channel for the third time, the second data is transmitted through the second data transmission channel for the third time; wherein, the first data includes the characteristic information of the (n - 1)-th layer chip.

[0023] In response to receiving the feedback signal of the (n - 1)-th layer chip, it is determined that the section of the second data transmission channel corresponding to the n-th layer chip is abnormal.

[0024] Wherein, the multi-layer stacked chip further includes a third data transmission channel, the third data transmission channel is arranged adjacent to the second data transmission channel, and the third data transmission channel is connected to all the chips in the multi-layer stacked chip;

[0025] After the step of determining that the section of the second data transmission channel corresponding to the n-th layer chip is abnormal, the test method further includes:

[0026] Transmit the second data through the third data transmission channel to test the performance of each layer of chip in the multi-layer stacked chip.

[0027] To solve the above technical problems, the present application also provides a computer-readable storage medium, the computer-readable storage medium includes program data, and the program data is executed by a processor to implement the test method as described above.

[0028] Beneficial effects of the present application: Different from the prior art, the test method of the multi-layer stacked chip provided by the present application is applied to test the performance of each layer of chip in the multi-layer stacked chip. The multi-layer stacked chip includes N layers of chips stacked in sequence, a first data transmission channel, and a second data transmission channel. Among them, the test method includes: transmitting the first data to the multi-layer stacked chip through the first data transmission channel to activate the n-th layer chip in the multi-layer stacked chip; then transmitting the second data to the multi-layer stacked chip through the second data transmission channel, and after receiving the feedback signal, determining that the performance of the n-th layer chip is normal. Transmitting the first data through the first data transmission channel activates the n-th layer chip first, and then transmitting the second data through the second data transmission channel to test the performance of the activated chip, avoiding the situation in the prior art where each layer of chip in the multi-layer stacked chip cannot be individually controlled and tested, and reducing the test efficiency of the multi-layer stacked chip. The test method of the present application can individually test the performance of each layer of chip in the multi-layer stacked chip, improve the test efficiency of the multi-layer stacked chip, and enhance the user experience of using the test method provided by the present application. Description of the Drawings

[0029] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0030] Among them:

[0031] Figure 1 is a schematic structural diagram of an embodiment of a multi-layer stacked chip of the present application;

[0032] Figure 2 is a schematic flowchart of a first embodiment of the test method for a multi-layer stacked chip of the present application;

[0033] Figure 3 is a schematic flowchart of a second embodiment of the test method for a multi-layer stacked chip of the present application;

[0034] Figure 4 is a schematic structural diagram of an embodiment of a computer-readable storage medium of the present application.

[0035] Reference numerals in the drawings: multi-layer stacked chip A; chip 1; first data transmission channel 2; second data transmission channel 3; logic chip 4. Detailed implementation manners

[0036] The following will detail the solutions of the embodiments of the present application in conjunction with the accompanying drawings of the specification.

[0037] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system structures, interfaces, and technologies are proposed to thoroughly understand the present application.

[0038] Referring to "embodiment" in the present application means that the specific features, structures, or characteristics described in conjunction with the embodiment can be included in at least one embodiment of the present application. The phrase appears at various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0039] In this application, the term "and / or" is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, in this text, the character " / " generally indicates that the associated objects before and after are in an "or" relationship. Furthermore, "multiple" in this text means two or more than two. Additionally, the term "at least one" in this text means any one of multiple types or any combination of at least two of multiple types. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set composed of A, B, and C. Additionally, the terms "first", "second", and "third" in this application are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features.

[0040] With the development of computer application technology, the demand for HBM is getting higher and higher. To meet the requirements for miniaturization and high performance of HBM, higher integration of HBM and more stacking layers of chips are required. In the HBM formed by stacking multiple layers of chips, it is more difficult to test the performance of each layer of chips in the HBM. To solve the above technical problems, this application provides a testing method for multi-layer stacked chips, which can test the performance of each layer of chips in the multi-layer stacked chips and improve the testing efficiency of the multi-layer stacked chips.

[0041] Specifically, please refer to Figure 1 , Figure 1 which is a schematic structural diagram of an embodiment of the multi-layer stacked chips in this application. The multi-layer stacked chips A provided by the embodiments of this application include N layers of chips 1, a first data transmission channel 2, and a second data transmission channel 3 stacked in sequence. Among them, the chip 1 can be a DRAM chip; the first data transmission channel 2 and the second data transmission channel 3 can be channels formed by the Through Silicon Via (TSV) technology, and the multi-layer stacked chips A can be HBM.

[0042] It can be understood that Figure 1 in the multi-layer stacked chips A including four chips 1 stacked in sequence is only an example, and this application does not limit the number of stacked chips 1.

[0043] Optionally, please continue to refer to Figure 2 , Figure 2 which is a schematic flowchart of the first embodiment of the testing method for the multi-layer stacked chips in this application. The testing method for the multi-layer stacked chips A provided by the embodiments of this application specifically includes the following steps:

[0044] S1: Transmit the first data to the multi-layer stacked chips A through the first data transmission channel 2 to activate the nth layer of chips 1 in the multi-layer stacked chips A.

[0045] Among them, as Figure 1 shown, the multi-layer chips 1 can be stacked on the logic chip 4 in sequence and connected to the logic chip 4 through TSVs. Furthermore, an external control unit (not shown in the figure) can drive the logic chip 4 to transmit first data to the nth layer chip 1 of the multi-layer stacked chip A through the first data transmission channel 2 to activate the nth layer chip 1 in the multi-layer stacked chip A. Among them, n is less than or equal to N and n is an integer greater than or equal to 1.

[0046] S2: Transmit second data to the multi-layer stacked chip A through the second data transmission channel 3, and determine that the performance of the nth layer chip 1 is normal after receiving the feedback signal.

[0047] Specifically, the control unit can drive the logic chip 4 to transmit second data to the multi-layer stacked chip A through the second data transmission channel 3. The second data can be test data of the chip 1 to test whether the performance of the chip 1 is normal. Since the nth layer chip 1 in the multi-layer stacked chip A has been activated when step S1 is executed, and the other chips 1 in the multi-layer stacked chip A have not been activated, when the logic chip 4 transmits the second data through the second data transmission channel 3, only the activated nth layer chip 1 will receive the second data, and the other unactivated chips 1 will not respond to the second data.

[0048] After the nth layer chip 1 receives the second data, if the performance of the nth layer chip 1 is normal, it will send a feedback signal to the logic chip 4 after receiving the second data signal. The logic chip 4 then conveys the information of the received feedback signal to the control unit. That is, after the control unit responds to receiving the feedback signal, it determines that the performance of the nth layer chip 1 is normal.

[0049] If the performance of the nth layer chip 1 is abnormal, it may be that the nth layer chip 1 cannot receive the second data or cannot respond to the received second data. The nth layer chip 1 will not send a feedback signal, then the control unit can determine that the performance of the nth layer chip 1 is abnormal when it does not receive a feedback signal within a preset time. Among them, the preset time can be 0.5 s, 1 s, etc., which can be set by the user himself / herself, and this application does not limit this.

[0050] In the test method provided in this embodiment, one layer of the chips 1 in the multi-layer stacked chip A is first activated, and then the specific layer of the chips 1 in the multi-layer stacked chip A can be tested, improving the test efficiency of the multi-layer stacked chip A.

[0051] Currently, in the HBM formed by chip stacking through TSV technology, the data channels formed by TSV cannot transmit data to the chips of a specific layer, that is, it is impossible to individually control and test the chips of a specific layer in the HBM. Therefore, in the prior art, multiple bare chips are generally individually tested first and then the tested bare chips are stacked and packaged to form the HBM. However, during the process of stacking and packaging the bare chips, the performance of the bare chips may also be damaged. Therefore, the performance of the packaged HBM cannot be accurately obtained. In this application, since the chips of a specific layer 1 in the multi-layer stacked chip A can be tested, that is, this application realizes testing the performance of the chips of layer 1 of each layer after chip stacking and packaging, improving the performance of the packaged HBM.

[0052] Meanwhile, in the prior art, in order to achieve individual control of the single-layer chips in the HBM, bonding wires can also be used. Bonding wires are connected in each layer of chips, and the chips are individually controlled through the bonding wires. However, when the number of chips increases, the number of bonding wires correspondingly increases, resulting in a chaotic layout of the bonding wires. Therefore, the number of chips in the HBM is limited.

[0053] This application realizes individual control and testing of the chips of layer 1 of each layer in the multi-layer stacked chip A formed by chip stacking through TSV technology. Without the participation of bonding wires, the stacking layers of the chips of layer 1 in the multi-layer stacked chip A can also be increased, improving the performance of the multi-layer stacked chip A, enhancing the practicability of the testing method provided in this embodiment, and improving the user experience of using the testing method.

[0054] Optionally, if the first data includes the characteristic information of the chip of layer n of layer 1, then the specific steps of transmitting the first data to the multi-layer stacked chip A through the first data transmission channel 2 in step S1 to activate the chip of layer n of layer 1 in the multi-layer stacked chip A include:

[0055] S11: Transmit the first data through the first data transmission channel 2, so that the chip of layer n of layer 1 receives the first data based on the characteristic information and activates the chip of layer n of layer 1.

[0056] Among them, the characteristic information of the chip of layer n of layer 1 can be the ID of the chip of layer n of layer 1. Furthermore, when the control unit controls the logic chip 4 to transmit the first data through the first data transmission channel 2, since the first data includes the ID of the chip of layer n of layer 1, the chip of layer n of layer 1 can receive the first data based on the characteristic information to activate the chip of layer n of layer 1.

[0057] Optionally, the multi-layer stacked chip A includes a plurality of second data transmission channels 3, each chip of layer 1 includes a plurality of switches, and the plurality of switches correspond to the plurality of second data transmission channels 3 one by one. Each switch is used to connect the corresponding second data transmission channel 3 to the chip of layer 1.

[0058] If the first data further includes switch information, then the step of activating the nth layer chip 1 by enabling the nth layer chip 1 to receive the first data based on the feature information in step S11 further includes the following steps:

[0059] S111: Control the first switch in the chip 1 to close based on the first data, so that the second data transmission channel 3 corresponding to the first switch is connected to the chip 1. Wherein, the first switch is one of multiple switches.

[0060] Wherein, the first data further includes switch information, such as Figure 1 switch K1, switch K2, switch K3 or switch K4 in [[]], etc. Further, after the chip 1 receives the first data, the corresponding switch can be controlled to close based on the first data. For example, if the first data contains the information of switch K2 (the first switch), then after the chip 1 receives the first data, the switch K2 on the chip 1 closes, so that the second data transmission channel 3 corresponding to the switch K2 is connected to the chip 1, that is, at this time, the chip 1 is activated.

[0061] Then the control unit can drive the logic chip 4 to transmit the second data to the corresponding chip 1 through the second data transmission channel 3 corresponding to the switch K2 to control and test the chip 1.

[0062] In one embodiment, since the connection between the chip 1 and the second data transmission channel 3 is controlled by multiple switches on the chip 1, therefore, when the control unit responds to the abnormal performance of the chip in a specific layer, there is no need to disassemble the chip 1 from the packaged multi-layer stacked chip A. It only needs to open all the switches on the chip 1 to remove the chip 1, reducing the operation steps and difficulty, and improving the user experience of using the multi-layer stacked chip A.

[0063] In another embodiment, as Figure 1 described, the multi-layer stacked chip A includes multiple second data transmission channels 3, then the control unit can drive the logic chip 4 to transmit the first data through the first data transmission channel 2 to respectively activate the connection between different layers of chips and different second data transmission channels 3. For example, but not limited to, activating the connection between the switch K1 of the first layer chip 1 and the corresponding second data transmission channel 3, activating the connection between the switch K2 of the second layer chip 1 and the corresponding second data transmission channel 3, activating the connection between the switch K3 of the third layer chip 1 and the corresponding second data transmission channel 3, and activating the connection between the switch K4 of the fourth layer chip 1 and the corresponding second data transmission channel 3. Wherein, the first layer chip 1 is the bottom chip 1 in the multi-layer stacked chips 1, the second layer chip 1 is the chip 1 directly stacked on the first layer chip 1, the third layer chip 1 is the chip 1 directly stacked on the second layer chip 1, and the fourth layer chip 1 is the top chip 1 in the multi-layer stacked chips 1.

[0064] Then, the control unit can drive the logic chip 4 to simultaneously control and test the chips 1 of different layers through different second data transmission channels 3, improving the test efficiency of the multi-layer stacked chip A.

[0065] It can be understood that the number of the second data transmission channels 3 can be the same as the number of the stacked chips 1 in the multi-layer stacked chip A, so that the control unit can control and test all the chips 1 in the multi-layer stacked chip A at one time.

[0066] Optionally, the step of transmitting the second data through the second data transmission channel 3 in step S2 and determining that the performance of the chip 1 of the nth layer is normal after receiving the feedback signal specifically includes:

[0067] S21: Transmit the second data to the chip 1 of the nth layer through the second data transmission channel 3 corresponding to the first switch, so that the chip 1 of the nth layer receives the second data and sends out a feedback signal.

[0068] Specifically, after the first data closes the first switch on the chip 1 of the nth layer and connects the second data transmission channel 3 corresponding to the first switch to the chip 1 of the nth layer, the control unit drives the logic chip 4 to transmit the second data to the chip 1 of the nth layer through the second data transmission channel 3 corresponding to the first switch. After the chip 1 of the nth layer receives the second data, if the chip 1 of the nth layer has normal performance, it will send out a feedback signal based on the second data. When the control unit responds to the feedback signal sent by the chip 1 of the nth layer, it is determined that the chip 1 of the nth layer has normal performance.

[0069] Optionally, the characteristic information may include the voltage information of the chip 1 of the nth layer. Among them, each layer of the chip 1 in the multi-layer stacked chip A may have different activation voltages. For example, but not limited to, the activation voltage of the chip 1 of the first layer is 1 mV, the activation voltage of the chip 1 of the second layer is 2 mV, etc. Then, in step S11, the step of activating the chip 1 of the nth layer so that the chip 1 of the nth layer receives the first data based on the characteristic information may further include the following steps:

[0070] S112: Transmit the first data through the first data transmission channel 2, so that the chip 1 of the nth layer with the activation voltage corresponding to the voltage information is activated.

[0071] As described above, different chips 1 in the multi-layer stacked chip A have different activation voltages, so the characteristic information may include the voltage information of the corresponding chip 1 to activate the chip 1 of a specific layer. For example, if the voltage information included in the characteristic information is 1 mV, the chip 1 of the first layer with the activation voltage of 1 mV can be activated, and the chips 1 with other activation voltages will not be activated. Thus, the control unit can separately control and test the chip 1 of a specific layer, improving the test efficiency of the multi-layer stacked chip A.

[0072] It can be understood that when the control module determines that the performance of the chip 1 in a certain layer is abnormal, the control unit can control the voltage information corresponding to the activation voltage of the chip 1 whose feature information does not include the abnormality. That is, the chip 1 will no longer be activated, so as to remove the chip 1 with abnormal performance in the multi-layer stacked chip A.

[0073] In summary, the testing method provided by this application first activates the chip 1 in the nth layer of the multi-layer stacked chip A, and then individually controls and tests the chip 1 in the nth layer. There may be unknowable damages to the tested chips during the packaging process in the prior art. However, the testing method of this application allows the chip 1 to be tested after packaging, improving the testing efficiency of the chip 1, increasing the yield rate of the multi-layer stacked chip A. At the same time, by removing the activation conditions of the chip 1 with abnormal performance, the operation of removing the abnormal chip 1 in the multi-layer stacked chip A is realized, simplifying the removal steps of the chip 1 with abnormal performance, reducing the manufacturing difficulty of the multi-layer stacked chip 1, and improving the user experience of the multi-layer stacked chip A and the testing method.

[0074] Optionally, please continue to refer to Figure 3 , Figure 3 which is a schematic flowchart of the second embodiment of the testing method for the multi-layer stacked chip of this application. In step S2, if the control unit does not receive a feedback signal within the preset time, the testing method provided by the embodiment of this application may further include the following steps:

[0075] S31: If no feedback signal is received within the preset time, then the first data is transmitted through the first data transmission channel 2 for the second time, and the second data is transmitted through the second data transmission channel 3 for the second time, where the first data includes the feature information of the chip 1 in the (n + 1)th layer.

[0076] Among them, if the control unit does not receive a feedback signal within the preset time, in addition to the abnormal performance of the chip 1 in the nth layer, it is also possible that the second data transmission channel 3 is abnormal, resulting in the second data not being transmitted to the chip 1 in the nth layer. Therefore, after the control unit does not receive a feedback signal, the control unit can drive the logic chip 4 to transmit the first data through the first data transmission channel 2 for the second time, where the first data includes the feature information of the chip 1 in the (n + 1)th layer, and n + 1 is less than or equal to N.

[0077] That is, the first data at this time is used to activate the chip 1 in the (n + 1)th layer, and then the control unit further transmits the second data through the second data transmission channel 3 for the second time. If the control unit can receive the feedback signal of the chip 1 in the (n + 1)th layer, it enters step S32; if the control unit cannot receive the feedback signal of the chip 1 in the (n + 1)th layer, it enters steps S33 - S34.

[0078] S32: In response to receiving the feedback signal, it is determined that the performance of the nth layer of chip 1 is abnormal.

[0079] Specifically, since the situation where the performance of two consecutive layers of chip 1 is abnormal is extremely rare, it is defaulted that the performance of the (n + 1)th layer of chip 1 is normal. Therefore, if the control unit responds to receiving the feedback signal of the (n + 1)th layer of chip 1, it is determined that the second data transmission channel 3 can transmit the second data to the (n + 1)th layer of chip 1, that is, the second data transmission channel 3 is normal, and then it is determined that the performance of the nth layer of chip 1 is abnormal.

[0080] S33: In response to not receiving the feedback signal of the (n + 1)th layer of chip 1 within the preset time, after the first data is transmitted through the first data transmission channel 2 for the third time, the second data is transmitted through the second data transmission channel 3 for the third time, where the first data includes the characteristic information of the (n - 1)th layer of chip 1.

[0081] Among them, since the situation where the performance of two consecutive layers of chip 1 is abnormal is extremely rare, if the feedback signal of the (n + 1)th layer of chip 1 is not received within the preset time, it is highly probable that the second data transmission channel 3 is abnormal, and the control unit further confirms it.

[0082] The control unit can drive the logic chip 4 to transmit the first data through the first data transmission channel 2 for the third time, where the first data includes the characteristic information of the (n - 1)th layer of chip 1. That is, the first data at this time is used to activate the (n - 1)th layer of chip 1, and then the control unit further transmits the second data through the second data transmission channel 3 for the third time to determine whether the second data transmission channel 3 is sectionally abnormal or overall abnormal, and enters step S34.

[0083] S34: In response to receiving the feedback signal of the (n - 1)th layer of chip 1, it is determined that the section of the second data transmission channel 3 corresponding to the nth layer of chip 1 is abnormal.

[0084] Specifically, it is defaulted that the performance of the (n - 1)th layer of chip is normal. If the control unit responds to receiving the feedback signal of the (n - 1)th layer of chip 1, it is determined that the second data transmission channel 3 can transmit the second data to the (n - 1)th layer of chip 1. Therefore, it is determined that the section of the second data transmission channel 3 corresponding to the nth layer of chip 1 is abnormal.

[0085] If the control unit responds to not receiving the feedback signal of the (n - 1)th layer of chip 1 within the preset time, it is determined that the second data transmission channel 3 is overall abnormal.

[0086] In one embodiment, when a multi-layer stacked chip A includes a plurality of second data transmission channels 3 and each layer of chip 1 includes a plurality of switches, it is also possible that the control unit drives the logic chip 4 to transmit the first data through the first data transmission channel 2 for the second time, where the first data includes the characteristic information of the nth layer of chip 1, and the characteristic information includes the second switch of the nth layer of chip 1 (it is default that the first data transmitted for the first time includes the characteristic information of the nth layer of chip 1, and the characteristic information includes the first switch), where the second switch is any one of the plurality of switches except the first switch. Then the control unit further drives the logic chip 4 to transmit the second data through the second data transmission channel 3 corresponding to the second switch. If a feedback signal is received in response, it is determined that the performance of the nth layer of chip 1 is normal and the second data transmission channel 3 corresponding to the first switch is abnormal; if no feedback signal is received within a preset time in response, it is determined that the second data transmission channel 3 is normal and the performance of the nth layer of chip 1 is abnormal.

[0087] In summary, by testing the upper and lower layers of the nth layer of chip 1, it is determined whether the performance of the nth layer of chip 1 or the second data transmission channel 3 is abnormal when the control unit cannot receive the feedback signal, improving the test efficiency of the chips of the multi-layer stacked chip A in the test method of the present application and enhancing the user experience of using the test method.

[0088] Optionally, the multi-layer stacked chip A may further include a third data transmission channel (not shown in the figure). The third data transmission channel is disposed adjacent to the second data transmission channel 3, and the third data transmission channel is connected to all the chips 1 in the multi-layer stacked chip A. Further, after the control unit determines that the second data transmission channel 3 is abnormal in step S34, the test method provided by the embodiment of the present application specifically further includes the following steps:

[0089] S341: Transmit the second data through the third data transmission channel to test the performance of each layer of chip 1 in the multi-layer stacked chip A.

[0090] Wherein, the third data transmission channel is a backup channel of the second data transmission channel 3, that is, when the control unit determines that the second data transmission channel 3 is abnormal, the control unit can drive the logic chip 4 to transmit the second data to each layer of chip 1 in the multi-layer stacked chip A through the third data transmission channel to test each layer of chip 1.

[0091] By setting up a backup data transmission channel, the normal transmission of the second data can still be achieved when the second data transmission channel 3 is abnormal, improving the stability of the multi-layer stacked chip A and enhancing the user experience of using the multi-layer stacked chip A.

[0092] In summary, the test method provided by this application realizes the individual control and testing of each layer of chip 1 in the multi-layer stacked chip A formed by chip stacking using the TSV technology. Without the participation of bonding wires in the operation, it is also possible to increase the stacking layers of chip 1 in the multi-layer stacked chip A, improve the performance of the multi-layer stacked chip A, enhance the practicability of the test method provided in this embodiment, and improve the user experience of using the test method.

[0093] To solve the above technical problems, this application also provides a computer-readable storage medium. Refer to Figure 4 , Figure 4 which is a schematic structural diagram of an embodiment of the computer-readable storage medium of this application. As shown in Figure 4 , the computer-readable storage medium 4 includes program data 41. When the program data 41 is executed by a processor (not shown in the figure), it realizes the test method in the above embodiment.

[0094] The computer-readable storage medium 4 in this embodiment may be, but is not limited to, a USB flash drive, an SD card, a PD optical drive, a mobile hard disk, a high-capacity floppy drive, a flash memory, a multimedia memory card, a server, a storage unit in an FPGA or an ASIC, etc.

[0095] The above description is only the implementation manner of this application, and does not limit the patent scope of this application. Any equivalent structural or equivalent process transformation made by using the content of the specification and drawings of this application, or directly or indirectly applied to other related technical fields, shall be equally included in the patent protection scope of this application.

Claims

1. A method for testing a multi-layer stacked chip, characterized in that: The method is applied to testing the performance of each layer of a multi-layer stacked chip, wherein the multi-layer stacked chip comprises N layers of chips stacked in sequence, a first data transmission channel, and a second data transmission channel, and the testing method comprises: Transmitting first data through the first data transmission channel to activate the nth layer chip in the multi-layer stacked chip, where n is less than or equal to N, and n is an integer greater than or equal to 1; transmitting second data through the second data transmission channel, and determining that the performance of the nth layer chip is normal after receiving a feedback signal; The feedback signal is a signal fed back by the n-th layer chip after receiving the second data.

2. The testing method according to claim 1, characterized in that: The first data includes characteristic information of the nth layer chip, and the step of transmitting the first data through the first data transmission channel to activate the first chip in the multi-layer stacked chips includes: The first data is transmitted through the first data transmission channel, so that the n-th layer chip receives the first data based on the characteristic information and activates the n-th layer chip.

3. The testing method according to claim 2, characterized in that: The multi-layer stacked chip includes a plurality of second data transmission channels, each of the chips includes a plurality of switches, the plurality of switches correspond to the plurality of second data transmission channels one by one, and each of the switches is used to connect the corresponding second data transmission channel with the chip; The first data further includes switch information, and the step of activating the n-layer chip by enabling the n-layer chip to receive the first data based on the characteristic information further includes: A first switch in the chip is controlled to be closed based on the first data, so that the second data transmission channel corresponding to the first switch is connected to the chip; wherein the first switch is one of the multiple switches.

4. The testing method according to claim 3, characterized in that: The step of transmitting the second data through the second data transmission channel and determining that the performance of the n-th layer chip is normal after receiving a feedback signal includes: The second data is transmitted to the n-th layer chip through the second data transmission channel corresponding to the first switch, so that the n-th layer chip receives the second data and sends a feedback signal.

5. The testing method according to claim 2, characterized in that: The characteristic information includes voltage information of the n-th layer chip, and the step of transmitting the first data through the first data transmission channel to activate the n-th layer chip in the multi-layer stacked chip includes: The first data is transmitted through the first data transmission channel, so that the n-th layer chip corresponding to the activation voltage of the voltage information is activated.

6. The testing method according to claim 1, characterized in that: The test method also includes: If the feedback signal is not received within a preset time, it is determined that the performance of the n-th layer chip is abnormal.

7. The testing method according to claim 1, characterized in that: The test method also includes: If the feedback signal is not received within the preset time, the first data is transmitted for the second time through the first data transmission channel, and then the second data is transmitted for the second time through the second data transmission channel; wherein the first data includes characteristic information of the n+1th layer chip, and n+1 is less than or equal to N; In response to receiving the feedback signal, it is determined that the performance of the n-th layer chip is abnormal.

8. The testing method according to claim 7, characterized in that: The test method also includes: In response to not receiving a feedback signal from the chip at the n+1th layer within the preset time, transmitting the first data through the first data transmission channel for the third time, and then transmitting the second data through the second data transmission channel for the third time; wherein the first data includes characteristic information of the chip at the n-1th layer; In response to receiving the feedback signal of the n-1th layer chip, it is determined that the section of the second data transmission channel corresponding to the nth layer chip is abnormal.

9. The testing method according to claim 8, characterized in that: The multi-layer stacked chip further includes a third data transmission channel, the third data transmission channel is arranged adjacent to the second data transmission channel, and the third data transmission channel is connected to all the chips in the multi-layer stacked chip; After the step of determining that the section of the second data transmission channel corresponding to the n-th layer chip is abnormal, the testing method further includes: The second data is transmitted through the third data transmission channel to test the performance of each layer of chips in the multi-layer stacked chips.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes program data, and the program data is executed by a processor to implement the testing method according to any one of claims 1 to 9.

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