Chip testing method and device, electronic equipment and computer readable storage medium

Abstract

The embodiment of the invention provides a chip testing method and device, electronic equipment and a computer readable storage medium. The chip testing method comprises the steps that chip mark information of a to-be-tested chip is acquired; determining target application scene information of the to-be-tested chip according to the chip marking information and a preset application scene setting library; determining a target test parameter from a preset scene parameter setting library according to the target application scene information; testing the to-be-tested chip based on the target function test parameter to obtain a first test result; testing the to-be-tested chip based on the target performance test parameter to obtain a second test result; testing the to-be-tested chip based on the target reliability test parameter to obtain a third test result; and determining a chip test result of the to-be-tested chip according to the first test result, the second test result and the third test result. According to the scheme of the embodiment of the invention, the chip test can be more reasonable.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and particularly relates to a chip testing method, device, electronic device and computer-readable storage medium. Background Art

[0002] Chip testing refers to a series of physical and electrical tests performed after a chip is manufactured to ensure that the functions and performance of the chip meet the design requirements, while detecting and eliminating any possible problems or defects. Chip testing is an important link to ensure the quality and reliability of chips, and it includes tests in multiple aspects. However, during the application of chips in various scenarios, there may be different functional and performance requirements. If all chips are tested according to a unified standard, the pass rate of chip testing will decrease. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art.

[0004] To this end, the present invention provides a chip testing method, which can select the test parameters of the chip according to different application scenarios, and effectively avoid the problem of the decrease in the pass rate of chip testing caused by the unified standard.

[0005] The present invention also provides a device applying the above chip testing method.

[0006] The present invention also provides an electronic device applying the above chip testing method.

[0007] The present invention also provides a computer-readable storage medium applying the above chip testing method.

[0008] The chip testing method according to the first aspect embodiment of the present invention includes:

[0009] Obtaining chip marking information of the chip to be tested;

[0010] Determining the target application scenario information of the chip to be tested according to the chip marking information and a preset application scenario setting library;

[0011] Determining target test parameters from a preset scenario parameter setting library according to the target application scenario information, where the target test parameters include target function test parameters, target performance test parameters and target reliability test parameters;

[0012] Testing the chip to be tested based on the target function test parameters to obtain a first test result; and, testing the chip to be tested based on the target performance test parameters to obtain a second test result; and, testing the chip to be tested based on the target reliability test parameters to obtain a third test result;

[0013] Determine the chip test result of the chip to be tested based on the first test result, the second test result, and the third test result.

[0014] According to some embodiments of the present invention, the application scenario setting library includes marker type information and application scenario information corresponding one-to-one to the marker type information. Determining the target application scenario information of the chip to be tested according to the chip marker information and the preset application scenario setting library includes:

[0015] Perform a matching process on the chip marker information and the marker type information of the application scenario setting library to obtain target marker type information;

[0016] Determine the application scenario information corresponding to the target marker type information as the target application scenario information.

[0017] According to some embodiments of the present invention, the scenario parameter setting library includes scenario type information and test parameters corresponding to the scenario type information. Determining the target test parameters from the preset scenario parameter setting library according to the target application scenario information includes:

[0018] Perform a matching process on the target application scenario information and the scenario type information of the scenario parameter setting library to obtain target scenario type information;

[0019] Determine the test parameters corresponding to the target scenario type information as the target test parameters.

[0020] According to some embodiments of the present invention, testing the chip to be tested based on the target functional test parameters to obtain a first test result includes:

[0021] Generate a first test signal according to the target functional test parameters;

[0022] Input the first test signal into the chip to be tested to perform a test process on the chip to be tested, and obtain the first test result.

[0023] According to some embodiments of the present invention, testing the chip to be tested based on the target performance test parameters to obtain a second test result includes:

[0024] Determine the clock frequency, power consumption, data processing rate, data transmission rate, and detection temperature from the target performance test parameters;

[0025] Perform a test process on the chip to be tested respectively based on the clock frequency, the power consumption, the data processing rate, the data transmission rate, and the detection temperature, and obtain the second test result.

[0026] According to some embodiments of the present invention, testing the chip under test based on the target reliability test parameters to obtain a third test result includes:

[0027] Determining a temperature control threshold, a humidity control threshold, and mechanical stress information from the target reliability test parameters;

[0028] Performing test processing on the chip under test based on the temperature control threshold, the humidity control threshold, and the mechanical stress information respectively to obtain the third test result.

[0029] According to some embodiments of the present invention, determining the chip test result of the chip under test based on the first test result, the second test result, and the third test result includes:

[0030] When the first test result, the second test result, and the third test result all indicate that the chip under test is normal, taking the chip test as normal as the chip test result;

[0031] When at least one of the first test result, the second test result, and the third test result indicates that the chip under test is abnormal, taking the chip test as abnormal as the chip test result.

[0032] A chip testing device according to an embodiment of the second aspect of the present invention includes:

[0033] A first processing unit for obtaining chip marking information of the chip under test;

[0034] A second processing unit for determining the target application scenario information of the chip under test according to the chip marking information and a preset application scenario setting library;

[0035] A third processing unit for determining target test parameters from a preset scenario parameter setting library according to the target application scenario information, where the target test parameters include target function test parameters, target performance test parameters, and target reliability test parameters;

[0036] A fourth processing unit for testing the chip under test based on the target function test parameters to obtain a first test result; and testing the chip under test based on the target performance test parameters to obtain a second test result; and testing the chip under test based on the target reliability test parameters to obtain a third test result;

[0037] A fifth processing unit for determining the chip test result of the chip under test according to the first test result, the second test result, and the third test result.

[0038] An electronic device according to an embodiment of the third aspect of the present invention includes:

[0039] A memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the computer program, the chip testing method described above is implemented.

[0040] A computer-readable storage medium according to an embodiment of the fourth aspect of the present invention stores computer-executable instructions, and when the computer-executable instructions are executed by a control processor, the chip testing method described above is implemented.

[0041] The chip testing method according to the embodiments of the present invention has at least the following beneficial effects: In the process of chip testing, first obtain the chip marking information of the chip to be tested; then determine the target application scenario information of the chip to be tested according to the chip marking information and the preset application scenario setting library; then determine the target test parameters from the preset scenario parameter setting library according to the target application scenario information, where the target test parameters include target function test parameters, target performance test parameters, and target reliability test parameters; then test the chip to be tested based on the target function test parameters to obtain a first test result; and test the chip to be tested based on the target performance test parameters to obtain a second test result; and test the chip to be tested based on the target reliability test parameters to obtain a third test result; finally, the chip test result of the chip to be tested can be determined according to the first test result, the second test result, and the third test result; through the above technical solution, determine the target application scenario information of the chip to be tested according to the application scenario setting library, and then determine the target test parameters according to the scenario parameter setting library, so that different chips to be tested will correspond to corresponding target test parameters, so that the chip testing process is more in line with the specific usage scenario, and well eliminates the problem of reduced chip testing qualification rate caused by a unified standard, and improves the qualification rate of the chip.

[0042] Other features and advantages of the present invention will be described in the subsequent description, and part of them will become obvious from the description, or will be understood by implementing the present invention. The objectives and other advantages of the present invention can be realized and obtained through the structures specifically pointed out in the description, the claims, and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings are used to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the description. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure.

[0044] Figure 1 It is a flowchart of the chip testing method provided by an embodiment of the present invention;

[0045] Figure 2 is a sub - flowchart of step S200;

[0046] Figure 3 is a sub - flowchart of step S300;

[0047] Figure 4 is the first sub - flowchart of step S400;

[0048] Figure 5 is the second sub - flowchart of step S400;

[0049] Figure 6 is the third sub - flowchart of step S400;

[0050] Figure 7 is a sub - flowchart of step S500;

[0051] Figure 8 is a schematic structural diagram of a chip testing device provided by an embodiment of the present invention;

[0052] Figure 9 is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0053] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0054] In the description of the present invention, the meaning of several is one or more, the meaning of multiple is two or more, greater than, less than, exceeding, etc. are understood as not including the present number, above, below, within, etc. are understood as including the present number. If there is a description of first and second, it is only for the purpose of distinguishing technical features and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0055] In the description of the present invention, unless otherwise clearly defined, words such as setting, installation, connection, etc. should be understood in a broad sense, and those skilled in the technical field can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.

[0056] The present invention provides a chip testing method, device, electronic device, and computer-readable storage medium. During the process of chip testing, first, obtain the chip marking information of the chip to be tested; then, determine the target application scenario information of the chip to be tested according to the chip marking information and a preset application scenario setting library; then, determine the target test parameters from a preset scenario parameter setting library according to the target application scenario information, where the target test parameters include target function test parameters, target performance test parameters, and target reliability test parameters; then, test the chip to be tested based on the target function test parameters to obtain a first test result; and test the chip to be tested based on the target performance test parameters to obtain a second test result; and test the chip to be tested based on the target reliability test parameters to obtain a third test result; finally, the chip test result of the chip to be tested can be determined according to the first test result, the second test result, and the third test result; through the above technical solution, determine the target application scenario information of the chip to be tested according to the application scenario setting library, and then determine the target test parameters according to the scenario parameter setting library, so that different chips to be tested will correspond to corresponding target test parameters, making the chip testing process more in line with the specific usage scenarios, and effectively preventing the problem of reduced chip test pass rate caused by a unified standard, and improving the pass rate of chips.

[0057] The following further elaborates on the embodiments of the present invention with reference to the accompanying drawings.

[0058] Refer to Figure 1 , the flowchart of the chip testing method provided by an embodiment of the present invention. The method includes but is not limited to steps S100, S200, S300, S400, and S500:

[0059] Step S100, obtain the chip marking information of the chip to be tested;

[0060] Step S200, determine the target application scenario information of the chip to be tested according to the chip marking information and a preset application scenario setting library;

[0061] Step S300, determine the target test parameters from a preset scenario parameter setting library according to the target application scenario information, where the target test parameters include target function test parameters, target performance test parameters, and target reliability test parameters;

[0062] Step S400, test the chip to be tested based on the target function test parameters to obtain a first test result; and, test the chip to be tested based on the target performance test parameters to obtain a second test result; and, test the chip to be tested based on the target reliability test parameters to obtain a third test result;

[0063] Step S500, determine the chip test result of the chip under test according to the first test result, the second test result, and the third test result.

[0064] It should be noted that during the chip test process, first obtain the chip marking information of the chip under test; then determine the target application scenario information of the chip under test according to the chip marking information and the preset application scenario setting library; then determine the target test parameters from the preset scenario parameter setting library according to the target application scenario information, where the target test parameters include target function test parameters, target performance test parameters, and target reliability test parameters; then test the chip under test based on the target function test parameters to obtain the first test result; and test the chip under test based on the target performance test parameters to obtain the second test result; and test the chip under test based on the target reliability test parameters to obtain the third test result; finally, the chip test result of the chip under test can be determined according to the first test result, the second test result, and the third test result; through the above technical solution, determine the target application scenario information of the chip under test according to the application scenario setting library, and then determine the target test parameters according to the scenario parameter setting library, so that different chips under test will correspond to corresponding target test parameters, so that the chip test process is more in line with the specific usage scenario, and effectively avoid the problem of reducing the chip test pass rate caused by the unified standard, and improve the pass rate of the chip.

[0065] It is worth noting that each chip under test will carry chip marking information. For example, the chip marking information of the chip under test for mobile phones is "01", the chip marking information of the chip under test for vehicles is "02", the chip marking information of the chip under test in the field of smart home appliances is "03", and the chip marking information of the chip under test in the medical field is "04". Chips under test applied to the same field will carry the same chip marking information. For example, the chip marking information of chips under test applied to the mobile phone field is all "01". In the case of obtaining the chip marking information of the chip under test, the target application scenario information of the chip under test can be determined according to the chip marking information and the preset application scenario setting library. For example, if the chip marking information of the chip under test is "02", the chip marking information "02" can be matched and compared with the preset application scenario setting library, so as to determine the vehicle field as the target application scenario information.

[0066] It should be noted that the target test parameters are determined from a preset scenario parameter setting library according to the target application scenario information, because for different application scenarios, the performance parameters of the chip can be different; for example, in the field of automotive electronics, the chip needs to have high reliability and be able to withstand extreme temperature changes, vibrations, and electromagnetic interference; in consumer electronics products, the requirement for reliability is relatively low, but corresponding designs will also be carried out according to the usage scenarios and user needs of the products. Moreover, during the process of testing the chip, corresponding test processing can be performed on the chip based on the target test parameters; and the target test parameters can include target function test parameters, target performance test parameters, and target reliability test parameters. During the process of testing the chip, functional testing, performance testing, and reliability testing of the chip all need to be carried out. Through the above technical solution, chips in different application fields can be tested based on different target test parameters, making the chip testing more reasonable and improving the qualified rate of the chips.

[0067] It should be noted that during the process of testing the chip to be tested, it is necessary to perform test processing on the chip to be tested based on the target function test parameters to obtain the first test result, and it is also necessary to perform test processing on the chip to be tested based on the target performance test parameters to obtain the second test result, and it is also necessary to perform test processing on the chip to be tested based on the target reliability test parameters to obtain the third test result. Finally, the chip test result can be comprehensively determined according to the first test result, the second test result, and the third test result, making the test process of the chip more reasonable.

[0068] In addition, in one embodiment, as Figure 2 shown, the application scenario setting library includes marker type information and application scenario information corresponding one-to-one to the marker type information. The above step S200 may include but is not limited to step S210 and step S220.

[0069] Step S210, perform matching processing on the chip marker information and the marker type information of the application scenario setting library to obtain the target marker type information;

[0070] Step S220, determine the application scenario information corresponding to the target marker type information as the target application scenario information.

[0071] It should be noted that during the process of determining the target application scenario information of the chip to be tested according to the chip marker information and the preset application scenario setting library, first, matching processing is performed on the chip marker information and the marker type information of the application scenario setting library to obtain the target marker type information; then, the application scenario information corresponding to the target marker type information can be determined as the target application scenario information, making preparations for the subsequent determination of the target test parameters.

[0072] It should be noted that the application scenario setting library includes tag type information, and each tag type information corresponds to an application scenario information. Therefore, by matching the chip tag information with the tag type information in the application scenario setting library, the target tag type information can be obtained; finally, the application scenario information corresponding to the target tag type information can be used as the target application scenario information; through the above settings, the determination of the application scenario information can be made more accurate and rapid.

[0073] Exemplarily, the application scenario setting library includes tag type information and application scenario information, and the tag type information and the application scenario information are in one-to-one correspondence. For example, the tag type information is "01", and the application scenario information corresponding to the tag type information "01" is the mobile phone field; the tag type information is "02", and the application scenario information corresponding to the tag type information "02" is the vehicle-mounted field.

[0074] In addition, in one embodiment, as Figure 3 shown, the scenario parameter setting library includes scenario type information and test parameters corresponding to the scenario type information. The above step S300 may include but is not limited to step S310 and step S320.

[0075] Step S310, matching the target application scenario information with the scenario type information in the scenario parameter setting library to obtain the target scenario type information;

[0076] Step S320, determining the test parameters corresponding to the target scenario type information as the target test parameters.

[0077] It should be noted that in the process of determining the target test parameters from the preset scenario parameter setting library according to the target application scenario information, the target application scenario information can be matched with the scenario type information in the scenario parameter setting library to obtain the target scenario type information; finally, the test parameters corresponding to the target scenario type information are determined as the target test parameters. Through the above settings, the target test parameters can be determined simply and quickly, preparing for the subsequent chip test.

[0078] It should be noted that the scenario parameter setting library includes scenario type information and test parameters corresponding to the scenario type information, and each scenario type information corresponds to the test parameters. For example, the vehicle-mounted field corresponds to the first test parameter, the mobile phone field corresponds to the second test parameter, and the medical field corresponds to the third test parameter.

[0079] In addition, in one embodiment, as Figure 4 shown, the above step S400 may include but is not limited to step S410 and step S420.

[0080] Step S410, generating a first test signal according to the target functional test parameter;

[0081] Step S420: Input the first test signal into the chip under test to perform test processing on the chip under test, and obtain a first test result.

[0082] It should be noted that in the process of obtaining the first test result by testing the chip under test based on the target function test parameters, first generate the first test signal according to the target function test parameters, then input the first test signal into the chip under test to perform test processing on the chip under test, and then the first test result can be obtained. Through the above technical solution, the function test of the chip can be well performed.

[0083] It is worth noting that first, the target function of the chip under test should be clarified, that is, the function expected to be achieved during chip design. For example, if it is an audio processing chip, the target function may be to perform operations such as filtering and amplifying the input audio signal; according to this target function, determine the test parameters; these parameters are used to simulate various situations that the chip may encounter in actual use. For example, for an audio processing chip, the test parameters may include audio signals with different frequencies and volumes, as well as different filtering parameters, etc., and then generate the first test signal according to these test parameters; this signal is designed for the specific function of the chip and is used to verify whether the chip can achieve the function as expected during the subsequent test process; input the generated first test signal into the chip under test, and this step takes the test signal as the input signal and allows the chip to process this signal according to its designed function; the chip will process the input test signal. For example, if it is an audio processing chip, it will perform operations such as filtering and amplifying the audio signal according to its internal algorithm; after the chip processes the test signal, an output result will be obtained, and this output result is the first test result, which reflects the performance of the chip when processing a specific test signal; by comparing this output result with the expected output result (calculated based on the target function and test parameters), it can be determined whether the chip is working properly and whether it meets the design requirements.

[0084] In addition, in one embodiment, as Figure 5 shown, the above step S400 may include but is not limited to step S430 and step S440.

[0085] Step S430: Determine the clock frequency, power consumption, data processing rate, data transmission rate, and detection temperature from the target performance test parameters;

[0086] Step S440: Respectively perform test processing on the chip under test based on the clock frequency, power consumption, data processing rate, data transmission rate, and detection temperature, and obtain a second test result.

[0087] It should be noted that in the process of testing the chip to be tested based on the target performance test parameters to obtain the second test result, first, the clock frequency, power consumption, data processing rate, data transmission rate, and detection temperature are determined from the target performance test parameters; then, the chip to be tested is respectively tested based on the clock frequency, power consumption, data processing rate, data transmission rate, and detection temperature to obtain the second test result. Through the above technical solution, the performance of the chip can be well tested.

[0088] It is worth noting that the target performance test parameters are used to evaluate the performance of the chip in actual use. These parameters include the clock frequency, power consumption, data processing rate, data transmission rate, and detection temperature, etc. The clock frequency refers to the frequency of the internal clock of the chip, which determines the operation speed of the chip; the power consumption refers to the electrical energy consumed by the chip during operation, usually expressed in watts; the data processing rate refers to the speed at which the chip processes data, usually expressed by the amount of data processed per second, such as the number of bytes processed per second; the data transmission rate refers to the speed at which the chip transmits data to other devices, usually expressed by the amount of data transmitted per second, such as the number of bytes transmitted per second; the detection temperature refers to whether the temperature of the chip is within the normal range during the test to ensure that the chip can work properly under various temperature conditions. According to the determined test parameters, the chip is respectively tested, which means that different test signals and test conditions need to be designed to evaluate the performance of the chip under these parameters. Exemplarily, to test the clock frequency, a test signal can be designed to make the chip work at different clock frequencies, and then observe whether the output result of the chip is correct; to test the power consumption, the current and voltage of the chip under different working conditions can be measured and the power consumption can be calculated; to test the data processing rate, a test signal can be designed to make the chip process a large amount of data, and then measure the time required to process these data; to test the data transmission rate, a test signal can be designed to make the chip transmit a large amount of data to other devices, and then measure the time required to transmit these data; to test the detection temperature, the chip can be placed under different temperature conditions, and then observe whether the output result of the chip is correct; after these tests on the chip, the second test result will be obtained, and this result reflects the performance of the chip under different performance parameters; by comparing this result with the expected performance parameters (determined according to the target performance test parameters), it can be judged whether the performance of the chip meets the design requirements.

[0089] In addition, in one embodiment, as Figure 6 shown, the above step S400 may include but is not limited to step S450 and step S460.

[0090] Step S450, determining the temperature control threshold, humidity control threshold, and mechanical stress information from the target reliability test parameters;

[0091] Step S460: Perform test processing on the chip under test respectively based on the temperature control threshold, humidity control threshold, and mechanical stress information to obtain a third test result.

[0092] It should be noted that in the process of obtaining the third test result by testing the chip under test based on the target reliability test parameters, first determine the temperature control threshold, humidity control threshold, and mechanical stress information from the target reliability test parameters; then perform test processing on the chip under test respectively based on the temperature control threshold, humidity control threshold, and mechanical stress information to obtain the third test result; through the above technical solution, the reliability of the chip can be well detected.

[0093] It is worth noting that according to the temperature control threshold, perform temperature cycle test or high-temperature storage test on the chip. For example, cycle the chip between high temperature (such as 125 °C or higher) and low temperature (such as -40 °C or lower), or store it in a high-temperature environment for a certain period of time (such as 1000 hours); observe whether the chip has problems such as cracking, delamination, and functional failure, and record the impact of temperature change on the chip performance. Perform damp heat test or temperature-humidity bias test, place the chip in a high-humidity environment (such as 85% relative humidity) and high temperature (such as 85 °C) for a certain period of time (such as 1000 hours) to evaluate the impact of moisture on the chip performance; detect whether the chip has problems such as corrosion, oxidation, and short circuit, and evaluate its reliability in a humid environment. Perform mechanical stress tests, including vibration tests, shock tests, etc. For example, apply vibrations with different frequencies and intensities on a vibration table, or freely drop the chip from a certain height (such as 1 meter) onto a hard surface to evaluate the impact of physical shock on the chip, observe whether the chip has problems such as cracks, solder joint detachment, and pin loosening, and evaluate its mechanical strength and durability. Through the above tests, the third test result can be obtained, and these results reflect the reliability performance of the chip under different environmental conditions; specific indicators may include the proportion of functional failures, changes in electrical performance, physical damage conditions, etc., and these data help to evaluate the stability and durability of the chip in actual use, providing a basis for the design improvement and process optimization of the chip.

[0094] In addition, in one embodiment, as Figure 7 shown, the above step S500 may include but is not limited to step S510 and step S520.

[0095] Step S510: When the first test result, the second test result, and the third test result all indicate that the chip under test is normal, take the chip test as normal as the chip test result.

[0096] Step S520, when at least one of the first test result, the second test result, and the third test result indicates that the chip under test is abnormal, the chip test abnormal is taken as the chip test result.

[0097] It should be noted that during the process of determining the chip test result, when the first test result, the second test result, and the third test result all indicate that the chip under test is normal, the chip test normal is taken as the chip test result; when at least one of the first test result, the second test result, and the third test result indicates that the chip under test is abnormal, the chip test abnormal is taken as the chip test result; through the above settings, the determination of the chip test result can be made more reasonable and the accuracy can be improved.

[0098] It should be noted that when the first test result, the second test result, and the third test result all indicate that the chip under test is normal, the chip test result is determined as "chip test normal", which means that the chip performs well in the function test (the first test result), the performance test (the second test result), and the reliability test (the third test result), without any abnormal conditions, indicating that the chip meets the design requirements and can be used normally in actual applications. When at least one of the first test result, the second test result, and the third test result indicates that the chip under test is abnormal, the chip test result is determined as "chip test abnormal", which means that there is at least one problem in the function, performance, or reliability test of the chip. Even if other test results are normal, as long as one test result is abnormal, it is sufficient to indicate that the chip does not meet the requirements and cannot be used normally. This determination logic is based on the strictness and comprehensiveness of the chip test to ensure that the chip meets the standards in all key aspects. Through the above settings, the chip test can be made more comprehensive, strict, and traceable. When the chip test is normal, the chip can enter the next step of packaging, assembly, or be directly delivered to the customer; when the chip test is abnormal, a detailed analysis of the abnormal situation needs to be carried out to determine whether it is a chip design problem, a process problem, or a test environment problem, etc.; according to the different problems, measures such as redesigning the chip, optimizing the process flow, or adjusting the test conditions may be required to ensure the quality of subsequent chips.

[0099] As Figure 8 shown, in some embodiments of the present invention, an embodiment of the present invention further provides a chip test device 10, including:

[0100] A first processing unit 100, configured to obtain the chip marking information of the chip under test;

[0101] A second processing unit 200, configured to determine the target application scenario information of the chip under test according to the chip marking information and a preset application scenario setting library;

[0102] A third processing unit 300 is configured to determine target test parameters from a preset scenario parameter setting library according to the target application scenario information, where the target test parameters include target function test parameters, target performance test parameters, and target reliability test parameters;

[0103] A fourth processing unit 400 is configured to test the chip under test based on the target function test parameters to obtain a first test result; and, test the chip under test based on the target performance test parameters to obtain a second test result; and, test the chip under test based on the target reliability test parameters to obtain a third test result;

[0104] A fifth processing unit 500 is configured to determine the chip test result of the chip under test according to the first test result, the second test result, and the third test result.

[0105] It should be noted that the specific implementation manner of the chip testing apparatus 10 in the embodiments of the present invention is basically the same as the specific embodiments of the above chip testing method, and will not be elaborated here.

[0106] In some embodiments of the present invention, as Figure 9 shown, an embodiment of the present invention further provides an electronic device 700, including: a memory 720, a processor 710, and a computer program stored on the memory 720 and executable on the processor 710. When the processor 710 executes the computer program, the error correction decoding method in the above embodiments is implemented. For example, the method steps S100 to step S500 described above are executed, Figure 1 the method steps S210 to step S220 in Figure 2 the method steps S310 to step S320 in Figure 3 the method steps S410 to step S420 in Figure 4 the method steps S430 to step S440 in Figure 5 the method steps S450 to step S460 in Figure 6 and the method steps S510 to step S520 in Figure 7 are executed.

[0107] In some embodiments of the present invention, an embodiment of the present invention further provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are executed by a processor or a controller, for example, executed by a processor in the above device embodiments, the processor can execute the error correction decoding method in the above embodiments. For example, the method steps S100 to step S500 described above are executed, Figure 1 the method steps S210 to step S220 in Figure 2 the method steps S310 to step S320 in Figure 3Method steps S310 to S320 in Figure 4 Method steps S410 to S420 in Figure 5 Method steps S430 to S440 in Figure 6 Method steps S450 to S460 in Figure 7 and method steps S510 to S520 in

[0108] Those of ordinary skill in the art can understand that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and their appropriate combinations. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or can be implemented as hardware, or can be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory, or other memory technologies, CD-ROM, digital versatile disk (DVD), or other optical disk storage, magnetic cassettes, tapes, magnetic disk storage, or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that a communication medium typically contains computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.

[0109] The above has specifically described the preferred embodiments of the present invention, but the present invention is not limited to the above embodiments. Those skilled in the art can also make various equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations or substitutions are all included within the scope defined by the claims of the present invention.

Claims

1. A chip testing method, characterized in that: include: Obtain chip marking information of the chip to be tested; Determine and obtain target application scenario information of the chip to be tested according to the chip marking information and a preset application scenario setting library; Determining target test parameters from a preset scenario parameter setting library according to the target application scenario information, wherein the target test parameters include target function test parameters, target performance test parameters, and target reliability test parameters; The chip under test is tested based on the target functional test parameters to obtain a first test result; and, the chip under test is tested based on the target performance test parameters to obtain a second test result; and, the chip under test is tested based on the target reliability test parameters to obtain a third test result; A chip test result of the chip to be tested is determined according to the first test result, the second test result and the third test result.

2. The chip testing method according to claim 1, characterized in that: The application scenario setting library includes tag type information and application scenario information corresponding to the tag type information one by one. The step of determining the target application scenario information of the chip to be tested according to the chip tag information and the preset application scenario setting library includes: Matching the chip tag information with the tag type information of the application scenario setting library to obtain target tag type information; The application scenario information corresponding to the target tag type information is determined as the target application scenario information.

3. The chip testing method according to claim 1, characterized in that: The scenario parameter setting library includes scenario type information and test parameters corresponding to the scenario type information, and determining target test parameters from a preset scenario parameter setting library according to the target application scenario information includes: Matching the target application scenario information with the scenario type information in the scenario parameter setting library to obtain target scenario type information; The test parameter corresponding to the target scene type information is determined as the target test parameter.

4. The chip testing method according to claim 1, characterized in that: The step of testing the chip to be tested based on the target functional test parameter to obtain a first test result includes: generating a first test signal according to the target functional test parameter; The first test signal is input to the chip under test to perform a test process on the chip under test and obtain the first test result.

5. The chip testing method according to claim 1, characterized in that: The step of testing the chip to be tested based on the target performance test parameter to obtain a second test result includes: Determining clock frequency, power consumption, data processing rate, data transmission rate and detection temperature from the target performance test parameters; The chip to be tested is tested based on the clock frequency, the power consumption, the data processing rate, the data transmission rate and the detected temperature to obtain the second test result.

6. The chip testing method according to claim 1, characterized in that: The step of testing the chip to be tested based on the target reliability test parameter to obtain a third test result includes: determining a temperature control threshold, a humidity control threshold, and mechanical stress information from the target reliability test parameters; The chip to be tested is tested based on the temperature control threshold, the humidity control threshold and the mechanical stress information to obtain the third test result.

7. The chip testing method according to claim 1, characterized in that: The step of determining the chip test result of the chip to be tested according to the first test result, the second test result and the third test result includes: When the first test result, the second test result and the third test result all indicate that the chip to be tested is normal, taking the chip test normal as the chip test result; In the case that at least one of the first test result, the second test result, and the third test result indicates that the chip to be tested is abnormal, the chip test abnormality is taken as the chip test result.

8. A chip testing device, characterized in that: include: A first processing unit, used to obtain chip marking information of the chip to be tested; A second processing unit, configured to determine target application scenario information of the chip to be tested according to the chip marking information and a preset application scenario setting library; A third processing unit, configured to determine target test parameters from a preset scenario parameter setting library according to the target application scenario information, wherein the target test parameters include target function test parameters, target performance test parameters, and target reliability test parameters; a fourth processing unit, configured to test the chip under test based on the target functional test parameter to obtain a first test result; and, to test the chip under test based on the target performance test parameter to obtain a second test result; and, to test the chip under test based on the target reliability test parameter to obtain a third test result; The fifth processing unit is used to determine the chip test result of the chip to be tested according to the first test result, the second test result and the third test result.

9. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the chip testing method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium storing computer-executable instructions, characterized in that: When the computer executable instructions are executed by the control processor, the chip testing method according to any one of claims 1 to 7 is implemented.

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