Power supply preprocessing circuit and reference source device

Abstract

According to the power supply preprocessing circuit and the reference source device, a depletion type MOS tube is adopted as a main device to design the reference current generating circuit, so that the reference current generating circuit can generate small reference current with a small area, an LDO circuit is adopted to preprocess a power supply, so that the power supply has good low-frequency PSR, and in combination with the design of a quick-response starting circuit, the power supply can be quickly started. And rapid and stable starting of loops of the LDO circuit and the band-gap reference source BG is effectively ensured. The design can be directly overlaid on a traditional PSR enhanced circuit, so that the low-frequency PSR is further improved, and the high-PSR requirements of part of application scenes are effectively met.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuit design, and relates to a power supply preprocessing circuit and a reference source device. Background Art

[0002] A voltage reference source (BG, also known as a bandgap reference source) is a device that obtains a reference voltage with a low temperature coefficient through the linear superposition of different temperature characteristics between devices. The generated reference voltage needs to have a high PSR (Power Supply Rejection Ratio) to offset the influence from power supply ripple, thereby ensuring the reliability and accuracy of the circuit. Currently, most traditional voltage reference sources use a self-biased current mirror to copy the power supply ripple to improve the PSR. Although its circuit structure is simple and the area is small, its PSR improvement ability is limited and it is difficult to meet the high PSR requirements of some application scenarios. Summary of the Invention

[0003] Aiming at the problems existing in the above traditional technologies, the present invention proposes a power supply preprocessing circuit and a voltage reference source device, which can improve the low-frequency PSR and meet the high PSR requirements of some application scenarios.

[0004] To achieve the above object, the embodiments of the present invention adopt the following technical solutions: Provide a power supply preprocessing circuit, including a reference current generation circuit, a startup circuit, and an LDO circuit. The output end of the LDO circuit is used to connect to the input end of the bandgap reference source BG, and the reference input ends of the startup circuit and the LDO circuit are respectively used to connect to the output end of the bandgap reference source BG; The reference current generation circuit is composed of depletion-type MOS transistors and is used to generate a reference current to the startup circuit and the LDO circuit. Before the bandgap reference source BG operates, the startup circuit is used to control the LDO circuit to output a power supply voltage to directly supply power to the bandgap reference source BG. After the bandgap reference source BG starts to operate, the startup circuit is used to control the normal operation of the low-dropout linear regulator in the LDO circuit, and the LDO circuit is used to output a power supply voltage that is not affected by the power supply to the bandgap reference source BG through negative feedback.

[0005] On the other hand, a voltage reference source device is also provided, including a bandgap reference source BG, a reference current generation circuit, a startup circuit, and an LDO circuit. The output end of the LDO circuit is connected to the input end of the bandgap reference source BG, and the reference input ends of the startup circuit and the LDO circuit are respectively connected to the output end of the bandgap reference source BG; The reference current generation circuit is composed of depletion MOS transistors and is used to generate a reference current for the startup circuit and the LDO circuit. Before the bandgap reference BG operates, the startup circuit is used to control the LDO circuit to output a power supply voltage directly to supply power to the bandgap reference BG. After the bandgap reference BG starts to operate, the startup circuit is used to control the normal operation of the low dropout linear regulator in the LDO circuit. The LDO circuit is used to output a power supply voltage that is not affected by the power supply to the bandgap reference BG through negative feedback.

[0006] One of the technical solutions in the above technical solutions has the following advantages and beneficial effects: In the above power supply preprocessing circuit and reference source device, by using depletion MOS transistors as the main devices to design the above reference current generation circuit, it can generate a small reference current with a small area, and use the LDO circuit to preprocess the power supply, so that it has good low-frequency PSR. Combined with the design of a fast-response startup circuit, it effectively ensures the fast and stable startup of the loop of the LDO circuit and the bandgap reference BG. This design can be directly superimposed on the traditional PSR enhancement circuit, thereby further improving the low-frequency PSR and effectively meeting the high-PSR requirements of some application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0008] Figure 1 It is a schematic diagram of the power supply preprocessing structure of the traditional BG circuit; Figure 2 It is a schematic diagram of the module structure of the power supply preprocessing circuit in an embodiment; Figure 3 It is a schematic diagram of the circuit structure of the power supply preprocessing circuit in an embodiment; Figure 4 It is a schematic diagram of the power supply preprocessing circuit for the BG circuit in an embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0009] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0010] It should be noted that referring to "embodiment" herein means that a specific feature, structure or characteristic described in connection with the embodiment may be included in at least one embodiment of the present invention. The phrase is shown at various positions in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term "and / or" used in the description and claims of the present invention refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0011] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0012] Most traditional BG circuit structures use a self-biased current mirror to replicate the power supply ripple to improve PSR, as Figure 1 shown. The BG circuit structure includes a bandgap reference source BG, transistors M01 to M05, and a constant current source IP0. Among them, the reference voltage output by the bandgap reference source BG serves as the reference voltage of transistor M04 at the same time. Although this BG circuit structure is simple and has a relatively small area, its PSR improvement ability is relatively limited and it is difficult to meet the high PSR requirements of some application scenarios.

[0013] In one embodiment, as Figure 2 shown, a power supply preprocessing circuit is provided, which includes a reference current generation circuit, a startup circuit, and an LDO circuit. The output terminal of the LDO circuit is used to connect to the input terminal of the bandgap reference source BG (refer to the IN terminal of Figure 1 to supply power to the bandgap reference source BG. The reference input terminals of the startup circuit and the LDO circuit are respectively used to connect to the output terminal of the bandgap reference source BG (refer to Figure 1The VREF terminal). The reference current generation circuit is composed of depletion MOS transistors and is used to generate a reference current to the startup circuit and the LDO circuit. Before the bandgap reference BG operates, the startup circuit is used to control the LDO circuit to output a power supply voltage directly to power the bandgap reference BG; after the bandgap reference BG starts to operate, the startup circuit is used to control the normal operation of the low dropout linear regulator in the LDO circuit, and the LDO circuit is used to output a power supply voltage that is not affected by the power supply to the bandgap reference BG through negative feedback, thereby realizing the preprocessing function.

[0014] It can be understood that the reference current generation circuit and the startup circuit can be collectively referred to as startup control (module circuit). In this embodiment, an LDO (Low Dropout Regulator) module power supply preprocessing with a startup circuit is used to power the bandgap reference BG. The output OUT of its LDO circuit with a startup circuit is used to connect to the input of the bandgap reference BG, where the output of the bandgap reference BG is output as the reference voltage VREF and is also used as the reference voltage for the input of the LDO circuit. Therefore, the design of the startup circuit is very important. Among them, the reference current generated by the reference current generation circuit is transmitted to each branch of the LDO circuit. Before the bandgap reference BG starts to operate, the startup circuit is used to control the LDO circuit to connect to the power supply VDD, and the power supply VDD directly powers the bandgap reference BG through the LDO circuit. When the bandgap reference BG starts to operate, the startup circuit outputs two startup levels (high level STAR_A and low level STAR_B) to the LDO circuit to make the low dropout linear regulator in the LDO circuit operate normally. When the bandgap reference BG operates stably, the output of the LDO circuit is stable, which has a good suppression effect on power supply ripple and can effectively improve the PSR of the circuit at low frequencies.

[0015] It should be noted that those skilled in the art can use depletion transistors and enhancement transistors according to the functions of the above-mentioned module circuits, combined with inverters INV, resistors, and capacitor components, and adopt a variety of different specific circuit structure designs to specifically implement according to the circuit layout design rules in the art, as long as the functions of the above-mentioned module circuits can be realized based on the above design concept.

[0016] For the above power supply preprocessing circuit, by using depletion MOS transistors as the main devices to design the above reference current generation circuit, it can generate a small reference current with a small area, and use the LDO circuit to preprocess the power supply to make it have a good low-frequency PSR. Combined with the design of a fast-response startup circuit, it effectively ensures the fast and stable startup of the loop of the LDO circuit and the bandgap reference BG. This design can be directly superimposed on the traditional PSR enhancement circuit, thereby further improving the low-frequency PSR and effectively meeting the high-PSR requirements of some application scenarios.

[0017] In one embodiment, as Figure 3 shown, the reference current generation circuit includes transistors M1 to M6 and resistor R1, and the startup circuit includes transistors M7 to M21, resistor R2, inverter INV1, and inverter INV2. Among them, transistors M2 to M5 are all depletion-type NMOS transistors, transistors M1, M8 to M16, and M20 to M21 are all enhancement-type NMOS transistors, and transistors M6, M7, and M17 to M19 are all enhancement-type PMOS transistors. The gate of transistor M1 is used to receive an enable signal (EN), the source of transistor M1 is grounded, the drain of transistor M1 is connected to the source of transistor M2 through resistor R1, transistors M2 to M5 are connected in series in sequence and their gates are all grounded (GND), the sources of transistors M2 to M5 are respectively grounded, and the drain of transistor M5 is respectively connected to the drain of transistor M6, the gate of transistor M7, the gate of transistor M17, the drain of transistor M18, and the input terminal of the LDO circuit.

[0018] The sources of transistor M6, transistor M7, transistor M17, transistor M18, and transistor M19 are all used to connect to the power supply. The gate of transistor M6 is connected to the gate of transistor M7. The drain of transistor M7 is respectively connected to the drain of transistor M8, the gate of transistor M8, the gate of transistor M9, the gate of transistor M12, and the gate of transistor M13. Transistors M8 to M11 are connected in series in sequence and their sources are respectively grounded. The gate of transistor M10 is respectively connected to the source of transistor M9 and the gate of transistor M11. Transistors M12 to M17 are connected in series in sequence. The sources of transistors M12 to M16 are respectively grounded. The gate of transistor M15 is connected to the gate of transistor M14 as the reference input terminal of the startup circuit. The gates of transistor M16, transistor M18, and transistor M19 are all used to receive the enable signal.

[0019] The input terminal of inverter INV1 is respectively connected to the drain of transistor M19 and the drain of transistor M16. The output terminal of inverter INV1 is respectively connected to the input terminal of inverter INV2, the gate of transistor M20, the gate of transistor M21, and the first control terminal of the LDO circuit. The output terminal of inverter INV2 is connected to the second control terminal of the LDO circuit. The drain of transistor M20 is connected to the drain of transistor M14. The source of transistor M20 is connected to the source of transistor M14. The drain of transistor M21 is connected to the source of transistor M13. The source of transistor M21 is grounded through resistor R2.

[0020] It can be understood that the NMOS transistor is also the N-channel Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and the PMOS transistor is also the P-channel Metal-Oxide-Semiconductor Field-Effect Transistor. The enable signal EN is one of the input signals of the above-mentioned reference current generation circuit and start-up circuit, and is used to realize the enable control of these two parts of the circuit, so that they start to work after being enabled. The above-mentioned start-up circuit and reference current generation circuit are specifically designed by using the transistors M1 to M21, the resistor R1, the inverter INV1 and the inverter INV2. The circuit structure is simple and the area is small. The start-up circuit with fast response effectively ensures the fast and stable start-up of the loop of the LDO circuit and the bandgap reference BG.

[0021] In one embodiment, as Figure 3 shown, the LDO circuit includes transistors M22 to M33, resistors R3, R4, capacitors C1 and C2. Among them, transistors M22, M27 to M30 and M33 are all enhancement-mode PMOS transistors, transistors M23, M24, M31 and M32 are all enhancement-mode NMOS transistors, and transistors M25 and M26 are both enhancement-mode deep N-well NMOS transistors.

[0022] The gate of transistor M22 is connected to the output terminal of the reference current generation circuit. The sources of transistor M22, transistor M29, transistor M30 and transistor M33 are all used to connect to the power supply. The drain of transistor M22 is respectively connected to the drain, gate and gate of transistor M23 and transistor M24. The sources of transistor M23 and transistor M24 are both grounded. The sources of transistor M25 and transistor M26 are connected together and connected to the drain of transistor M24. The gate of transistor M26 is used as the reference input terminal of the LDO circuit. The drain of transistor M26 is connected to the drain of transistor M28. The drain of transistor M25 is respectively connected to the drain of transistor M27. The gate of transistor M27 is connected to the gate of transistor M28 and connected to the drain of transistor M27. The source of transistor M27 is connected to the drain of transistor M29. The source of transistor M28 is connected to the drain of transistor M30.

[0023] The gates of transistor M29, transistor M30, and transistor M31 (i.e., the second control terminal of the LDO circuit) are all connected to the second start control output terminal of the start circuit (i.e., the output terminal of inverter INV2). The gate of transistor M32 (i.e., the first control terminal of the LDO circuit) is connected to the first start control output terminal of the start circuit (i.e., the output terminal of inverter INV1). The drain of transistor M31 is respectively connected to the drain of transistor M26, the gate of transistor M33, and one end of capacitor C1. The source of transistor M31 is grounded. The drain of transistor M33 serves as the output terminal (OUT) of the LDO circuit. The drain of transistor M33 is also respectively connected to the other end of capacitor C1, one end of capacitor C2, and one end of resistor R3. The other end of capacitor C2 is respectively connected to the other end of resistor R3 and the gate of transistor M25. The other end of resistor R3 is connected to the drain of transistor M32 through resistor R4. The source of transistor M32 is grounded.

[0024] It can be understood that in a traditional NMOS transistor, the N-type source and drain regions are usually fabricated on a P-type substrate. For a deep N-well NMOS transistor, on top of the P-type substrate, a deep N-type region, i.e., a deep N-well, is first formed through processes such as high-energy ion implantation. Similar to a common NMOS transistor, the deep N-well NMOS transistor uses the gate voltage to control the current between the source and the drain. When the gate voltage is higher than the source voltage and reaches or exceeds a certain threshold voltage, electrons in the P-type well under the gate are attracted to the surface, forming an N-type conductive channel near the interface between the deep N-well and the P-type well, enabling conduction between the source and the drain, and electrons flow from the source to the drain to form a current. When the gate voltage is lower than the threshold voltage, the channel is not formed, and the source and the drain are cut off. In this embodiment, transistors M25 and M26 of enhanced deep N-well NMOS transistors are used, reducing the mutual interference between different devices, being able to further provide better isolation performance, contributing to improving the accuracy and stability of the circuit. At the same time, due to the deep N-well process, the body terminals of transistors M25 and M26 can be connected to the source terminals, reducing their threshold voltages and maximizing their input ranges.

[0025] Specifically, transistors M22 to M33, capacitor C1, capacitor C2, resistor R3, and resistor R4 are arranged according to Figure 3The connection structure therein constitutes an LDO circuit. Among them, transistors M1 to M5 and resistor R1 generate a reference current that is transmitted to each branch through transistors M6, M7, M17, M22, M23, and M24. Transistors M8 to M11 are used to provide a bias voltage for transistors M12 and M13, so that transistors M12 and M13 operate in a region with a lower noise figure, reducing the noise during circuit startup. Before the bandgap reference BG starts operating, transistors M31 and M32 are controlled by the startup circuit to pull down transistor M31 and turn off the gate of transistor M32, and the power supply directly supplies power to the bandgap reference BG through transistor M33; after the bandgap reference BG starts operating, transistors M14 and M15 are turned on, the input of inverter INV1 is pulled down, the first startup control signal STAR_A outputs a high level, and the second startup control signal STAR_B outputs a low level, enabling the LDO to operate normally. When the bandgap reference BG operates stably, the LDO circuit outputs stably, has a good suppression effect on power supply ripple, and can greatly improve the PSR of the circuit at low frequencies.

[0026] In one embodiment, as Figure 4 shown, a voltage reference source device is further provided, including a bandgap reference BG, a reference current generation circuit, a startup circuit, and an LDO circuit. The output end of the LDO circuit is connected to the input end of the bandgap reference BG, and the reference input ends of the startup circuit and the LDO circuit are respectively connected to the output end of the bandgap reference BG. The reference current generation circuit is composed of depletion-type MOS transistors and is used to generate a reference current to the startup circuit and the LDO circuit. Before the bandgap reference BG starts operating, the startup circuit is used to control the LDO circuit to output a power supply voltage to directly supply power to the bandgap reference BG. After the bandgap reference BG starts operating, the startup circuit is used to control the normal operation of the low-dropout linear regulator in the LDO circuit, and the LDO circuit is used to output a power supply voltage that is not affected by the power supply to the bandgap reference BG through negative feedback.

[0027] It can be understood that in this embodiment, the bandgap reference BG can be various existing BG circuits in the art. By applying the above power supply preprocessing circuit, the above voltage reference source device can generate a small reference current with a small area, and use the LDO circuit to preprocess the power supply, so that it has a good low-frequency PSR. Combined with the design of a fast-response startup circuit, it effectively ensures the fast and stable startup of the loop of the LDO circuit and the bandgap reference BG. This design can be directly superimposed on the traditional PSR enhancement circuit, thereby further improving the low-frequency PSR and effectively meeting the high-PSR requirements of some application scenarios.

[0028] In one embodiment, the reference current generation circuit includes transistors M1 to M6 and resistor R1, and the startup circuit includes transistors M7 to M21, resistor R2, inverter INV1, and inverter INV2. Among them, transistors M2 to M5 are all depletion-type NMOS transistors, transistors M1, M8 to M16, and M20 to M21 are all enhancement-type NMOS transistors, and transistors M6, M7, and M17 to M19 are all enhancement-type PMOS transistors. The gate of transistor M1 is used to receive an enable signal, the source of transistor M1 is grounded, the drain of transistor M1 is connected to the source of transistor M2 through resistor R1, transistors M2 to M5 are connected in series in sequence and their gates are all grounded, the sources of transistors M2 to M5 are respectively grounded, and the drain of transistor M5 is respectively connected to the drain of transistor M6, the gate of transistor M7, the gate of transistor M17, the drain of transistor M18, and the input terminal of the LDO circuit.

[0029] The sources of transistors M6, M7, M17, M18, and M19 are all used to connect to the power supply. The gate of transistor M6 is connected to the gate of transistor M7. The drain of transistor M7 is respectively connected to the drain of transistor M8, the gate of transistor M8, the gate of transistor M9, the gate of transistor M12, and the gate of transistor M13. Transistors M8 to M11 are connected in series in sequence and their sources are respectively grounded. The gate of transistor M10 is respectively connected to the source of transistor M9 and the gate of transistor M11. Transistors M12 to M17 are connected in series in sequence. The sources of transistors M12 to M16 are respectively grounded. The gate of transistor M15 is connected to the gate of transistor M14 as the reference input terminal of the startup circuit. The gates of transistors M16, M18, and M19 are all used to receive an enable signal.

[0030] The input terminal of inverter INV1 is respectively connected to the drain of transistor M19 and the drain of transistor M16. The output terminal of inverter INV1 is respectively connected to the input terminal of inverter INV2, the gate of transistor M20, the gate of transistor M21, and the first control terminal of the LDO circuit. The output terminal of inverter INV2 is connected to the second control terminal of the LDO circuit. The drain of transistor M20 is connected to the drain of transistor M14. The source of transistor M20 is connected to the source of transistor M14. The drain of transistor M21 is connected to the source of transistor M13. The source of transistor M21 is grounded through resistor R2.

[0031] In one embodiment, the LDO circuit includes transistors M22 to M33, resistor R3, resistor R4, capacitor C1, and capacitor C2. Among them, transistors M22, M27 to M30, and M33 are all enhancement-mode PMOS transistors, transistors M23, M24, M31, and M32 are all enhancement-mode NMOS transistors, and transistors M25 and M26 are both enhancement-mode deep N-well NMOS transistors.

[0032] The gate of transistor M22 is connected to the output terminal of the reference current generation circuit. The sources of transistors M22, M29, M30, and M33 are all used to connect to the power supply. The drain of transistor M22 is respectively connected to the drains of transistors M23, the gate of transistor M23, and the gate of transistor M24. The sources of transistors M23 and M24 are both grounded. The sources of transistors M25 and M26 are connected together and connected to the drain of transistor M24. The gate of transistor M26 serves as the reference input terminal of the LDO circuit. The drain of transistor M26 is connected to the drain of transistor M28. The drain of transistor M25 is respectively connected to the drain of transistor M27. The gate of transistor M27 is connected to the gate of transistor M28 and connected to the drain of transistor M27. The source of transistor M27 is connected to the drain of transistor M29. The source of transistor M28 is connected to the drain of transistor M30.

[0033] The gates of transistors M29, M30, and M31 are all connected to the second startup control output terminal of the startup circuit. The gate of transistor M32 is connected to the first startup control output terminal of the startup circuit. The drain of transistor M31 is respectively connected to the drain of transistor M26, the gate of transistor M33, and one end of capacitor C1. The source of transistor M31 is grounded. The drain of transistor M33 serves as the output terminal of the LDO circuit. The drain of transistor M33 is also respectively connected to the other end of capacitor C1, one end of capacitor C2, and one end of resistor R3. The other end of capacitor C2 is respectively connected to the other end of resistor R3 and the gate of transistor M25. The other end of resistor R3 is connected to the drain of transistor M32 through resistor R4. The source of transistor M32 is grounded.

[0034] It can be understood that for the explanatory descriptions of the respective module circuits of the above voltage reference source device, specific reference can be made to the corresponding explanatory descriptions of the respective embodiments of the above power supply preprocessing circuit for the same understanding, and details will not be repeated here.

[0035] The technical features of the above embodiments can be combined arbitrarily. For the sake of brief description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0036] The above embodiments only represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the protection scope of the invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, which all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the appended claims.

Claims

1. A power preprocessing circuit, characterized in that: It includes a reference current generating circuit, a startup circuit and an LDO circuit, wherein the output end of the LDO circuit is used to connect to the input end of a bandgap reference source BG, and the startup circuit and the reference input end of the LDO circuit are respectively used to connect to the output end of the bandgap reference source BG; The reference current generating circuit is composed of a depletion-type MOS tube, and is used to generate a reference current to the startup circuit and the LDO circuit. Before the bandgap reference source BG is not running, the startup circuit is used to control the LDO circuit to output a power supply voltage to directly power the bandgap reference source BG. After the bandgap reference source BG is running, the startup circuit is used to control the low-voltage difference linear regulator in the LDO circuit to work normally. The LDO circuit outputs a power supply voltage that is not affected by the power supply to the bandgap reference source BG through negative feedback.

2. The power preprocessing circuit according to claim 1, characterized in that: The reference current generating circuit includes transistors M1 to M6 and a resistor R1, and the startup circuit includes transistors M7 to M21, a resistor R2, an inverter INV1 and an inverter INV2, wherein the transistors M2 to M5 are all depletion-type NMOS transistors, the transistors M1, M8 to M16, and M20 to M21 are all enhancement-type NMOS transistors, and the transistors M6, M7, and M17 to M19 are all enhancement-type PMOS transistors; The gate of the transistor M1 is used to access the enable signal, the source of the transistor M1 is grounded, the drain of the transistor M1 is connected to the source of the transistor M2 through the resistor R1, the transistors M2 to M5 are connected in series in sequence and their gates are all grounded, the sources of the transistors M2 to M5 are grounded respectively, and the drain of the transistor M5 is connected to the drain of the transistor M6, the gate of the transistor M7, the gate of the transistor M17, the drain of the transistor M18 and the input end of the LDO circuit respectively; The source of the transistor M6, the source of the transistor M7, the source of the transistor M17, the source of the transistor M18 and the source of the transistor M19 are all used to connect to a power supply, the gate of the transistor M6 is connected to the gate of the transistor M7, the drain of the transistor M7 is respectively connected to the drain of the transistor M8, the gate of the transistor M8, the gate of the transistor M9, the gate of the transistor M12 and the gate of the transistor M13, the transistors M8 to the transistor M11 are sequentially connected in series and their sources are respectively grounded, the gate of the transistor M10 is respectively connected to the source of the transistor M9 and the gate of the transistor M11, the transistors M12 to the transistor M17 are sequentially connected in series, the sources of the transistors M12 to the transistor M16 are respectively grounded, the gate of the transistor M15 is connected to the gate of the transistor M14 as a reference input terminal of the startup circuit, and the gates of the transistor M16, the gates of the transistor M18 and the gates of the transistor M19 are all used to access an enable signal; The input end of the inverter INV1 is respectively connected to the drain of the transistor M19 and the drain of the transistor M16, the output end of the inverter INV1 is respectively connected to the input end of the inverter INV2, the gate of the transistor M20, the gate of the transistor M21 and the first control end of the LDO circuit, the output end of the inverter INV2 is connected to the second control end of the LDO circuit, the drain of the transistor M20 is connected to the drain of the transistor M14, the source of the transistor M20 is connected to the source of the transistor M14, the drain of the transistor M21 is connected to the source of the transistor M13, and the source of the transistor M21 is grounded through the resistor R2.

3. The power preprocessing circuit according to claim 1 or 2, characterized in that: The LDO circuit includes transistors M22 to M33, resistors R3, R4, capacitors C1 and C2, wherein transistors M22, M27 to M30 and M33 are all enhanced PMOS transistors, transistors M23, M24, M31 and M32 are all enhanced NMOS transistors, and transistors M25 and M26 are all enhanced deep N-well NMOS transistors; The gate of the transistor M22 is connected to the output end of the reference current generating circuit, the source of the transistor M22, the source of the transistor M29, the source of the transistor M30 and the source of the transistor M33 are all used to connect to the power supply, the drain of the transistor M22 is respectively connected to the drain of the transistor M23, the gate of the transistor M23 and the gate of the transistor M24, the source of the transistor M23 and the source of the transistor M24 are both grounded, the source of the transistor M25 and the source of the transistor M26 are connected to each other. The gate of the transistor M26 is connected to the drain of the transistor M24, the gate of the transistor M26 is used as the reference input terminal of the LDO circuit, the drain of the transistor M26 is connected to the drain of the transistor M28, the drain of the transistor M25 is respectively connected to the drain of the transistor M27, the gate of the transistor M27 is connected to the gate of the transistor M28 and connected to the drain of the transistor M27, the source of the transistor M27 is connected to the drain of the transistor M29, and the source of the transistor M28 is connected to the drain of the transistor M30; The gate of the transistor M29, the gate of the transistor M30 and the gate of the transistor M31 are all connected to the second startup control output terminal of the startup circuit, the gate of the transistor M32 is connected to the first startup control output terminal of the startup circuit, the drain of the transistor M31 is respectively connected to the drain of the transistor M26, the gate of the transistor M33 and one end of the capacitor C1, the source of the transistor M31 is grounded, the drain of the transistor M33 serves as the output end of the LDO circuit, the drain of the transistor M33 is also respectively connected to the other end of the capacitor C1, one end of the capacitor C2 and one end of the resistor R3, the other end of the capacitor C2 is respectively connected to the other end of the resistor R3 and the gate of the transistor M25, the other end of the resistor R3 is connected to the drain of the transistor M32 through the resistor R4, and the source of the transistor M32 is grounded.

4. A voltage reference source device, characterized in that: It includes a bandgap reference source BG, a reference current generating circuit, a startup circuit and an LDO circuit, wherein the output end of the LDO circuit is connected to the input end of the bandgap reference source BG, and the reference input ends of the startup circuit and the LDO circuit are respectively connected to the output end of the bandgap reference source BG; The reference current generating circuit is composed of a depletion-type MOS tube, and is used to generate a reference current to the startup circuit and the LDO circuit. Before the bandgap reference source BG is not running, the startup circuit is used to control the LDO circuit to output a power supply voltage to directly power the bandgap reference source BG. After the bandgap reference source BG is running, the startup circuit is used to control the low-voltage difference linear regulator in the LDO circuit to work normally, and the LDO circuit is used to output a power supply voltage that is not affected by the power supply to the bandgap reference source BG through negative feedback.

5. The voltage reference source device according to claim 4, characterized in that: The reference current generating circuit includes transistors M1 to M6 and a resistor R1, and the startup circuit includes transistors M7 to M21, a resistor R2, an inverter INV1 and an inverter INV2, wherein the transistors M2 to M5 are all depletion-type NMOS transistors, the transistors M1, M8 to M16, and M20 to M21 are all enhancement-type NMOS transistors, and the transistors M6, M7, and M17 to M19 are all enhancement-type PMOS transistors; The gate of the transistor M1 is used to access the enable signal, the source of the transistor M1 is grounded, the drain of the transistor M1 is connected to the source of the transistor M2 through the resistor R1, the transistors M2 to M5 are connected in series in sequence and their gates are all grounded, the sources of the transistors M2 to M5 are grounded respectively, and the drain of the transistor M5 is connected to the drain of the transistor M6, the gate of the transistor M7, the gate of the transistor M17, the drain of the transistor M18 and the input end of the LDO circuit respectively; The source of the transistor M6, the source of the transistor M7, the source of the transistor M17, the source of the transistor M18 and the source of the transistor M19 are all used to connect to a power supply, the gate of the transistor M6 is connected to the gate of the transistor M7, the drain of the transistor M7 is respectively connected to the drain of the transistor M8, the gate of the transistor M8, the gate of the transistor M9, the gate of the transistor M12 and the gate of the transistor M13, the transistors M8 to the transistor M11 are sequentially connected in series and their sources are respectively grounded, the gate of the transistor M10 is respectively connected to the source of the transistor M9 and the gate of the transistor M11, the transistors M12 to the transistor M17 are sequentially connected in series, the sources of the transistors M12 to the transistor M16 are respectively grounded, the gate of the transistor M15 is connected to the gate of the transistor M14 as a reference input terminal of the startup circuit, and the gates of the transistor M16, the gates of the transistor M18 and the gates of the transistor M19 are all used to access an enable signal; The input end of the inverter INV1 is respectively connected to the drain of the transistor M19 and the drain of the transistor M16, the output end of the inverter INV1 is respectively connected to the input end of the inverter INV2, the gate of the transistor M20, the gate of the transistor M21 and the first control end of the LDO circuit, the output end of the inverter INV2 is connected to the second control end of the LDO circuit, the drain of the transistor M20 is connected to the drain of the transistor M14, the source of the transistor M20 is connected to the source of the transistor M14, the drain of the transistor M21 is connected to the source of the transistor M13, and the source of the transistor M21 is grounded through the resistor R2.

6. The voltage reference source device according to claim 4 or 5, characterized in that: The LDO circuit includes transistors M22 to M33, resistors R3, R4, capacitors C1 and C2, wherein transistors M22, M27 to M30 and M33 are all enhanced PMOS transistors, transistors M23, M24, M31 and M32 are all enhanced NMOS transistors, and transistors M25 and M26 are all enhanced deep N-well NMOS transistors; The gate of the transistor M22 is connected to the output end of the reference current generating circuit, the source of the transistor M22, the source of the transistor M29, the source of the transistor M30 and the source of the transistor M33 are all used to connect to the power supply, the drain of the transistor M22 is respectively connected to the drain of the transistor M23, the gate of the transistor M23 and the gate of the transistor M24, the source of the transistor M23 and the source of the transistor M24 are both grounded, the source of the transistor M25 and the source of the transistor M26 are connected to each other. The gate of the transistor M26 is connected to the drain of the transistor M24, the gate of the transistor M26 is used as the reference input terminal of the LDO circuit, the drain of the transistor M26 is connected to the drain of the transistor M28, the drain of the transistor M25 is respectively connected to the drain of the transistor M27, the gate of the transistor M27 is connected to the gate of the transistor M28 and connected to the drain of the transistor M27, the source of the transistor M27 is connected to the drain of the transistor M29, and the source of the transistor M28 is connected to the drain of the transistor M30; The gate of the transistor M29, the gate of the transistor M30 and the gate of the transistor M31 are all connected to the second startup control output terminal of the startup circuit, the gate of the transistor M32 is connected to the first startup control output terminal of the startup circuit, the drain of the transistor M31 is respectively connected to the drain of the transistor M26, the gate of the transistor M33 and one end of the capacitor C1, the source of the transistor M31 is grounded, the drain of the transistor M33 serves as the output end of the LDO circuit, the drain of the transistor M33 is also respectively connected to the other end of the capacitor C1, one end of the capacitor C2 and one end of the resistor R3, the other end of the capacitor C2 is respectively connected to the other end of the resistor R3 and the gate of the transistor M25, the other end of the resistor R3 is connected to the drain of the transistor M32 through the resistor R4, and the source of the transistor M32 is grounded.

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