Band-gap reference voltage source circuit

Abstract

The invention provides a band-gap reference voltage source circuit. The band-gap reference voltage source circuit comprises a starting circuit, a core circuit and a current compensation circuit. The core circuit comprises a first NMOS tube, first and second triodes, a first operational amplifier, first to third resistors and a compensation resistor, a drain electrode of the first NMOS tube is connected to a power supply, a source electrode is connected with a first end of the first resistor, a base electrode of the first triode and a collector electrode of the second triode, and a grid electrode is connected with an output end of the first operational amplifier; the second end of the first resistor is connected with the collector electrode of the first triode and the base electrode of the second triode. The first end of the first resistor serves as the output end of the core circuit. The emitter of the first triode is connected with the first end of the second resistor and the non-inverting input end of the first operational amplifier; the emitter of the second triode is connected with the first end of the third resistor and the reverse input end of the first operational amplifier; the second end of the second resistor and the second end of the third resistor are respectively connected with the first end of the compensation resistor and the output end of the current compensation circuit, and the second end of the compensation resistor is grounded.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of integrated circuits, and in particular, to a bandgap reference voltage source circuit. Background Art

[0002] As is well known, temperature can affect the performance of a circuit. Therefore, a circuit that outputs a reference voltage unaffected by temperature changes is particularly important.

[0003] Since the invention of the bandgap reference voltage source, extensive research has been conducted. Its principle is to add a voltage with a negative temperature coefficient and a voltage with a positive temperature coefficient through weighting to obtain a voltage with an approximate zero temperature coefficient. To achieve a voltage with a negative temperature coefficient, the base-emitter voltage V of a transistor (BJT, Bipolar Junction Transistor) with its collector biased with a positive temperature coefficient current is generally used. be To achieve a voltage with a positive temperature coefficient, the base-emitter voltage difference ΔV of two transistors with their collectors biased at different positive temperature coefficient current densities is generally used. be Enlarge a certain proportion to balance the first-order temperature term of the negative temperature coefficient voltage.

[0004] The Early effect, also known as the base-width modulation effect, refers to the fact that when the voltage between the collector and emitter of a triode changes, the effective width of the base also changes, resulting in a non-linear change in the relationship between the collector current and the voltage between the collector and emitter. This effect can affect the current amplification factor and output characteristics of the triode, and thus affect the overall performance of the circuit. The non-linear term of the base-emitter voltage difference of the transistor changing with temperature is the main reason for the deterioration of the temperature drift. Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide a bandgap reference voltage source circuit that can effectively reduce the temperature drift of the reference voltage.

[0006] One aspect of the embodiment of the present application provides a bandgap reference voltage source circuit. The bandgap reference voltage source circuit includes a startup circuit, a bandgap reference core circuit, and a current compensation circuit. The startup circuit is used to make the bandgap reference core circuit get rid of metastability; the bandgap reference core circuit is used to generate a reference voltage; the current compensation circuit is used to compensate for the temperature drift of the reference voltage. Among them, the bandgap reference core circuit includes a first NMOS transistor, a first triode, a second triode, a first operational amplifier, a first resistor, a second resistor, a third resistor, and a compensation resistor. The drain of the first NMOS transistor is connected to the power supply voltage. The source of the first NMOS transistor is connected to the first end of the first resistor, the base of the first triode, and the collector of the second triode. The gate of the first NMOS transistor is connected to the output end of the first operational amplifier; the second end of the first resistor is respectively connected to the collector of the first triode and the base of the second triode, and the first end of the first resistor is used as the output end of the bandgap reference core circuit; the emitter of the first triode is connected to the first end of the second resistor and the non-inverting input end of the first operational amplifier; the emitter of the second triode is connected to the first end of the third resistor and the inverting input end of the first operational amplifier; the second end of the second resistor and the second end of the third resistor are respectively connected to the first end of the compensation resistor and the output end of the current compensation circuit, and the second end of the compensation resistor is grounded.

[0007] Further, the voltage difference across the first resistor is equal to the difference between the base-emitter voltage of the first triode and the base-emitter voltage of the second triode.

[0008] Further, the second resistor and the third resistor have the same resistance value.

[0009] Further, the first-order temperature drift of the reference voltage generated by the bandgap reference core circuit is adjusted by adjusting the ratio of the second resistor to the first resistor; the non-linear temperature drift of the reference voltage is adjusted by adjusting the compensation current output by the output end of the current compensation circuit and the resistance value of the compensation resistor.

[0010] Further, the startup circuit includes a fourth resistor, a fifth resistor, a sixth resistor, a first PMOS transistor, a third triode, and a startup transistor. Among them, the first end of the fourth resistor is connected to the emitter of the third triode, and the second end of the fourth resistor is grounded; the first ends of the fifth resistor, the sixth resistor, and the source of the first PMOS transistor are connected to the power supply voltage. The second end of the fifth resistor is connected to the collector and the base of the third triode; the gate of the startup transistor is connected to the base of the third triode, the drain of the startup transistor is connected to the second end of the sixth resistor and the gate of the first PMOS transistor, and the source of the startup transistor is connected to the output end of the bandgap reference core circuit; the drain of the first PMOS transistor is connected to the gate of the first NMOS transistor.

[0011] Further, the current compensation circuit includes a positive temperature coefficient current generation circuit, a low dropout linear voltage regulator circuit, and a current combiner circuit. Among them, the positive temperature coefficient current generation circuit is used to generate a positive temperature coefficient current; the low dropout linear voltage regulator circuit is used to generate a zero temperature coefficient current, a first zero temperature coefficient voltage, and a second zero temperature coefficient voltage; the current combiner circuit is used to generate a segmented compensation current based on the positive temperature coefficient voltage output from the first end of the third resistor, the first zero temperature coefficient voltage, the second zero temperature coefficient voltage, the positive temperature coefficient current, and the zero temperature coefficient current.

[0012] Further, the current combiner circuit includes a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first switch, a second switch, a third switch, a fourth switch, and a second compensation resistor. Among them, the sources of the second PMOS transistor and the third PMOS transistor are connected to the positive temperature coefficient current; the sources of the fourth PMOS transistor and the fifth PMOS transistor are connected to the zero temperature coefficient current; the gate of the second PMOS transistor is connected to the first zero temperature coefficient voltage; the gates of the third PMOS transistor and the fourth PMOS transistor are connected to the positive temperature coefficient voltage; the gate of the fifth PMOS transistor is connected to the second zero temperature coefficient voltage; the currents flowing out from the drains of the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor respectively pass through the first switch, the second switch, the third switch, and the fourth switch and are selectively connected to the output end of the current compensation circuit or the first end of the second compensation resistor; the second end of the second compensation resistor is grounded.

[0013] Further, the resistance value of the second compensation resistor is equal to the resistance value of the compensation resistor in the bandgap reference core circuit.

[0014] Further, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor have the same size.

[0015] Further, the second zero-temperature coefficient voltage is greater than the first zero-temperature coefficient voltage.

[0016] Further, when the temperature drift curve of the reference voltage is convex upward, the first switch and the third switch are connected to the first end of the second compensation resistor; the second switch and the fourth switch are connected to the first end of the compensation resistor.

[0017] Further, when the temperature drift curve of the reference voltage is concave downward, the first switch and the third switch are connected to the first end of the compensation resistor; the second switch and the fourth switch are connected to the first end of the second compensation resistor.

[0018] Further, when the reference voltage does not need to be compensated, the first switch, the second switch, the third switch, and the fourth switch are all connected to the first end of the second compensation resistor.

[0019] Further, the low-dropout linear voltage regulator circuit includes a second operational amplifier, a second NMOS transistor, and a resistor voltage division branch. Among them, the non-inverting input terminal of the second operational amplifier is connected to the output terminal of the bandgap reference core circuit, the inverting input terminal of the second operational amplifier is connected to one end of the resistor voltage division branch and the source electrode of the second NMOS transistor, and the output terminal of the second operational amplifier is connected to the gate electrode of the second NMOS transistor; the other end of the resistor voltage division branch is grounded, the resistor voltage division branch has a first voltage division output terminal and a second voltage division output terminal, the first voltage division output terminal is used to output the first zero-temperature coefficient voltage, and the second voltage division output terminal is used to output the second zero-temperature coefficient voltage; the drain electrode of the second NMOS transistor is used as the output terminal of the zero-temperature coefficient current.

[0020] Further, the low-dropout linear voltage regulator circuit further includes a sixth PMOS transistor, a seventh PMOS transistor, and an eleventh resistor. Among them, the second end of the eleventh resistor is connected to the drain electrode of the second NMOS transistor, the first end of the eleventh resistor is connected to the drain electrode of the sixth PMOS transistor and the gate electrode of the seventh PMOS transistor; the gate electrode of the sixth PMOS transistor is connected to the second end of the eleventh resistor, and the source electrode of the sixth PMOS transistor is connected to the drain electrode of the seventh PMOS transistor; the source electrode of the seventh PMOS transistor is connected to the power supply voltage.

[0021] Further, the positive temperature coefficient current generating circuit includes a fourth triode and a twelfth resistor. Among them, the base of the fourth triode is connected to the output end of the bandgap reference core circuit, the emitter of the fourth triode is connected to the first end of the twelfth resistor, and the collector of the fourth triode serves as the output end of the positive temperature coefficient current generating circuit; the second end of the twelfth resistor is grounded.

[0022] Further, the positive temperature coefficient current generating circuit further includes an eighth PMOS transistor, a ninth PMOS transistor, and a thirteenth resistor. Among them, the first end of the thirteenth resistor is connected to the drain of the eighth PMOS transistor and the gate of the ninth PMOS transistor; the second end of the thirteenth resistor is connected to the collector of the fourth triode and the gate of the eighth PMOS transistor; the source of the eighth PMOS transistor is connected to the drain of the ninth PMOS transistor, and the source of the ninth PMOS transistor is connected to the power supply voltage.

[0023] Further, the current combiner circuit further includes a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, and a thirteenth PMOS transistor. Among them, the gates of the tenth PMOS transistor and the eleventh PMOS transistor are respectively connected to the gate of the ninth PMOS transistor and the gate of the eighth PMOS transistor; the drain of the tenth PMOS transistor is connected to the source of the eleventh PMOS transistor; the source of the tenth PMOS transistor is connected to the power supply voltage; the drain of the eleventh PMOS transistor outputs the positive temperature coefficient current; the gates of the twelfth PMOS transistor and the thirteenth PMOS transistor are respectively connected to the gate of the seventh PMOS transistor and the gate of the sixth PMOS transistor; the drain of the twelfth PMOS transistor is connected to the source of the thirteenth PMOS transistor; the source of the twelfth PMOS transistor is connected to the power supply voltage; the drain of the thirteenth PMOS transistor outputs the zero temperature coefficient current.

[0024] The bandgap reference voltage source circuit according to one or more embodiments of the present application can at least achieve the following beneficial technical effects:

[0025] (1) In the bandgap reference core circuit of the present application, the base currents of the first triode and the second triode do not affect the collector current flowing through, and the current required by the base can be separately extracted from the path of the first NMOS transistor and the power supply voltage, without setting an additional base compensation current circuit;

[0026] (2) In the bandgap reference core circuit of the present application, the collector and base voltages of the first triode and the second triode maintain a fixed voltage difference in a wide temperature range, reducing the influence of the Early effect (base width modulation effect) on the accuracy of the positive temperature coefficient current;

[0027] (3) In the bandgap reference core circuit of the present application, by adjusting the ratio of the first resistor to the second resistor and the magnitudes of the compensation current output by the current compensation circuit and the compensation resistor, a reference voltage with an extremely low temperature coefficient can be output;

[0028] (4) In the bandgap reference core circuit of the present application, the first operational amplifier, the first NMOS transistor, the first resistor, and the second triode form a negative feedback loop, effectively suppressing the influence of other interference sources on the output reference voltage, making the bandgap reference voltage source circuit have good stability;

[0029] (5) The current combiner circuit of the present application can achieve three functions: compensating the reference voltage with a convex temperature drift curve, compensating the reference voltage with a concave temperature drift curve, and not compensating the reference voltage through different closing combinations of the first switch, the second switch, the third switch, and the fourth switch. Brief Description of the Drawings

[0030] Figure 1 It is a schematic structural diagram of a bandgap reference voltage source circuit according to an embodiment of the present application. Detailed Embodiments

[0031] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices consistent with some aspects of the present application as detailed in the appended claims.

[0032] Next, in conjunction with the drawings, the bandgap reference voltage source circuit of each embodiment of the present application will be described in detail. Without conflict, the features in the following embodiments and implementation manners can be combined with each other.

[0033] Figure 1 Disclosed is a schematic structural diagram of a bandgap reference voltage source circuit 100 according to an embodiment of the present application. As Figure 1 shown, a bandgap reference voltage source circuit 100 according to an embodiment of the present application includes a bandgap reference core circuit 110, a startup circuit 120, and a current compensation circuit. The startup circuit 120 is used to make the bandgap reference core circuit 110 get rid of the metastable state; the bandgap reference core circuit 110 is used to generate a reference voltage Vref; the current compensation circuit is used to compensate the temperature drift of the reference voltage Vref, thereby reducing the temperature drift of the reference voltage Vref output by the bandgap reference core circuit 110.

[0034] In some embodiments, the bandgap reference core circuit 110 of the present application includes a first NMOS transistor MN1, a first triode Q1, a second triode Q2, a first operational amplifier Opma1, a first resistor R1, a second resistor R2, a third resistor R3, and a compensation resistor R comp .

[0035] The drain of the first NMOS transistor MN1 is connected to the power supply voltage. The source of the first NMOS transistor MN1 is connected to the first end of the first resistor R1, the base of the first triode Q1, and the collector of the second triode Q2. The gate of the first NMOS transistor MN1 is connected to the output terminal of the first operational amplifier Opma1. The second end of the first resistor R1 is connected to the collector of the first triode Q1 and the base of the second triode Q2, and the first end of the first resistor R1 serves as the output terminal of the bandgap reference core circuit 110. The emitter of the first triode Q1 is connected to the first end of the second resistor R2 and the non-inverting input terminal of the first operational amplifier Opma1. The emitter of the second triode Q2 is connected to the first end of the third resistor R3 and the inverting input terminal of the first operational amplifier Opma1. The second ends of the second resistor R2 and the third resistor R3 are respectively connected to the first end of the compensation resistor R comp and the output terminal of the current compensation circuit, and the second end of the compensation resistor R comp is grounded.

[0036] Optionally, the second resistor R2 and the third resistor R3 have the same resistance value.

[0037] In the bandgap reference core circuit 110, the first operational amplifier Opma1, the first NMOS transistor MN1, and the first triode Q1 form a positive feedback loop; the first operational amplifier Opma1, the first NMOS transistor MN1, the first resistor R1, and the second triode Q2 form a negative feedback loop. By reasonably setting the resistance value of the first resistor R1 to satisfy that the gain of the negative feedback loop is greater than the gain of the positive feedback loop, the overall circuit realizes negative feedback, so that the bandgap reference core circuit 110 can maintain a stable static operating point.

[0038] The voltage difference across the first resistor R1 is equal to the difference ΔV between the base-emitter voltage of the first triode Q1 and the base-emitter voltage of the second triode Q2 be .

[0039] The difference ΔV between the base-emitter voltage of the first triode Q1 and the base-emitter voltage of the second triode Q2 be is:[[]]

[0040]

[0041] where V be1 , V be2are the base-emitter voltages of the first transistor Q1 and the second transistor Q2, k is the Boltzmann constant, T is the absolute temperature, q is the charge of a single electron, and I C1 and I C2 are the collector currents of the first transistor Q1 and the second transistor Q2 respectively, and A 1 and A 2 are the emitter cross-sectional areas of the first transistor Q1 and the second transistor Q2 respectively.

[0042] Under the gain effect of the first operational amplifier Opma1, the voltages at the first ends of the second resistor R2 and the third resistor R3 are approximately equal. Therefore, the current I R1 flowing through the first resistor R1 is equal to:

[0043]

[0044] Ignoring the base currents of the first transistor Q1 and the second transistor Q2, the emitter currents flowing through the first transistor Q1 and the second transistor Q2 are approximately equal to the current flowing through the first resistor R1 respectively. Then, the voltage generated by this current across the second resistor R2 is calculated as follows:

[0045] V R2 = I R1 * R2

[0046] The voltage V comp of this current across the compensation resistor R 1 is calculated as follows:

[0047] V1 = 2 * I R1 * R comp

[0048] Furthermore, the compensation current I comp flowing through the compensation resistor R comp generates a compensation voltage V comp . This compensation voltage V comp is calculated as follows:

[0049] V comp = I comp * R comp

[0050] Furthermore, the formula for the reference voltage Vref generated by the bandgap reference core circuit 110 is as follows:

[0051]

[0052] where V be1 is the base-emitter voltage of the first transistor Q1, and its variation formula with temperature T is as follows:

[0053]

[0054] Among them, V G0 is the bandgap voltage of silicon, T 0 is the reference temperature point of the fitting curve, V be0 is the base-emitter voltage of the first triode Q1 at temperature T 0 ; η is a process-related parameter, generally between 3 and 4;

[0055] Furthermore, the detailed calculation formula for the reference voltage Vref is obtained as follows:

[0056]

[0057] It can be seen from the above formula that the first-order temperature drift of the reference voltage Vref generated by the bandgap reference core circuit 110 can be adjusted by adjusting the ratio of the second resistor R2 to the first resistor R1, that is, using the positive first-order term that causes the temperature drift to offset the negative first-order term

[0058] In addition, by introducing the compensation current I comp output by the current compensation circuit, the non-linear temperature drift of the reference voltage Vref can be adjusted by adjusting the compensation current I comp output at the output end of the current compensation circuit and reasonably setting the resistance value of the compensation resistor R comp , that is, using the term I comp *R comp to reduce the temperature non-linear term brought by the first triode Q1 over the entire temperature range

[0059] The bandgap reference core circuit 110 of this application can have the following advantages:

[0060] (1) The base currents of the first triode Q1 and the second triode Q2 do not affect the collector currents flowing through them, and the currents required by the bases can be separately extracted from the path of the first NMOS transistor MN1 and the power supply voltage, without setting an additional base compensation current circuit;

[0061] (2) The collector and base voltages of the first triode Q1 and the second triode Q2 maintain a fixed voltage difference within a wide temperature range, reducing the accuracy influence of the Early effect (base width modulation effect) on the positive temperature coefficient current I ptat ;

[0062] (3) By adjusting the proportional relationship between the first resistor R1 and the second resistor R2 and the compensation current I comp output by the current compensation circuit and the compensation resistor Rcomp The resistance value can ensure that the output reference voltage Vref has an extremely low temperature coefficient;

[0063] (4) The first operational amplifier Opma1, the first NMOS transistor MN1, the first resistor R1, and the second triode Q2 form a negative feedback loop, effectively suppressing the influence of other interference sources on the output reference voltage Vref, making the bandgap reference voltage source circuit 100 have good stability.

[0064] Continue to refer to Figure 1 As shown, the startup circuit 120 includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first PMOS transistor MP1, a third triode Q3, and a startup transistor Mstart. The startup transistor Mstart is an NMOS transistor.

[0065] The first end of the fourth resistor R4 is connected to the emitter of the third triode Q3, and the second end of the fourth resistor R4 is grounded; the first ends of the fifth resistor R5, the sixth resistor R6, and the source of the first PMOS transistor MP1 are connected to the power supply voltage. The second end of the fifth resistor R5 is connected to the collector and the base of the third triode Q3; the gate of the startup transistor Mstart is connected to the base of the third triode Q3, the drain of the startup transistor Mstart is connected to the second end of the sixth resistor R6 and the gate of the first PMOS transistor MP1, and the source of the startup transistor Mstart is connected to the output end of the bandgap reference core circuit 110; the drain of the first PMOS transistor MP1 is connected to the gate of the first NMOS transistor MN1.

[0066] The startup circuit 120 of the present application is a dual-startup circuit. The dual-startup circuit can ensure that the core circuit works in a normal state rather than a metastable state. At the same time, after the bandgap reference core circuit 110 of the present application works normally, the startup transistor Mstart and the first PMOS transistor MP1 in the startup circuit 120 will be turned off.

[0067] In use, when the circuit is powered on, the branch where the fifth resistor R5, the third triode Q3, and the fourth resistor R4 are located is connected in series to divide the power supply voltage, such as 1.8V, to generate a voltage of approximately 1.25V at the base of the third triode Q3. The source of the startup transistor Mstart is connected to the reference voltage Vref. When the reference voltage Vref is 0 or the gate-source voltage of the startup transistor Mstart is greater than the threshold voltage of the startup transistor Mstart, the startup transistor Mstart conducts. At this time, current is injected into the bases and collectors of the first triode Q1 and the second triode Q2 that generate the reference voltage Vref. Meanwhile, by reasonably setting the resistance value of the sixth resistor R6, the gate voltage of the first PMOS transistor MP1 is pulled down, and the first PMOS transistor MP1 is turned on, causing its source voltage to rise, thereby turning on the first NMOS transistor MN1. At the same time, current is injected into the bases and collectors of the first triode Q1 and the second triode Q2 that generate the reference voltage Vref, and the bandgap reference core circuit 110 establishes a static operating point, achieving the startup effect of double-path current injection. When the reference voltage Vref output by the bandgap reference core circuit 110 reaches 1.25, the startup transistor Mstart is turned off, and the current injected into the bases and collectors of the first triode Q1 and the second triode Q2 decreases. At the same time, the gate voltage of the first PMOS transistor MP1 is raised, and the first PMOS transistor MP1 is turned off, no longer affecting the gate voltage of the first NMOS transistor MN1, and the bandgap reference core circuit 110 operates normally. Therefore, the startup circuit 120 of the present application can ensure that the bandgap reference core circuit 110 operates in a normal state rather than a metastable state. At the same time, after the bandgap reference core circuit 110 operates normally, the startup circuit 120 will be turned off to avoid increasing the power consumption of the circuit by the startup circuit 120.

[0068] Continuing to refer to Figure 1 , in some embodiments, the current compensation circuit of the present application includes a positive temperature coefficient current generation circuit 130, a low dropout linear voltage regulator circuit 140, and a current combiner circuit 150. Among them, the positive temperature coefficient current generation circuit 130 is used to generate a positive temperature coefficient current I ptat ; the low dropout linear voltage regulator circuit 140 is used to generate a zero temperature coefficient current I ztat , a first zero temperature coefficient voltage V ztat1 and a second zero temperature coefficient voltage V ztat2 ; the current combiner circuit 150 is used to generate a segmented compensation current I ptat based on the positive temperature coefficient voltage V ztat1 output from the first end of the third resistor R3, the first zero temperature coefficient voltage V ztat2 , the second zero temperature coefficient voltage V ptat , the positive temperature coefficient current I ztat and the zero temperature coefficient current I comp .

[0069] In some embodiments, the low dropout linear voltage regulator circuit 140 of the present application includes a second operational amplifier Opma2, a second NMOS transistor MN2, and a resistor voltage dividing branch 142.

[0070] The non-inverting input terminal of the second operational amplifier Opma2 is connected to the output terminal of the bandgap reference core circuit 110. The inverting input terminal of the second operational amplifier Opma2 is connected to one end of the resistor voltage dividing branch 142 and the source electrode of the second NMOS transistor MN2. The output terminal of the second operational amplifier Opma2 is connected to the gate electrode of the second NMOS transistor MN2. The other end of the resistor voltage dividing branch 142 is grounded. The resistor voltage dividing branch 142 has a first voltage dividing output terminal and a second voltage dividing output terminal. The first voltage dividing output terminal is used to output a first zero temperature coefficient voltage V ztat1 , and the second voltage dividing output terminal is used to output a second zero temperature coefficient voltage V ztat2 ; the drain electrode of the second NMOS transistor MN2 serves as the output terminal of the low dropout linear voltage regulator circuit 140. Optionally, the second zero temperature coefficient voltage V ztat2 is greater than the first zero temperature coefficient voltage V ztat1 .

[0071] In an embodiment of the present application, the resistor voltage dividing branch 142 may include a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10. The first end of the seventh resistor R7 is connected to the second end of the eighth resistor R8, and the second end of the seventh resistor R7 is grounded; the first end of the eighth resistor R8 is connected to the second end of the ninth resistor R9; the first end of the ninth resistor R9 is connected to the second end of the tenth resistor R10; the first end of the tenth resistor R10 is connected to the inverting input terminal of the second operational amplifier Opma2 and the source electrode of the second NMOS transistor MN2. The first end of the seventh resistor R7 serves as the first voltage dividing output terminal for outputting the first zero temperature coefficient voltage V ztat1 ; the first end of the eighth resistor R8 serves as the second voltage dividing output terminal for outputting the second zero temperature coefficient voltage V ztat2 .

[0072] It can be understood that Figure 1 the resistor voltage dividing branch 142 shown including the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, and the tenth resistor R10 is only a schematic example of the resistor voltage dividing branch 142 of the present application. However, the resistor voltage dividing branch 142 of the present application is not limited to Figure 1 shown, and may include other numbers of voltage dividing resistors according to actual needs. In addition, the inverting input terminal of the second operational amplifier Opma2 is not limited to being connected to the first end of the tenth resistor R10, and may also be connected to the first end of the ninth resistor R9, etc. The present application also does not limit this.

[0073] The reference voltage Vref of 1.25V is input to the non-inverting input terminal of the second operational amplifier Opma2, and the negative feedback loop formed by the second NMOS transistor MN2 makes the voltage at the non-inverting input terminal of the second operational amplifier Opma2 approximately equal to the reference voltage Vref of 1.25V. Then, the current flowing through the second NMOS transistor MN2 is the zero temperature coefficient current I ztat . When the resistor voltage division branch 142 includes the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, and the tenth resistor R10, the zero temperature coefficient current I ztat is calculated as follows:

[0074]

[0075] Furthermore, the reference voltage Vref of 1.25V is divided by the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, and the tenth resistor R10 to generate the first zero temperature coefficient voltage V ztat1 and the second zero temperature coefficient voltage V ztat2 .

[0076] In some embodiments, the low dropout linear voltage regulator circuit 140 of the present application may further include a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, and an eleventh resistor R11.

[0077] The second end of the eleventh resistor R11 is connected to the drain of the second NMOS transistor MN2, the first end of the eleventh resistor R11 is connected to the drain of the sixth PMOS transistor MP6 and the gate of the seventh PMOS transistor MP7; the gate of the sixth PMOS transistor MP6 is connected to the second end of the eleventh resistor R11, and the source of the sixth PMOS transistor MP6 is connected to the drain of the seventh PMOS transistor MP7; the source of the seventh PMOS transistor MP7 is connected to the power supply voltage.

[0078] In some embodiments, the positive temperature coefficient current generation circuit 130 of the present application includes a fourth triode Q4 and a twelfth resistor R12.

[0079] The base of the fourth triode Q4 is connected to the output terminal of the bandgap reference core circuit 110, the emitter of the fourth triode Q4 is connected to the first end of the twelfth resistor R12, and the collector of the fourth triode Q4 serves as the output terminal of the positive temperature coefficient current generation circuit 130; the second end of the twelfth resistor R12 is grounded.

[0080] The output reference voltage Vref of 1.25V serves as the base voltage of the fourth triode Q4, and the positive temperature coefficient current I ptat flowing through the twelfth resistor R12 is calculated as follows:

[0081]

[0082] where, Vbe4 is the base-emitter voltage of the fourth triode Q4.

[0083] In some embodiments, the positive temperature coefficient current generation circuit 130 of the present application may further include an eighth PMOS transistor MP8, a ninth PMOS transistor MP9, and a thirteenth resistor R13.

[0084] The first end of the thirteenth resistor R13 is connected to the drain of the eighth PMOS transistor MP8 and the gate of the ninth PMOS transistor MP9; the second end of the thirteenth resistor R13 is connected to the collector of the fourth triode Q4 and the gate of the eighth PMOS transistor MP8; the sources of the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are connected, and the source of the ninth PMOS transistor MP9 is connected to the power supply voltage.

[0085] Continue to refer to Figure 1 , in some embodiments, the current combiner circuit 150 of the present application includes a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, and a second compensation resistor R comp2 .

[0086] The sources of the second PMOS transistor MP2 and the third PMOS transistor MP3 are connected to the positive temperature coefficient current I ptat ; the sources of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are connected to the zero temperature coefficient current I ztat ; the gate of the second PMOS transistor MP2 is connected to the first zero temperature coefficient voltage V ztat1 ; the gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to the positive temperature coefficient voltage V ptat ; the gate of the fifth PMOS transistor MP5 is connected to the second zero temperature coefficient voltage V ztat2 ; the currents flowing out from the drains of the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 respectively flow through the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 and are selectively input to the output end of the current compensation circuit or input to the first end of the second compensation resistor R comp2 ; the second end of the second compensation resistor R comp2 is grounded.

[0087] Optionally, the resistance value of the second compensation resistor R comp2 is equal to the resistance value of the compensation resistor R comp in the bandgap reference core circuit 110.

[0088] The current combiner circuit 150 of the present application can achieve three functions through different closing combinations of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4: compensating the reference voltage Vref with a convex temperature drift curve, compensating the reference voltage Vref with a concave temperature drift curve, and not compensating the reference voltage Vref.

[0089] In some embodiments, the current combiner circuit 150 of the present application may further include a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, and a thirteenth PMOS transistor MP13.

[0090] The tenth PMOS transistor MP10, the eleventh PMOS transistor MP11, the ninth PMOS transistor MP9, and the eighth PMOS transistor MP8 form a first current mirror. Among them, the gates of the tenth PMOS transistor MP10 and the eleventh PMOS transistor MP11 are respectively connected to the gates of the ninth PMOS transistor MP9 and the eighth PMOS transistor MP8; the drain of the tenth PMOS transistor MP10 is connected to the source of the eleventh PMOS transistor MP11; the source of the tenth PMOS transistor MP10 is connected to the power supply voltage; the drain of the eleventh PMOS transistor MP11 outputs a positive temperature coefficient current I ptat . Thus, through the first current mirror, the positive temperature coefficient current I flowing through the ninth PMOS transistor MP9 and the eighth PMOS transistor MP8 ptat is supplied to the current combiner circuit 150.

[0091] The twelfth PMOS transistor MP12, the thirteenth PMOS transistor MP13, the seventh PMOS transistor MP7, and the sixth PMOS transistor MP6 form a second current mirror. Among them, the gates of the twelfth PMOS transistor MP12 and the thirteenth PMOS transistor MP13 are respectively connected to the gates of the seventh PMOS transistor MP7 and the sixth PMOS transistor MP6; the drain of the twelfth PMOS transistor MP12 is connected to the source of the thirteenth PMOS transistor MP13; the source of the twelfth PMOS transistor MP12 is connected to the power supply voltage; the drain of the thirteenth PMOS transistor MP13 outputs a zero temperature coefficient current I ztat . Thus, through the second current mirror, the zero temperature coefficient current I flowing through the seventh PMOS transistor MP7 and the sixth PMOS transistor MP6 ztat is supplied to the current combiner circuit 150.

[0092] For the uncompensated reference voltage Vref, although its first-order temperature coefficient can be accurately cancelled by the positive temperature coefficient voltage V ptat , due to the base-emitter voltage V of the first triode Q1 be1Due to the existence of the temperature non - linear term of the negative temperature coefficient voltage, the shape of the voltage temperature drift may present two cases: convex upward or concave downward. The current compensation circuit provided in this application can generate a compensation current I comp and reasonably set the resistance value of the compensation resistor R comp to perform segmented current compensation on the temperature non - linear term, and can achieve compensating the convex - upward temperature drift curve of the reference voltage Vref into a voltage similar to the M shape, or compensating the concave - downward temperature drift curve of the reference voltage Vref into a voltage similar to the W shape.

[0093] In one embodiment, the following will take the compensation of the convex - upward reference voltage Vref as an example for introduction.

[0094] Optionally, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 have the same size. The second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 all have the width - to - length ratio W / L of the MOS transistor.

[0095] The positive temperature coefficient voltage V at the first end of the third resistor R3 ptat comes from the bandgap reference core circuit 110 and increases with the increase of temperature; the first zero - temperature coefficient voltage V at the first end of the seventh resistor R7 ztat1 and the second zero - temperature coefficient voltage V at the first end of the eighth resistor R8 ztat2 are approximately independent of temperature within - 40°C to 125°C; reasonably set the voltage values of the first zero - temperature coefficient voltage V ztat1 and the second zero - temperature coefficient voltage V ztat2 As the positive temperature coefficient voltage V ptat gradually increases, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 turn from on to off, and the source voltage of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 gradually increases, then the gate - source voltages V sg,MP2 and V sg,MP5 of the second PMOS transistor MP2 and the fifth PMOS transistor MP5 gradually increase.

[0096] Assume that before compensation, the reference voltage Vref is in a convex - upward shape, then a non - linear compensation voltage with a concave - downward shape needs to be generated; then the two voltages are connected in series and added together, so that the reference voltage Vref after the first compensation is convex - upward from - 40°C to 80°C and convex - upward from 80°C to 125°C. This compensation can halve the fluctuation voltage range within the full temperature range through one - time temperature halving, thereby halving the temperature drift coefficient.

[0097] In one embodiment, the industrial standard temperature range of -40°C ≤ T ≤ 125°C is taken as an example for introduction. By reasonably designing the resistance value of the twelfth resistor R12 and the first zero-temperature coefficient voltage V ztat1 and the second zero-temperature coefficient voltage V ztat2 in the circuit, when the temperature is higher than 80°C, the fifth PMOS transistor MP5 can pass through an exponential-shaped subthreshold conduction current, and when the temperature is lower than 80°C, the fifth PMOS transistor MP5 is turned off, and the source-drain current of the fifth PMOS transistor MP5 is 0. The expression for the source-drain current I sd5 of the fifth PMOS transistor MP5 is:

[0098]

[0099] wherein, I 0 is proportional to the width-to-length ratio W / L of the MOS transistor, V sg5 is the source-gate voltage of the fifth PMOS transistor MP5, ξ > 1, is a non-ideal factor, and V T is the thermal voltage.

[0100] Thus, the first segmented current can be obtained, and the source-drain current of the corresponding fourth PMOS transistor MP4 is the zero-temperature coefficient current I ztat minus the current segmented with temperature flowing through the fifth PMOS transistor MP5.

[0101] Similarly, when the temperature is lower than 80°C, as the positive temperature coefficient voltage V ptat increases, the conduction current of the third PMOS transistor MP3 gradually decreases; when the temperature is higher than 80°C, the third PMOS transistor MP3 is turned off, and the source-drain current of the third PMOS transistor MP3 is zero. The expression for the source-drain current I sd3 of the third PMOS transistor MP3 is:

[0102]

[0103] wherein, I 0 is proportional to the width-to-length ratio W / L of the MOS transistor, V sg3 is the source-gate voltage of the third PMOS transistor MP3, ξ > 1, is a non-ideal factor, and V T is the thermal voltage.

[0104] Thus, the second segmented current can be obtained, and the source-drain current of the corresponding second PMOS transistor MP2 is the positive temperature coefficient current I ptat minus the current segmented with temperature flowing through the third PMOS transistor MP3.

[0105] Thus, the current flowing through the second PMOS transistor MP2 and the fifth PMOS transistor MP5 can be turned on or off at the 80 °C temperature point, so as to obtain a segmented current that turns on or off at 80 °C.

[0106] These two currents are combined in parallel to obtain a non-linear compensation current I comp , and the expression is as follows:

[0107]

[0108] This current flows through the compensation resistor R comp to obtain a non-linearly compensated voltage V comp , and the expression is as follows:

[0109]

[0110] This voltage is serially added to the uncompensated reference voltage Vref of 1.25V, and the temperature non-linear voltage of the exponent is used to cancel the temperature non-linear voltage of the logarithm, so as to achieve segmented current compensation and halve the temperature drift.

[0111] It can be understood that this application can also compensate for the concave reference voltage Vref. The compensation principle of the segmented current generation is similar to that when compensating for the convex reference voltage Vref, so it will not be elaborated here.

[0112] In one embodiment, when the temperature drift curve of the reference voltage Vref is convex, the current combiner circuit 150 can, for example, assign 0101 to the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4. Then, the first switch S1 is connected to the first end of the second compensation resistor R comp2 ; the second switch S2 is connected to the first end of the compensation resistor R comp ; the third switch S3 is connected to the first end of the second compensation resistor R comp2 ; the fourth switch S4 is connected to the first end of the compensation resistor R comp to achieve the segmented current compensation function for the convex reference voltage Vref.

[0113] In another embodiment, when the temperature drift curve of the reference voltage Vref is concave, the current combiner circuit 150 can, for example, assign 1010 to the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4. Then, the first switch S1 is connected to the first end of the compensation resistor R comp ; the second switch S2 is connected to the first end of the second compensation resistor R comp2 ; the third switch S3 is connected to the first end of the compensation resistor R comp ; the fourth switch S4 is connected to the first end of the second compensation resistor R comp2The first end realizes the segmented current compensation function for the concave reference voltage Vref.

[0114] In yet another embodiment, when the reference voltage Vref does not need compensation, the current combiner circuit 150 can, for example, assign 1111 to the switches S1_S2_S3_S4. Then the first switch S1 is connected to the first end of the second compensation resistor R comp2 The first end; the second switch S2 is connected to the first end of the second compensation resistor R comp2 The first end; the third switch S3 is connected to the first end of the second compensation resistor R comp2 The first end; the fourth switch S4 is connected to the first end of the second compensation resistor R comp2 The first end realizes the isolation of the bandgap reference core circuit 110 and the current compensation circuit, and the segmented compensation current I comp Is zero, achieving the function of no compensation.

[0115] The bandgap reference voltage source circuit 100 of the present application can achieve an extremely low temperature drift coefficient in a wide temperature range.

[0116] The bandgap reference voltage source circuit provided by the embodiments of the present application has been introduced in detail above. Specific examples are used herein to elaborate on the bandgap reference voltage source circuit of the embodiments of the present application. The descriptions of the above embodiments are only used to help understand the core idea of the present application and are not intended to limit the present application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the spirit and principle of the present application, several improvements and modifications can still be made to the present application, and these improvements and modifications should also fall within the protection scope of the appended claims of the present application.

Claims

1. A bandgap reference voltage source circuit, characterized in that: It includes a startup circuit, a bandgap reference core circuit and a current compensation circuit, wherein the startup circuit is used to make the bandgap reference core circuit get rid of the metastable state; the bandgap reference core circuit is used to generate a reference voltage; the current compensation circuit is used to compensate for the temperature drift of the reference voltage, wherein: The bandgap reference core circuit includes a first NMOS transistor, a first triode, a second triode, a first operational amplifier, a first resistor, a second resistor, a third resistor and a compensation resistor. The drain of the first NMOS tube is connected to the power supply voltage, the source of the first NMOS tube is connected to the first end of the first resistor, the base of the first transistor and the collector of the second transistor, and the gate of the first NMOS tube is connected to the output end of the first operational amplifier; the second end of the first resistor is respectively connected to the collector of the first transistor and the base of the second transistor, and the first end of the first resistor serves as the output end of the bandgap reference core circuit; the emitter of the first transistor is connected to the first end of the second resistor and the non-inverting input end of the first operational amplifier; the emitter of the second transistor is connected to the first end of the third resistor and the reverse input end of the first operational amplifier; the second end of the second resistor and the second end of the third resistor are respectively connected to the first end of the compensation resistor and the output end of the current compensation circuit, and the second end of the compensation resistor is grounded.

2. The bandgap reference voltage source circuit according to claim 1, wherein: The voltage difference across the first resistor is equal to the difference between the base and emitter voltage of the first transistor and the base and emitter voltage of the second transistor.

3. The bandgap reference voltage source circuit according to claim 1, wherein: The second resistor and the third resistor have the same resistance value.

4. The bandgap reference voltage source circuit as claimed in claim 3, characterized in that: The first-order temperature drift of the reference voltage generated by the bandgap reference core circuit is adjusted by adjusting the ratio of the second resistor to the first resistor; the nonlinear temperature drift of the reference voltage is adjusted by adjusting the compensation current output from the output end of the current compensation circuit and the resistance value of the compensation resistor.

5. The bandgap reference voltage source circuit according to claim 1, wherein: The startup circuit includes a fourth resistor, a fifth resistor, a sixth resistor, a first PMOS transistor, a third triode and a startup transistor, wherein: The first end of the fourth resistor is connected to the emitter of the third transistor, and the second end of the fourth resistor is grounded; the first end of the fifth resistor, the first end of the sixth resistor and the source of the first PMOS tube are connected to the power supply voltage, and the second end of the fifth resistor is connected to the collector and base of the third transistor; the gate of the start-up tube is connected to the base of the third transistor, the drain of the start-up tube is connected to the second end of the sixth resistor and the gate of the first PMOS tube, and the source of the start-up tube is connected to the output end of the bandgap reference core circuit; the drain of the first PMOS tube is connected to the gate of the first NMOS tube.

6. The bandgap reference voltage source circuit according to claim 1, wherein: The current compensation circuit includes a positive temperature coefficient current generating circuit, a low voltage drop linear voltage regulator circuit and a current combiner circuit, wherein: The positive temperature coefficient current generating circuit is used to generate a positive temperature coefficient current; The low voltage difference linear voltage stabilization circuit is used to generate a zero temperature coefficient current, a first zero temperature coefficient voltage and a second zero temperature coefficient voltage; The current combiner circuit is used to generate a segmented compensation current based on the positive temperature coefficient voltage outputted from the first end of the third resistor, the first zero temperature coefficient voltage, the second zero temperature coefficient voltage, the positive temperature coefficient current, and the zero temperature coefficient current.

7. The bandgap reference voltage source circuit according to claim 6, wherein: The current combiner circuit includes a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first switch, a second switch, a third switch, a fourth switch and a second compensation resistor, wherein: The source of the second PMOS tube and the source of the third PMOS tube are connected to the positive temperature coefficient current; the source of the fourth PMOS tube and the source of the fifth PMOS tube are connected to the zero temperature coefficient current; the gate of the second PMOS tube is connected to the first zero temperature coefficient voltage; the gate of the third PMOS tube and the gate of the fourth PMOS tube are connected to the positive temperature coefficient voltage; the gate of the fifth PMOS tube is connected to the second zero temperature coefficient voltage; the current flowing out of the drain of the second PMOS tube, the drain of the third PMOS tube, the drain of the fourth PMOS tube and the drain of the fifth PMOS tube respectively passes through the first switch, the second switch, the third switch and the fourth switch to selectively flow into the output end of the current compensation circuit or into the first end of the second compensation resistor; the second end of the second compensation resistor is grounded.

8. The bandgap reference voltage source circuit according to claim 7, wherein: The resistance value of the second compensation resistor is equal to the resistance value of the compensation resistor in the bandgap reference core circuit.

9. The bandgap reference voltage source circuit according to claim 7, wherein: The second PMOS tube, the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube have the same size.

10. The bandgap reference voltage source circuit according to claim 7, wherein: The second zero temperature coefficient voltage is greater than the first zero temperature coefficient voltage.

11. The bandgap reference voltage source circuit according to claim 10, wherein: When the temperature drift curve of the reference voltage is convex, the first switch and the third switch are connected to the first end of the second compensation resistor; the second switch and the fourth switch are connected to the first end of the compensation resistor.

12. The bandgap reference voltage source circuit according to claim 10, wherein: When the temperature drift curve of the reference voltage is concave, the first switch and the third switch are connected to the first end of the compensation resistor; and the second switch and the fourth switch are connected to the first end of the second compensation resistor.

13. The bandgap reference voltage source circuit according to claim 10, wherein: When the reference voltage does not need to be compensated, the first switch, the second switch, the third switch and the fourth switch are all connected to the first end of the second compensation resistor.

14. The bandgap reference voltage source circuit according to claim 7, wherein: The low voltage difference linear voltage stabilization circuit comprises a second operational amplifier, a second NMOS tube and a resistor voltage divider branch, wherein: The non-inverting input terminal of the second operational amplifier is connected to the output terminal of the bandgap reference core circuit, the inverting input terminal of the second operational amplifier is connected to one end of the resistive voltage divider branch and the source of the second NMOS tube, and the output terminal of the second operational amplifier is connected to the gate of the second NMOS tube; the other end of the resistive voltage divider branch is grounded, and the resistive voltage divider branch has a first voltage divider output terminal and a second voltage divider output terminal, the first voltage divider output terminal is used to output the first zero temperature coefficient voltage, and the second voltage divider output terminal is used to output the second zero temperature coefficient voltage; the drain of the second NMOS tube serves as the output terminal of the zero temperature coefficient current.

15. The bandgap reference voltage source circuit according to claim 14, wherein: The low voltage difference linear voltage regulator circuit further includes a sixth PMOS tube, a seventh PMOS tube and an eleventh resistor, wherein: The second end of the eleventh resistor is connected to the drain of the second NMOS tube, and the first end of the eleventh resistor is connected to the drain of the sixth PMOS tube and the gate of the seventh PMOS tube; the gate of the sixth PMOS tube is connected to the second end of the eleventh resistor, and the source of the sixth PMOS tube is connected to the drain of the seventh PMOS tube; the source of the seventh PMOS tube is connected to the power supply voltage.

16. The bandgap reference voltage source circuit according to claim 15, wherein: The positive temperature coefficient current generating circuit comprises a fourth transistor and a twelfth resistor, wherein: The base of the fourth transistor is connected to the output end of the bandgap reference core circuit, the emitter of the fourth transistor is connected to the first end of the twelfth resistor, the collector of the fourth transistor serves as the output end of the positive temperature coefficient current generating circuit; the second end of the twelfth resistor is grounded.

17. The bandgap reference voltage source circuit according to claim 16, wherein: The positive temperature coefficient current generating circuit further includes an eighth PMOS tube, a ninth PMOS tube and a thirteenth resistor, wherein: The first end of the thirteenth resistor is connected to the drain of the eighth PMOS tube and the gate of the ninth PMOS tube; the second end of the thirteenth resistor is connected to the collector of the fourth transistor and the gate of the eighth PMOS tube; the source of the eighth PMOS tube is connected to the drain of the ninth PMOS tube, and the source of the ninth PMOS tube is connected to the power supply voltage.

18. The bandgap reference voltage source circuit according to claim 17, wherein: The current combiner circuit further includes a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor and a thirteenth PMOS transistor, wherein: The gate of the tenth PMOS tube and the gate of the eleventh PMOS tube are respectively connected to the gate of the ninth PMOS tube and the gate of the eighth PMOS tube; the drain of the tenth PMOS tube is connected to the source of the eleventh PMOS tube; the source of the tenth PMOS tube is connected to the power supply voltage; the drain of the eleventh PMOS tube outputs the positive temperature coefficient current; the gate of the twelfth PMOS tube and the gate of the thirteenth PMOS tube are respectively connected to the gate of the seventh PMOS tube and the gate of the sixth PMOS tube; the drain of the twelfth PMOS tube is connected to the source of the thirteenth PMOS tube; the source of the twelfth PMOS tube is connected to the power supply voltage; the drain of the thirteenth PMOS tube outputs the zero temperature coefficient current.

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