Data synchronization circuit and device

Abstract

The invention provides a data synchronization circuit and device. The circuit comprises a signal input module, a signal modulation module, a demodulation module and a quick push-pull logic module, the signal input module is used for acquiring input data and clock signals; the signal modulation module is used for modulating input data based on a clock signal to generate a modulation signal; the quick push-pull logic module is used for performing quick push-pull based on the input data and the clock signal to obtain a quick push-pull signal; the demodulation module comprises a Schmitt trigger; the demodulation module is used for carrying out preliminary demodulation on the modulation signal to obtain a preliminary demodulation signal, then the preliminary demodulation signal is pushed and pulled based on the rapid push-pull signal to obtain a push-pull modulation signal, and the Schmitt trigger is used for filtering the push-pull modulation signal and outputting a terminal demodulation signal. The invention provides a data synchronization circuit and device, which can reduce the phenomena of signal delay and pulse width distortion, guarantee the stability and reliability of a sequential logic circuit, and reduce the problems of data errors and circuit misoperation.

Description

Technical Field

[0001] The present invention relates to the field of digital information transmission, and particularly to a data synchronization circuit and device. Background Art

[0002] In today's field of electronic circuit technology, especially in sequential logic circuits, data generally only changes when the clock edge arrives. For synchronous logic circuits, all the clock signals that control the internal circuit actions are derived from the same reference clock source, and data will only change when triggered by a unified clock edge. In asynchronous logic circuits, the dynamic change of data may be driven by different clock sources. Therefore, the phase relationship between the input data and the clock is completely irrelevant. When the clock edge arrives, the input data may be exactly in the process of changing, causing the output of the asynchronous logic circuit to be in an indeterminate state, affecting the stability and reliability of the circuit.

[0003] In addition to paying attention to the correctness of the output logic level, two other indicators are also relatively important. One is the delay of the output signal compared to the input signal. For example, the time difference between the rising edge of the output signal and the rising edge of the input signal. The other is pulse width distortion, that is, the difference between the pulse width of the output signal and the pulse width of the input signal, which can also be defined as the difference between the rising edge delay time and the falling edge delay time. In the prior art, when data is transmitted in different clock domains, in order to avoid indeterminate states, conventional asynchronous data synchronization methods, the two-time synchronization - double sampling method, are often used to reduce the probability of generating indeterminate states. During the double sampling method process, in the worst case, there is a delay of nearly 2 clock cycles. The maximum pulse width distortion is close to 1 clock cycle. For some fields with extremely high time sensitivity requirements such as high-speed signal processing, real-time communication, and precision measurement, this processing method will cause delays and pulse width distortions, affecting the stability and reliability of the sequential logic circuit, resulting in problems such as data errors and circuit malfunction. Summary of the Invention

[0004] The present invention aims to provide a data synchronization circuit and device to solve the above technical problems, reduce signal delay and pulse width distortion phenomena, ensure the stability and reliability of the sequential logic circuit, and reduce problems such as data errors and circuit malfunction.

[0005] To solve the above technical problems, the present invention provides a data synchronization circuit, including a signal input module, a signal modulation module, a demodulation module, and a fast push-pull logic module; wherein:

[0006] The signal input module is used to obtain input data and a clock signal;

[0007] The signal modulation module is used to modulate the input data based on the clock signal to generate a modulation signal;

[0008] The fast push-pull logic module is used to perform fast push-pull based on the input data and the clock signal to obtain a fast push-pull signal;

[0009] The demodulation module includes a Schmitt trigger;

[0010] The demodulation module is used to perform preliminary demodulation on the modulation signal to obtain a preliminary demodulation signal, and then push-pull the preliminary demodulation signal based on the fast push-pull signal to obtain a push-pull modulation signal. The Schmitt trigger is used to filter the push-pull modulation signal and output a terminal demodulation signal.

[0011] In the above solution, the input data and the clock signal are jointly input into the fast push-pull logic module to generate a fast push-pull signal, so as to perform fast push-pull on the modulation signal; using the fast push-pull logic module can avoid the situation where the first falling edge of the preliminary demodulation signal is fast and the last rising edge is slow, thereby preventing the problem that the rising edge delay of the terminal demodulation signal after being processed by the Schmitt trigger is small and the falling edge delay is large, effectively reducing the delay of the terminal demodulation signal and suppressing the pulse width distortion phenomenon, so as to achieve accurate data synchronization, ensure the stability and reliability of the sequential logic circuit, and reduce the occurrence of data errors and circuit malfunction problems.

[0012] Further, the signal modulation module includes a first inverter and a first NOR gate;

[0013] The first inverter is used to convert the input data into logically inverted data and transmit the logically inverted data to the first NOR gate;

[0014] The first NOR gate is used to perform a NOR operation on the logically inverted data based on the clock signal and generate a modulation signal.

[0015] In the above solution, the first NOR gate performs a NOR operation: when the input data is at a low level, the modulation signal modulated by the first NOR gate is at a low level state; when the input data is at a high level, the modulation signal modulated by the first NOR gate is the inverse of the clock signal.

[0016] Further, the demodulation module includes a pulse narrowing module and a filtering module;

[0017] The pulse narrowing module is used to perform preliminary demodulation and pulse narrowing on the modulation signal to obtain a preliminary demodulation signal and transmit the preliminary demodulation signal to the filtering module;

[0018] The Schmitt trigger is arranged in the filtering module;

[0019] The filtering module is used to push-pull the preliminary demodulation signal based on the fast push-pull signal and output a terminal demodulation signal through the Schmitt trigger.

[0020] In the above solution, the pulse narrowing module can perform pulse width compression processing on the modulation signal to obtain a preliminary demodulation signal with a 2-fold clock frequency; the filtering module can make the waveform of the signal smoother. It can make the irregular signal waveform more regular, reduce signal jitter, and improve signal stability.

[0021] Further, the pulse narrowing module includes a delay element and a second NOR gate;

[0022] The delay element is used to delay the modulation signal to obtain a delayed modulation signal, and transmit the delayed modulation signal to the second NOR gate;

[0023] The second NOR gate is used to perform a NOR operation on the modulation signal and the delayed modulation signal to generate a preliminary demodulation signal, and transmit the preliminary demodulation signal to the filtering module.

[0024] In the above solution, the delay element works in cooperation with the modulation signal, and the second NOR gate performs a NOR operation on the modulation signal and the delayed modulation signal to achieve pulse width compression processing and obtain a preliminary demodulation signal with a 2-fold clock frequency; the delay element has a signal timing adjustment function, and by delaying the modulation signal, it changes the time correlation of the signal to achieve precise control of the timing of each signal in the circuit.

[0025] Further, the filtering module includes a first NMOS transistor, a second PMOS transistor, a current limiting resistor, a voltage stabilizing capacitor, and a second inverter;

[0026] The gate of the second PMOS transistor is connected to the output end of the second NOR gate, the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, and the source of the second PMOS transistor is connected to the power supply; the gate of the first NMOS transistor is connected to the output end of the second NOR gate, and the source of the first NMOS transistor is grounded; the first NMOS transistor and the second PMOS transistor are used to perform asymmetric charge and discharge on the preliminary demodulation signal to obtain a pre-push-pull signal, and transmit the pre-push-pull signal to the fast push-pull logic module, so that the fast push-pull logic module performs push-pull on the pre-push-pull signal to obtain a push-pull modulation signal, and transmit the push-pull modulation signal to the Schmitt trigger;

[0027] The first connection end of the current limiting resistor is connected to the source of the second PMOS transistor, the second connection end of the current limiting resistor is connected to the drain of the first NMOS transistor and the input end of the Schmitt trigger, and the current limiting resistor is used to limit the charging current of the voltage stabilizing capacitor;

[0028] The first connection terminal of the voltage stabilizing capacitor is connected to the second connection terminal of the current limiting resistor and the input terminal of the Schmitt trigger. The second connection terminal of the voltage stabilizing capacitor is connected to the ground. The voltage stabilizing capacitor is used to stabilize the pre-push-pull signal;

[0029] The second inverter is used to invert the logical state of the push-pull modulation signal filtered by the Schmitt trigger to output a terminal demodulation signal.

[0030] In the above solution, the asymmetric charge and discharge changes the characteristics of the pre-push-pull signal by controlling the charge and discharge speed and path of the voltage stabilizing capacitor, playing a role in adjusting the signal waveform, reducing pulse width distortion, and achieving precise data synchronization.

[0031] Further, the asymmetric charge and discharge method has two modes: slow charge and fast discharge, and fast charge and slow discharge;

[0032] The slow charge and fast discharge mode is specifically as follows: in the charging stage, the gate-source voltage of the first PMOS transistor is greater than the turn-on voltage of the first PMOS transistor, and the first PMOS transistor is in a relatively cut-off state. The power supply current slowly charges the voltage stabilizing capacitor through the current limiting resistor, causing the voltage of the voltage stabilizing capacitor to rise slowly; in the discharging stage, the gate-source voltage of the first NMOS transistor is greater than the turn-on voltage of the first NMOS transistor, and the first NMOS transistor is quickly turned on, enabling the charge stored on the voltage stabilizing capacitor to be quickly released through the first NMOS transistor, and the voltage of the voltage stabilizing capacitor quickly drops, obtaining a pre-push-pull signal with slow charge and fast discharge;

[0033] The fast charge and slow discharge mode is specifically as follows: in the charging stage, the gate-source voltage of the first PMOS transistor is less than the turn-on voltage of the first PMOS transistor, and the first PMOS transistor is quickly turned on. The power supply current quickly flows to the voltage stabilizing capacitor, and the voltage of the voltage stabilizing capacitor quickly rises; in the discharging stage, the gate-source voltage of the first NMOS transistor is less than the turn-on voltage of the first NMOS transistor, and the first NMOS transistor is in a relatively cut-off state. The voltage stabilizing capacitor discharges through the current limiting resistor, and the discharge current is small, and the voltage of the voltage stabilizing capacitor slowly drops, obtaining a pre-push-pull signal with fast charge and slow discharge.

[0034] In the above solution, slow charge and fast discharge make the signal before push-pull exhibit the characteristics of a slow rising edge and a fast falling edge. Without this processing, the signal before push-pull may have a small delay in the rising edge and a large delay in the falling edge after passing through the Schmitt trigger, resulting in the pulse width of the terminal demodulated signal being greater than the pulse width of the input data; while slow charge and fast discharge can improve this situation, reduce the pulse width distortion, and ensure the accuracy of data transmission; fast charge and slow discharge make the signal before push-pull exhibit the characteristics of a fast rising edge and a slow falling edge. Without this processing, the signal before push-pull may have a large delay in the rising edge and a small delay in the falling edge after passing through the Schmitt trigger, resulting in the pulse width of the terminal demodulated signal being greater than the pulse width of the input data; while fast charge and slow discharge can improve this situation, reduce the pulse width distortion, and ensure the accuracy of data transmission;

[0035] Further, the fast push-pull logic module includes an AND gate and a first PMOS transistor;

[0036] The AND gate is used to perform an AND operation on the clock signal and the input data to obtain a preliminary push-pull signal, and transmit the preliminary push-pull signal to the first PMOS transistor;

[0037] The drain of the first PMOS transistor is connected to the input end of the Schmitt trigger, the gate of the first PMOS transistor is connected to the output end of the AND gate, and the source of the first PMOS transistor is connected to the power supply; the first PMOS transistor is used to quickly push and pull the potential of the signal before push-pull to obtain a push-pull modulation signal, and transmit the push-pull modulation signal to the Schmitt trigger.

[0038] In the above solution, after introducing the fast push-pull module to quickly push and pull the signal before push-pull, the problem of pulse width distortion caused by asymmetric charge and discharge can be improved, and excessive pulse width distortion can be avoided.

[0039] Further, the fast push-pull has two modes: fast pull-up and fast pull-down;

[0040] The specific method of the fast pull-up mode is: the first PMOS transistor is used to pull up the potential of the signal before push-pull to the power supply voltage to obtain a pull-up push-pull modulation signal, and transmit the push-pull modulation signal to the Schmitt trigger;

[0041] The specific method of the fast pull-down mode is: the first PMOS transistor is used to pull down the potential of the signal before push-pull to the ground potential to obtain a pull-down push-pull modulation signal, and transmit the push-pull modulation signal to the Schmitt trigger.

[0042] In the above solution, during the slow charging and fast discharging process, if only the second PMOS transistor and the current-limiting resistor are relied on to charge the voltage-stabilizing capacitor, the rising edge of the push-pull modulation signal will be very slow. When adopting the fast pull-up method, the first PMOS transistor pulls up the push-pull modulation signal. When the gate-source voltage of the first PMOS transistor is less than its turn-on voltage, the first PMOS transistor conducts. At this time, the first PMOS transistor can quickly pull up the potential of the pre-push-pull signal to the power supply voltage, obtaining the pulled-up push-pull modulation signal, avoiding the problem of pulse-width distortion caused by the slow rising edge of the push-pull modulation signal; during the fast charging and slow discharging process, there is a problem that the falling edge of the pre-push-pull signal is not fast enough. Fast pulling down can ensure that the signal quickly drops to a low level, avoiding the adverse effect of pulse-width distortion caused by the slow falling of the pre-push-pull signal, ensuring the accuracy of data transmission and the stability of signal processing.

[0043] The present invention provides a data synchronization device. The data synchronization circuit device includes a housing, and the above-mentioned data synchronization circuit is arranged in the housing; a data input interface, a data output interface and a power supply interface are arranged on the housing; the data input interface is electrically connected to the signal input module, the data output interface is electrically connected to the demodulation module, and the power supply interface is electrically connected to the fast push-pull logic module.

[0044] The data synchronization device provided by the above solution has a simple structure. In practical applications, only the signal input module needs to be connected through the data input interface, the demodulation module needs to be connected through the data output interface, and the fast push-pull logic module needs to be powered on through the power supply interface, so that data synchronization can be completed stably and reliably. At the same time, the delay of the terminal demodulation signal can be effectively reduced, and the pulse-width distortion phenomenon can be suppressed, realizing accurate data synchronization, ensuring the stability and reliability of the sequential logic circuit, and reducing the occurrence of data errors and circuit malfunction problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a structural diagram of a data synchronization circuit provided by an embodiment of the present invention;

[0046] Figure 2 It is a circuit diagram of a data synchronization circuit provided by an embodiment of the present invention;

[0047] Figure 3 It is a signal waveform diagram of a data synchronization circuit provided by an embodiment of the present invention;

[0048] Figure 4 It is a signal waveform diagram of a data synchronization circuit without a fast push-pull module provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0049] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0050] Please refer to Figure 1 , this embodiment provides a data synchronization circuit, and its architecture is specifically shown in Figure 1 , including:

[0051] A signal input module for acquiring input data and a clock signal;

[0052] A signal modulation module for modulating the input data based on the clock signal to generate a modulation signal;

[0053] A fast push-pull logic module for performing fast push-pull based on the input data and the clock signal to obtain a fast push-pull signal;

[0054] A demodulation module includes a Schmitt trigger; the demodulation module is used for preliminarily demodulating the modulation signal to obtain a preliminary demodulation signal, and then pushing and pulling the preliminary demodulation signal based on the fast push-pull signal to obtain a push-pull modulation signal, and the Schmitt trigger is used for filtering the push-pull modulation signal and outputting a terminal demodulation signal.

[0055] The data synchronization circuit provided in this embodiment proposes a new data synchronization method to provide smaller delay and data pulse width distortion; the input data and the clock signal are jointly input to the fast push-pull logic module to generate a fast push-pull signal, so as to perform fast push-pull on the modulation signal; the fast push-pull logic module can avoid the situation that the first falling edge of the preliminary demodulation signal is fast and the last rising edge is slow, thereby preventing the problem that the rising edge delay of the terminal demodulation signal processed by the Schmitt trigger is small and the falling edge delay is large, effectively reducing the delay of the terminal demodulation signal and suppressing the pulse width distortion phenomenon, so as to achieve accurate data synchronization, ensure the stability and reliability of the sequential logic circuit, and reduce the occurrence of data errors and circuit malfunction problems.

[0056] Please refer to Figure 2 , which is the circuit structure diagram of a data synchronization circuit provided in this embodiment. The signal modulation module includes a first inverter and a first NOR gate;

[0057] The first inverter is used to convert the input data into logically inverted data and transmit the logically inverted data to the first NOR gate;

[0058] The first NOR gate is configured to perform a NOR operation on the logic state inverted data based on the clock signal and generate a modulation signal.

[0059] In this embodiment, first, the input data is subjected to OOK modulation using a clock. OOK modulation can be implemented using a NOR gate or an AND gate. In this embodiment, a NOR gate is adopted. The first NOR gate performs a NOR operation: when the input data is at a low level, the modulation signal after being modulated by the first NOR gate is at a low level state; when the input data is at a high level, the modulation signal after being modulated by the first NOR gate is the inversion of the clock signal, solving the problem of data synchronization; adopting a NOR gate can effectively reduce the delay, enabling the circuit to detect the level of the input data once every half clock signal period.

[0060] Further, the demodulation module includes a pulse narrowing module and a filtering module;

[0061] The pulse narrowing module is configured to perform preliminary demodulation and pulse narrowing on the modulation signal to obtain a preliminary demodulation signal, and transmit the preliminary demodulation signal to the filtering module;

[0062] The Schmitt trigger is disposed within the filtering module;

[0063] The filtering module is configured to push-pull the preliminary demodulation signal based on the fast push-pull signal and output a terminal demodulation signal through the Schmitt trigger.

[0064] In this embodiment, the pulse narrowing module can perform pulse width compression processing on the modulation signal to obtain a preliminary demodulation signal with a 2-fold clock frequency; the filtering module can make the waveform of the signal smoother. It can make the irregular signal waveform more regular, filter out the lower charging waveform, reduce signal jitter, obtain a square wave signal output, and improve signal stability; the terminal demodulation signal is only changed when the clock signal is at a low level, so that when the terminal demodulation signal is sampled at the rising edge of the clock signal, no metastable error will occur.

[0065] Further, the pulse narrowing module includes a delay element and a second NOR gate;

[0066] The delay element is configured to delay the modulation signal to obtain a delayed modulation signal, and transmit the delayed modulation signal to the second NOR gate;

[0067] The second NOR gate is configured to perform a NOR operation on the modulation signal and the delayed modulation signal to generate a preliminary demodulation signal, and transmit the preliminary demodulation signal to the filtering module.

[0068] In this embodiment, the delay device works in cooperation with the modulation signal. The second NOR gate performs a NOR operation on the modulation signal and the delayed modulation signal to implement pulse width compression processing, and obtains a preliminary demodulation signal of a narrow pulse with a 2-fold clock frequency. The delay device has a signal timing adjustment function. By delaying the modulation signal, the time correlation of the signal is changed, and precise control of the timing of each signal in the circuit is achieved.

[0069] Further, the filtering module includes a first NMOS transistor, a second PMOS transistor, a current limiting resistor, a voltage stabilizing capacitor, and a second inverter;

[0070] The gate of the second PMOS transistor is connected to the output end of the second NOR gate. The drain of the second PMOS transistor is connected to the drain of the first NMOS transistor. The source of the second PMOS transistor is connected to the power supply. The gate of the first NMOS transistor is connected to the output end of the second NOR gate. The source of the first NMOS transistor is grounded. The first NMOS transistor and the second PMOS transistor are used to perform asymmetric charge and discharge on the preliminary demodulation signal, obtain a signal before push-pull, and transmit the signal before push-pull to the fast push-pull logic module, so that the fast push-pull logic module performs push-pull on the signal before push-pull, obtains a push-pull modulation signal, and transmits the push-pull modulation signal to the Schmitt trigger;

[0071] The first connection end of the current limiting resistor is connected to the source of the second PMOS transistor. The second connection end of the current limiting resistor is connected to the drain of the first NMOS transistor and the input end of the Schmitt trigger. The current limiting resistor is used to limit the charging current of the voltage stabilizing capacitor;

[0072] The first connection end of the voltage stabilizing capacitor is connected to the second connection end of the current limiting resistor and the input end of the Schmitt trigger. The second connection end of the voltage stabilizing capacitor is connected to the ground. The voltage stabilizing capacitor is used to stabilize the signal before push-pull;

[0073] The second inverter is used to invert the logical state of the push-pull modulation signal filtered by the Schmitt trigger to output a terminal demodulation signal.

[0074] In this embodiment, the first NMOS transistor and the second PMOS transistor form an inverter to perform asymmetric charge and discharge. The asymmetric charge and discharge changes the characteristics of the signal before push-pull by controlling the charge and discharge speed and path of the voltage stabilizing capacitor, plays a role in adjusting the signal waveform, reducing pulse width distortion, and achieving precise data synchronization.

[0075] Further, the asymmetric charge and discharge method has two methods: slow charge and fast discharge, and fast charge and slow discharge;

[0076] The slow charge and fast discharge method is specifically as follows: in the charging stage, the gate-source voltage of the first PMOS transistor is greater than the turn-on voltage of the first PMOS transistor, and the first PMOS transistor is in a relatively cut-off state. The power supply current slowly charges the voltage-stabilizing capacitor through the current-limiting resistor, causing the voltage of the voltage-stabilizing capacitor to rise slowly; in the discharging stage, the gate-source voltage of the first NMOS transistor is greater than the turn-on voltage of the first NMOS transistor, and the first NMOS transistor is quickly turned on, enabling the charge stored on the voltage-stabilizing capacitor to be quickly released through the first NMOS transistor, and the voltage of the voltage-stabilizing capacitor quickly drops to obtain the push-pull pre-signal for slow charge and fast discharge;

[0077] The fast charge and slow discharge method is specifically as follows: in the charging stage, the gate-source voltage of the first PMOS transistor is less than the turn-on voltage of the first PMOS transistor, and the first PMOS transistor is quickly turned on. The power supply current quickly flows to the voltage-stabilizing capacitor, and the voltage of the voltage-stabilizing capacitor quickly rises; in the discharging stage, the gate-source voltage of the first NMOS transistor is less than the turn-on voltage of the first NMOS transistor, and the first NMOS transistor is in a relatively cut-off state. The voltage-stabilizing capacitor discharges through the current-limiting resistor, and the discharge current is small, and the voltage of the voltage-stabilizing capacitor slowly drops to obtain the push-pull pre-signal for fast charge and slow discharge.

[0078] In this embodiment, slow charge and fast discharge make the push-pull pre-signal exhibit the characteristics of a slow rising edge and a fast falling edge. Without this processing, the push-pull pre-signal may have a small rising-edge delay and a large falling-edge delay after passing through the Schmitt trigger, resulting in the pulse width of the terminal demodulation signal being greater than the pulse width of the input data; while slow charge and fast discharge can improve this situation, reduce the pulse-width distortion, and ensure the accuracy of data transmission; fast charge and slow discharge make the push-pull pre-signal exhibit the characteristics of a fast rising edge and a slow falling edge. Without this processing, the push-pull pre-signal may have a large rising-edge delay and a small falling-edge delay after passing through the Schmitt trigger, resulting in the pulse width of the terminal demodulation signal being greater than the pulse width of the input data; while fast charge and slow discharge can improve this situation, reduce the pulse-width distortion, and ensure the accuracy of data transmission;

[0079] Further, the fast push-pull logic module includes an AND gate and a first PMOS transistor;

[0080] The AND gate is used to perform an AND operation on the clock signal and the input data to obtain a preliminary push-pull signal and transmit the preliminary push-pull signal to the first PMOS transistor;

[0081] The drain of the first PMOS transistor is connected to the input end of the Schmitt trigger, the gate of the first PMOS transistor is connected to the output end of the AND gate, and the source of the first PMOS transistor is connected to the power supply; the first PMOS transistor is used to quickly push and pull the potential of the push-pull pre-signal to obtain a push-pull modulation signal and transmit the push-pull modulation signal to the Schmitt trigger.

[0082] In this embodiment, since the AND gate is used to perform an AND operation on the clock signal and the input data, if the input data has become low at this time, when the clock signal changes from high level to low level, the preliminary push-pull signal will follow the falling edge of the clock signal and become low level; after the preliminary push-pull signal becomes low level, the first PMOS transistor will become conducting, and at this time the push-pull modulation signal will be pulled high to high level; if the fast push-pull logic module is not added, the rise of the push-pull modulation signal without the fast push-pull logic module is slow and the fall is fast. After passing through the Schmitt trigger, the terminal demodulation signal will have a phenomenon that the rising edge delay is small and the falling edge delay is large, and the pulse width of the terminal demodulation signal will be greater than the pulse width of the input data, resulting in an increase in pulse width distortion; while introducing the fast push-pull module to perform fast push-pull on the signal before push-pull can improve the pulse width distortion problem caused by asymmetric charge and discharge and avoid excessive pulse width distortion.

[0083] Further, the fast push-pull has two modes: fast pull-up and fast pull-down;

[0084] The specific fast pull-up mode is: the first PMOS transistor is used to pull the potential of the signal before push-pull up to the power supply voltage, obtain the pull-up push-pull modulation signal, and transmit the push-pull modulation signal to the Schmitt trigger;

[0085] The specific fast pull-down mode is: the first PMOS transistor is used to pull the potential of the signal before push-pull down to the ground potential, obtain the pull-down push-pull modulation signal, and transmit the push-pull modulation signal to the Schmitt trigger.

[0086] In this embodiment, during the slow charge and fast discharge process, if only relying on the second PMOS transistor and the current limiting resistor to charge the voltage stabilizing capacitor, the rising edge of the push-pull modulation signal will be very slow. When adopting the fast pull-up mode, the first PMOS transistor pulls up the push-pull modulation signal. When the gate-source voltage of the first PMOS transistor is less than its turn-on voltage, the first PMOS transistor conducts. At this time, the first PMOS transistor can quickly pull the potential of the signal before push-pull up to the power supply voltage, obtain the pull-up push-pull modulation signal, and avoid the pulse width distortion problem caused by the slow rising edge of the signal before push-pull; during the fast charge and slow discharge process, there is a problem that the falling edge of the signal before push-pull is not fast enough. Fast pull-down can quickly pull down the signal before push-pull to low level, avoid the adverse effect of pulse width distortion caused by the slow falling of the signal before push-pull, and ensure the accuracy of data transmission and the stability of signal processing; after fast push-pull, the terminal demodulation signal delay is reduced from 2 cycles to 0.5 cycles.

[0087] Please refer to Figure 3, which is the signal waveform diagram of a data synchronization circuit provided in this embodiment. This embodiment uses the fast pull-up method in fast push-pull to generate the signal waveform diagram. In the figure, data_in is the input data, clk is the clock signal, a is the modulation signal, b is the preliminary demodulation signal, c is the preliminary push-pull signal, d is the push-pull modulation signal, and data_out is the terminal demodulation signal; Figure 4 is the signal waveform diagram without the fast push-pull logic module. In the figure, data_in is the input data, clk is the clock signal, a is the modulation signal, b is the preliminary demodulation signal, c is the preliminary push-pull signal, d is the push-pull modulation signal, and data_out is the terminal demodulation signal; By comparing Figure 4 and Figure 3 , it is found that only the last edge signals of the push-pull modulation signal and the terminal demodulation signal are different; Figure 3 After adopting the fast pull-up method in fast push-pull, the maximum delay and pulse width distortion of the terminal demodulation signal data_out are both 1 / 2 clock cycle, achieving the purpose of effectively reducing the delay of the terminal demodulation signal and suppressing the pulse width distortion phenomenon.

[0088] Furthermore, this embodiment provides a data synchronization device. The data synchronization circuit device includes a housing, and the above-mentioned data synchronization circuit is arranged inside the housing; a data input interface, a data output interface, and a power supply interface are arranged on the housing; the data input interface is electrically connected to the signal input module, the data output interface is electrically connected to the demodulation module, and the power supply interface is electrically connected to the fast push-pull logic module.

[0089] The data synchronization device provided in this embodiment has a simple structure. In practical applications, it only needs to connect the signal input module through the data input interface, connect the demodulation module through the data output interface, and power on the fast push-pull logic module through the power supply interface, so as to be able to complete data synchronization stably and reliably. At the same time, it effectively reduces the delay of the terminal demodulation signal and suppresses the pulse width distortion phenomenon, realizes the precise synchronization of data, ensures the stability and reliability of the timing logic circuit, and reduces the occurrence of data errors and circuit malfunction problems.

[0090] This embodiment can be applied to the transmission scenario of the motor PWM drive signal within the isolation chip. Since the PWM signal is closely related to the dead time, and the dead time directly affects the energy loss and efficiency during the motor drive process; at the same time, the pulse width distortion plays a key role in the accuracy of motor control. Therefore, reducing the delay of the PWM signal during transmission and reducing the pulse width distortion phenomenon are crucial for optimizing the motor drive performance, improving the overall energy efficiency of the motor system, and achieving precise motor control. This embodiment provides a data synchronization circuit, effectively solving the problems of signal delay and pulse width distortion, reducing the energy loss while improving the motor control accuracy, providing a reliable guarantee for the efficient and stable operation of the motor, and having broad application prospects and significant practical value.

[0091] The above is the preferred embodiment of the present invention. It should be noted that for those of ordinary skill in the art of this technology, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements are also regarded as the protection scope of the present invention.

Claims

1. A data synchronization circuit, characterized in that: It includes a signal input module, a signal modulation module, a demodulation module and a fast push-pull logic module; wherein: The signal input module is used to obtain input data and clock signals; The signal modulation module is used to modulate the input data based on the clock signal to generate a modulation signal; The fast push-pull logic module is used to perform fast push-pull based on the input data and the clock signal to obtain a fast push-pull signal; The demodulation module includes a Schmitt trigger; The demodulation module is used to perform preliminary demodulation on the modulated signal to obtain a preliminary demodulated signal, and then push and pull the preliminary demodulated signal based on the fast push-pull signal to obtain a push-pull modulation signal. The Schmitt trigger is used to filter the push-pull modulation signal and output a terminal demodulated signal.

2. A data synchronization circuit according to claim 1, characterized in that: The signal modulation module includes a first inverter and a first NOR gate; wherein: The first inverter is used to convert the input data into logic state inversion data, and transmit the logic state inversion data to the first NOR gate; The first NOR gate is used to perform a NOR operation on the logic state inversion data based on the clock signal and generate a modulation signal.

3. A data synchronization circuit according to claim 2, characterized in that: The demodulation module includes a pulse narrowing module and a filtering module; wherein: The pulse narrowing module is used to perform preliminary demodulation and pulse narrowing on the modulated signal to obtain a preliminary demodulated signal, and transmit the preliminary demodulated signal to the filtering module; The Schmitt trigger is arranged in the filtering module; The filtering module is used to push and pull the preliminary demodulation signal based on the fast push-pull signal and output the demodulated signal through the Schmitt trigger terminal.

4. A data synchronization circuit according to claim 3, characterized in that: The narrowed pulse module includes a delayer and a second NOR gate; wherein: The delayer is used to delay the modulation signal, obtain a delayed modulation signal, and transmit the delayed modulation signal to the second NOR gate; The second NOR gate is used to perform a NOR operation on the modulation signal and the delayed modulation signal to generate a preliminary demodulation signal, and transmit the preliminary demodulation signal to the filtering module.

5. A data synchronization circuit according to claim 4, characterized in that: The filtering module includes a first NMOS tube, a second PMOS tube, a current limiting resistor, a voltage stabilizing capacitor and a second inverter; wherein: The gate of the second PMOS tube is connected to the output end of the second NOR gate, the drain of the second PMOS tube is connected to the drain of the first NMOS tube, and the source of the second PMOS tube is connected to the power supply; the gate of the first NMOS tube is connected to the output end of the second NOR gate, and the source of the first NMOS tube is grounded; the first NMOS tube and the second PMOS tube are used to asymmetrically charge and discharge the preliminary demodulated signal, obtain the pre-push-pull signal, and transmit the pre-push-pull signal to the fast push-pull logic module, so that the fast push-pull logic module pushes and pulls the pre-push-pull signal, obtains the push-pull modulation signal, and transmits the push-pull modulation signal to the Schmitt trigger; The first access end of the current limiting resistor is connected to the source of the second PMOS tube, the second access end of the current limiting resistor is connected to the drain of the first NMOS tube and the input end of the Schmitt trigger, and the current limiting resistor is used to limit the charging current of the voltage stabilizing capacitor; The first access terminal of the voltage-stabilizing capacitor is connected to the second access terminal of the current-limiting resistor and the input terminal of the Schmitt trigger, the second access terminal of the voltage-stabilizing capacitor is connected to the ground, and the voltage-stabilizing capacitor is used to stabilize the pre-push-pull signal; The second inverter is used to invert the logic state of the push-pull modulation signal filtered by the Schmitt trigger to output a terminal demodulation signal.

6. A data synchronization circuit according to claim 5, characterized in that: The asymmetric charging and discharging method includes two modes: slow charging and fast discharging and fast charging and slow discharging; wherein: The slow charge and fast discharge mode is specifically as follows: in the charging stage, the gate-source voltage of the first PMOS tube is greater than the turn-on voltage of the first PMOS tube, the first PMOS tube is in a relatively cut-off state, and the power current slowly charges the voltage-stabilizing capacitor through the current-limiting resistor, so that the voltage of the voltage-stabilizing capacitor slowly rises; in the discharging stage, the gate-source voltage of the first NMOS tube is greater than the turn-on voltage of the first NMOS tube, the first NMOS tube is quickly turned on, so that the charge stored on the voltage-stabilizing capacitor can be quickly released through the first NMOS tube, the voltage of the voltage-stabilizing capacitor drops rapidly, and the push-pull front signal of the slow charge and fast discharge is obtained; The fast charging and slow discharging method is specifically as follows: in the charging stage, the gate-source voltage of the first PMOS tube is less than the turn-on voltage of the first PMOS tube, the first PMOS tube is quickly turned on, the power supply current quickly flows to the voltage-stabilizing capacitor, and the voltage of the voltage-stabilizing capacitor rises rapidly; in the discharging stage, the gate-source voltage of the first NMOS tube is less than the turn-on voltage of the first NMOS tube, the first NMOS tube is in a relatively cut-off state, the voltage-stabilizing capacitor is discharged through the current-limiting resistor, the discharge current is small, and the voltage of the voltage-stabilizing capacitor slowly decreases, thereby obtaining the push-pull front signal of the fast charging and slow discharging.

7. A data synchronization circuit according to claim 6, characterized in that: The fast push-pull logic module includes an AND gate and a first PMOS tube; wherein: The AND gate is used to perform an AND operation on the clock signal and the input data to obtain a preliminary push-pull signal, and transmit the preliminary push-pull signal to the first PMOS tube; The drain of the first PMOS tube is connected to the input end of the Schmitt trigger, the gate of the first PMOS tube is connected to the output end of the AND gate, and the source of the first PMOS tube is connected to the power supply; the first PMOS tube is used to quickly push and pull the potential of the pre-push-pull signal, obtain a push-pull modulation signal, and transmit the push-pull modulation signal to the Schmitt trigger.

8. A data synchronization circuit according to claim 7, characterized in that: The fast push and pull has two modes: fast pull up and fast pull down; wherein: The fast pull-up method is specifically as follows: the first PMOS tube is used to pull up the potential of the pre-push-pull signal to the power supply voltage, obtain the pull-up push-pull modulation signal, and transmit the push-pull modulation signal to the Schmitt trigger; The fast pull-down method is specifically as follows: the first PMOS tube is used to pull down the potential of the pre-push-pull signal to the ground potential, obtain the pull-down push-pull modulation signal, and transmit the push-pull modulation signal to the Schmitt trigger.

9. A data synchronization device, characterized in that: It comprises a shell, in which a data synchronization circuit as described in any one of claims 1 to 8 is arranged; the shell is provided with a data input interface, a data output interface and a power interface; the data input interface is electrically connected to the signal input module, the data output interface is electrically connected to the demodulation module, and the power interface is electrically connected to the fast push-pull logic module.

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