Instruction set processing method and device, electronic equipment and storage medium

Abstract

The invention provides an instruction set processing method and device, electronic equipment and a storage medium, and the method comprises the steps: responding to the triggering of a setting signal, and starting guide logic; an external signal input through an external fetch interface is analyzed, fetch logic of the external signal is determined, and a corresponding running program is obtained according to the position pointed by the program counter based on the fetch logic; and calling the running program until the running program is executed completely. The embedded microprocessor provided by the embodiment of the invention is simple in structure and very suitable for scenes such as motor rotating speed measurement and control, and the expanded application of the embedded microprocessor core is realized.

Description

Technical Field

[0001] The present disclosure relates to instruction set processing technology, and in particular to an instruction set processing method and device, an electronic device and a storage medium. Background Art

[0002] At present, the motor can modulate the rotation of the rotating shaft into a preset excitation carrier signal in the form of a sine wave through a resolver voltage sensor, and induce a pair of sine / cosine signals in two orthogonal secondary coils. The sine / cosine signals are sampled by an analog-to-digital converter (ADC), and then the motor rotor angular position and speed can be calculated in digital form through analysis and processing such as demodulation and filtering. The corresponding control circuit can also be adjusted according to the calculated results to achieve the desired purpose. According to the processing method of the ADC sampling signal, it can be divided into hard decoding method and soft decoding method.

[0003] The hard decoding method requires the design of dedicated integrated circuits, which have a variety of analog and digital combinations, so it requires more development costs and lacks the flexibility of soft decoding. Soft decoding requires an embedded processor to complete the corresponding algorithm calculation, processing and control, and the embedded processor core often requires licensed IP from companies such as ARM, which requires additional costs. In addition, the simplest 32-bit embedded core logic scale is still quite complex for this algorithm implementation, and the computing power of low-cost microcontrollers is insufficient. Summary of the invention

[0004] The present disclosure provides an instruction set processing method and device, an electronic device and a storage medium to at least solve the above technical problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, there is provided an instruction set processing method, which is applied to a system on chip (SoC), wherein at least a first type of register and a second type of register are provided in the SoC, wherein the first type of register is used for operand calculation, and the second type of register is used for processing program calls; and an instruction set is set according to an application scenario, wherein an instruction setting bit in the instruction set is used as an instruction identifier; the SoC is provided with an external instruction fetch interface to respond to external instruction fetching; the method comprises:

[0006] In response to the setting signal triggering, starting the guidance logic;

[0007] Analyze the external signal input through the external instruction fetch interface, determine the instruction fetch logic of the external signal, and obtain the corresponding running program at the position pointed to by the program counter based on the instruction fetch logic;

[0008] The running program is called until the running program is executed.

[0009] In some executable embodiments, calling the running program until the running program is executed to completion includes:

[0010] When it is determined based on a conditional jump instruction that the operand is a first identification value, the program counter is incremented by a first value, the conditional jump instruction is executed, and a corresponding program block is called; when it is determined based on a conditional jump instruction that the operand is a second identification value, the program counter is incremented by a second value, the conditional transfer instruction is executed, and a corresponding subroutine block is called;

[0011] In response to the execution of the program block or subroutine block being completed, the call of the program block is returned via a jump condition instruction until a stop instruction is executed and the system enters the standby state.

[0012] In some executable embodiments, the method further includes:

[0013] The instruction code bit width in the instruction set is 8 bits, the data bit width is 32 bits, and the bit widths of the instruction fetch instruction and the data access instruction are 32 bits.

[0014] In some executable embodiments, the first type of register is used to store operands in binary operations and unary operations;

[0015] The second type of register is used to support the loading of the running program, address storage, and to support subroutine jumps and the counting of the program counter.

[0016] In some executable embodiments, the instruction settings in the instruction set serve as instruction identifiers, including:

[0017] The instructions in the instruction set are classified according to the value of the lowest set bit in the instruction encoding, as follows:

[0018] The first type of instructions includes control instructions, conditional jump instructions, and custom instructions;

[0019] The second type of instructions includes load instructions and store instructions;

[0020] The third type of instructions includes logical instructions;

[0021] The fourth type of instructions are arithmetic operation instructions.

[0022] In some executable embodiments, the second type of instructions and the conditional jump instructions are followed by an immediate number to reduce the number of instructions for controlling, conditioning, and fetching operands in more complex program blocks.

[0023] According to a second aspect of the present disclosure, there is provided an instruction set processing device applied to a system-on-chip (SoC). In the SoC, at least a first type of register and a second type of register are provided. The first type of register is used for operand operations, and the second type of register is used for processing program calls. Further, an instruction set is set according to the application scenario, wherein the instruction bits in the instruction set are used as instruction identifiers. The SoC is provided with an external instruction fetch interface to respond to external instruction fetch requests. The device includes:

[0024] A startup unit, configured to trigger and start a boot logic in response to a set signal;

[0025] An analysis unit, configured to analyze an external signal input through the external instruction fetch interface to determine the instruction fetch logic of the external signal;

[0026] An acquisition unit, configured to obtain a corresponding running program based on the instruction fetch logic at the position pointed to by the program counter;

[0027] A call unit, configured to call the running program until the running program is executed completely.

[0028] In some executable embodiments, the call unit is further configured to:

[0029] When it is determined based on a conditional jump instruction that the operand is a first identifier value, the program counter is incremented by a first value, the conditional jump instruction is executed, and a corresponding program block is called; when it is determined based on a conditional jump instruction that the operand is a second identifier value, the program counter is incremented by a second value, the conditional transfer instruction is executed, and a corresponding subprogram block is called;

[0030] In response to the execution end of the program block or the subprogram block, the call of the program block is returned through a jump condition instruction until a stop instruction is executed and the device enters a standby state.

[0031] In some executable embodiments, the instruction code bit width in the instruction set is 8 bits, the data bit width is 32 bits, and the bit widths of the instruction fetch instruction and the data access instruction are 32 bits.

[0032] In some executable embodiments, the first type of register is used to store operands in binary operations and unary operations;

[0033] The second type of register is used to support the loading of the running program, address storage, and support subprogram jumps and program counter counting.

[0034] In some executable embodiments, the instruction bits in the instruction set are used as instruction identifiers, including:

[0035] The instructions in the instruction set are classified according to the value of the lowest set bit in the instruction encoding, as follows:

[0036] The first type of instructions includes control instructions, conditional jump instructions, and custom instructions;

[0037] The second type of instructions includes load instructions and store instructions;

[0038] The third type of instructions includes logical instructions;

[0039] The fourth type of instructions is arithmetic operation instructions.

[0040] In some executable embodiments, the second type of instructions and the conditional jump instructions follow an immediate number to reduce the number of instructions for controlling, conditioning, and fetching operands in a more complex program block.

[0041] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0042] At least one processor; and

[0043] A memory communicatively connected to the at least one processor; wherein,

[0044] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the steps of the instruction set processing method described in the present disclosure.

[0045] According to a fourth aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions, and the computer instructions are used to cause a computer to execute the steps of the instruction set processing method described in the present disclosure.

[0046] The instruction set processing method, apparatus, electronic device, and storage medium of the present disclosure achieve instruction control for a resolver voltage sensor by configuring a first type of register and a second type of register for the SoC, and by setting the instruction code bit width, data bit width, and fetch / data access bit width. The structure of the embedded microprocessor in the embodiments of the present disclosure is simple and very suitable for implementing motor speed measurement and control. By reasonably setting the control instruction bit width and data bit width, a reasonable parsing of the instruction program is achieved, and the control instructions therein are quickly executed to achieve control of a control object such as a motor. Moreover, the technical solution of the present disclosure is also applicable to application domains such as audio signal processing with a relatively low sampling rate, such as the algorithm implementation of a class D audio amplifier. The processing solution of the embedded instructions in the embodiments of the present disclosure is portable and can be logically adjusted according to the actual application scenario to meet different application scenarios.

[0047] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] By referring to the following detailed description with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the drawings, several embodiments of the present disclosure are shown in an exemplary but not restrictive manner, wherein:

[0049] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0050] Figure 1 The flowchart of the instruction set processing method according to an embodiment of the present disclosure is shown Figure 1 ;

[0051] Figure 2 The schematic diagram of the implementation structure of the embedded microprocessor core according to an embodiment of the present disclosure is shown;

[0052] Figure 3 The flowchart of the instruction set processing method according to an embodiment of the present disclosure is shown Figure 2 ;

[0053] Figure 4 The schematic diagram of the structure of instruction execution in the instruction set according to an embodiment of the present disclosure is shown;

[0054] Figure 5 The schematic diagram of the motor control structure based on a resolver according to an embodiment of the present disclosure is shown;

[0055] Figure 6 The schematic diagram of the composition structure of the instruction set processing device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0056] In order to make the objects, features, and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the scope of protection of the present disclosure.

[0057] Figure 1 The flowchart of the instruction set processing method according to an embodiment of the present disclosure is shown Figure 1 , such as Figure 1As shown, the instruction set processing method of the embodiment of the present disclosure is applied to a system on chip SoC; at least a first type of register and a second type of register are provided in the SoC, the first type of register is used for operand calculation, and the second type of register is used for processing program calls; and the instruction set is set according to the application scenario, wherein the instruction setting bit in the instruction set serves as an instruction identifier; the SoC is provided with an external instruction fetch interface to respond to external instruction calls.

[0058] Figure 2 The schematic diagram of the implementation structure of the embedded microprocessor core of the embodiment of the present disclosure is shown as follows: Figure 2 As shown, the disclosed embodiment is a structure of an embedded microprocessor core based on SoC, which includes four 32-bit general registers R0-R3, all binary operations use R0 and R1 as operands, and all unary operations use R0 as an operand; four special registers R4-R7, among which there are a 14-bit Load address register R4, a 14-bit Store address register R5, a 14-bit subroutine jump address register R6, and a 13-bit program counter R7 (PC). R0-R7 can be used as operands or destination registers of corresponding instructions respectively.

[0059] like Figure 2 As shown, the disclosed embodiment may adopt the design of an optional external instruction fetch interface, or the internal instruction fetch module may call the corresponding program in response to a startup control signal. When the external instruction fetch interface is adopted, the program / data space needs to be uniformly addressed. When the external instruction fetch interface is not used, the two storage spaces can be considered to be independent of each other. Specifically, the external storage space access is responsible for accessing on-chip resources, which can be merged into the external instruction fetch interface to complete the mapping logic with the on-chip SoC space, and the eMCore program ROM / RAM and registers in the SoC can also be accessed through the external instruction fetch interface.

[0060] In the disclosed embodiment, external storage space access is mapped to the on-chip SoC space, and a seamless connection from the external storage space to the on-chip SoC space is achieved through a dedicated mapping register and address conversion circuit. Specifically, when the processor needs to access a specific resource on the chip (such as a peripheral register), the external storage space access module converts the access request into the corresponding on-chip address according to a preset mapping rule. This mapping rule may be based on the calculation of an address offset or index value to ensure that each external storage address can be accurately mapped to the corresponding resource address on the chip. In this process, an address legitimacy check is also performed to prevent illegal access to on-chip resources and protect the security of the system.

[0061] In the design of this embedded microprocessor core, a variety of low-power design strategies are incorporated. First of all, at the hardware circuit level, low-power transistor processes and circuit design technologies are adopted. For example, transistors with low threshold voltages are selected, which reduces the static power consumption of the circuit while ensuring the circuit performance. At the same time, the clock network is optimized, and clock gating technology is used to dynamically turn off or turn on the clock signal according to the working state of the circuit module, reducing the dynamic power consumption caused by unnecessary clock flips. For example, when a certain functional module is in an idle state for a period of time, the clock input of the module is turned off through the clock gating circuit, making it enter the low-power standby mode until a new task requires the module to process and then the clock is turned on again.

[0062] At the instruction set design and software levels, low-power factors are also considered. By reasonably arranging the execution order and frequency of instructions, the workload and running time of the processor are reduced, thereby reducing power consumption. For example, for some non-critical tasks that can be delayed, they are arranged to be executed during periods when the processor load is low, avoiding running multiple high-power-consuming instructions simultaneously when the processor is under high load. In addition, the processor can enter the low-power sleep mode during idle time and resume work in a timely manner through the interrupt wake-up mechanism, further saving energy. In terms of algorithm implementation, some low-power algorithm optimization technologies are adopted, such as data compression and approximate computing, etc., to reduce the amount of computation and data storage within the accuracy range that meets the application requirements, thereby reducing the power consumption requirements of the processor.

[0063] Based on Figure 2 the structure of the embedded microprocessor core shown, the instruction set processing method of the embodiments of the present disclosure includes the following processing steps:

[0064] Step 101, in response to the trigger of the set signal, start the boot logic.

[0065] The instruction fetch trigger of the embodiments of the present disclosure can be triggered by an external instruction fetch interface or actively triggered by an instruction fetch module within the Soc system. That is, the set signal is triggered by an external signal (the signal is valid or set by the main controller), or can be triggered by the instruction fetch module within the Soc. The instruction fetch logic fetches and runs the program at the position pointed to by the program counter (PC) and calls the program.

[0066] Step 102, parse the external signal input through the external instruction fetch interface, determine the instruction fetch logic of the external signal, and obtain the corresponding running program based on the position pointed to by the program counter according to the instruction fetch logic.

[0067] To further improve the program code density and reduce the logic cost, the instruction code bit width in the instruction set of the embodiments of the present disclosure is 8 bits, the data bit width is 32 bits, and the bit widths of the instruction fetch instruction and the data access instruction are 32 bits. This bit width is only an example and is not used for limitation, and it can also be other bit widths. The total limit of the program and data storage space is 64k bytes (16 bits). The storage space can be allocated as needed. As an example, the storage space of the program is 8k, and the rest is the data space.

[0068] In the embodiments of the present disclosure, the instruction execution pipeline is divided into stages such as instruction fetch, decoding, execution, and write-back. In the instruction fetch stage, the processor fetches an instruction from the program memory (which can be a storage device connected to an external instruction fetch interface or an internal program ROM) according to the value of the program counter (PC) and passes it to the decoding stage. The decoding stage decodes the instruction to determine the opcode and operands of the instruction, and at the same time generates corresponding control signals. The execution stage performs arithmetic operations on the operands or executes other operations, such as data loading and storage, using the ALU or other functional units according to the decoding result. The write-back stage writes the execution result back to the target register or storage unit. Through this pipeline design, multiple instructions can be processed simultaneously in different stages, achieving parallel execution of instructions and improving the throughput of the processor. In the pipeline design, the handling of data dependencies and control dependencies is also considered. Techniques such as data bypassing technology and branch prediction technology are adopted to improve the execution efficiency of the processor.

[0069] Step 103, call the running program until the running program is executed completely.

[0070] During the instruction execution process, there is a close interaction between the general-purpose registers R0-R3 and the special registers R4-R7. Taking a program segment containing arithmetic operations and data storage as an example, when executing an addition instruction, the operands may come from R0 and R1, and the operation result will be stored back to R0. During this process, the instruction decoding unit will identify the operand register and the target register according to the instruction code, and the control unit coordinates the arithmetic logic unit (ALU) to perform the addition operation.

[0071] When an external instruction fetch interface is adopted, the unified addressing of the program / data space brings unique operation logics. After receiving an external instruction fetch request, the external instruction fetch interface will resolve the instruction address according to specific address mapping rules. For example, for a given instruction address 0x2000, the interface first determines whether it is in the program space or the data space. If it is in the program space, it will read the instruction from the corresponding storage area (such as program ROM) and pass it to the instruction fetch logic unit of the processor. In this process, the instruction fetch logic unit will decode according to the format and operation code of the instruction to determine the type of the instruction and the required operands. If the instruction involves data access and the access address is in the data space, due to the unified addressing at this time, the processor can directly use the same address bus and data bus to access the storage unit in the data space to obtain or store data. This unified addressing method reduces the complexity of address conversion and improves the efficiency of data transmission and instruction execution.

[0072] When the external instruction fetch interface is not used, the program and data spaces can be considered independent of each other. At this time, there is an independent program counter PC inside the processor to track the execution position of the program, and the reading and storage of data are carried out through dedicated data access paths. For example, when executing a LOAD instruction, if data is read from the data space, the processor will read the data from the data RAM or other data storage units according to the data address specified in the instruction through the data access path and store it in the specified register. This independent space design can improve the security and stability of the system in some cases, avoid accidental modification of data by program errors, and is also convenient for separately managing and optimizing the program and data.

[0073] Figure 3 The implementation process of the instruction set processing method according to the embodiments of the present disclosure is shown Figure 2 , as Figure 3 shown, the instruction set processing method according to the embodiments of the present disclosure includes the following processing steps;

[0074] Step 301, in response to the trigger of the set signal, start the boot logic.

[0075] The instruction fetch trigger according to the embodiments of the present disclosure can be triggered by an external instruction fetch interface or actively triggered by an instruction fetch module inside the Soc system. That is, the set signal is triggered by an external signal (the signal is valid or set by the main controller), or can be triggered by the instruction fetch module inside the Soc. The instruction fetch logic fetches and runs the program at the position pointed to by the program counter (PC) and calls the program.

[0076] Step 302, parse the external signal input through the external instruction fetch interface, determine the instruction fetch logic of the external signal, and obtain the corresponding running program based on the instruction fetch logic at the position pointed to by the program counter.

[0077] In the embodiments of the present disclosure, an embedded microprocessor core with an instruction code length of only 8 bits has the following architectural features: the instruction code width is 8 bits, the data width is 32 bits, and the instruction fetch / data access bit width is 32 bits; the total limit of the program and data storage spaces is 64k bytes (16 bits).

[0078] In the embodiments of the present disclosure, the first type of register is used to store operands in binary operations and unary operations; the second type of register is used to support the loading of the running program, address storage, and support for subroutine jumps and program counter counting. The instruction encodings in the instruction set are classified according to the value of the lowest set bit as follows: the first type of instructions includes control instructions, conditional jump instructions, and custom instructions; the second type of instructions includes load instructions and store instructions; the third type of instructions includes logical instructions; the fourth type of instructions includes arithmetic operation instructions.

[0079] Specifically, the instruction set encoding is based on the lowest two bits B0 - B1 and specifically includes:

[0080] Instructions of class 00 are control instructions, which include MOVE, GOTO, SKIPNm (conditional jump), control / status register operation instructions, Halt, custom instructions such as CORDIC operation, and other necessary control instructions. For the MOVE instruction, its operation process is to move the data in the source operand register to the target operand register. The source operand and the target operand can be general registers R0 - R3 or specific fields in special registers. The specific move operation is decoded and executed by the control unit of the processor according to the instruction code. The GOTO instruction directly sets the program counter PC to the specified jump address, thus realizing an unconditional jump of the program flow. When the SKIPNm conditional jump instruction is executed, it will judge the operand R0[0]. If the condition is met (such as being '1'), it will jump to the corresponding program block for execution according to a preset offset (such as PC + 2); if the condition is not met (being '0'), it will execute the subsequent instructions according to another offset (such as PC + 1). This conditional jump mechanism provides the basis for the branch structure of the program. Custom instructions such as CORDIC operation will call a dedicated hardware module or software algorithm to implement coordinate rotation digital calculation when executed. Its input data comes from specified registers, and the calculation result is then stored back to the corresponding registers. The whole process involves multiple steps such as data reading, operation, and storage, and needs to strictly follow the operation specifications and timing requirements of the instructions.

[0081] 10 types of instructions, including LOAD / STORE instructions. Both use special registers R4 / R5 as the base addresses respectively and access the storage space in units of words (WORD), and define instruction types that can follow an immediate value with an offset of one byte. For example, LOAD_ofst can directly access the address (R4 + offset). When LOAD / STORE is executed, it uses special registers R4 / R5 as the base addresses and calculates the final storage address according to the offset value carried in the instruction (which can be an immediate value or a value in a register). For example, when executing the LOAD instruction, the processor reads data from the calculated address and stores it in the specified register; while the STORE instruction stores the data in the register into the storage unit corresponding to the calculated address. Taking the LOAD_ofst instruction as an example, assuming the value stored in R4 is the base address 0x1000 and the offset value in the instruction is 0x10, then the actual access address is 0x1010, and the processor reads data from this address and stores it in the target register. This addressing method based on special registers and offset values facilitates the efficient storage and reading of data and also increases the flexibility of the instructions.

[0082] 01 type of logical instructions, whose operations are relatively intuitive. The greater-than comparison instruction compares two operands (usually values in registers). If the first operand is greater than the second operand, it sets the corresponding flag bit (such as in the status register), and subsequent instructions can determine the program flow based on this flag bit. The equal comparison instruction is similar, setting the flag bit when the two operands are equal. As logical instructions, they can include logical operation instructions such as OR / AND / NOT / XOR, which perform corresponding logical operations on the binary bits of the operands. For example, the OR instruction performs an OR operation on the corresponding bits of the two operands and stores the result in the target register. The left / right shift instructions shift the binary bits of the operand by the specified number of bits. During the shift process, it may involve filling the vacated bits (such as filling with 0 or the sign bit). These logical instructions provide important support for data processing and program logical judgment.

[0083] 11 types of arithmetic operation instructions, including: addition, subtraction, multiplication, division, modulo, etc. Addition and subtraction operations directly perform corresponding operation operations in the ALU. The operands come from the specified registers, and the operation results are stored back in the target registers. Operations such as multiplication, division, and modulo are implemented iteratively by reusing the adder for addition and subtraction operations. For example, the multiplication operation can be completed through multiple addition and shift operations. Taking the multiplication operation as an example, assuming that the product of R0 and R1 needs to be calculated, the processor will use R0 as the initial value of the accumulator, and then, according to the binary bits of R1, judge bit by bit whether R0 needs to be added to itself and perform shift operations. After multiple iterations, the final product result is obtained and stored in the specified register. This way of reusing the adder saves hardware resources to a certain extent and also utilizes the existing computing power of the processor to implement complex arithmetic operations.

[0084] Instructions such as GOTO / LOAD / STORE can follow an immediate value of one byte to reduce the number of instructions for controlling, conditioning, and fetching operands in more complex program blocks. The instruction code is 2 bytes. When the operands and conditional branches of the algorithm are restricted, this definition increases the flexibility of the program logic and reduces the length of the program.

[0085] Step 303, when it is judged based on the conditional jump instruction that the operand is the first identification value, the program counter is incremented by the first value, the conditional jump instruction is executed, and the corresponding program block is called; when it is judged based on the conditional jump instruction that the operand is the second identification value, the program counter is incremented by the second value, the conditional transfer instruction is executed, and the corresponding subroutine block is called.

[0086] Figure 4 The structural diagram of the instruction execution in the instruction set according to the embodiments of the present disclosure is shown, as Figure 4 shown, the set signal is triggered by an external signal (the signal is valid or set by the main controller). After being triggered, the instruction fetch logic fetches instructions and runs the program at the position pointed to by the program counter (PC). The SKIPN1 conditional jump instruction judges whether the operand R0[0] is '1'. If it is 1, PC+2, and the program block 'rP0' is executed; if it is '0', PC+1, and GOTO'sP0' is executed, jumping to the subroutine block'sP0'. After execution to the end, it returns to the program block 'rp0' through GOTO 'rP0'... and keeps executing until the Halt instruction is reached, then the startup controller is cleared and enters the standby state.

[0087] During the program execution, to ensure the stability and reliability of the system, a perfect error handling and exception response mechanism is set up. First, before the instruction execution, the legality of the input instruction is verified. For example, it checks whether the instruction encoding conforms to the predefined instruction set format, whether the operands are within the legal range, etc. If an illegal instruction is found, the processor will trigger an error interrupt and process it according to the predefined error handling program. The error handling program may record the error information into a specific register or storage area, and at the same time send an error report signal to an external device (such as the main controller) for further analysis and processing.

[0088] For the possible exceptions of conditional jump instructions, such as incorrect jump address or out-of-program-space range, the processor also has corresponding handling measures. When such an exception is detected, the processor will suspend the execution of the current program, set the program counter PC to a predefined error handling program entry address, and enter the error handling process. In the error handling process, it will attempt to repair the error, such as correcting the incorrect jump address by looking up the jump table or using the backup program address information. If the error cannot be repaired, some emergency measures may be taken, such as resetting some system modules or entering the safe mode to avoid more serious system failures.

[0089] During the data processing, if data overflow or underflow occurs, for example, when the result of an arithmetic operation exceeds the range that can be represented by the register, the processor will set the corresponding overflow flag bit and decide whether to perform overflow handling according to the program settings. Some programs may choose to ignore the overflow and continue to execute the subsequent instructions, but record the overflow event; while some programs may require to stop the execution immediately and perform error handling, such as adjusting the operation parameters or recalculating. This flexible overflow handling mechanism can meet the requirements of different application scenarios and ensure the accuracy and reliability of data processing.

[0090] Step 304, in response to the end of the execution of a program block or a subprogram block, return to the call of the program block through a jump conditional instruction until the execution stop instruction is executed and enter the standby state.

[0091] After the execution reaches the end, return to the program block 'rp0' through GOTO 'rP0'... and keep executing until the Halt instruction is executed to clear the start controller and enter the standby state.

[0092] Figure 5 The schematic diagram of the motor control structure based on a resolver sensor according to an embodiment of the present disclosure is shown, as Figure 5 shown, taking the measurement of the motor position and speed based on a resolver sensor as an example, to further clarify the essence of the technical solution of the embodiment of the present disclosure.

[0093] In the embodiments of the present disclosure, a resolver is installed on the rotating shaft of an external motor. The resolver outputs orthogonal sine / cosine analog signals modulated by an excitation signal. The SoC chip includes an analog-to-digital converter that converts the above sine / cosine analog signals into corresponding digital signals. An algorithm program (as an example, the program length can be limited to 2K bytes) for implementing the technical solution of the embodiments of the present disclosure is installed in the program RAM (or ROM) of the eMCore. By default, the sampling / control module executes it once at each specified sampling position. When the conditions are normal, the position and rotation speed information of the corresponding resolver are given. When an abnormal condition occurs, an error status code is reported and the interrupt status is set. The interrupt status can be implemented using on-chip resources or locally customized. When executing the abnormal status code, the time may exceed the normal sampling interval. Intermediate variables, program parameters, calculation results, and status codes can be stored in the data RAM, and the size of the data RAM is 512 bytes. The typical envelope signal frequency is 2Khz - 20Khz. When the eMCore operating frequency is 120Mhz, there is at least (120Mhz / (20Khz*2)) = 3000 clock cycles of program execution time for each half cycle of the envelope.

[0094] The embedded microprocessor core of the embodiments of the present disclosure has a simple and efficient structure and is very suitable for implementing motor speed measurement and control. Moreover, it is also applicable to other signal processing applications with relatively low audio sampling rates, such as the algorithm implementation of class D audio amplifiers. The algorithm is implemented in software, maintaining flexibility in the application. The embedded implementation is portable, facilitating logical adjustment according to the usage scenario to meet different scenario requirements.

[0095] Figure 6 The composition structure diagram of the instruction set processing device of the embodiments of the present disclosure is shown, as Figure 6 shown, the instruction set processing device of the embodiments of the present disclosure is applied to a system-on-chip (SoC). At least a first type of register and a second type of register are provided in the SoC. The first type of register is used for operand operations, and the second type of register is used for processing program calls. In addition, an instruction set is set according to the application scenario, where the set bit of the instruction in the instruction set serves as an instruction identifier. The SoC is provided with an external instruction fetch interface to respond to external instruction fetches. The device includes:

[0096] A start unit 60, configured to trigger and start the boot logic in response to a set signal

[0097] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0098] In addition, the terms "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of this disclosure, "a plurality" means two or more, unless otherwise specifically defined.

[0099] As described above, the above are only specific embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed in this disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be subject to the protection scope of the claims.

Claims

1. An instruction set processing method, applied to a system on chip (SoC), characterized in that: The SoC is provided with at least a first type register and a second type register, wherein the first type register is used for operand calculation and the second type register is used for processing program calls; and an instruction set is set according to an application scenario, wherein an instruction setting bit in the instruction set is used as an instruction identifier; the SoC is provided with an external instruction fetch interface to respond to external instruction fetching; the method comprises: In response to the setting signal triggering, starting the guidance logic; Analyze the external signal input through the external instruction fetch interface, determine the instruction fetch logic of the external signal, and obtain the corresponding running program at the position pointed to by the program counter based on the instruction fetch logic; The running program is called until the running program is executed.

2. The method according to claim 1, characterized in that The calling of the running program until the running program is executed completely includes: When the conditional jump instruction determines that the operand is a first identification value, the program counter is incremented by the first value, the conditional jump instruction is executed, and the corresponding program block is called; when the conditional jump instruction determines that the operand is a second identification value, the program counter is incremented by the second value, the conditional transfer instruction is executed, and the corresponding subroutine block is called; In response to the completion of execution of a program block or a sub-program block, the program block is returned to by a jump conditional instruction until a stop instruction is executed to enter a standby state.

3. The method according to claim 1, characterized in that The method further comprises: The instruction code bit width in the instruction set is 8 bits, the data bit width is 32 bits, and the bit width of the instruction fetch instruction and the data access instruction is 32 bits.

4. The method according to claim 1, characterized in that: The first type of register is used to store operands in binary operations and unary operations; The second type register is used to support the loading and address storage of the running program, as well as the subroutine jump and the counting of the program counter.

5. The method according to claim 1, characterized in that The instruction setting bits in the instruction set serve as instruction identifiers, including: The instruction encodings in the instruction set are classified by the value of the lowest set bit, as follows: The first category of instructions includes control instructions, conditional jump instructions and custom instructions; The second category of instructions includes load instructions and store instructions; The third category of instructions includes logic instructions; The fourth category of instructions is arithmetic operation instructions.

6. The method according to claim 5, characterized in that The second type of instruction and the conditional jump instruction are followed by an immediate value to reduce the number of control, conditional and operand fetching instructions of more complex program blocks.

7. An instruction set processing device, applied to a system on chip (SoC), characterized in that: The SoC is provided with at least a first type register and a second type register, wherein the first type register is used for operand calculation and the second type register is used for processing program calls; and an instruction set is set according to an application scenario, wherein an instruction setting bit in the instruction set is used as an instruction identifier; the SoC is provided with an external instruction fetch interface to respond to external instruction fetching; the device comprises: A start unit, configured to start the boot logic in response to a trigger of a set signal; A parsing unit, used for parsing an external signal input through an external instruction fetch interface, and determining an instruction fetch logic of the external signal; An acquisition unit, used for acquiring a corresponding running program at a position pointed to by a program counter based on an instruction fetch logic; The calling unit is used to call the running program until the running program is executed.

8. The device according to claim 7, characterized in that The calling unit is further used for: When the conditional jump instruction determines that the operand is a first identification value, the program counter is incremented by the first value, the conditional jump instruction is executed, and the corresponding program block is called; when the conditional jump instruction determines that the operand is a second identification value, the program counter is incremented by the second value, the conditional transfer instruction is executed, and the corresponding subroutine block is called; In response to the completion of execution of a program block or a sub-program block, the program block is returned to by a jump conditional instruction until a stop instruction is executed to enter a standby state.

9. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the steps of the instruction set processing method according to any one of claims 1 to 6.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable the computer to execute the steps of the instruction set processing method according to any one of claims 1 to 6.

Images