Multi-core-based interrupt task parallel execution method and device, equipment and medium

Abstract

The invention provides a parallel execution method and device of interrupt tasks based on multiple cores, equipment and a medium, and relates to the technical field of computer processing, task information is obtained by analyzing an external program file, and then a task linked list is generated; and periodically monitoring the state of registering the interrupt task by the system, when the task is ready, acquiring the to-be-executed core and the interrupt task number, triggering the interrupt task, responding to the interrupt task by the to-be-executed core, and processing the interrupt task execution function according to the task linked list. By defining the abstract interrupt and the interrupt execution function corresponding to the interrupt, various tasks in the external program file are represented in a concrete mode, and accurate deployment of the interrupt tasks is achieved. According to the invention, cross-core task processing is realized, parallel deployment of the interrupt tasks on a plurality of to-be-executed cores is realized, the parallel processing capability of multiple cores is fully mined and utilized, and the efficiency of simultaneously processing a plurality of interrupt tasks is improved. According to the invention, the interrupt task with the highest priority is ensured to obtain instant response through an interrupt priority mechanism.

Description

Technical Field

[0001] The present invention relates to the field of computer processing technologies, and in particular, to a method, apparatus, device, and medium for parallel execution of interrupt tasks based on multiple cores. Background Art

[0002] With the rapid development of information technology and the continuous expansion of application fields, high-computing-power-demand products have become the key to the pursuit of efficient, intelligent, and reliable solutions in all walks of life. Especially in the field of power system relay protection, in the face of a complex and changing power system environment and the increasing demand for relay protection, in order to meet this demand, exploring and utilizing advanced computing technologies has become an inevitable trend in the industry's development.

[0003] Traditional interrupt handling mechanisms are often limited to a single-core environment. In the face of a large number of interrupt tasks, the efficiency of this single-core interrupt handling mechanism is low. Summary of the Invention

[0004] The present invention provides a method, apparatus, device, and medium for parallel execution of interrupt tasks based on multiple cores, to solve the defect of low efficiency of the single-core interrupt handling mechanism in the prior art, and to improve the efficiency of processing a large number of interrupt tasks.

[0005] The present invention provides a method for parallel execution of interrupt tasks based on multiple cores, including: parsing an external program file to obtain task information, generating a task linked list based on the task information, the task linked list including the mapping relationship among an interrupt task number, a core to be executed, and an interrupt execution function, and the interrupt execution function being used to execute a task at the software layer; periodically monitoring the status of interrupt tasks, and when the interrupt task reaches a trigger condition, obtaining at least one triggered interrupt task and the core to be executed for each triggered interrupt task; and sequentially calling the cores to be executed for the triggered interrupt tasks to process the triggered interrupt tasks based on the task linked list.

[0006] According to the method for parallel execution of interrupt tasks based on multiple cores provided by the present invention, sequentially calling the execution cores of the to-be-triggered interrupt tasks to process the triggered interrupt tasks based on the task linked list includes: in the triggered interrupt tasks, sequentially selecting the triggered interrupt task with the highest priority as the target interrupt task, and obtaining the execution core of the target interrupt task; matching the corresponding target interrupt execution function from the task linked list based on the target interrupt task; modifying the status of the target interrupt task to obtain the target interrupt task with the status modified; and calling the execution core to respond to the target interrupt task with the status modified, and activating the target interrupt execution function to process the target interrupt task.

[0007] According to the parallel execution method of interrupt tasks based on multiple cores provided by the present invention, modifying the state of the target interrupt task to obtain the target interrupt task with the modified state includes: when the state of the target interrupt task is the waiting state, modifying the state of the target interrupt task to the active state, and the active state is used to activate the target interrupt execution function to process the target interrupt task; when the state of the target interrupt task is the waiting state and the target interrupt task is a task generated after execution, modifying the state of the target interrupt task to the active and waiting state, and the active and waiting state is used to activate the target interrupt execution function and wait for the next execution cycle of the target interrupt task; when the state of the target interrupt task is the active state, modifying the state of the target interrupt task to the active and waiting state.

[0008] According to the parallel execution method of interrupt tasks based on multiple cores provided by the present invention, after obtaining the execution core of the target interrupt task, it further includes: if the execution core is processing other interrupt tasks and the priority of the other interrupt tasks is lower than the priority of the target interrupt task, controlling the execution core to perform interrupt nesting processing, so as to first call the execution core to process the target interrupt task, and then call the execution core to process the other interrupt tasks; if the execution core is processing other interrupt tasks and the priority of the other interrupt tasks is higher than the priority of the target interrupt task, waiting for the other interrupt tasks to finish execution, and then calling the execution core to process the target interrupt task.

[0009] According to the parallel execution method of interrupt tasks based on multiple cores provided by the present invention, before parsing the external program file to obtain task information, it further includes: allocating independent stack spaces for each execution core to be called, so as to process the triggered interrupt tasks based on the task list by sequentially calling the independent stack spaces of the execution cores to be called that trigger the interrupt tasks.

[0010] According to the parallel execution method of interrupt tasks based on multiple cores provided by the present invention, before parsing the external program file to obtain task information, it further includes: after starting the main core, based on the start commands sent by the main core to each slave core, sequentially starting the slave cores. After the multiple cores are synchronized, the main core executes the main function, and the slave cores enter the waiting state to obtain at least one execution core to be called.

[0011] According to the parallel execution method of interrupt tasks based on multiple cores provided by the present invention, parsing the external program file to obtain task information includes: parsing the external program file to extract the interrupt task number, the task type of the interrupt task, the execution cycle of the interrupt task, the priority of the interrupt task, the execution core to be called of the interrupt task, and the interrupt execution function of the interrupt task; based on the interrupt task number, task type, execution cycle, priority, execution core to be called, and interrupt execution function, obtaining the task information.

[0012] The present invention also provides a parallel execution device for interrupt tasks based on multiple cores, including: a configuration module, configured to parse an external program file to obtain task information, generate a task linked list based on the task information, the task linked list including the mapping relationship among an interrupt task number, a core to be executed, and an interrupt execution function, and the interrupt execution function being used to execute a task at the software layer; a monitoring module, configured to periodically monitor the status of an interrupt task, and when the interrupt task reaches a triggering condition, obtain at least one triggered interrupt task and the core to be executed for each triggered interrupt task; and a processing module, configured to sequentially call the cores to be executed of the triggered interrupt tasks to process the triggered interrupt tasks based on the task linked list.

[0013] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, where when the processor executes the computer program, the parallel execution method for interrupt tasks based on multiple cores as described in any one of the above is implemented.

[0014] The present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the parallel execution method for interrupt tasks based on multiple cores as described in any one of the above is implemented.

[0015] The parallel execution method, device, equipment, and medium for interrupt tasks based on multiple cores provided by the present invention obtain task information by parsing an external program file, generate a task linked list based on the task information, the task linked list including the mapping relationship among an interrupt task number, a core to be executed, and an interrupt execution function, and the interrupt execution function being used to execute a task at the software layer; periodically monitor the status of an interrupt task, and when the interrupt task reaches a triggering condition, obtain at least one triggered interrupt task and the core to be executed for each triggered interrupt task; and sequentially call the cores to be executed of the triggered interrupt tasks to process the triggered interrupt tasks based on the task linked list. The present invention realizes the precise deployment of interrupt tasks by defining an abstract interrupt and its corresponding interrupt execution function to concretely represent each task in the external program file. The present invention realizes cross-core processing of interrupt tasks, realizes parallel deployment of interrupt tasks on multiple cores to be executed, fully exploits and utilizes the parallel processing ability of multiple cores, and improves the efficiency of simultaneously processing multiple interrupt tasks. The present invention ensures that the interrupt task with the highest priority is immediately responded to through an interrupt priority mechanism. Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1It is one of the schematic flowcharts of the parallel execution method for interrupt tasks based on multi-core provided by the present invention.

[0018] Figure 2 It is the schematic structural diagram of the BMP system provided by the present invention.

[0019] Figure 3 It is the second schematic flowchart of the parallel execution method for interrupt tasks based on multi-core provided by the present invention.

[0020] Figure 4 It is the third schematic flowchart of the parallel execution method for interrupt tasks based on multi-core provided by the present invention.

[0021] Figure 5 It is the schematic startup flowchart of the BMP system provided by the present invention.

[0022] Figure 6 It is the schematic structural diagram of the parallel execution device for interrupt tasks based on multi-core provided by the present invention.

[0023] Figure 7 It is the schematic structural diagram of the electronic device provided by the present invention. Detailed implementation manners

[0024] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without making creative efforts based on the embodiments in the present invention belong to the scope of protection of the present invention.

[0025] A multi-core processor can execute multiple different interrupt tasks simultaneously, significantly accelerating the computing speed through parallel processing and improving the response efficiency and overall processing capacity of the system. The present invention proposes a Bound Multi-Processing (BMP) mode based on the CPU bare-metal running environment. The present invention aims to make full use of the parallel computing power of the multi-core processor and optimize the interrupt processing mechanism through multi-core static deployment design. On the basis of maintaining the stability of the original front-backstage framework of the platform's bare-running program, the efficient and real-time parallel execution of interrupt tasks among multiple cores is realized.

[0026] The following combines Figures 1-7 to describe the parallel execution method, device and electronic device for interrupt tasks based on multi-core of the present invention.

[0027] Figure 1 It is one of the schematic flowcharts of the parallel execution method for interrupt tasks based on multi-core provided by the present invention, as Figure 1As shown in the figure, the parallel execution method for interrupt tasks based on multi-cores includes steps S100 to S300, and the specific steps are as follows.

[0028] S100: Parse an external program file to obtain task information, and generate a task linked list based on the task information. The task linked list includes the mapping relationship among the interrupt task number, the core to be executed, and the interrupt execution function. The interrupt execution function is used to execute tasks at the software layer.

[0029] Before parsing the external program file to obtain task information, it further includes: allocating independent stack spaces for each core to be executed, so as to successively call the independent stack spaces of the cores to be executed that trigger interrupt tasks to process the triggered interrupt tasks based on the task linked list.

[0030] The multi-core processor of the present invention is an advanced reduced instruction set computer (Advanced RISC Machines, ARM) multi-core processor, including a main core and multiple slave cores. One core represents a CPU (Central Processing Unit). The execution entity of the present invention is a server that controls the BMP system. The BMP system includes an ARM multi-core processor. Start the main core (core0) and each slave core to obtain multiple cores to be executed (for example, core1, core2, and core3). Execute the BMP operation mode through the main core and multiple cores to be executed. As Figure 2 shown, the BMP system includes a system-on-chip (SOS), a bus (BUS), and a random access memory (RAM). Input / output (IO) timing, flash memory (FLASH), and inter-integrated circuit communication (Inter-Integrated Circuit, IIC) are carried out through the bus. The random access memory (RAM) includes the shared memory of core0, core1, core2, and core3.

[0031] Initialize the ARM multi-core processor, allocate independent stack spaces for each core and different exception modes of the ARM, and build the environment for the bare-metal operation of the power device system.

[0032] By allocating independent stack spaces for each core to be executed, the present invention is conducive to realizing the parallel processing of interrupt tasks by multiple cores to be executed, and improving the processing efficiency of a large number of interrupt tasks.

[0033] In the solution of the BMP operating mode, each core needs to execute a series of common initialization steps after startup. These initialization steps include allocating stack spaces of different modes for each core, configuring caches, performing mode switching, setting the page table attributes of the Memory Management Unit (MMU) and the Translation Lookaside Buffer (TLB), and configuring the Generic Interrupt Controller (GIC), etc., to ensure that the basic operating environment of each core is correctly established.

[0034] In addition, specific processing tasks are also undertaken among different cores. Among them, the main core, as the control entity running in the BMP mode, is responsible for initializing the peripheral resources (serial port, network port) allocated by the system, starting the bare-metal system, loading the HAL (Hardware Abstraction Layer) configuration file (adapting to different boards), and undertaking the responsibility of starting core1, core2, and core3.

[0035] Multi-core processors run in the BMP mode. They execute the same code and share the program space and data space. To ensure the consistency and efficiency of multi-core processors when accessing shared data, the MMU page table attributes of the memory are set to be Cacheable and Shareable. In addition, multi-core processors can use special instructions provided by ARM to obtain the IDs of each core, which enables different cores to be executed to execute corresponding branch code logic according to their own IDs, thus achieving more flexible and efficient task scheduling and processing.

[0036] To avoid unpredictable interrupts during system initialization, the interrupts are disabled and the Instruction Cache (Icache), Data Cache (Dcahce), and Memory Management Unit (MMU) are closed before compiling the code of the program file.

[0037] Based on the above embodiments, the external program file is parsed to obtain task information, including: parsing the external program file to extract the interrupt task number, the task type of the interrupt task, the execution period of the interrupt task, the priority of the interrupt task, the core to be executed of the interrupt task, and the interrupt execution function of the interrupt task; based on the interrupt task number, task type, execution period, priority, core to be executed, and interrupt execution function, the task information is obtained.

[0038] As Figure 3As shown, the main core in the ARM multi-core processor parses an external program file, which includes multiple task information. Parse the code of the external program file to obtain multiple task details. Each task information includes an interrupt task number, the task type of the interrupt task, the execution period of the interrupt task, the priority of the interrupt task, the core to be executed for the interrupt task, and the interrupt execution function of the interrupt task. The interrupt execution function is used to execute tasks at the software layer. Register the interrupt task in the interrupt controller according to the priority of the interrupt task.

[0039] Configure the interrupt controller and the task list according to the multiple task information. The task list includes a one-to-one mapping relationship among the interrupt task number, the core to be executed for the interrupt task, and the interrupt execution function of the interrupt task.

[0040] Configure the interrupt controller in the main core, and then determine whether the interrupt task reaches the trigger condition and the execution order of the interrupt task according to the task type, execution period, and priority. As Figure 3 shown, the main core of the ARM multi-core processor uses the hardware interrupt triggered by the Field-Programmable Gate Array (FPGA) as the periodic timing interrupt task. This periodic timing interrupt task has the highest priority, and the subsequent periodic detection of the interrupt task status in the task list is realized through this periodic timing interrupt task.

[0041] The present invention determines the task information according to the interrupt task number, task type, execution period, priority, core to be executed, and interrupt execution function, which not only facilitates the management and configuration of interrupt tasks, but also improves the flexibility and scalability of the BMP system.

[0042] S200: Periodically monitor the status of the interrupt task. When the interrupt task reaches the trigger condition, obtain at least one triggered interrupt task and the core to be executed for each triggered interrupt task.

[0043] Start the task monitoring and scheduling mechanism, and at the same time integrate the error handling and recovery functions to ensure the high efficiency and stability of the power device running in bare metal.

[0044] In an ARM multi-core processor, the main core and multiple slave cores operate in the BMP mode. Among them, the main core (core0) is the control center responsible for bare-metal operation. To ensure that the main core can monitor the task interruption status in real time, the main core will configure an external interrupt with the highest priority as a periodic timing interrupt task (main function), which is executed in the independent stack space of the main core, and monitors the status of the interrupt tasks in the system in real time to determine whether each interrupt task reaches the trigger condition. Once an interrupt task reaches the trigger condition, at least one triggered interrupt task and the execution cores to be executed for each triggered interrupt task are obtained. The corresponding interrupt execution function of the triggered interrupt task on the execution core to be executed is accurately triggered through the interrupt controller, so as to ensure that the triggered interrupt task can be executed in a timely and efficient manner.

[0045] S300: Sequentially call the execution cores to be executed for the triggered interrupt tasks to process the triggered interrupt tasks based on the task list.

[0046] As Figure 3 shown, the interrupt controller determines the execution cores to be executed for the triggered interrupt tasks, and sequentially calls the execution cores to be executed for the triggered interrupt tasks to activate the corresponding target interrupt execution function to complete the processing of the triggered interrupt tasks in the current cycle.

[0047] The parallel execution method of interrupt tasks based on multi-cores provided by the present invention obtains task information by parsing an external program file, generates a task list based on the task information, and the task list includes the mapping relationship among the interrupt task number, the execution core to be executed, and the interrupt execution function. The interrupt execution function is used to execute tasks at the software layer; periodically monitor the status of the interrupt tasks, and when an interrupt task reaches the trigger condition, obtain at least one triggered interrupt task and the execution cores to be executed for each triggered interrupt task; sequentially call the execution cores to be executed for the triggered interrupt tasks to process the triggered interrupt tasks based on the task list. The present invention realizes the precise deployment of interrupt tasks by defining abstract interrupts and their corresponding interrupt execution functions to represent each task in the external program file in a concrete form. The present invention realizes cross-core processing of interrupt tasks, realizes parallel deployment of interrupt tasks on multiple execution cores to be executed, fully exploits and utilizes the parallel processing capabilities of multi-cores, and improves the efficiency of simultaneously processing multiple interrupt tasks. The present invention ensures that the interrupt task with the highest priority can be immediately responded through the interrupt priority mechanism.

[0048] The present invention adopts a multi-core BMP mode in the CPU bare-metal operating environment. On the basis of maintaining the stability of the original front-back stage framework of the platform's bare-running program, an innovative multi-core static deployment design is carried out for the interrupt processing mechanism. Through this design, interrupt tasks can be efficiently and real-timely executed in parallel among multiple cores, thereby greatly improving the response speed and overall processing capacity of the system.

[0049] Based on the above embodiments, the execution core to be triggered for the interrupt task is sequentially called to process the triggered interrupt task based on the task linked list, including: in the triggered interrupt task, sequentially select the triggered interrupt task with the highest priority as the target interrupt task, and obtain the execution core of the target interrupt task; match the corresponding target interrupt execution function from the task linked list based on the target interrupt task; modify the status of the target interrupt task to obtain the target interrupt task with the status modified; call the execution core to respond to the target interrupt task with the status modified, and activate the target interrupt execution function to process the target interrupt task.

[0050] Modifying the status of the target interrupt task to obtain the target interrupt task with the status modified includes: when the status of the target interrupt task is the waiting state, modify the status of the target interrupt task to the active state, and the active state is used to activate the target interrupt execution function to process the target interrupt task; when the status of the target interrupt task is the waiting state and the target interrupt task is a task generated after execution, modify the status of the target interrupt task to the active and waiting state, and the active and waiting state is used to activate the target interrupt execution function and wait for the next execution cycle of the target interrupt task; when the status of the target interrupt task is the active state, modify the status of the target interrupt task to the active and waiting state.

[0051] The present invention activates the target interrupt execution function through the target interrupt task with the status modified, and realizes the execution of the target interrupt task at the software level. The present invention realizes the precise processing of different types of target interrupt tasks by modifying the status of the target interrupt task in different situations.

[0052] Based on the above embodiments, after obtaining the execution core of the target interrupt task, it further includes: if the execution core is processing other interrupt tasks and the priority of the other interrupt tasks is lower than the priority of the target interrupt task, control the execution core to perform interrupt nesting processing, so as to first call the execution core to process the target interrupt task, and then call the execution core to process the other interrupt tasks; if the execution core is processing other interrupt tasks and the priority of the other interrupt tasks is higher than the priority of the target interrupt task, wait for the other interrupt tasks to be executed and then call the execution core to process the target interrupt task.

[0053] Other interrupt tasks are interrupt tasks other than the target interrupt task. Such as Figure 4As shown in the figure, the interrupt controller obtains the target interrupt task number and the execution core, and then determines the target execution interrupt function through the task linked list. If the execution core is executing other interrupt tasks, the interrupt controller will decide whether to perform interrupt preemption according to the preset priority rules. Once interrupt preemption occurs, the execution core will enter the interrupt nesting processing flow, first execute the relevant interrupt execution function of the high-priority interrupt task, and then process the interrupt execution function of the low-priority interrupt task. Further, when the execution core enters the interrupt nesting processing flow, the independent stack space of the execution core saves the context information of the target interrupt task and the context information of other interrupt tasks, so that the target interrupt execution function of the nested target interrupt task and the interrupt execution functions of other interrupt tasks can share the independent stack space of the execution core, without the need to allocate a separate stack space for each interrupt task, thus optimizing the memory usage of the core and facilitating the improvement of the efficiency of simultaneously processing multiple interrupt tasks.

[0054] When the priority of other interrupt tasks is lower than that of the target interrupt task, the interrupt nesting processing flow is to stop processing other interrupt tasks, first give priority to processing the target interrupt task, and then process other interrupt tasks.

[0055] When the priority of other interrupt tasks is higher than that of the target interrupt task, the interrupt nesting processing flow is to wait for other interrupt tasks to finish executing and then process the target interrupt task.

[0056] The present invention decides whether to perform interrupt preemption according to the priority of the interrupt task, ensuring that high-priority interrupt tasks are executed first.

[0057] Based on the above embodiments, before parsing the external program file to obtain task information, it further includes: after starting the main core, based on the start commands sent by the main core to each slave core, starting the slave cores in sequence. After multi-core synchronization, the main core executes the main function, and the slave cores enter the waiting state to obtain at least one execution core.

[0058] Before parsing the external program file, start the BMP system. As Figure 5 shown, starting the BMP system includes starting the main core (for example, core0) and slave cores (for example, core1, core2, and core3) of the ARM multi-core processor. First start the main core, and then the started main core sends start commands to each slave core, starting the slave cores in sequence to enter the waiting state to obtain at least one execution core.

[0059] For example, as Figure 5 shown, starting the main core and slave cores of the ARM multi-core processor includes the following steps.

[0060] (1)After the system is powered on, core0 starts. After core0 is initialized, the bare-metal system is initialized. Core0 sends a startup command to slave core1 and waits for core1 to complete startup.

[0061] (2)After being awakened by core0, core1 is initialized, notifies core0 that startup is complete, and core1 enters the waiting state.

[0062] (3)After determining that core1 has completed startup, core0 then continues to start core2 and waits for core2 to complete startup.

[0063] (4)After being awakened by core0, core2 is initialized, notifies core0 that startup is complete, and core2 enters the waiting state.

[0064] (5)After determining that core2 has completed startup, core0 then continues to start core3 and waits for core3 to complete startup.

[0065] (6)After being awakened by core0, core3 is initialized, notifies core0 that startup is complete, and core3 enters the waiting state.

[0066] (7)After determining that core3 has completed startup, the four cores are synchronized to obtain the main core (core0) after startup and the pending execution cores 1 (core1 after startup), 2 (core2 after startup), and 3 (core3 after startup).

[0067] (8)Core0, core1, core2, and core3 run in the BMP mode. Core0 is responsible for the unified scheduling of the entire system, and core0 executes main (the main function). Core1, core2, and core3 execute main idle and wait for the allocation of interrupt tasks.

[0068] The present invention adopts a BMP processing solution for a multi-core processor based on a bare-metal system. External interrupts are directly provided to the main core by the FPGA.

[0069] The main core will periodically scan the status of the interrupt tasks registered in the task list of the BMP system to check whether there are interrupt tasks that have reached the trigger condition. If an interrupt task is found to be ready, the pending execution core and the interrupt task number are obtained. Further, the target interrupt task execution function is determined by querying through the task list. Further, the execution core is controlled to activate the target interrupt execution function to process the target interrupt task.

[0070] The present invention starts multiple slave cores in sequence according to a master core, achieving simultaneous startup of multiple slave cores. By controlling multiple cores to be executed by the master core, it ensures that at the same moment, different cores to be executed can execute different trigger interrupt tasks, giving full play to the parallel execution ability of the multi-core processor and significantly improving the overall efficiency of the system.

[0071] The parallel execution device for interrupt tasks based on multi-cores provided by the present invention will be described below. The parallel execution device for interrupt tasks based on multi-cores described below can be correspondingly referred to the parallel execution method for interrupt tasks based on multi-cores described above.

[0072] As Figure 6 shown, a parallel execution device for interrupt tasks based on multi-cores includes: a configuration module 601, configured to parse an external program file to obtain task information, generate a task linked list based on the task information, the task linked list including the mapping relationship among an interrupt task number, a core to be executed, and an interrupt execution function, and the interrupt execution function being used to execute tasks at the software layer.

[0073] A monitoring module 602, configured to periodically monitor the status of interrupt tasks, and when an interrupt task reaches a trigger condition, obtain at least one trigger interrupt task and the core to be executed for each trigger interrupt task.

[0074] A processing module 603, configured to sequentially call the cores to be executed of the trigger interrupt tasks to process the trigger interrupt tasks based on the task linked list.

[0075] The parallel execution device for interrupt tasks based on multi-cores provided by the present invention parses an external program file to obtain task information, generates a task linked list based on the task information, the task linked list including the mapping relationship among an interrupt task number, a core to be executed, and an interrupt execution function, and the interrupt execution function being used to execute tasks at the software layer; periodically monitors the status of interrupt tasks, and when an interrupt task reaches a trigger condition, obtains at least one trigger interrupt task and the core to be executed for each trigger interrupt task; sequentially calls the cores to be executed of the trigger interrupt tasks to process the trigger interrupt tasks based on the task linked list. The present invention realizes precise deployment of interrupt tasks by defining abstract interrupts and their corresponding interrupt execution functions to represent various tasks in the external program file in a concrete manner. The present invention realizes cross-core processing of interrupt tasks, realizes parallel deployment of interrupt tasks on multiple cores to be executed, fully excavates and utilizes the parallel processing ability of multi-cores, and improves the efficiency of simultaneously processing multiple interrupt tasks. The present invention ensures that the interrupt task with the highest priority is immediately responded to through an interrupt priority mechanism.

[0076] In one embodiment, the processing module 603 is configured to: in a triggered interrupt task, sequentially select the triggered interrupt task with the highest priority as the target interrupt task, and obtain the execution core of the target interrupt task; match the corresponding target interrupt execution function from the task linked list based on the target interrupt task; modify the status of the target interrupt task to obtain the target interrupt task with the modified status; call the execution core to respond to the target interrupt task with the modified status and activate the target interrupt execution function to process the target interrupt task.

[0077] In one embodiment, the processing module 603 is configured to: when the status of the target interrupt task is the waiting state, modify the status of the target interrupt task to the active state, and the active state is used to activate the target interrupt execution function to process the target interrupt task; when the status of the target interrupt task is the waiting state and the target interrupt task is a task generated after execution, modify the status of the target interrupt task to the active and waiting state, and the active and waiting state is used to activate the target interrupt execution function and then wait for the next execution cycle of the target interrupt task; when the status of the target interrupt task is the active state, modify the status of the target interrupt task to the active and waiting state.

[0078] In one embodiment, after obtaining the execution core of the target interrupt task, the processing module 603 is further configured to: if the execution core is processing other interrupt tasks and the priority of the other interrupt tasks is lower than the priority of the target interrupt task, control the execution core to perform interrupt nesting processing to first call the execution core to process the target interrupt task, and then call the execution core to process the other interrupt tasks; if the execution core is processing other interrupt tasks and the priority of the other interrupt tasks is higher than the priority of the target interrupt task, wait for the other interrupt tasks to be executed and then call the execution core to process the target interrupt task.

[0079] In one embodiment, the parallel execution device for interrupt tasks based on multiple cores further includes an initialization module. Before parsing the external program file to obtain task information, the initialization module is configured to: allocate independent stack spaces for each execution core to be called, and sequentially call the independent stack spaces of the execution cores to be called for the triggered interrupt tasks to process the triggered interrupt tasks based on the task linked list.

[0080] In one embodiment, before parsing the external program file to obtain task information, the initialization module is further configured to: after starting the main core, sequentially start the slave cores based on the start commands sent by the main core to each slave core. After the multiple cores are synchronized, the main core executes the main function, and the slave cores enter the waiting state to obtain at least one execution core to be called.

[0081] In one embodiment, the configuration module 601 is configured to: parse an external program file to extract the interrupt task number, the task type of the interrupt task, the execution period of the interrupt task, the priority of the interrupt task, the core to be executed of the interrupt task, and the interrupt execution function of the interrupt task; and obtain task information based on the interrupt task number, task type, execution period, priority, core to be executed, and interrupt execution function.

[0082] Figure 7 FIG. illustrates a schematic physical structure diagram of an electronic device, as Figure 7 shown. The electronic device may include: a processor 710, a communication interface 720, a memory 730, and a communication bus 740. Among them, the processor 710, the communication interface 720, and the memory 730 communicate with each other through the communication bus 740. The processor 710 may call logic instructions in the memory 730 to execute a method for parallel execution of interrupt tasks based on multiple cores. The method includes: parsing an external program file to obtain task information, generating a task linked list based on the task information, the task linked list including the mapping relationship among the interrupt task number, the core to be executed, and the interrupt execution function, and the interrupt execution function being used to execute a task at the software layer; periodically monitoring the status of the interrupt task, and when the interrupt task reaches a trigger condition, obtaining at least one triggered interrupt task and the core to be executed for each triggered interrupt task; and sequentially calling the cores to be executed of the triggered interrupt tasks to process the triggered interrupt tasks based on the task linked list.

[0083] In addition, when the logic instructions in the foregoing memory 730 are implemented in the form of a software functional unit and sold or used as an independent product, they may be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that makes a contribution to the prior art, or a part of the technical solution, may be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk, or an optical disc that can store program codes.

[0084] In another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements a parallel execution method of interrupt tasks based on multiple cores, and the method includes: parsing an external program file to obtain task information, generating a task linked list based on the task information, where the task linked list includes the mapping relationship among an interrupt task number, a core to be executed, and an interrupt execution function, and the interrupt execution function is used to execute tasks at the software layer; periodically monitoring the status of interrupt tasks, and when an interrupt task reaches a trigger condition, obtaining at least one triggered interrupt task and the core to be executed for each triggered interrupt task; and sequentially calling the cores to be executed of the triggered interrupt tasks to process the triggered interrupt tasks based on the task linked list.

[0085] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative efforts.

[0086] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the above technical solution, in essence, or the part that contributes to the prior art can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of each embodiment of the present invention.

Claims

1. A method for parallel execution of interrupt tasks based on multiple cores, characterized in that: include: Parsing an external program file to obtain task information, generating a task linked list based on the task information, wherein the task linked list includes a mapping relationship between an interrupt task number, a core to be executed, and an interrupt execution function, wherein the interrupt execution function is used to execute the task at the software layer; Periodically monitoring the status of the interrupt task, and when the interrupt task reaches a trigger condition, obtaining at least one triggered interrupt task and a to-be-executed core of each triggered interrupt task; The to-be-executed cores of the triggered interrupt task are called in sequence to process the triggered interrupt task based on the task linked list.

2. The method for parallel execution of interrupt tasks based on multiple cores according to claim 1, characterized in that: The calling in sequence the to-be-executed cores of the triggered interrupt task to process the triggered interrupt task based on the task linked list includes: Among the triggering interrupt tasks, selecting the triggering interrupt tasks with the highest priority in turn as target interrupt tasks, and obtaining the execution core of the target interrupt tasks; Matching a corresponding target interrupt execution function from the task chain list based on the target interrupt task; Modify the state of the target interrupt task to obtain the target interrupt task after the state is modified; The execution core is called to respond to the target interrupt task after the state is modified, and the target interrupt execution function is activated to process the target interrupt task.

3. The method for parallel execution of interrupt tasks based on multiple cores according to claim 2, characterized in that: The step of modifying the state of the target interrupt task to obtain the target interrupt task after the state is modified includes: When the state of the target interrupt task is a waiting state, modifying the state of the target interrupt task to an active state, wherein the active state is used to activate the target interrupt execution function to process the target interrupt task; When the state of the target interrupt task is a waiting state, and the target interrupt task is a task generated after execution, the state of the target interrupt task is modified to an active and waiting state, wherein the active and waiting state is used to activate the target interrupt execution function and wait for the next execution cycle of the target interrupt task; When the state of the target interrupt task is the active state, the state of the target interrupt task is modified to the active and waiting state.

4. The method for parallel execution of interrupt tasks based on multiple cores according to claim 2, characterized in that: After acquiring the execution core of the target interrupt task, the method further includes: If the execution core is processing other interrupt tasks, and the priority of the other interrupt tasks is lower than the priority of the target interrupt task, control the execution core to perform interrupt nesting processing, so as to first call the execution core to process the target interrupt task, and then call the execution core to process the other interrupt tasks; If the execution core is processing the other interrupt task and the priority of the other interrupt task is higher than the priority of the target interrupt task, wait until the other interrupt task is completed, and then call the execution core to process the target interrupt task.

5. The method for parallel execution of interrupt tasks based on multiple cores according to claim 1, characterized in that: Before parsing the external program file to obtain task information, the method further includes: An independent stack space is allocated to each of the to-be-executed cores, so as to sequentially call the independent stack spaces of the to-be-executed cores of the interrupt-triggering task to process the interrupt-triggering task based on the task linked list.

6. The method for parallel execution of interrupt tasks based on multiple cores according to claim 1, characterized in that: Before parsing the external program file to obtain task information, the method further includes: After starting the master core, the slave cores are started in sequence based on the start command sent by the master core to each slave core. After multi-core synchronization, the master core executes the main function, and the slave core enters a waiting state to obtain at least one of the cores to be executed.

7. The method for parallel execution of interrupt tasks based on multiple cores according to claim 1, characterized in that: The parsing of the external program file to obtain task information includes: Parsing the program file to extract the interrupt task number, the task type of the interrupt task, the execution cycle of the interrupt task, the priority of the interrupt task, the core to be executed of the interrupt task and the interrupt execution function of the interrupt task; The task information is obtained based on the interrupt task number, the task type, the execution cycle, the priority, the core to be executed and the interrupt execution function.

8. A parallel execution device for interrupt tasks based on multiple cores, characterized in that: include: A configuration module, used for parsing an external program file to obtain task information, and generating a task linked list based on the task information, wherein the task linked list includes a mapping relationship between an interrupt task number, a core to be executed, and an interrupt execution function, wherein the interrupt execution function is used to execute the task at the software layer; A monitoring module, used for periodically monitoring the status of interrupt tasks, and when the interrupt tasks reach a trigger condition, obtaining at least one triggered interrupt task and a to-be-executed core of each of the triggered interrupt tasks; The processing module is used to sequentially call the to-be-executed cores of the triggered interrupt task to process the triggered interrupt task based on the task linked list.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the method for parallel execution of interrupt tasks based on multiple cores as claimed in any one of claims 1 to 7 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for parallel execution of interrupt tasks based on multiple cores as claimed in any one of claims 1 to 7 is implemented.

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