Data processing method, readable storage medium, program product and electronic equipment

Abstract

The invention relates to the technical field of processors, and discloses a data processing method, a readable storage medium, a program product and electronic equipment. The method can be applied to a scene in which the processor executes the conditional branch instruction. Specifically, the method comprises the following steps: the electronic equipment obtains a first result by comparing high three bits of a condition code with an NZCV flag bit; and the electronic equipment obtains a prediction result obtained by the processor through the branch prediction method, and performs XOR operation on the prediction result and the lowest bit of the condition code to obtain a second result. It can be understood that if the first result is the same as the second result, the electronic device reads the to-be-executed instruction from the first memory space and executes the to-be-executed instruction. According to the data processing method, the circuit contained in the electronic equipment only needs to obtain the first result and the second result and judge whether the first result is the same as the second result or not, so that the logic stage number of the circuit is reduced, the operation efficiency of the circuit can be improved, and then the efficiency of executing the conditional branch instruction by the processor is improved.

Description

Technical Field

[0001] This application relates to the technical field of processors, and particularly to a data processing method, a readable storage medium, a program product, and an electronic device. Background Art

[0002] During the process of a processor executing a conditional branch instruction, the processor needs to determine the next instruction to be executed according to the execution result of the conditional branch instruction (the execution result is 1 or 0). Moreover, after the processor obtains the execution result of the conditional branch instruction, the processor reads the next instruction to be executed from the instruction cache or the main memory. In the case where the processor does not obtain the execution result of the conditional branch instruction, the processor will stop running to wait for the execution result of the conditional branch instruction. Thus, the efficiency of the processor in processing conditional branch instructions will be reduced, and further the operating efficiency of the electronic device will be reduced. Summary of the Invention

[0003] The purpose of this application is to provide a data processing method, a readable storage medium, a program product, and an electronic device. Among them, the data processing method includes:

[0004] A first aspect of this application provides a data processing method, including: obtaining a prediction result of a conditional branch instruction, and storing the instruction to be executed corresponding to the prediction result into a first memory space; obtaining execution result information of the conditional branch instruction and an execution result status flag; obtaining a first result based on a first field in the execution result information and the value of a first flag bit in the execution result status flag; performing an exclusive OR operation on a second field in the execution result information and the prediction result of the conditional branch instruction to obtain a second result; when the first result is the same as the second result, reading the instruction to be executed from the first memory space and executing the instruction to be executed.

[0005] In this method, the data processing method of this application can pre-store the instruction to be executed corresponding to the prediction result into the first memory space, and determine whether the prediction result of the branch prediction is consistent with the condition code detection result. When the prediction result of the branch prediction is consistent with the condition code detection result, the processor can read the instruction to be executed from the first memory space and execute the instruction to be executed. It can be understood that the first memory space is a branch target buffer (BTB), and the BTB is a high-speed cache. Since the speed at which the processor reads the instruction to be executed from the BTB is greater than the speed at which the processor reads the instruction to be executed from the instruction cache or the main memory. Therefore, the data processing method of this application can improve the efficiency of the processor in performing data processing involving conditional branch instructions.

[0006] In addition, the circuit corresponding to the data processing method of the present application involves an exclusive-OR gate in the logic of performing an exclusive-OR operation on the second field in the execution result information and the prediction result of the conditional branch instruction, and the logic level is 1 level. When determining whether the first result and the second result are the same, that is, performing an exclusive-OR operation on the first result and the second result, the logic of this exclusive-OR operation involves an exclusive-OR gate, and the logic level is 1 level. Therefore, the logic level of the circuit corresponding to the data processing method of the present application is 2 levels. In this way, compared with the method of using a 1-of-2 multiplexer to determine whether the prediction result is correct in some embodiments, the data processing method of the present application can reduce the circuit operation time and improve the efficiency of the processor in processing conditional branch instructions.

[0007] In a possible implementation of the foregoing first aspect, the foregoing method further includes: when the first result and the second result are different, clearing the instructions to be executed in the first memory space.

[0008] In this method, when the first result and the second result are different, the electronic device can determine that the prediction result of the branch prediction is inconsistent with the condition code detection result, and then the electronic device can clear the instructions to be executed in the first memory space.

[0009] In a possible implementation of the foregoing first aspect, the foregoing execution result information includes a condition code; the first field in the foregoing execution result information is the upper three bits cond[3:1] of the condition code; the second field in the foregoing execution result information is the lowest bit cond[0] of the condition code; the foregoing execution result status flag is a negative flag, a zero flag, a carry flag, and an overflow flag.

[0010] In a possible implementation of the foregoing first aspect, the foregoing obtaining the first result based on the first field in the execution result information and the value of the first flag bit in the execution result status flag includes: if the first field is 000 and the value corresponding to the flag bit Z is 1, then the first result is 1; if the first field is 001 and the value corresponding to the flag bit C is 1, then the first result is 1; if the first field is 010 and the value corresponding to the flag bit N is 1, then the first result is 1; if the first field is 011 and the value corresponding to the flag bit V is 1, then the first result is 1; if the first field is 100 and the value corresponding to the flag bit C is 1 and the value corresponding to the flag bit Z is 0, then the first result is 1; if the first field is 101 and the value corresponding to the flag bit N is equal to the value corresponding to the flag bit V, then the first result is 1; if the first field is 110 and the value corresponding to the flag bit N is equal to the value corresponding to the flag bit V and the value corresponding to the flag bit Z is 0, then the first result is 1; if the first field is 111, then the first result is 1.

[0011] In a possible implementation of the foregoing first aspect, obtaining the first result based on the value of the first field in the execution result information and the first flag bit in the execution result status flag further includes: if the first field is 000 and the value corresponding to flag bit Z is 0, the first result is 0; if the first field is 001 and the value corresponding to flag bit C is 0, the first result is 0; if the first field is 010 and the value corresponding to flag bit N is 0, the first result is 0; if the first field is 011 and the value corresponding to flag bit V is 0, the first result is 0; if the first field is 100 and the value corresponding to flag bit C is 0 and / or the value corresponding to flag bit Z is 1, the first result is 0; if the first field is 101 and the value corresponding to flag bit N is not equal to the value corresponding to flag bit V, the first result is 0; if the first field is 110 and the value corresponding to flag bit N is not equal to the value corresponding to flag bit V and / or the value corresponding to flag bit Z is 1, the first result is 0.

[0012] In a possible implementation of the foregoing first aspect, performing an exclusive OR operation on the second field in the execution result information and the predicted result of the conditional branch instruction to obtain the second result includes: if the second field is 0 and the predicted result of the conditional branch instruction is 0, the second result is 0; if the second field is 0 and the predicted result of the conditional branch instruction is 1, the second result is 1; if the second field is 1 and the predicted result of the conditional branch instruction is 0, the second result is 1; if the second field is 1 and the predicted result of the conditional branch instruction is 1, the second result is 0.

[0013] In a possible implementation of the foregoing first aspect, when the first result and the second result are different, clearing the instructions to be executed in the first memory space includes: when the first result and the second result are different, the electronic device generates an electrical signal, where the electrical signal can indicate deleting all the instructions to be executed in the first memory space.

[0014] A second aspect of the present application provides a readable storage medium, on which instructions are stored, and when the instructions are executed on an electronic device, the electronic device is caused to execute any one of the data processing methods in the foregoing first aspect.

[0015] A third aspect of the present application provides an electronic device, including a memory for storing instructions executed by one or more processors of the electronic device, and a processor, which is one of the processors of the electronic device, for executing any one of the data processing methods in the foregoing first aspect.

[0016] A fourth aspect of the present application provides a program product, including instructions, and when the instructions are executed on an electronic device, the electronic device is caused to execute any one of the data processing methods in the foregoing first aspect. Description of the Drawings

[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 According to some embodiments of the present application, a schematic diagram of an application scenario of a conditional branch instruction is shown;

[0019] Figure 2 According to some embodiments of the present application, a schematic diagram of a conditional code detection process is shown;

[0020] Figure 3 According to some embodiments of the present application, a schematic diagram of a circuit principle for data processing is shown;

[0021] Figure 4 According to some embodiments of the present application, a schematic diagram of a data processing method process is shown;

[0022] Figure 5 According to some embodiments of the present application, another schematic diagram of a circuit principle for data processing is shown;

[0023] Figure 6 According to some embodiments of the present application, a schematic diagram of the structure of an electronic device is shown;

[0024] Figure 7 According to some embodiments of the present application, a block diagram of a system on a chip is shown. Specific Embodiments

[0025] The illustrative embodiments of the present application include, but are not limited to, a data processing method, a readable storage medium, a program product, and an electronic device.

[0026] It can be understood that the data processing method mentioned in the embodiments of this application can be applied to any data processing electronic device. Among them, the electronic device can be referred to as a terminal, user equipment (UE), mobile station (MS), mobile terminal (MT), etc. Moreover, the electronic device can be a mobile phone, smart TV, wearable device, tablet computer (Pad), computer with wireless transceiver function, virtual reality (VR) terminal device, augmented reality (AR) terminal device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home and other devices.

[0027] The data processing method mentioned in the embodiments of this application can be applied to different processor architectures, including but not limited to ARM (advanced RISC machine, ARM) architecture, x86 architecture, PowerPC (performance optimization with enhanced RISC–performance computing, PowerPC) architecture, RISC-V architecture, MIPS (microprocessor without interlocked pipelined stages, MIPS) architecture, SPARC (scalable processor architecture, SPARC) architecture.

[0028] To facilitate the understanding of this solution, some basic concepts and technical terms involved in this application are introduced first.

[0029] (1) Condition code

[0030] The condition code is used to represent the execution result of the most recent instruction executed by the processor. In the processor architecture, the condition code is usually represented by a set of binary bits. Exemplarily, as shown in Table 1, Table 1 shows the condition codes, the corresponding mnemonics of the condition codes, and the meanings represented by the condition codes in the ARM instruction set.

[0031] Table 1 Condition Codes, Mnemonics Corresponding to Condition Codes, and Meanings of Condition Codes

[0032] Condition Code Mnemonic Meaning Condition Code Mnemonic Meaning 0000 EQ Equal 0001 NE Not Equal 0010 CS Unsigned Greater Than or Equal 0011 CC Unsigned Less Than 0100 MI Negative 0101 PL Positive or Zero 0110 VS Overflow 0111 VC No Overflow 1000 HI Unsigned Greater Than 1001 LS Unsigned Less Than or Equal 1010 GE Signed Greater Than or Equal 1011 LT Signed Less Than 1100 GT Signed Greater Than 1101 LE Signed Less Than or Equal 1110 AL Always 1111 NV Never

[0033] Exemplarily, the mnemonic for the condition code '0000' is EQ, and the meaning of the condition code '0000' is equal. That is, when the execution result of the most recent instruction executed by the processor is that two data are equal, the corresponding condition code of this execution result is '0000'. The mnemonics and meanings of other condition codes can be deduced by analogy and will not be described here.

[0034] (2) NZCV Flag Bits (or Called Flag Bits)

[0035] The NZCV flag bits are used to represent the status information of the processor execution result. The specific introduction is as follows:

[0036] N (Negative) is the negative flag. If the execution result of the processor is negative, the processor will set the N flag bit to 1, otherwise it will set the N flag bit to 0.

[0037] Z (Zero) is the zero flag. If the execution result of the processor is 0, the Z flag bit is set to 1, otherwise the Z flag bit is set to 0.

[0038] C (Carry) is the carry flag. For addition operations, if the execution result of the processor generates an unsigned overflow, the C flag bit is set to 1, otherwise the C flag bit remains unchanged. For subtraction operations, if the execution result of the processor generates an unsigned underflow, the C flag bit is set to 0, otherwise the C flag bit is set to 1.

[0039] V (Overflow) is the overflow flag. If the execution result of the processor causes a signed overflow, the V flag bit is set to 1, otherwise the V flag bit remains unchanged.

[0040] It can be understood that the NZCV flag bits represent the status information of the processor's most recent execution result. For example, whether the execution result is zero, whether it is negative, whether there is a carry or overflow, etc.

[0041] According to the status information of the NZCV flag bits, the electronic device can determine the condition codes corresponding to the NZCV flag bits. The following are some common condition codes and their corresponding relationships with the NZCV flag bits, including:

[0042] EQ: When the Z flag bit is 1, it means the execution result is zero, then the condition code EQ is true.

[0043] NE: When the Z flag bit is 0, it means the execution result is not zero, then the condition code NE is true.

[0044] CS: When the C flag is 1, it indicates that the execution result of the unsigned number is greater than or equal to, and then the condition code CS is true.

[0045] CC: When the C flag is 0, it indicates that the execution result of the unsigned number is less than, and then the condition code CC is true.

[0046] MI: When the N flag is 1, it indicates that the execution result is negative, and then the condition code MI is true.

[0047] PL: When the N flag is 0, it indicates that the execution result is positive or zero, and then the condition code PL is true.

[0048] VS: When the V flag is 1, it indicates that the execution result of the signed number overflows, and then the condition code VS is true.

[0049] VC: When the V flag is 0, it indicates that the execution result of the signed number does not overflow, and then the condition code VC is true.

[0050] HI: When C = 1 and Z = 0, it indicates that the execution result of the unsigned number is greater than, and then the condition code HI is true.

[0051] LS: When C = 0 or Z = 1, it indicates that the execution result of the unsigned number is less than or equal to, and then the condition code LS is true.

[0052] GE: When the N flag and the V flag are the same (i.e., N = V), it indicates that the execution result of the signed number is greater than or equal to, and then the condition code GE is true.

[0053] LT: When the N flag and the V flag are different (i.e., N ≠ V), it indicates that the execution result of the signed number is less than, and then the condition code LT is true.

[0054] GT: When Z = 0 and N = V, it indicates that the execution result of the signed number is greater than, and then the condition code GT is true.

[0055] LE: When Z = 1 or N ≠ V, it indicates that the execution result of the signed number is less than or equal to, and then the condition code LE is true.

[0056] AL: Unconditionally execute the instruction.

[0057] NV: Never execute the instruction.

[0058] It can be understood that according to whether the condition code is true, the electronic device can determine whether to execute the corresponding instruction. For example, in the ARM architecture, conditional branch instructions determine whether to perform a jump based on the status information of the Z flag bit. For example, BEQ (branch if equal) means that if the electronic device detects that the Z flag bit is 1 (i.e., the execution result is zero), it will perform a jump. BNE (branch if not equal) means that if the electronic device detects that the Z flag bit is 0 (i.e., the execution result is not zero), it will perform a jump.

[0059] Exemplarily, for the instruction

[0060] BEQ label;

[0061] The electronic device can use BEQ to check the Z flag bit. If the Z flag bit is 1, that is, the condition code EQ is true, it will jump to the instruction label.

[0062] It can be understood that through the above corresponding relationship, the electronic device can use the NZCV flag bits and condition codes, enabling the program to execute different instructions according to different execution results, thereby achieving complex logical control.

[0063] (3) Conditional branch instructions

[0064] Conditional branch instructions refer to instructions that can change the order of instruction execution during the process of the processor executing instructions. That is, conditional branch instructions can determine whether the processor jumps to other instructions according to the condition code, rather than executing instructions according to the instruction arrangement order.

[0065] Exemplarily, during the process of the processor executing instructions, the instruction set that the processor needs to execute can be [Instruction 1, Instruction 2, Conditional branch instruction 10 (if the execution result of Conditional branch instruction 10 is 1, the processor executes Instruction 4, otherwise it executes Instruction 5), Instruction 3, Instruction 4, Instruction 5, Instruction 6, Instruction 7, Instruction 8]. It can be understood that after the processor executes Conditional branch instruction 10, the next instruction to be executed may be Instruction 4 or Instruction 5, not the next sequential instruction of Conditional branch instruction 10 in the instruction set (i.e., Instruction 3).

[0066] (4) Branch prediction

[0067] Branch prediction refers to an electronic device predicting the execution result of a conditional branch instruction based on preset data (for example, historical record data of the next instruction to be executed after the processor executes a conditional branch instruction), and the next instruction that the processor may execute after executing the conditional branch instruction. It can be understood that in practice, the next instruction that the electronic device predicts may execute may include one or more instructions, and among the multiple instructions, there may be the next instruction actually executed by the processor after executing the conditional branch instruction. Moreover, before the processor obtains the execution result of the conditional branch instruction, the electronic device can store the predicted multiple instructions in a specified memory (i.e., the branch target buffer (BTB)).

[0068] It can be understood that if the execution result of the conditional branch instruction is consistent with the predicted result, the processor can directly obtain the next instruction from the specified memory; if the execution result of the conditional branch instruction is inconsistent with the predicted result, the electronic device needs to clear all the instructions predicted and obtained stored in the specified memory, and re-obtain the correct instructions from the memory of the processor (i.e., the instruction cache or the main memory) according to the execution result of the conditional branch instruction.

[0069] Exemplarily, after the processor obtains the conditional branch instruction 10 and before the processor obtains the execution result of the conditional branch instruction 10, the electronic device can perform branch prediction on the conditional branch instruction 10. It can be understood that the multiple instructions for branch prediction may be [instruction 3, instruction 4, instruction 5]. Therefore, the electronic device stores [instruction 3, instruction 4, instruction 5] in the specified memory.

[0070] In an implementable manner, if the predicted result obtained by the electronic device is 1, and the actual execution result of the conditional branch instruction 10 obtained by the processor is 1, the predicted result is correct at this time. According to the execution result, the next instruction of the conditional branch instruction 10 is instruction 4, then the electronic device can directly obtain instruction 4 from the specified memory.

[0071] In another implementable manner, if the execution result of the conditional branch instruction 10 is 0, then according to the execution result, the next instruction of the conditional branch instruction 10 is instruction 5, then the predicted result is incorrect, and the electronic device can generate an electrical signal (such as a KILL signal) to clear all the instructions stored in the specified memory, and re-obtain the correct instructions from the memory of the processor.

[0072] It can be understood that the conditional branch instructions mentioned in this application can be conditional branch instructions of any type such as image processing, audio processing, voice communication, industrial data processing (such as machine fault diagnosis), etc.

[0073] For example, as Figure 1As shown, when the mobile phone 100 detects that the user clicks the shooting button 101 in the camera application (e.g., camera), the mobile phone 100 can shoot the image 102. Among them, during the process of shooting the image 102, the mobile phone 100 can adjust parameters such as the contrast, exposure, and saturation of the image 102, so that the captured image 102 has higher clarity and authenticity, thereby improving the image quality of the image 102 captured by the mobile phone 100. For example, the mobile phone 100 can adjust the contrast of the image 102 by executing the conditional branch instruction "if the contrast of the image 102 is less than the contrast threshold, increase the contrast; if the contrast of the image 102 is greater than the contrast threshold, decrease the contrast", so that the captured image 102 has higher clarity. Specifically, the electronic device can use the condition code CC being true to indicate that the electronic device detects that the contrast is less than the contrast threshold, and use CS to indicate that the contrast is greater than the contrast threshold. It can be understood that when CC is true (the operation result is 0), the electronic device can increase the contrast. When CS is true (the operation result is 1), the electronic device can decrease the contrast.

[0074] It can be understood that the conditional branch instruction mentioned in this application can be any type of conditional branch instruction, and this application does not limit this.

[0075] As mentioned above, during the process of the processor executing the conditional branch instruction, the processor needs to determine the next instruction to be executed according to the execution result of the conditional branch instruction (the execution result is 1 or 0). And after the processor obtains the execution result of the conditional branch instruction, the processor will read the next instruction to be executed from the instruction cache or the main memory. In the case where the processor does not obtain the execution result of the conditional branch instruction, the processor will stop running to wait for the execution result of the conditional branch instruction. In this way, the efficiency of the processor in processing the conditional branch instruction will be reduced, and thus the operating efficiency of the electronic device will be reduced.

[0076] Based on this, during the process of the processor processing the conditional branch instruction, the electronic device can predict whether the execution result of the conditional branch instruction is 1 or 0, and predict one or more instructions that the processor may execute, and then store the predicted one or more instructions in the specified memory. When the prediction result (the prediction result is 1 or 0) is consistent with the execution result of the conditional branch instruction, the processor can directly obtain the next instruction from the specified memory. Since determining whether the prediction result is consistent with the execution result of the conditional branch instruction only requires the processor to make a judgment of 1 or 0, and the speed at which the processor reads the instruction to be executed from the BTB is greater than the speed at which the processor reads the instruction to be executed from the instruction cache or the main memory. Therefore, the data processing method of this application improves the efficiency of the processor in executing the conditional branch instruction.

[0077] In some implementable ways, the electronic device may first obtain the execution result of the conditional branch instruction and the prediction result of the branch prediction, and then determine whether the prediction result of the branch prediction is consistent with the execution result of the conditional branch instruction.

[0078] Exemplarily, as described above, the condition code can be used to represent the execution result of the most recent instruction executed by the processor. Therefore, the electronic device can obtain the execution result of the conditional branch instruction by detecting the condition code, that is, the electronic device can use the condition code detection result as the execution result of the conditional branch instruction. During the process of detecting the condition code, the electronic device first identifies the high three bits (cond[3:1]) of the condition code, and then obtains the initial condition code detection result according to the value of the flag bit. Finally, the electronic device identifies the lowest bit (cond[0]) of the condition code to obtain the condition code detection result. The specific process of detecting the condition code is as Figure 2 shown, including:

[0079] S201: Detect the values of cond[1:3] of the condition code and the corresponding flag bits to obtain the initial condition code detection result.

[0080] In some implementable ways, the electronic device first identifies the high three bits (i.e., cond[3:1]) of the condition code, and then obtains the initial condition code detection result according to the value of the flag bit.

[0081] Exemplarily, if the electronic device detects that cond[1:3] of the condition code is '000', the condition code may be '0000' or '0001', that is, the electronic device can determine that the condition code may be EQ or NE. Further, if the electronic device detects that the Z flag bit of the processor is 1, that is, the condition code EQ is true. For the case where the condition code EQ is true, the electronic device can set the initial condition code detection result to 1. If the electronic device detects that the Z flag bit of the processor is 0, that is, the condition code NE is true. For the case where the condition code NE is true, the electronic device can set the initial condition code detection result to 0.

[0082] Exemplarily, if the electronic device detects that cond[1:3] of the condition code is '001', the condition code may be '0010' or '0011', that is, the electronic device can determine that the condition code may be CS or CC. Further, if the electronic device detects that the C flag bit of the processor is 1, that is, CS is true. For the case where the condition code CS is true, the electronic device can set the initial condition code detection result to 1. If the electronic device detects that the C flag bit of the processor is 0, that is, CC is true. For the case where the condition code CC is true, the electronic device can set the initial condition code detection result to 0.

[0083] Exemplarily, if the electronic device detects that cond[1:3] of the condition code is '010', the condition code may be '0100' or '0101', that is, the electronic device can determine that the condition code may be MI or PL. Further, if the electronic device detects that the N flag bit of the processor is 1, that is, MI is true. For the case where the condition code MI is true, the electronic device can set the initial condition code detection result to 1. If the electronic device detects that the N flag bit of the processor is 1, that is, PL is true. For the case where the condition code PL is true, the electronic device can set the initial condition code detection result to 0.

[0084] Exemplarily, if the electronic device detects that cond[1:3] of the condition code is '011', the condition code may be '0110' or '0111', that is, the electronic device can determine that the condition code may be VS or VC. Further, if the electronic device detects that the V flag bit of the processor is 1, that is, VS is true. For the case where the condition code VS is true, the electronic device can set the initial condition code detection result to 1. If the electronic device detects that the V flag bit of the processor is 1, that is, VC is true. For the case where the condition code VC is true, the electronic device can set the initial condition code detection result to 0.

[0085] Exemplarily, if the electronic device detects that cond[1:3] of the condition code is '100', the condition code may be '1000' or '1001', that is, the electronic device can determine that the condition code may be HI or LS. Further, if the electronic device detects that the C flag bit of the processor is 1 and the Z flag bit is 0, that is, HI is true. For the case where the condition code HI is true, the electronic device can set the initial condition code detection result to 1. If the electronic device detects that the C flag bit of the processor is not 1 or the Z flag bit is not 0, that is, LS is true. For the case where the condition code LS is true, the electronic device can set the initial condition code detection result to 0.

[0086] Exemplarily, if the electronic device detects that cond[1:3] of the condition code is '101', the condition code may be '1010' or '1011', that is, the electronic device can determine that the condition code may be GE or LT. Further, if the electronic device detects that the N flag bit of the processor is equal to the V flag bit, that is, GE is true. For the case where the condition code GE is true, the electronic device can set the initial condition code detection result to 1. If the electronic device detects that the N flag bit of the processor is not equal to the V flag bit, that is, LT is true. For the case where the condition code LT is true, the electronic device can set the initial condition code detection result to 0.

[0087] Exemplarily, if the electronic device detects that cond[1:3] of the condition code is '110', the condition code may be '1100' or '1101', that is, the electronic device can determine that the condition code may be GT or LE. Further, if the electronic device detects that the N flag bit and the V flag bit of the processor are equal, and the Z flag bit is 0, that is, GT is true. For the case where the condition code GT is true, the electronic device can set the initial condition code detection result to 1. If the electronic device detects that the N flag bit and the V flag bit of the processor are not equal, or the Z flag bit is not 0, that is, LE is true. For the case where the condition code LE is true, the electronic device can set the initial condition code detection result to 0.

[0088] Exemplarily, if the electronic device detects that cond[1:3] of the condition code is '111', the condition code may be '1110' or '1111', that is, the electronic device can determine that the condition code may be AL or NV. Specifically, AL means "always", that is, regardless of the state of the flag bits, the processor will execute the instruction unconditionally. NV means "never", regardless of the state of the flag bits, the processor will never execute the instruction. When the electronic device detects that cond[1:3] of the condition code is '111', the electronic device can set the initial condition code detection result to 1 to simplify the process of condition code detection.

[0089] S202: Detect cond[0] of the condition code and return the condition code detection result.

[0090] In some implementable ways, when the electronic device detects that cond[0] of the condition code is 1 and the condition code (i.e., cond) is not '1111', the electronic device can reverse the initial condition code detection result to obtain the condition code detection result. And determine whether to perform a jump according to the condition code detection result and execute the instruction corresponding to the condition code.

[0091] Exemplarily, in S201, the electronic device can detect that cond[1:3] is '000'. When PSTATE.Z == 1, the initial condition code detection result is 1. When PSTATE.Z == 0, the initial condition code detection result is 0. Then, in S202, in an implementable way, if the electronic device detects that cond[0] of the condition code is 0, the electronic device can determine that the detected condition code is '0000' (i.e., EQ). Therefore, when the electronic device detects that PSTATE.Z == 1, that is, the execution result of the processor is zero and the condition code EQ is true, the condition code detection result is 1, that is, the electronic device will perform a jump next and execute the instruction corresponding to the condition code.

[0092] When the electronic device detects that PSTATE.Z == 0, that is, the execution result of the processor is not zero and the condition code EQ is not true, the condition code detection result is 0, which means that the electronic device will not jump next.

[0093] It can be understood that compared with the initial condition code detection result (that is, the electronic device can detect that cond[1:3] is '000'. When PSTATE.Z == 1, the initial condition code detection result is 1. When PSTATE.Z == 0, the initial condition code detection result is 0), when the electronic device detects that cond[0] is 0, the electronic device does not invert the initial condition code detection result. That is, when the initial condition code detection result is 1, the condition code detection result is 1. When the initial condition code detection result is 0, the condition code detection result is 0.

[0094] In another implementable way, if the electronic device detects that cond[0] of the condition code is 1, the electronic device can determine that the detected condition code is '0001' (i.e., NE), not '1111'. Therefore, when the electronic device detects that PSTATE.Z == 1, that is, the execution result of the processor is zero and the condition code NE is not true, the condition code detection result is 0, which means that the electronic device will not jump next. When the electronic device detects that PSTATE.Z == 0, that is, the execution result of the processor is not zero and the condition code NE is true, the condition code detection result is 1, which means that the electronic device will jump next and execute the instruction corresponding to the condition code. It can be understood that compared with the initial condition code detection result (that is, the electronic device can detect that cond[1:3] is '000'. When PSTATE.Z == 1, the initial condition code detection result is 1. When PSTATE.Z == 0, the initial condition code detection result is 0), when the electronic device detects that cond[0] is 1 and the condition code is not '1111', the electronic device inverts the initial condition code detection result. That is, when the initial condition code detection result is 1, the condition code detection result is 0. When the initial condition code detection result is 0, the condition code detection result is 1.

[0095] The condition code detection results for other condition codes where cond[1:3] is '001', '010', '011', '100', '101', '110', '111' can be deduced by analogy and will not be described here.

[0096] It can be understood that based on the condition code detection result, the electronic device can determine whether the processor jumps when executing a conditional branch instruction according to the status information of the processor's most recent execution result and the condition code. If the processor jumps when executing the conditional branch instruction, the electronic device needs to determine whether the prediction result of branch prediction is consistent with the condition code detection result, and when the prediction result of branch prediction is consistent with the condition code detection result, obtain the next instruction that the processor needs to execute from the specified memory. If the processor does not jump when executing the conditional branch instruction, the electronic device sequentially executes the next instruction.

[0097] Exemplarily, the instruction set that the processor needs to execute can be [Instruction 1, Instruction 2, Conditional Branch Instruction 10 (if the execution result of Conditional Branch Instruction 10 is 1, the processor executes Instruction 4, otherwise it executes Instruction 5), Instruction 3, Instruction 4, Instruction 5, Instruction 6, Instruction 7, Instruction 8]. It can be understood that if the processor does not jump when executing the conditional branch instruction, the electronic device sequentially executes Instruction 3. If the processor jumps when executing the conditional branch instruction, the electronic device can determine whether to execute Instruction 4 or Instruction 5 according to the condition code detection result (including 1 and 0).

[0098] In an implementable manner, as Figure 3 shown, the electronic device can determine whether the prediction result of branch prediction is consistent with the condition code detection result through the circuit shown in Figure 3 .

[0099] It can be understood that Figure 3 the circuit in first uses a 1-bit multiplexer to select cond[3:1] or NOT cond[3:1] according to cond[0]. According to the selection result of the 1-bit multiplexer, an exclusive OR operation is performed with the predict value (the prediction result of branch prediction) to determine whether the prediction result of branch prediction is consistent with the execution result of the conditional branch instruction.

[0100] It can be understood that the process of obtaining the initial condition code detection result according to the condition code cond[3:1] and the flag bit is introduced in detail in S201, and this process is Figure 3The "cond[3:1] field detection" in []. It can be understood that the result of the "cond[3:1] field detection" is the initial condition code detection result in S201. Therefore, one input of the 2-to-1 multiplexer is the initial condition code detection result, and the other input of the 2-to-1 multiplexer is NOT cond[3:1], which is the inversion of the initial condition code detection result in S202. Specifically, if the result of the "cond[3:1] field detection" of the condition code is 1, then NOT cond[3:1] is 0. If the result of the "cond[3:1] field detection" of the condition code is 0, then NOT cond[3:1] is 1.

[0101] In Figure 3 the electronic device uses the cond[0] field of the condition code to determine whether the condition code detection result is the result of the "cond[3:1] field detection" or NOT cond[3:1] through a 2-to-1 multiplexer.

[0102] Exemplarily, if the electronic device detects that cond[3:1] = '000' and the Z flag bit is 1, then the initial condition code detection result is 1, that is, the result of the "cond[3:1] field detection" is 1, and then NOT cond[3:1] is 0. It can be understood that when cond[0] = 1, the 2-to-1 multiplexer selects NOT cond[3:1] as 0, that is, the condition code detection result is 0. When cond[0] = 0, the 2-to-1 multiplexer selects the result 1 of the "cond[3:1] field detection", that is, the condition code detection result is 1. The situations of other condition codes can be deduced by analogy and will not be described here.

[0103] In an implementable manner, if the prediction result of branch prediction is consistent with the condition code detection result, the result of the exclusive OR operation is 0. If the prediction result of branch prediction is inconsistent with the condition code detection result, the result of the exclusive OR operation is 1.

[0104] It can be understood that if the condition code detection result is 0 and the prediction result obtained by the electronic device is 1, then the result of the exclusive OR operation is 1. If the condition code detection result is 0 and the prediction result obtained by the electronic device is 0, then the result of the exclusive OR operation is 0. If the condition code detection result is 1 and the prediction result obtained by the electronic device is 1, then the result of the exclusive OR operation is 0.

[0105] It can be understood that when the result of the exclusive OR operation is 1, the electronic device can determine that the prediction result of branch prediction is inconsistent with the condition code detection result. Therefore, the electronic device can generate an electrical signal (e.g., a KILL signal) to clear one or more instructions of the branch prediction stored in the specified memory. When the result of the exclusive OR operation is 0, the electronic device can determine that the prediction result of branch prediction is consistent with the condition code detection result, and the electronic device can directly obtain the next instruction to be executed from the specified memory.

[0106] However, since the implementation of a 2-to-1 multiplexer generally involves a combination of AND gates, OR gates, and NOT gates, especially in high-speed circuits (such as circuits in a processor), the 2-to-1 multiplexer will require a longer circuit delay. Therefore, the 2-to-1 multiplexer will become the factor that most restricts the circuit timing. Specifically, according to the estimation of the logic level (in digital circuit design, the number of logic gates required for a signal to propagate from one input to the output in a circuit is estimated), the 2-to-1 multiplexer requires approximately 1.5 to 2 levels of logic, while basic logic gates (such as AND gates, OR gates, NOT gates, XOR gates, etc.) are 1 level of logic. Therefore, the 2-to-1 multiplexer restricts the circuit timing more than basic logic gates.

[0107] Exemplarily, as Figure 3 shown, the logic for obtaining NOT cond[3:1] involves a NOT gate and is 1 level. The logic for the electronic device to select between cond[3:1] and NOT cond[3:1] using cond[0] through a 2-to-1 multiplexer involves the 2-to-1 multiplexer and is at least 1.5 levels. The logic for performing an exclusive OR operation on the selection result of the 2-to-1 multiplexer and the prediction result involves an XOR gate and is 1 level. Therefore, Figure 3 the logic level of the circuit is at least 3.5 levels.

[0108] Therefore, in order to increase the maximum frequency of the processor to improve the processing efficiency of the processor, the present application provides a data processing method to determine whether the prediction result of branch prediction is consistent with the condition code detection result. The present application removes the 2-to-1 multiplexer in the circuit and adjusts the arithmetic logic of the circuit after removing the 2-to-1 multiplexer, so that the adjusted circuit can determine whether the prediction result of branch prediction is consistent with the condition code detection result. In this way, the maximum frequency of the processor can be increased.

[0109] Specifically, in this method, the electronic device can generate a first result by detecting the cond[3:1] field and the NZCV flag bits of the condition code, and the first result can be the initial condition code detection result. The electronic device can also generate a second result by performing an exclusive OR operation on the cond[0] field of the condition code and the prediction result of the branch prediction method. Further, when the first result is different from the second result, the electronic device can clear one or more predicted instructions stored in the specified memory.

[0110] Exemplarily, the electronic device can generate a KILL signal to clear one or more predicted instructions stored in the specified memory.

[0111] Exemplarily, when the electronic device detects that the cond[3:1] field of the condition code is '000' and the Z flag bit is 1, the first result is 1. If the cond[0] of the condition code is 0 and the prediction result is 1, the second result is 1. Therefore, the first result is the same as the second result, and the exclusive OR operation of the first result and the second result is 0, then the electronic device does not generate a KILL signal.

[0112] Exemplarily, when the electronic device detects that the cond[3:1] field of the condition code is '000' and the Z flag bit is 1, the first result is 1. If the cond[0] of the condition code is 1 and the prediction result is 1, the second result is 0. Therefore, the first result is different from the second result, and the exclusive OR operation of the first result and the second result is 1, then the electronic device generates a KILL signal.

[0113] Exemplarily, when the electronic device detects that the cond[3:1] field of the condition code is '000' and the Z flag bit is 1, the first result is 1. If the cond[0] of the condition code is 0 and the prediction result is 0, the second result is 0. Therefore, the first result is different from the second result, and the exclusive OR operation of the first result and the second result is 1, then the electronic device generates a KILL signal.

[0114] Exemplarily, when the electronic device detects that the cond[3:1] field of the condition code is '000' and the Z flag bit is 1, the first result is 1. If the cond[0] of the condition code is 1 and the prediction result is 0, the second result is 1. Therefore, the first result is the same as the second result, and the exclusive OR operation of the first result and the second result is 0, then the electronic device does not generate a KILL signal.

[0115] In summary, the adjusted circuit removes the 2-to-1 multiplexer, and the logic level of the adjusted circuit is 2 levels. Among them, the logic of performing the exclusive OR operation between cond[0] and the prediction result involves an exclusive OR gate, which is 1 level. The logic of performing the exclusive OR operation between the second result and cond[3:1] involves an exclusive OR gate, which is 1 level. Therefore, the logic level of the adjusted circuit is 2 levels.

[0116] In this way, the electronic device can use a more efficient operation logic to accelerate the operation efficiency of the circuit, thereby improving the efficiency of the processor in executing conditional branch instructions.

[0117] The data processing mentioned in the embodiments of the present application will be introduced in detail below. As Figure 4 shown, a schematic flowchart of a data processing is shown, and the specific process may include:

[0118] S401: Obtain the prediction result of the conditional branch instruction, and store the instruction to be executed corresponding to the prediction result in the first memory space.

[0119] In an implementable manner, the electronic device can obtain the prediction result of the conditional branch instruction. As described above, the prediction result is obtained by branch prediction. That is, the electronic device can predict the execution result of the conditional branch instruction according to preset data (for example, the historical record data of the next instruction executed by the processor after executing the conditional branch instruction), and the next instruction that the processor may execute after executing the conditional branch instruction, that is, the instruction to be executed corresponding to the prediction result.

[0120] It can be understood that, as described above, the prediction result can be 1 or 0, and the instruction to be executed corresponding to the prediction result can be one instruction or multiple instructions. There is no limitation here.

[0121] It can be understood that when the electronic device stores the instruction to be executed corresponding to the prediction result in the first memory space, on the premise that the prediction result is correct, the running speed of the electronic device to obtain the instruction to be executed from the first memory space is less than the running speed of the electronic device to obtain the instruction to be executed from other memory spaces. Therefore, the electronic device obtaining the instruction to be executed from the first memory space can improve the running efficiency of the processor.

[0122] S402: Obtain the execution result information of the conditional branch instruction and the execution result status flag.

[0123] In an implementable manner, the electronic device can obtain the execution result information of the conditional branch instruction and the execution result status flag. Among them, the execution result information of the conditional branch instruction can be represented by a condition code, and the execution result status flag can be represented by an NZCV flag bit. The detailed information of the condition code and the NZCV flag bit is in the basic concepts and technical terms described above, and will not be elaborated here.

[0124] S403: Obtain a first result based on the first field in the execution result information and the value of the first flag bit in the execution result status flag.

[0125] In an implementable manner, the electronic device may obtain a first result based on the first field in the execution result information and the value of the first flag bit in the execution result status flag. Specifically, the execution result information may be represented by a condition code, and the first field in the execution result information is the upper three bits of the condition code, that is, cond[1:3]. For example, for the condition code '0000', cond[1:3] is '000'. For the condition code '0010', cond[1:3] is '001'.

[0126] Exemplarily, the first flag bit in the execution result status flag may be an N flag bit, a Z flag bit, a C flag bit, or a V flag bit. The value of the flag bit may be 1 or 0. It can be understood that, as described above, different values of different flag bits represent different execution results of the processor. For example, when the value of the Z flag bit is 1, it indicates that the execution result of the processor is zero. The details of the first field in the execution result information and the execution result status flag are in the basic concepts and technical terms described above, and will not be elaborated here.

[0127] It can be understood that the first result may be the initial condition code detection result as described above. Based on this, the electronic device may obtain a first result based on the first field in the execution result information and the value of the first flag bit in the execution result status flag.

[0128] Exemplarily, the cond[3:1] field of the condition code that the electronic device may obtain is '001'. Then, the electronic device may detect the status of the C flag bit of the processor. When the status of the C flag bit is 1, the electronic device may use 1 as the first result.

[0129] Exemplarily, the cond[3:1] field of the condition code that the electronic device may obtain is '010'. Then, the electronic device may detect the status of the N flag bit of the processor. When the status of the N flag bit is 1, the electronic device may use 1 as the first result.

[0130] It can be understood that according to the condition code detection process described above, the electronic device may also detect other forms of the cond[3:1] field and the NZCV flag bits, which will not be elaborated here.

[0131] S404: Perform an exclusive OR operation on the second field in the execution result information and the prediction result of the conditional branch instruction to obtain a second result.

[0132] In an implementable manner, the electronic device may perform an exclusive OR operation on the second field in the obtained execution result information and the prediction result of the conditional branch instruction to obtain a second result. Specifically, the second field in the execution result information may be the least significant bit of the condition code, that is, cond[0], and cond[0] may be 1 or 0. As described in S401 above, the prediction result may be 1 or 0.

[0133] Exemplarily, during the process of performing an exclusive OR operation on the cond[0] field of the condition code and the prediction result, when the cond[0] field obtained by the electronic device is 1 and the prediction result is 1, the electronic device may use 0 as the second result.

[0134] Exemplarily, during the process of performing an exclusive OR operation on the cond[0] field of the condition code and the prediction result, when the cond[0] field obtained by the electronic device is 1 and the prediction result is 0, the electronic device may use 1 as the second result.

[0135] Exemplarily, during the process of performing an exclusive OR operation on the cond[0] field of the condition code and the prediction result, when the cond[0] field obtained by the electronic device is 0 and the prediction result is 1, the electronic device may use 1 as the second result.

[0136] Exemplarily, during the process of performing an exclusive OR operation on the cond[0] field of the condition code and the prediction result, when the cond[0] field obtained by the electronic device is 0 and the prediction result is 0, the electronic device may use 0 as the second result.

[0137] S405: When the first result and the second result are the same, read the instruction to be executed from the first memory space and execute the instruction to be executed.

[0138] In an implementable manner, when the first result and the second result are the same, it indicates that the prediction result is the same as the actual detection result of the condition code. The electronic device may read the instruction to be executed from the first memory space and execute the instruction to be executed.

[0139] Exemplarily, if both the first result and the second result are 1, the electronic device may determine that the prediction result is correct. Further, the electronic device may read the instruction to be executed from the first memory space and execute the instruction to be executed.

[0140] Other cases where the first result and the second result are the same can be deduced by analogy and will not be described here.

[0141] S406: When the first result and the second result are different, clear the instruction to be executed in the first memory space.

[0142] In an implementable manner, when the first result is different from the second result, the electronic device may generate an electrical signal (such as a KILL signal), which can clear the instructions to be executed in the first memory space and obtain the correct next instruction for the processor to execute from the memory of the electronic device.

[0143] Exemplarily, if the first result is 0 and the second result is 1, the electronic device may determine that the prediction result is incorrect, that is, the prediction result is different from the actual detection result. Furthermore, the electronic device may generate a KILL signal to clear the instructions to be executed in the first memory space and obtain the correct next instruction for the processor to execute from the memory of the electronic device.

[0144] Other cases where the first result and the second result are different can be deduced by analogy and will not be described here.

[0145] The following combines Figure 5 to introduce the data processing mentioned in the embodiments of the present application. As Figure 5 shown, a circuit schematic diagram after data processing is shown.

[0146] It can be understood that Figure 5 the circuit in

[0147] can detect the cond[3:1] field of the condition code and the NZCV flag bit to obtain the first result. The electronic device can also perform an exclusive OR operation on cond[0] and the predict value (the prediction result of branch prediction) to obtain the second result. Then, the electronic device performs an exclusive OR operation on the first result and the second result. When the result of the exclusive OR operation is 1, the electronic device generates a KILL signal. Figure 5 It can be understood that for Figure 3 the circuit in

[0148] Specifically, Figure 5 the circuit in Figure 3The logical level of the circuit in [it] is at least 3.5 levels. As mentioned above, obtaining the logic of NOT cond[3:1] involves an inverter, which is 1 level. The logic for the electronic device to select between cond[3:1] and NOT cond[3:1] using cond[0] through a 2-to-1 multiplexer involves a 2-to-1 multiplexer and is at least 1.5 levels. The logic for performing an exclusive-OR operation on the selection result of the 2-to-1 multiplexer and the prediction result involves an exclusive-OR gate and is 1 level. Therefore, Figure 3 the logical level of the circuit is at least 3.5 levels. However, Figure 5 the logical level of the circuit in [it] is 2 levels. Among them, the logic for performing an exclusive-OR operation on cond[0] and the prediction result involves an exclusive-OR gate and is 1 level. The logic for performing an exclusive-OR operation on the second result and cond[3:1] involves an exclusive-OR gate and is 1 level. Therefore, Figure 5 the logical level of the circuit in [it] is less than Figure 3 the logical level of the circuit in [it].

[0149] Therefore, compared with Figure 3 the original circuit in [it], after the above data processing (Optimized), during the process of the processor processing conditional branch instructions, when the electronic device runs Figure 5 the circuit will reduce the circuit operation time and improve the efficiency of the processor executing instructions.

[0150] Through the above method, the efficiency of the processor in processing conditional branch instructions can be improved, which is beneficial to improving the running speed of the electronic device.

[0151] An embodiment of the present application also provides a readable storage medium, in which instructions are stored. When the instructions are executed by a device, the device implements the data processing method provided in the foregoing embodiments.

[0152] An embodiment of the present application also provides a computer program product. When the computer program product is executed on a device, the device can implement the data processing method provided in the foregoing embodiments.

[0153] An embodiment of the present application also provides an electronic device, which includes: a memory for storing instructions executed by one or more processors of the electronic device, and a processor, which is one of the one or more processors of the electronic device, for implementing the code detection method provided in the foregoing embodiments.

[0154] To better understand the technical solution of the embodiments of the present application, the following introduces the hardware structure of the electronic device involved in the present application with reference to the drawings.

[0155] Exemplarily, Figure 6 According to the embodiments of the present application, a schematic structural diagram of an electronic device 10 is shown.

[0156] Figure 6 Shown is a schematic structural diagram of an electronic device 10 according to an embodiment of the present application. Figure 6 Schematically shown are example electronic devices 10 according to multiple embodiments. In one embodiment, the electronic device 10 may include one or more processors 1604, system control logic 1608 connected to at least one of the processors 1604, system memory 1612 connected to the system control logic 1608, non-volatile memory (NVM) 1616 connected to the system control logic 1608, and a network interface 1620 connected to the system control logic 1608.

[0157] In some embodiments, the processor 1604 may include one or more single-core or multi-core processors. In some embodiments, the processor 1604 may include any combination of a general-purpose processor and a dedicated processor (e.g., a graphics processor, an application processor, a baseband processor, etc.). In embodiments where the electronic device 10 employs an evolved node b (eNB) or a radio access network (RAN) controller, the processor 1604 may be configured to execute various conforming embodiments, e.g., one or more of the multiple embodiments Figures 2 to 5 as shown.

[0158] In some embodiments, the system control logic 1608 may include any suitable interface controller to provide any suitable interface to at least one of the processors 1604 and / or any suitable device or component communicating with the system control logic 1608.

[0159] In some embodiments, the system control logic 1608 may include one or more memory controllers to provide an interface to the system memory 1612. The system memory 1612 may be used to load and store data and / or instructions. In some embodiments, the memory 1612 of the system 1600 may include any suitable volatile memory, such as a suitable dynamic random access memory (DRAM).

[0160] NVM 1616 may include one or more tangible, non-transitory computer-readable media for storing data and / or instructions. In some embodiments, NVM 1616 may include any suitable non-volatile memory such as flash memory and / or any suitable non-volatile storage device, such as at least one of a hard disk drive (HDD), a compact disc (CD) drive, and a digital versatile disc (DVD) drive.

[0161] NVM 1616 may include a portion of the storage resources on the device in which the electronic device 10 is installed, or it may be accessible by the device but not necessarily part of the device. For example, NVM 1616 may be accessed via the network interface 1620 over a network.

[0162] In particular, the system memory 1612 and NVM 1616 may respectively include: a temporary copy and a permanent copy of the instructions 1624. The instructions 1624 may include: instructions that, when executed by at least one of the processors 1604, cause the electronic device 10 to implement the method as Figure 5 shown. In some embodiments, the instructions 1624, hardware, firmware, and / or its software components may additionally / alternatively be disposed in the system control logic 1608, the network interface 1620, and / or the processor 1604.

[0163] The network interface 1620 may include a transceiver for providing a radio interface for the electronic device 10, and thus communicating with any other suitable device (such as a front-end module, an antenna, etc.) over one or more networks. In some embodiments, the network interface 1620 may be integrated with other components of the electronic device 10. For example, the network interface 1620 may be integrated with at least one of the processor 1604, the system memory 1612, the NVM 1616, and a firmware device (not shown) having instructions, and when at least one of the processors 1604 executes the instructions, the electronic device 10 implements the method as Figures 2 to 5 shown.

[0164] The network interface 1620 may further include any suitable hardware and / or firmware to provide a multiple-input multiple-output radio interface. For example, the network interface 1620 may be a network adapter, a wireless network adapter, a telephone modem, and / or a wireless modem.

[0165] In one embodiment, at least one of the processors 1604 may be logically packaged with one or more controllers for the system control logic 1608 to form a system in package (SiP). In one embodiment, at least one of the processors 1604 may be integrated with the logic of one or more controllers for the system control logic 1608 on the same die to form a system on chip (SOC).

[0166] The electronic device 10 may further include: an input / output (I / O) device 1632.

[0167] According to an embodiment of the present application, Figure 7 A block diagram of a SOC 1700 is shown. The SOC 1700 is disposed in the electronic device 10. In Figure 7 , similar components have the same reference numerals. In Figure 7 , the SOC 1700 includes: an interconnect unit 1750, which is coupled to the application processor 1710; a system agent unit 1770; a bus controller unit 1780; an integrated memory controller unit 1740; a video processor 1720, the video processor 1720 further includes an entropy encoding module 20; a static random access memory (SRAM) unit 1730; a direct memory access (DMA) unit 1760. In one embodiment, the SOC 1700 may further include, for example, a network or communication processor, a compression engine, a graphic processing unit (GPU), a high throughput microphone (MIC) processor, or an embedded processor, etc.

[0168] Embodiments of the mechanisms disclosed in the present application may be implemented in hardware, software, firmware, or a combination of these implementation methods. Embodiments of the present application may be implemented as a computer program or program code executed on a programmable system, which includes at least one processor, a storage system (including volatile and non-volatile memories and / or storage elements), at least one input device, and at least one output device.

[0169] Program code can be applied to the input instructions to perform the various functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0170] The program code can be implemented in a high-level procedural language or an object-oriented programming language to communicate with the processing system. When needed, the program code can also be implemented in assembly language or machine language. In fact, the mechanisms described in this application are not limited to the scope of any particular programming language. In any case, the language can be a compiled language or an interpreted language.

[0171] In some cases, the disclosed embodiments can be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments can also be implemented as instructions carried or stored on one or more transient or non-transient machine-readable (e.g., computer-readable) storage media, which can be read and executed by one or more processors. For example, the instructions can be distributed via a network or via other computer-readable media. Thus, a machine-readable medium can include any mechanism for storing or transmitting information in a machine (e.g., computer) readable form, including but not limited to, floppy disks, optical disks, optical discs, compact disc read-only memories (CD-ROMs), magneto-optical discs, read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or tangible machine-readable memories for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) in electrical, optical, acoustic, or other forms via the Internet. Thus, a machine-readable medium includes any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine (e.g., computer) readable form.

[0172] In the accompanying drawings, some structural or method features may be shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or order may not be required, but rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Additionally, the inclusion of a structural or method feature in a particular figure does not imply that such a feature is required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0173] It should be noted that each unit / module mentioned in the device embodiments of this application is a logical unit / module. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or can be implemented as a combination of multiple physical units / module. The physical implementation manner of these logical units / modules themselves is not the most important. The combination of the functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. In addition, to highlight the innovative part of this application, the above-mentioned device embodiments of this application do not introduce units / modules that are not closely related to solving the technical problems proposed in this application, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0174] It should be noted that in the examples and descriptions of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one" does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0175] Although this application has been illustrated and described by reference to certain preferred embodiments of the present application, those of ordinary skill in the art should understand that various changes can be made in form and detail without departing from the spirit and scope of the present application.

Claims

1. A data processing method, characterized in that: For use in an electronic device, and the method comprises: Obtaining a prediction result of a conditional branch instruction, and storing the to-be-executed instruction corresponding to the prediction result in a first memory space; Obtaining the execution result information and execution result status identification of the conditional branch instruction; Obtain a first result based on the first field in the execution result information and the value of the first flag bit in the execution result status identifier; Performing an XOR operation on the second field in the execution result information and the predicted result of the conditional branch instruction to obtain a second result; When the first result and the second result are the same, the to-be-executed instruction is read from the first memory space, and the to-be-executed instruction is executed.

2. The method according to claim 1, characterized in that: The method further comprises: When the first result and the second result are different, clear the to-be-executed instructions in the first memory space.

3. The method according to claim 1, characterized in that The execution result information includes a condition code; The first field in the execution result information is the upper three bits of the condition code cond[3:1]; The second field in the execution result information is the lowest bit cond[0] of the condition code; The execution result status flags are a negative number flag, a zero flag, a carry flag, and an overflow flag.

4. The method according to claim 1, characterized in that The obtaining the first result based on the value of the first field in the execution result information and the first flag bit in the execution result status identifier includes: If the first field is 000 and the value corresponding to the flag bit Z is 1, the first result is 1; If the first field is 001 and the value corresponding to the flag bit C is 1, the first result is 1; If the first field is 010 and the value corresponding to the flag bit N is 1, the first result is 1; If the first field is 011 and the value corresponding to the flag bit V is 1, the first result is 1; If the first field is 100, the value corresponding to the flag bit C is 1 and the value corresponding to the flag bit Z is 0, then the first result is 1; If the first field is 101, and the value corresponding to the flag bit N is equal to the value corresponding to the flag bit V, then the first result is 1; If the first field is 110, the value corresponding to the flag bit N is equal to the value corresponding to the flag bit V and the value corresponding to the flag bit Z is 0, then the first result is 1; If the first field is 111, the first result is 1.

5. The method according to claim 1, characterized in that The obtaining of the first result based on the value of the first field in the execution result information and the first flag bit in the execution result status identifier also includes: If the first field is 000 and the value corresponding to the flag bit Z is 0, the first result is 0; If the first field is 001 and the value corresponding to the flag bit C is 0, the first result is 0; If the first field is 010 and the value corresponding to the flag bit N is 0, the first result is 0; If the first field is 011 and the value corresponding to the flag bit V is 0, the first result is 0; If the first field is 100, the value corresponding to the flag bit C is 0 and / or the value corresponding to the flag bit Z is 1, then the first result is 0; If the first field is 101, and the value corresponding to the flag bit N is not equal to the value corresponding to the flag bit V, then the first result is 0; If the first field is 110, the value corresponding to the flag bit N is not equal to the value corresponding to the flag bit V and / or the value corresponding to the flag bit Z is 1, then the first result is 0.

6. The method according to claim 1, characterized in that The performing an XOR operation on the second field in the execution result information and the predicted result of the conditional branch instruction to obtain the second result includes: If the second field is 0, the predicted result of the conditional branch instruction is 0, and the second result is 0; If the second field is 0, the predicted result of the conditional branch instruction is 1, and the second result is 1; If the second field is 1, the predicted result of the conditional branch instruction is 0, and the second result is 1; If the second field is 1, the predicted result of the conditional branch instruction is 1, and the second result is 0.

7. The method according to claims 1 and 2, characterized in that When the first result and the second result are different, clearing the to-be-executed instructions in the first memory space includes: When the first result and the second result are different, the electronic device generates an electrical signal, wherein the electrical signal may indicate deletion of all pending instructions in the first memory space.

8. A readable storage medium, characterized in that: The readable storage medium stores instructions, which, when executed on an electronic device, enable the electronic device to execute the method according to any one of claims 1 to 7.

9. An electronic device, characterized in that: include: a memory for storing instructions to be executed by one or more processors of the electronic device, and The processor is one of the processors of an electronic device, and is used to execute the method according to any one of claims 1 to 7.

10. A program product, characterized in that The program product includes instructions, and when the instructions are executed on an electronic device, the electronic device implements the method according to any one of claims 1 to 7.

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