Memory controller and memory system

Abstract

The invention discloses a memory controller and a memory system. A memory controller for controlling a memory module including a data chip and a parity chip includes an error correction code (ECC) engine. The ECC engine includes an ECC decoder to perform a first ECC decoding to correct symbol errors in the read codeword set, and perform a second ECC decoding in parallel with performing the first ECC decoding to correct multi-bit errors in the read codeword set and detect three-bit errors in the read codeword set. The ECC decoder generates a syndrome comprising a first sub-syndrome, a second sub-syndrome, and a third sub-syndrome, corrects the symbol error, corrects the multi-bit error, and detects the three-bit error.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0170324, filed with the Korean Intellectual Property Office on November 30, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure generally relates to memories, and more particularly, to memory controllers and memory systems. Background Art

[0003] Memory devices may be implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc. Memory devices are generally classified into volatile memory devices and non-volatile memory devices.

[0004] A volatile memory device is a memory device in which data stored is lost when power is turned off. On the other hand, a non-volatile memory device is a memory device in which data stored is retained when power is turned off. Since dynamic random access memory (DRAM), which is a type of volatile memory device, has a high access speed, DRAM is widely used as a working memory, a buffer memory, a main memory, etc. of a computing system. In addition, in order to provide a relatively large storage capacity, a plurality of volatile memory devices may be provided in the form of a memory module. Therefore, research is being conducted to efficiently correct errors occurring in the memory module. Summary of the Invention

[0005] Generally, in some aspects, the present disclosure relates to a memory controller capable of efficiently correcting errors occurring in a memory module.

[0006] Generally, according to some aspects of the present disclosure, a memory controller for controlling a memory module including a plurality of data chips and at least one parity chip includes: an error correction code (ECC) engine; and a processor for controlling the ECC engine. The ECC engine includes: an ECC decoder for performing first ECC decoding by using a first sub-check matrix and a second sub-check matrix of a parity check matrix to correct symbol errors in a read codeword set read from the memory module, and performing second ECC decoding in parallel with the first ECC decoding by using the second sub-check matrix and a third sub-check matrix of the parity check matrix to correct multiple-bit errors in the read codeword set and detect three-bit errors in the read codeword set. The ECC decoder generates a syndrome including a first sub-syndrome, a second sub-syndrome, and a third sub-syndrome based on the parity check matrix and the read codeword set, corrects the symbol errors based on a comparison between the first sub-syndrome and the second sub-syndrome, and corrects the multiple-bit errors and detects the three-bit errors based on a sum value obtained by summing the syndrome values of the first sub-syndrome.

[0007] According to some aspects of the present disclosure, a memory system includes: a memory module and a memory controller. The memory module includes a plurality of data chips and at least one parity chip. The memory controller controls the memory module and includes an error correction code (ECC) engine and a processor for controlling the ECC engine. The ECC engine includes: an ECC decoder for correcting symbol errors in a read codeword set read from the memory module by using a first sub-check matrix and a second sub-check matrix of a parity check matrix, and for performing a second ECC decoding in parallel with the first ECC decoding by using the second sub-check matrix and a third sub-check matrix of the parity check matrix to correct multiple-bit errors in the read codeword set and to detect three-bit errors in the read codeword set. The ECC decoder generates a syndrome including a first sub-syndrome, a second sub-syndrome, and a third sub-syndrome based on the parity check matrix and the read codeword set, corrects the symbol errors based on a comparison between the first sub-syndrome and the second sub-syndrome, and corrects the multiple-bit errors and detects the three-bit errors based on a sum value obtained by summing the syndrome values of the first sub-syndrome.

[0008] According to some aspects of the present disclosure, a memory controller for controlling a memory module including a plurality of data chips and at least one parity chip by communicating with one or more hosts via a Compute Express Link (CXL) interface includes: an error correction code (ECC) engine; and a processor for controlling the ECC engine. The ECC engine includes: an ECC decoder for performing a first ECC decoding by using a first sub-check matrix and a second sub-check matrix of a parity check matrix to correct symbol errors in a read codeword set read from the memory module, and for performing a second ECC decoding in parallel with the first ECC decoding by using the second sub-check matrix and a third sub-check matrix of the parity check matrix to correct multiple-bit errors in the read codeword set and to detect three-bit errors in the read codeword set. The ECC decoder generates a syndrome including a first sub-syndrome, a second sub-syndrome, and a third sub-syndrome based on the parity check matrix and the read codeword set, corrects symbol errors based on a comparison between the first sub-syndrome and the second sub-syndrome, and corrects the multiple-bit errors and detects the three-bit errors based on a sum value obtained by summing the syndrome values of the first sub-syndrome. The first ECC decoding corresponds to Reed-Solomon decoding. The second ECC decoding corresponds to Bose-Chaudhuri-Hocquenghem decoding.

[0009] According to some aspects of the present disclosure, an ECC decoder in a memory controller may perform first ECC decoding and second ECC decoding in parallel, and may share a part of a parity check matrix when performing the first ECC decoding and the second ECC decoding. The first ECC decoding is used to correct symbol errors in a codeword set read from a memory module, and the second ECC decoding is used to correct multiple-bit errors in the codeword set. Accordingly, the ECC engine may reduce the complexity and decoding latency of the ECC. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating an example of a memory system according to some embodiments.

[0012] Figure 2 is a block diagram illustrating a memory controller in a Figure 1 memory system according to some embodiments.

[0013] Figure 3 illustrates an example of a data set corresponding to multiple burst lengths in a Figure 1 memory system according to some embodiments.

[0014] Figure 4 is a block diagram illustrating an example of Figure 1 one of data chips in a memory module according to some embodiments.

[0015] Figure 5 illustrates an example of Figure 4 a first bank array in a data chip according to some embodiments.

[0016] Figure 6 is a block diagram illustrating an example of a Figure 2 system ECC engine in according to some embodiments.

[0017] Figure 7 illustrates an example of an Figure 6 ECC encoder in an ECC engine according to some embodiments.

[0018] Figure 8A illustrates an example of a parity check matrix stored in a Figure 6 memory in an ECC engine according to some embodiments.

[0019] Figure 8B illustrates an example of Figure 8A one unit sub-matrix and one zero sub-matrix among multiple unit sub-matrices and multiple zero sub-matrices in a first sub parity check matrix in according to some embodiments.

[0020] Figure 9A Shows an example of the vector representation of the read codeword set according to some embodiments. Figure 6 in.

[0021] Figure 9B Shows an example of the vector representation of the syndrome according to some embodiments.

[0022] Figure 10 Shows the parity generation matrix stored in the memory of the ECC engine according to some embodiments Figure 6 in.

[0023] Figure 11 Is a block diagram showing an example of the ECC decoder in the ECC engine according to some embodiments Figure 6 of.

[0024] Figure 12 Is a block diagram showing an example of the buffer circuit in the ECC decoder according to some embodiments Figure 11 of.

[0025] Figure 13 Is a block diagram showing an example of the symbol error correction circuit in the ECC decoder according to some embodiments Figure 11 of.

[0026] Figure 14 Shows an example operation of the symbol error correction circuit according to some embodiments Figure 13 of.

[0027] Figure 15 Is a block diagram showing an example of the random error correction circuit in the ECC decoder according to some embodiments Figure 11 of.

[0028] Figure 16 Shows an example operation of the random error correction circuit according to some embodiments Figure 15 of.

[0029] Figure 17 Is a table showing an example of a decision circuit configured to determine an error based on a decision signal according to some embodiments.

[0030] Figure 18 Is a flowchart showing an example of the operation of an ECC decoder according to some embodiments.

[0031] Figure 19 Is a flowchart showing an example of an operation of correcting symbol errors and random bit errors in parallel according to some embodiments.

[0032] Figures 20 to 22Shows an example of errors correctable by an ECC decoder according to some embodiments.

[0033] Figure 23 Is a block diagram showing an example of a memory module that can be adopted by a memory system according to some embodiments.

[0034] Figure 24 Is a block diagram showing an example of a memory system having a four-column memory module according to some embodiments.

[0035] Figure 25 Is a block diagram showing an example of a mobile system including a memory module according to some embodiments.

[0036] Figure 26 Is a block diagram showing an example of a computing system according to some embodiments.

[0037] Figure 27 Is a block diagram showing an example of Figure 26 One of multiple hosts in a computing system according to some embodiments.

[0038] Figure 28 Shows an example of a multi-protocol for communication in a computing system according to some embodiments for Figure 26

[0039] Figure 29 Is an example of a computing system when a memory system according to an example embodiment corresponds to a type 3 memory system defined by the CXL protocol according to some embodiments.

[0040] Figure 30 Is a block diagram showing a data center including a computing system according to some embodiments. Detailed Description of Embodiments

[0041] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0042] Figure 1 Is a block diagram showing an example of a memory system according to some embodiments. In Figure 1 the memory system 20 may include a memory controller 100 and a memory module MM. The memory module MM may include a plurality of semiconductor memory devices 200a to 200p and 200s. Here, p may be a natural number equal to or greater than four, and may be sixteen. Hereinafter, the plurality of semiconductor memory devices 200a to 200p and 200s may be referred to as a plurality of memory chips. The plurality of memory chips 200a to 200p and 200s may include a plurality of data chips 200a to 200p and at least one parity chip 200s.

[0043] The memory controller 100 may control the overall operation of the memory system 20. The memory controller 100 may control the overall data exchange between the host and the multiple memory chips 200a to 200p and 200s. For example, in response to a request from the host, the memory controller 100 may write data into or read data from the multiple memory chips 200a to 200p and 200s. In addition, the memory controller 100 may issue operation commands to the multiple memory chips 200a to 200p and 200s to control the multiple memory chips 200a to 200p and 200s.

[0044] In some embodiments, each of the multiple memory chips 200a to 200p and 200s includes volatile memory cells (such as dynamic random access memory (DRAM)). In some embodiments, the number of data chips 200a to 200p may be 8. However, the number of data chips 200a to 200p is not limited thereto. In some embodiments, each of the data chips 200a to 200p may be referred to as a data memory, and at least one parity chip 200s may be referred to as an error correction code (ECC) memory or a redundant memory.

[0045] The memory controller 100 may send an address ADDR and a command CMD to the memory module MM, and may exchange a codeword set SCW with the memory module MM. The memory controller 100 may include a processor 110 and an error correction code (ECC) engine 400. The processor 110 may control the overall operation of the memory controller 100 and may control the ECC engine 400. The ECC engine 400 may perform ECC encoding on a user data set to generate parity data, and may provide a codeword set SCW including the user data set and the parity data to the memory module MM in a write operation of the memory system 20. The user data set may be stored in the data chips 200a to 200p, and the parity data may be stored in at least one parity chip 200s.

[0046] The ECC engine 400 may receive the codeword set SCW from the memory module MM in a read operation. The ECC engine 400 may include an ECC decoder (refer to 430 in Figure 2 ). The ECC decoder 430 may perform first ECC decoding by using a first sub-check matrix and a second sub-check matrix of a parity check matrix to correct symbol errors in the read codeword set SCW, and may perform second ECC decoding by using the second sub-check matrix and a third sub-check matrix of the parity check matrix in parallel with the first ECC decoding to correct multiple-bit errors in the read codeword set SCW and detect three-bit errors in the read codeword set SCW.

[0047] The ECC decoder 430 may generate a syndrome including a first sub-syndrome, a second sub-syndrome, and a third sub-syndrome based on a parity-check matrix and a read codeword set SCW, may correct symbol errors based on a comparison between the first sub-syndrome and the second sub-syndrome, and may correct multiple-bit errors and detect three-bit errors based on a sum value obtained by summing the syndrome values of the first sub-syndrome.

[0048] Accordingly, the ECC engine 400 may quickly correct symbol errors and multiple-bit errors by performing first ECC decoding and second ECC decoding in parallel, and may reduce the ECC decoding latency.

[0049] Figure 2 is a block diagram showing an example of a memory controller in a Figure 1 memory system according to some embodiments. In Figure 2 this, the memory controller 100 may include a processor 110, a host interface 120, a data register 125, an ECC engine 400, a command buffer 190, and an address buffer 195. The ECC engine 400 may include an ECC encoder 410, an ECC decoder 430, and a memory 405.

[0050] The host interface 120 may receive a request REQ and a user data set SDQ from a host, and may provide the user data set SDQ to the data register 125. The data register 125 may provide the user data set SDQ to the ECC engine 400.

[0051] The ECC encoder 410 may perform ECC encoding on the user data set SDQ using a parity-check generation matrix to generate parity-check data, and may output a codeword set SCW1 including the user data set SDQ and the parity-check data.

[0052] The ECC decoder 430 may receive a codeword set SCW2 from a memory module MM, may correct symbol errors in the codeword set SCW2, may correct multiple-bit errors in the codeword set SCW2, and may detect three-bit errors in the codeword set SCW2. The ECC decoder 430 may perform first ECC decoding to correct symbol errors in the codeword set SCW2 by using a first sub parity-check matrix and a second sub parity-check matrix of the parity-check matrix, and may perform second ECC decoding in parallel with the first ECC decoding to correct multiple-bit errors in the codeword set SCW2 and detect three-bit errors in the codeword set SCW2 by using the second sub parity-check matrix and a third sub parity-check matrix of the parity-check matrix.

[0053] The ECC decoder 430 may generate a decision signal DS indicating the results of the first ECC decoding and the second ECC decoding, and may provide the decision signal DS to the processor 110.

[0054] The result of the first ECC decoding may indicate whether a symbol error is corrected, and the result of the second ECC decoding may indicate at least one of whether a multi-bit error is corrected, whether a three-bit error is detected, and whether a single-bit error is detected.

[0055] The ECC decoder 430 may provide one of the user data set SDQ and the corrected user data set C_SDQ to the processor 110 by performing the first ECC decoding and the second ECC decoding.

[0056] The processor 110 may receive the user data set SDQ or the corrected user data set C_SDQ, and may control the ECC engine 400, the command buffer 190, and the address buffer 195. The command buffer 190 may store a command CMD corresponding to the request REQ, and may send the command CMD to the memory module MM under the control of the processor 110. The address buffer 195 may store an address ADDR, and may send the address ADDR to the memory module MM under the control of the processor 110.

[0057] Figure 3 Illustrates an example of data sets corresponding to multiple burst lengths in Figure 1 the memory system according to some embodiments. In Figure 3 each of the data chips 200a to 200p and the parity chip 200s may perform a burst operation. Here, a burst operation refers to an operation of writing or reading a large amount of data by sequentially increasing or decreasing an initial address provided from the memory controller 100. A basic unit of the burst operation may be referred to as a burst length BL.

[0058] Each of the data sets DQ_BL1 to DQ_BLp corresponding to multiple burst lengths is input to / output from a corresponding one of the data chips 200a to 200p.

[0059] Each of the data sets DQ_BL1 to DQ_BLp may include data segments DQ_BL_SG1 to DQ_BL_SG4 corresponding to each of the multiple burst lengths. The data sets DQ_BL1 to DQ_BLp may correspond to the user data set SDQ. Each of the data segments DQ_BL_SG1 to DQ_BL_SG4 may include data bits DQ1 to DQ8.

[0060] In Figure 3In this case, it is assumed that the burst length is 8, and it is assumed that the burst operation is performed four times. When a burst operation is performed once in each of the data chips 200a to 200p, data bits DQ1 to DQ8 are input to / output from each of the data chips 200a to 200p, and parity data PRTS corresponding to a plurality of burst lengths is input to / output from the parity chip 200s.

[0061] Figure 4 is a block diagram showing an example of one of the data chips in a Figure 1 memory module according to some embodiments. In Figure 4 it is assumed that Figure 1 each of the data chips 200a to 200p in

[0062] employs a volatile memory device. Figure 4 Referring to

[0063]

[0064] the data chip 200a may include control logic circuit 210, address register 220, bank control logic 230, row address multiplexer (RAMUX) 240, column address (CA) latch 250, row decoder 260, column decoder 270, memory cell array 310, sense amplifier unit 285, input / output (I / O) gating circuit 290, on-die ECC engine 320, data input / output (I / O) buffer 295, and refresh counter 245. The memory cell array 310 may include first bank arrays 310a to eighth bank arrays 310h.

[0065] Although the data chip 200a is shown in Figure 4 as including eight banks, the data chip 200a may include any number of banks.

[0066] The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100. The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230, may provide the received row address ROW_ADDR to the row address multiplexer 240, and may provide the received column address COL_ADDR to the column address latch 250.

[0067] The bank control logic 230 may generate bank control signals in response to the bank address BANK_ADDR. One of the first row decoders 260a to eighth row decoders 260h corresponding to the bank address BANK_ADDR may be activated in response to the bank control signals, and one of the first column decoders 270a to eighth column decoders 270h corresponding to the bank address BANK_ADDR may be activated in response to the bank control signals.

[0068] The row address multiplexer 240 may receive the row address ROW_ADDR from the address register 220, and may receive a refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to the first row decoders 260a to eighth row decoders 260h.

[0069] The activated row decoder among the first row decoders 260a to eighth row decoders 260h may decode the row address RA output from the row address multiplexer 240, and may activate the word line WL corresponding to the row address RA. For example, the activated row decoder may generate a word line driving voltage, and may apply the word line driving voltage to the word line WL corresponding to the row address RA.

[0070] The column address latch 250 may receive the column address COL_ADDR from the address register 220, and may temporarily store the received column address COL_ADDR. In an exemplary embodiment of the inventive concept, in burst mode, the column address latch 250 may generate a column address COL_ADDR' incremented from the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored or generated column address COL_ADDR' to the first column decoders 270a to eighth column decoders 270h.

[0071] The activated column decoders among the first column decoder 270a to the eighth column decoder 270h can decode the column address COL_ADDR output from the column address latch 250, and can control the I / O gating circuit 290 to output data corresponding to the column address COL_ADDR.

[0072] The I / O gating circuit 290 can include a circuit for gating input / output data. The I / O gating circuit 290 can also include a read data latch for storing data output from the first bank array 310a to the eighth bank array 310h, and a write driver for writing data into the first bank array 310a to the eighth bank array 310h.

[0073] The codeword read from one of the first bank array 310a to the eighth bank array 310h can be sensed by a sense amplifier coupled to the one bank array from which data is to be read, and can be stored in the read data latch.

[0074] The codeword stored in the read data latch can be provided to the on-die ECC engine 320. The on-die ECC engine 320 can generate a data set by performing ECC decoding on the codeword, and can provide the data set to the data I / O buffer 295. The data I / O buffer 295 can provide the data set DQ_BL1 to the memory controller 100.

[0075] The data set DQ_BL1 to be written into one of the first bank array 310a to the eighth bank array 310h can be provided from the memory controller 100 to the data I / O buffer 295. The data I / O buffer 295 can provide the data set to the on-die ECC engine 320. The on-die ECC engine 320 can generate parity bits based on the data set, and can provide a codeword including the data set and the parity bits to the I / O gating circuit 290. The I / O gating circuit 290 can store the codeword in a sub-page of one bank array.

[0076] In a write operation, the on-die ECC engine 320 can generate parity bits by performing ECC encoding on the data set DQ_BL1 from the data I / O buffer 295, and can store a codeword including the data set DQ_BL1 and the parity bits in a target page of the memory cell array 310.

[0077] In some embodiments, the on-die ECC engine 320 may not be included in the data chip 200a.

[0078] In some embodiments, the on-die ECC engine 320 can correct symbol errors and multiple-bit errors in parallel, similar to the ECC engine 400 in the memory controller 100.

[0079] The control logic circuit 210 can control the operation of the data die 200a. For example, the control logic circuit 210 can generate control signals for the data die 200a to perform write operations or read operations. The control logic circuit 210 can include a command decoder 211 that decodes a command CMD received from the memory controller 100 and a mode register 212 that sets the operation mode of the data die 200a.

[0080] For example, the command decoder 211 can generate control signals corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc.

[0081] The control logic circuit 210 can generate a first control signal CTL1 for controlling the I / O gating circuit 290 and a second control signal CTL2 for controlling the on-die ECC engine 320 by decoding the command CMD.

[0082] Figure 1 At least one of the parity dies 200s can have substantially the same configuration as the data die 200a.

[0083] Figure 5 Shows an example of a first bank array in a Figure 4 data die according to some embodiments. In Figure 5 it, the first bank array 310a can include a plurality of word lines WL0 to WLm-1 (where m is an even number equal to or greater than two), a plurality of bit lines BTL0 to BTLn-1 (where n is an even number equal to or greater than two), and a plurality of memory cells MC disposed at the intersections between the word lines WL0 to WLm-1 and the bit lines BTL0 to BTLn-1. The word lines WL0 to WLm-1 can extend in a first direction D1, and the bit lines BTL0 to BTLn-1 can extend in a second direction D2.

[0084] Each memory cell MC includes an access (cell) transistor coupled to one of the word lines WL0 to WLm-1 and one of the bit lines BTL0 to BTLn-1 and a storage (cell) capacitor coupled to the cell transistor. That is, each memory cell MC has a DRAM cell structure.

[0085] In addition, the memory cell MC may have different arrangements depending on whether it is coupled to an even-numbered word line (e.g., WL0) or an odd-numbered word line (e.g., WL1). That is, the bit lines coupled to adjacent memory cells may be different depending on whether the word line selected by the access address is an even-numbered word line or an odd-numbered word line.

[0086] Figure 6 is a block diagram showing an example of an Figure 2 ECC engine in. In Figure 6 , the ECC engine 400 may include an ECC encoder 410, an ECC decoder 430, and a memory 405. The memory 405 may be referred to as an ECC memory.

[0087] The memory 405 may be connected to the ECC encoder 410 and the ECC decoder 430, and may store a parity generation matrix PGM and a parity check matrix PCM.

[0088] The ECC encoder 410 may perform ECC encoding on the user data set SDQ by using the parity generation matrix PGM to generate parity data PRTS, and may output a codeword set SCW1 including the user data set SDQ and the parity data PRTS.

[0089] The ECC decoder 430 may perform first ECC decoding by using a first sub parity check matrix and a second sub parity check matrix of the parity check matrix PCM to correct symbol errors in the codeword set SCW2, and may perform second ECC decoding in parallel with the first ECC decoding by using a second sub parity check matrix and a third sub parity check matrix of the parity check matrix PCM to correct multiple-bit errors in the codeword set SCW2 and detect three-bit errors in the codeword set SCW2, and may output the corrected user data set C_SDQ. When the ECC decoder 430 cannot correct symbol errors and multiple-bit errors (or when the codeword set SCW2 does not include errors), the ECC decoder 430 may output the user data set SDQ.

[0090] Figure 7 showing an example of an ECC encoder in an Figure 6 ECC engine according to some embodiments. In Figure 7 , the ECC encoder 410 may include a parity generator 415 and a buffer 420.

[0091] The parity generator 415 may perform ECC encoding on the user data set SDQ by using the parity generation matrix PGM to generate parity data PRTS, and may provide the parity data PRTS to the buffer 420.

[0092] The buffer 420 may temporarily store the user data set SDQ and the parity data PRTS, and may provide the codeword set SCW1 including the user data set SDQ and the parity data PRTS to the memory module MM.

[0093] Figure 8A According to some embodiments, storage in Figure 6 Example of a parity check matrix in a memory in an ECC engine of . Figure 8A An example of the parity check matrix PCM is shown, but the parity check generation matrix PGM may have a similar configuration to the parity check matrix PCM.

[0094] exist Figure 8A In the present invention, the parity check matrix PCM may be generated based on the Reed-Solomon (RS) code and the Bose-Chaudhuri-Hocquenghem (BCH) code and may be used to generate a syndrome. The parity check matrix PCM may include a first sub-check matrix HS 21 , the second sub-check matrix HS 22 And the third sub-check matrix HS 23 .

[0095] exist Figure 8A , for ease of explanation, a plurality of sub-data units SDU1, ..., SDUp read from a plurality of memory chips 200a to 200p and parity data PRTS read from a parity chip 200s are shown, and the sub-data unit SDU1 may include a plurality of symbols SB11, SB12, SB13, and SB14. Each of the plurality of symbols SB11, SB12, SB13, and SB14 may include a predetermined number of data bits. Each of the plurality of sub-data units SDU2, ..., SDUp and the parity data PRTS may include a plurality of symbols corresponding to the symbols SB11, SB12, SB13, and SB14.

[0096] The first sub-check matrix HS 21may include a plurality of unit sub - matrices ISM11, ……, ISM14, ……, ISMp1, ……, ISMp4, ISMs1, ……, ISMs4 and a plurality of zero sub - matrices ZSM11, ……, ZSM14, ……, ZSMp1, ……, ZSMp4, ZSMs1, ……, ZSMs4. The plurality of unit sub - matrices ISM11, ……, ISM14, ……, ISMp1, ……, ISMp4, ISMs1, ……, ISMs4 may correspond to a plurality of symbols in the read codeword set SCW, and the plurality of zero sub - matrices ZSM11, ……, ZSM14, ……, ZSMp1, ……, ZSMp4, ZSMs1, ……, ZSMs4 may respectively correspond to the plurality of unit sub - matrices ISM11, ……, ISM14, ……, ISMp1, ……, ISMp4, ISMs1, ……, ISMs4.

[0097] Each of the plurality of unit sub - matrices ISM11, ……, ISM14, ……, ISMp1, ……, ISMp4, ISMs1, ……, ISMs4 may have the same configuration, and each of the plurality of zero sub - matrices ZSM11, ……, ZSM14, ……, ZSMp1, ……, ZSMp4, ZSMs1, ……, ZSMs4 may have the same configuration. The number of rows in each of the plurality of zero sub - matrices ZSM11, ……, ZSM14, ……, ZSMp1, ……, ZSMp4, ZSMs1, ……, ZSMs4 may correspond to half of the number of rows in each of the plurality of unit sub - matrices ISM11, ……, ISM14, ……, ISMp1, ……, ISMp4, ISMs1, ……, ISMs4.

[0098] The second sub - check matrix HS 22 may include a first alpha matrix α corresponding to the bits of a plurality of symbols in the read codeword set SCW 0 ……α 7 、……、α 24 ……α 31 、……、α 480 ……α 487 、……、α 504 ……α 511 、α 512 ……α 519 、……α 536 ……α 543 ,and the first alpha matrix α 0 ……α 7 、……、α 24 ……α 31 、……、α……α 487 、……、α……α、α……α 519 、……α536 ……α 543 may have exponentially increasing values in sequence.

[0099] The third sub-check matrix HS 23 may include a second alpha matrix α obtained by cubing each of the first alpha matrices α 0 ……α 7 、……、α 24 ……α 31 、……、α 480 ……α 487 、……、α 504 ……α 511 、α 512 ……α 519 、……α 536 ……α 543 in the second alpha matrix α 0 ……α 21 、……、α 72 ……α 93 、……、α 1440 ……α 1461 、……、α 1512 ……α 1533 、α 1536 ……α 1557 、……α 1608 ……α 1629 。

[0100] The alpha matrix α 0 may indicate an identity matrix and may be obtained using a k-th order primitive polynomial. α 2 can be obtained through the involution of α. The elements of the alpha matrix may belong to a Galois field. Here, k may represent the number of elements of each alpha matrix.

[0101] The first sub-check matrix HS 21 and the second sub-check matrix HS 22 can implement the RS code H RS (i.e., can be used to perform RS decoding corresponding to the first ECC decoding), and the second sub-check matrix HS 22 and the third sub-check matrix HS 23 can implement the BCH code H BCH (i.e., can be used to perform BCH decoding corresponding to the second ECC decoding).

[0102] Figure 8B shows according to some embodiments Figure 8AAn example of one unit sub-matrix and one zero sub-matrix among multiple unit sub-matrices in the first sub parity-check matrix in Figure 8B In, the unit sub-matrix ISM11 includes h high-level elements arranged diagonally among h×h elements and the remaining elements with zero values. Here, h represents the number of bits in a symbol, and h can be eight. Additionally, the zero sub-matrix ZSM11 includes h / 2 (rows) × h (columns) elements, and each of the h / 2×h elements has a zero value.

[0103] When the vector representation of the codeword set SCW1 stored in the memory module MM corresponds to CV, Equation 1 is derived.

[0104] [Equation 1] CV = WDV × G,

[0105] where WDV is the vector representation of the user data set SDQ, and G is the vector representation of the parity-check generation matrix PGM.

[0106] When the vector representation of the codeword set SCW2 read from the memory module MM corresponds to R, R may include errors and can be represented by Equation 2.

[0107] [Equation 2] R = WDV × G + E,

[0108] where E corresponds to the vector representation of the error.

[0109] The ECC decoder 430 can perform calculations on the read codeword set SCW2 using the parity-check matrix PCM. When the vector representation of the parity-check matrix PCM corresponds to H, the result of the calculation corresponds to Equation 3.

[0110] [Equation 3] R × H T = WDV × G × H T + E × H T

[0111] The parity-check generation matrix G and the parity-check matrix H are set to satisfy Equation 4.

[0112] [Equation 4] G × H T = 0

[0113] Therefore, Equation 5 is derived.

[0114] [Equation 5] R × H T = E × H T

[0115] The result of Equation 5 may correspond to the vector representation S of the syndrome. The vector representation S of the syndrome can be obtained by multiplying the vector representation of the error with the transpose matrix PCM T of the parity-check matrix PCM.

[0116] Figure 9A showing an example of a vector representation of a read codeword set according to some embodiments Figure 6 In Figure 9A the vector representation R of the read codeword set SCW2 may include a first read symbol to an Nth read symbol r 0 、r 1 、r 2 、r 3 、……、r N-1 . Here, N may represent the number of symbols in the read codeword set SCW2 and may be a natural number equal to or greater than four.

[0117] Figure 9B showing an example of a vector representation of a syndrome according to some embodiments. In Figure 9B the vector representation S of the syndrome may be represented by Equation 6.

[0118] [Equation 6] S = R × H T

[0119] Here, S may correspond to (S 0 , S 1 , S 2 ). T S 0 may be a first sub-syndrome, S 1 may be a second sub-syndrome, S 2 may be a third sub-syndrome.

[0120] Figure 10 showing an example of a parity check generation matrix stored in a memory of an ECC engine in Figure 6 . In Figure 10 the parity check generation matrix PGM may include a first sub-generation matrix HS 11 , a second sub-generation matrix HS 12 and a third sub-generation matrix HS 13 .

[0121] The first sub-generation matrix HS 11may include a plurality of unit sub - matrices ISM11, ISM12, ISM13, ISM14, ……, ISMp1, ISMp2, ISMp3, ISMp4 and a plurality of zero sub - matrices ZSM11, ZSM12, ZSM13, ZSM14, ……, ZSMp1, ZSMp2, ZSMp3, ZSMp4. The plurality of unit sub - matrices ISM11, ……, ISM14, ……, ISMp1……, ISMp4 may correspond to a plurality of symbols in the user data set SDQ to be stored in the memory chips 200a to 200p, and the plurality of zero sub - matrices ZSM11, ZSM12, ZSM13, ZSM14, ……, ZSMp1, ZSMp2, ZSMp3, ZSMp4 may respectively correspond to the plurality of unit sub - matrices ISM11, ISM12, ISM13, ISM14, ……, ISMp1, ISMp2, ISMp3, ISMp4.

[0122] Each of the plurality of unit sub - matrices ISM11, ISM12, ISM13, ISM14, ……, ISMp1, ISMp2, ISMp3, ISMp4 may have the same configuration, and each of the plurality of zero sub - matrices ZSM11, ZSM12, ZSM13, ZSM14, ……, ZSMp1, ZSMp2, ZSMp3, ZSMp4 may have the same configuration.

[0123] The second sub - generation matrix HS 12 may include a first alpha matrix α corresponding to the bits of a plurality of symbols 0 ……α 7 、α 8 ……α 15 、α 16 ……α 23 、α 24 ……α 31 、……、α 480 ……α 487 、α 488 ……α 495 、α 496 ……α 503 、α 504 ……α 511 and the first alpha matrix α 0 ……α 7 、α 8 ……α 15 、α 16 ……α 23 、α 24 ……α 31 、……、α 480 ……α 487 、α 488 ……α 495, α 496 ……α 503 , α 504 ……α 511 may have exponentially increasing values in sequence.

[0124] The third sub-generator matrix HS 13 may include a second alpha matrix α obtained by cubing each of the first alpha matrices α 0 ……α 7 , α 8 ……α 15 , α 16 ……α 23 , α 24 ……α 31 , ……, α 480 ……α 487 , α 488 ……α 495 , α 496 ……α 503 , α 504 ……α 511 in the following. 0 ……α 21 , α 24 ……α 45 , α 48 ……α 69 , α 72 ……α 93 , ……, α 1440 ……α 1461 , α 1464 ……α 1485 , α 1488 ……α 1509 , α 1512 ……α 1533 .

[0125] The parity-check generator matrix PGM can be generated by the generating polynomial of Equation 7.

[0126] [Equation 7] g(x) = (x 8 +1)p(x)p 3 (x)

[0127] In Equation 7, p(x) represents the primitive polynomial, and p 3 (x) represents the minimal polynomial element of the conjugate class with respect to α 3 . Additionally, the alpha matrix can be a primitive element of the Galois field GF 12 .

[0128] In Equation 7, (x 8 +1) may correspond to the first sub-generator matrix HS 11 (in Figure 10) and the first sub-check matrix HS 21 (exist Figure 8A ), p(x) can correspond to the second sub-generator matrix HS 12 (exist Figure 10 ) and the second sub-check matrix HS 22 (exist Figure 8A ), and p 3 (x) can correspond to the third sub-generator matrix HS 13 (exist Figure 10 ) and the third sub-check matrix HS 23 (exist Figure 8A middle).

[0129] Therefore, the ECC decoder 430 can decode the 8 +1)p(x) to correct the symbol error in the read codeword set SCW2, and can be corrected by using p(x)p 3 (x) to correct random multi-bit errors in the read codeword set SCW2.

[0130] Figure 11 is a diagram showing that according to some embodiments Figure 6 A block diagram of an example of an ECC decoder in an ECC engine of FIG. Figure 11 , the ECC decoder 430 may include a syndrome generator 440 , a demultiplexer 445 , a buffer circuit 450 , a symbol error correction circuit 460 , a random error correction circuit 470 , and a decision circuit 480 .

[0131] The syndrome generator 440 can generate the syndrome by reading the codeword set SCW2 and the transposed matrix PCM of the parity check matrix PCM. T The matrix multiplication operation is performed to generate the syndrome SDR, a check signal CKS1 indicating whether each syndrome value of the syndrome SDR is zero may be generated, and the syndrome SDR and the check signal CKS1 may be provided to the demultiplexer 445 .

[0132] The syndrome generator 440 may be based on the read codeword set SCW2 and the first sub-check matrix HS 21 Generate the first sub-syndrome S 0 , based on the read codeword set SCW2 and the second sub-check matrix HS 22 Generate the second sub-syndrome S 1 , and can be based on the read code word set SCW2 and the third sub-check matrix HS 23 Generate the third sub-syndrome S 2 . The first sub-syndrome S 0 , the second sub-syndrome S 1 and the third syndrome S 2 Each of can be represented by a vector having one row and twelve columns.

[0133] The demultiplexer 445 can provide the syndrome SDR to the buffer circuit 450 in response to the check signal CKS1 having a logic low level, and can provide the syndrome SDR to the symbol error correction circuit 460 and the random error correction circuit 470 in response to the check signal CKS1 having a logic high level. The check signal CKS1 having a logic low level can indicate that each of the syndrome values in the syndrome SDR is zero. The check signal CKS1 having a logic high level can indicate that at least one of the syndrome values in the syndrome SDR is non-zero.

[0134] The buffer circuit 450, the symbol error correction circuit 460, and the random error correction circuit 470 can receive the read codeword set SCW2.

[0135] In response to the check signal CKS1 having a logic low level, the buffer circuit 450 can output the user data set SDQ in the read codeword set SCW2 without correcting the user data set SDQ, and can output an error-free signal NE indicating that the read codeword set SCW2 does not include an error.

[0136] The symbol error correction circuit 460 can receive the syndrome SDR, the read codeword set SCW2, and the transposed matrix PCM T ; in response to at least one of the syndrome values in the syndrome SDR having a non-zero value, perform a first ECC decoding on the read codeword set SCW2 by using a first sub-check matrix and a second sub-check matrix of the parity check matrix PCM; can output the corrected user data set C_SDQ1; and can generate a first error flag EF1 indicating whether a symbol error is corrected.

[0137] The random error correction circuit 470 can receive the syndrome SDR, the read codeword set SCW2, and the transposed matrix PCM T ; in response to at least one of the syndrome values in the syndrome SDR having a non-zero value, perform a second ECC decoding on the read codeword set by using a second sub-check matrix and a third sub-check matrix of the parity check matrix; can output the corrected user data set C_SDQ2; and can generate a second error flag EF2, where the second error flag EF2 indicates at least one of whether a multi-bit error is corrected, whether a three-bit error is detected, and whether a single-bit error is detected. The random error correction circuit 470 can perform the second ECC decoding in parallel with the first ECC decoding performed by the symbol error correction circuit 460.

[0138] The decision circuit 480 can receive the first error flag EF1 and the second error flag EF2, can generate a decision signal DS indicating the results of the first ECC decoding and the second ECC decoding based on the logic levels of the first error flag EF1 and the second error flag EF2, and can provide the decision signal DS toFigure 2 the processor 110 in

[0139] When symbol errors and random multi-bit errors are included in the read codeword set SCW2, the ECC decoder 430 can reduce the decoding delay corresponding to the time interval required to correct symbol errors and random multi-bit errors by performing the first ECC decoding and the second ECC decoding that share the second sub-check matrix in parallel.

[0140] Figure 12 is a block diagram showing an example of a buffer circuit in an Figure 11 ECC decoder according to some embodiments. In Figure 12 it, the buffer circuit 450 may include a buffer 451 and a signal generator 453.

[0141] The buffer 451 can temporarily store the read codeword set SCW2 and can output the user data set SDQ in the read codeword set SCW2 in response to the check signal CKS1 having a logic low level.

[0142] The signal generator 453 can receive the syndrome SDR and the check signal CKS1, can generate an error-free signal NE indicating that the read codeword set SCW2 does not include errors in response to the check signal CKS1 having a logic low level, and can output the error-free signal NE.

[0143] Figure 13 is a block diagram showing an example of a symbol error correction circuit in an Figure 11 ECC decoder according to some embodiments. In Figure 13 it, the symbol error correction circuit 460 may include an error size and symbol position estimator (also referred to as, an error size and error symbol position estimator) 461, a symbol error corrector 463, and an error syndrome checker 465.

[0144] The error size and symbol position estimator 461 can receive the read codeword set SCW2 and the syndrome SDR including the first sub-syndrome S 0 , the second sub-syndrome S 1 and the third sub-syndrome S 2 , can estimate the size of the symbol error and the position of the target symbol where the symbol error occurs based on the ratio of the second sub-syndrome S 1 to the first sub-syndrome S 0 , and can provide the target symbol position information i to the symbol error corrector 463.

[0145] In response to the first alpha matrix α 0 ……α 7 、……、α 24 ……α 31 、……、α 480……α 487 、……、α 504 ……α 511 、α 512 ……α 519 、……α 536 ……α 543 There is no target alpha matrix, and the error magnitude and symbol position estimator 461 can output a first error flag EF11 indicating that the first ECC decoding fails. The target alpha matrix matches the ratio of the second syndrome S1 to the first syndrome S0.

[0146] The symbol error corrector 463 can generate a corrected user data set C_SDQ1 by correcting the error of the target symbol among multiple symbols of the read codeword set SCW2 based on the position information i of the target symbol, and can estimate a first error vector based on the position information i of the target symbol and the first syndrome S 0 and can output the estimated first error vector E 1 ' to the syndrome checker 465. That is, the symbol error corrector 463 can output the estimated first error vector E 0 ' to the syndrome checker 465 based on the position information i of the target symbol and the first syndrome S 1 '.

[0147] In response to the first alpha matrix α 0 ……α 7 、……、α 24 ……α 31 、……、α 480 ……α 487 、……、α 504 ……α 511 、α 512 ……α 519 、……α 536 ……α 543 there is a target alpha matrix that "matches the ratio of the second syndrome S 1 to the first syndrome S 0 ", and the error magnitude and symbol position estimator 461 can estimate the symbol corresponding to "the value obtained by dividing the exponent of the target symbol by the number of bits in each symbol among multiple symbols" as the target symbol.

[0148] The symbol error corrector 463 can output the estimated first error vector E 0 ' by replacing a part of the target symbol with the first syndrome S 1 and setting each bit other than the target symbol among multiple symbols to zero.

[0149] The syndrome checker 465 can perform a first vector multiplication operation on the estimated first error vector E 1 ' and the transposed matrix PCM T and generate a first error flag EF12 based on the result of the first vector multiplication operation.

[0150] The syndrome checker 465 can output the first error flag EF12 indicating successful first ECC decoding in response to the result of the first vector multiplication operation matching the syndrome SDR.

[0151] The syndrome checker 465 can output the first error flag EF12 indicating failed first ECC decoding in response to the result of the first vector multiplication operation being different from the syndrome SDR.

[0152] Figure 14 Shows an example operation of a symbol error correction circuit according to some embodiments. In Figure 13 and Figure 13 and Figure 14 the error magnitude and symbol position estimator 461 can determine whether there is a target alpha matrix α in the first alpha matrix α 0 ……α 7 、……、α 24 ……α 31 、……、α 480 ……α 487 、……、α 504 ……α 511 、α 512 ……α 519 、……α 536 ……α 543 that matches the ratio of the second sub-syndrome S 1 to the first sub-syndrome S 0 (e.g., determining whether there is a target alpha matrix in the first alpha matrix that is equal to the ratio of the second sub-syndrome S 8i to the first sub-syndrome S 1 )(operation S110), and can, in response to there being no target alpha matrix in the first alpha matrix α 0 ……α 0 ……α 7 、……、α 24 ……α 31 、……、α 480 ……α 487 、……、α 504 ……α 511 、α 512 ……α 519 、……α 536 ……α 543 that matches the second sub-syndrome S 1The target alpha matrix α that matches the ratio with the first syndrome S 0 and outputs a first error flag EF11 indicating a first ECC decoding failure (for example, outputs a first error flag EF11 with a logic low level). 8i (No in S110)

[0153] When there is a target alpha matrix α in the first alpha matrices α 0 ……α 7 、……、α 24 ……α 31 、……、α 480 ……α 487 、……、α 504 ……α 511 、α 512 ……α 519 、……α 536 ……α 543 that matches the ratio of the second syndrome S 1 and the first syndrome S 0 (Yes in S110), the error magnitude and symbol position estimator 461 can provide the position information i of the target symbol to the symbol error corrector 463, and the symbol error corrector 463 can output the estimated first error vector E 8i ' to the error corrector checker 465. The error corrector checker 465 can perform a first vector multiplication operation on the estimated first error vector E 1 ' and the transposed matrix PCM 1 and can determine whether the result of the first vector multiplication operation matches the syndrome SDR (operation S120). T When the result of the first vector multiplication operation matches the syndrome SDR (Yes in S120), the error corrector checker 465 can output a first error flag EF12 with a logic high level indicating a first ECC decoding success. When the result of the first vector multiplication operation is different from the syndrome SDR (No in S120), the error corrector checker 465 can output a first error flag EF12 with a logic low level indicating a first ECC decoding failure. The first error flags EF11 and EF12 can be included in the

[0154] first error flag EF1 in Figure 11 .

[0155] Therefore, the ECC decoder 430 can estimate the first error vector associated with the symbol error based on the comparison of the second syndrome S 1 and the first syndrome S 0 , and can perform a comparison on the estimated first error vector E 1 ' and the transposed matrix PCMT Perform a first vector multiplication operation to generate a first error flag EF1 indicating the result of the first ECC decoding.

[0156] Figure 15 is a block diagram showing an example of a random error correction circuit in an Figure 11 ECC decoder according to some embodiments. In Figure 15 , the random error correction circuit 470 may include a first syndrome value checker 471, a second syndrome value checker 473, a multi-bit (2-bit) error corrector (e.g., 2-bit random error corrector) 475, and an error correction syndrome checker 477. The first syndrome value checker 471 may receive a syndrome SDR including a first sub-syndrome S 0 , a second sub-syndrome S 1 , and a third sub-syndrome S 2 , may determine whether a first sum value of the syndrome value of the first sub-syndrome S 0 is "zero or two", may generate a check signal CKS2 indicating the result of the determination, and may provide the check signal CKS2 to the second syndrome value checker 473 and the multi-bit error corrector 475.

[0157] The second syndrome value checker 473 may receive a syndrome SDR including a first sub-syndrome S 0 , a second sub-syndrome S 1 , and a third sub-syndrome S 2 , may determine whether the first sum value is one in response to the first sum value not being zero and not being two, may output a second error flag EF21 indicating that a three-bit error is detected in response to the first sum value not being one, and may output a second error flag EF21 indicating one of whether a three-bit error is detected and whether a single-bit error is detected based on the second sub-syndrome S 1 and the third sub-syndrome S 2 in response to the first sum value being one.

[0158] In response to the result of cubing the second sub-syndrome S 1 matching the third sub-syndrome S 2 , the second syndrome value checker 473 may output a second error flag EF21 indicating that a single-bit error is detected. In response to the result of cubing the second sub-syndrome S 1 being different from the third sub-syndrome S 2 , the second syndrome value checker 473 may output a second error flag EF21 indicating that a three-bit error is detected.

[0159] The multi-bit error corrector 475 may receive a read codeword set SCW2, a transposed matrix PCM T , a second sub-syndrome S1 and a third syndrome S 2 , in response to the check signal CKS2 indicating that the first sum value is zero or two, based on the second syndrome S 1 and the third syndrome S 2 to estimate the position of a multi-bit error, generate a corrected user data set C_SDQ2 by correcting the multi-bit error in the read codeword set SCW2 based on the estimated position, estimate a second error vector E 2 ', and output the estimated second error vector E 2 '.

[0160] The multi-bit error corrector 475 can output the estimated second error vector E 2 ' by setting the first bit at the position corresponding to the multi-bit error in the read codeword set SCW2 to a logic high level and setting the second bits other than the first bit in the read codeword set SCW2 to a logic low level.

[0161] The syndrome checker 477 can perform a second vector multiplication operation on the estimated second error vector E 2 ' and the transposed matrix PCM T and generate a second error flag EF22 based on the result of the second vector multiplication operation.

[0162] The syndrome checker 477 can output the second error flag EF22 indicating that a two-bit error has been corrected in response to the result of the second vector multiplication operation matching the syndrome SDR.

[0163] The syndrome checker 477 can output the second error flag EF22 indicating that a three-bit error has been detected in response to the result of the second vector multiplication operation being different from the syndrome SDR.

[0164] Figure 16 Illustrates an example operation of a Figure 15 random error correction circuit according to some embodiments. In Figure 15 and Figure 16 , the first syndrome value checker 471 can determine the first sum value S 0 of the syndrome value of the first syndrome S 0 [0]+S 0 [1]+S 0 [2]+S 0 [3]+S 0 [4]+S 0 [5]+S 0 [6]+S 0 [7] is "zero or two" (operation S210). By performing an operation on the read codeword set SCW2 and the first sub-check matrix HS 21Perform a vector multiplication to obtain a first syndrome S 0 , and a first parity-check matrix HS 21 includes a plurality of unit sub-matrices ISM11, ……, ISM14, ……, ISMp1, ……, ISMp4, ISMs1, ……, ISMs4 and a plurality of zero sub-matrices ZSM11, ……, ZSM14, ……, ZSMp1, ……, ZSMp4, ZSMs1, ……, ZSMs4 corresponding to the plurality of unit sub-matrices ISM11, ……, ISM14, ……, ISMp1, ……, ISMp4, ISMs1, ……, ISMs4 respectively. Therefore, since the syndrome value S 0 [8], S 0 [9], S 0

[10] , and S 0

[11] correspond to the result of the vector multiplication of the read codeword set SCW2 and the plurality of zero sub-matrices ZSM11, ……, ZSM14, ……, ZSMp1, ……, ZSMp4, ZSMs1, ……, ZSMs4, the syndrome values S 0 of the first syndrome S 0 [8], S 0 [9], S 0

[10] , and S 0

[11] are all zeros.

[0165] When the first sum value S 0 [0]+S 0 [1]+S 0 [2]+S 0 [3]+S 0 [4]+S 0 [5]+S 0 [6]+S 0 [7] is not zero and not two (No in operation S210), the second syndrome value checker 473 can determine whether the first sum value S 0 [0]+S 0 [1]+S 0 [2]+S 0 [3]+S 0 [4]+S 0 [5]+S 0 [6]+S 0 [7] is one (operation S220).

[0166] When the first sum value S 0 [0]+S 0 [1]+S 0 [2]+S 0 [3]+S 0 [4]+S 0 [5]+S0 [6] + S 0 If it is not one (No in operation S220), the second syndrome value checker 473 can output the second error flag EF21 as "11" indicating that a three-bit error has been detected.

[0167] When the first sum value S 0 [0] + S 0 [1] + S 0 [2] + S 0 [3] + S 0 [4] + S 0 [5] + S 0 [6] + S 0 If it is one (Yes in operation S220), the second syndrome value checker 473 can determine whether the result of cubing the second sub-syndrome S 1 matches the third sub-syndrome S 2 (operation S240).

[0168] When the result of cubing the second sub-syndrome S 1 is different from the third sub-syndrome S 2 (No in operation S240), the second syndrome value checker 473 can output the second error flag EF21 as "11" indicating that a three-bit error has been detected. When the result of cubing the second sub-syndrome S 1 matches the third sub-syndrome S 2 (Yes in operation S240), the second syndrome value checker 473 can output the second error flag EF21 as "01" indicating that a single-bit error has been detected.

[0169] When the first sum value S 0 [0] + S 0 [1] + S 0 [2] + S 0 [3] + S 0 [4] + S 0 [5] + S 0 [6] + S 0 is zero or two (Yes in operation S210), the multi-bit error corrector 475 can correct the multi-bit error in the read codeword set SCW2 (operation S230), and can output the estimated second error vector E 2 ' to the syndrome checker 477.

[0170] The syndrome checker 477 can calculate the estimated second error vector E 2 ' and the transposed matrix PCM TPerform a second vector multiplication operation and determine whether the result of the second vector multiplication operation matches the syndrome SDR (operation S250).

[0171] When the result of the second vector multiplication operation is different from the syndrome SDR (No in operation S250), the error syndrome checker 477 may output a second error flag EF22 of "11" indicating that a three-bit error is detected. When the result of the second vector multiplication operation matches the syndrome SDR (Yes in operation S250), the error syndrome checker 477 may output a second error flag EF22 of "10" indicating that multiple-bit errors are corrected.

[0172] The second error flags EF21 and EF22 may be included in Figure 11 the second error flag EF2 in

[0173] Therefore, the ECC decoder 430 may estimate a second error vector associated with multiple-bit errors based on the first sum value S 0 [0]+S 0 [1]+S 0 [2]+S 0 [3]+S 0 [4]+S 0 [5]+S 0 [6]+S 0 [7], and generate a second error flag EF2 associated with correcting multiple-bit errors. Additionally, the ECC decoder 430 may generate a second error flag EF2 indicating whether a single-bit error is detected or a three-bit error is detected based on the first sum value S0[0]+S0[1]+S0[2]+S0[3]+S0[4]+S0[5]+S0[6]+S0[7], the second sub-syndrome S 1 and the third sub-syndrome S 2 Generate a second error flag EF2 indicating whether a single-bit error is detected or a three-bit error is detected.

[0174] In the description with reference to Figures 11 to 16 the operations on the first sub-syndrome S 0 , the second sub-syndrome S 1 and the third sub-syndrome S 2 may be performed within the Galois field.

[0175] Figure 17 is a table showing an example of a decision circuit configured to determine an error based on a decision signal. In Figures 11 to 17 the decision signal DS may include a first error flag EF1 and a second error flag EF2.

[0176] The first error flag EF1 may include one bit, and the second error flag EF2 may include two (i.e., double) bits. When the first error flag EF1 has a logic low level (i.e., "0") and the second error flag EF2 is "01", the decision circuit 480 may output a decision signal DS indicating that an uncorrectable error UE (e.g., a single-bit error) is detected in the read codeword set SCW2. When the first error flag EF1 has a logic low level (i.e., "0") and the second error flag EF2 is "10", the decision circuit 480 may output a decision signal DS indicating that a two-bit error is corrected in the read codeword set SCW2. When the first error flag EF1 has a logic low level (i.e., "0") and the second error flag EF2 is "11", the decision circuit 480 may output a decision signal DS indicating that a three-bit error is detected in the read codeword set SCW2. When the first error flag EF1 has a logic high level (i.e., "1") and the second error flag EF2 is one of "01", "10", and "11", the decision circuit 480 may output a decision signal DS indicating that a symbol error is corrected in the read codeword set SCW2.

[0177] Figure 18 is a flowchart showing an example of the operation of an ECC decoder according to some embodiments. In Figures 8A to 18 the ECC decoder 430 in the memory controller 100 that controls the memory module MM including a plurality of data chips 200a to 200p and at least one parity chip 200s, the ECC decoder 430 generates a syndrome SDR by performing a matrix multiplication operation on the read codeword set SCW2 and the transposed matrix PCM of the parity check matrix PCM T (operation S310). The parity check matrix PCM may include a first sub parity check matrix HS 21 , a second sub parity check matrix HS 22 and a third sub parity check matrix HS 23 , and the syndrome SDR may include a first sub syndrome S 0 , a second sub syndrome S 1 and a third sub syndrome S 2 .

[0178] The ECC decoder 430 may determine whether each of the syndrome values of the syndrome SDR is zero (operation S330).

[0179] When each of the syndrome values of the syndrome SDR is zero (Yes in operation S330), since the read codeword set SCW2 does not include an error, the ECC decoder 430 may output the user data set SDQ in the read codeword set SCW2 (operation S350).

[0180] When at least one of the syndrome values of the syndrome SDR is non-zero (No in operation S330), since the read codeword set SCW2 includes an error, the ECC decoder 430 can correct symbol errors and random (multiple) bit errors in the read codeword set SCW2 in parallel (operation S370).

[0181] Figure 19 is a flowchart showing an example of an operation of correcting symbol errors and random bit errors in parallel according to some embodiments. For example, Figure 19 Operation S400 (including operations S410, S420, S430, S460, S470, and S480) in Figure 18 can correspond to Figure 11 、 Figures 13 to 17 and Figure 19 Operation S370 in. In 1 、the symbol error correction circuit 460 can estimate the magnitude of the symbol error and the position of the target symbol where the symbol error occurs based on the ratio of the second sub-syndrome S 0 to the first sub-syndrome S 1 '(operation S410), can correct the error of the target symbol among the multiple symbols of the read codeword set SCW2 based on the position information i of the target symbol (operation S420), can output the estimated first error vector E 1 ', can perform a first vector multiplication operation on the estimated first error vector E T ' and the transposed matrix PCM

[0182] 0 In parallel with the operation of the symbol error correction circuit 460, the random error correction circuit 470 can determine whether the first summation value of the syndrome values of the first sub-syndrome S 1 is "zero or two" (operation S460), can estimate the position of the multiple bit errors based on the second sub-syndrome S 2 and the third sub-syndrome S 2 ' in response to the first summation value being zero or two, can correct multiple (e.g., two-bit) errors in the read codeword set SCW2 based on the estimated position (operation S470), can output the estimated second error vector E 2 ', can perform a second vector multiplication operation on the estimated second error vector E T ' and the transposed matrix PCM

[0183] Figures 20 to 22 shows an example of errors that can be corrected by an ECC decoder according to some embodiments. In Figures 20 to 22In this case, it is assumed that chips CHIP1 to CHIP16 correspond to Figure 3 data chips 200a to 200p in Figures 20 to 22 , and for each of output data sets DQ_BL1 to DQ_BL16 in chips CHIP1 to CHIP16, a corresponding one, a parity chip 200s outputs parity data PRTS. Additionally, in

[0184] In Figure 20 , when the data set DQ_BL2 output from chip CHIP2 includes a symbol error and the data set DQ_BL1 output from chip CHIP1 includes a single-bit error, Figure 11 the ECC decoder in

[0185] can correct the symbol error, can output a first error flag EF1 indicating that the symbol error has been corrected, cannot correct the single-bit error, and can output a second error flag EF2 indicating that the single-bit error has been detected. Figure 21 In Figure 11 , when the data set DQ_BL2 output from chip CHIP2 includes a symbol error, the data set DQ_BL3 output from chip CHIP3 includes a single-bit error, and the data set DQ_BL4 output from chip CHIP4 includes a single-bit error,

[0186] In Figure 22 , when the data set DQ_BL2 output from chip CHIP2 includes a symbol error, the data set DQ_BL1 output from chip CHIP1 includes a single-bit error, and the data set DQ_BL3 output from chip CHIP3 includes a multi-bit error, Figure 11 the ECC decoder in

[0187] can correct the symbol error, can output a first error flag EF1 indicating that the symbol error has been corrected, can correct the multi-bit error corresponding to the single-bit errors in data sets DQ_BL3 and DQ_BL4, and can output a second error flag EF2 indicating that the multi-bit error has been corrected.

[0188] Figure 23is a block diagram illustrating an example of a memory module that can be adopted by a memory system according to some embodiments. In Figure 23 , the memory module 500 may include a register clock driver (RCD) 590 disposed in or mounted on a circuit board 501, a plurality of semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d, a plurality of data buffers (DBs) 541 to 545 and 551 to 554, module resistor units 560 and 570, a serial presence detect (SPD) chip 580, and a power management integrated circuit (PMIC) 585.

[0189] The RCD 590 may control the semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d and the PMIC 585 under the control of the memory controller 100. For example, the RCD 590 may receive an address ADDR, a command CMD, and a clock signal CK from the memory controller 100.

[0190] The SPD chip 580 may be a programmable read-only memory (e.g., EEPROM). The SPD chip 580 may include initial information or device information DI of the memory module 500. In an exemplary embodiment, the SPD chip 580 may include initial information or device information DI (such as module shape, module configuration, storage capacity, module type, execution environment, etc.) of the memory module 500.

[0191] When a memory system including the memory module 500 is powered on, the memory controller 100 may read the device information DI from the SPD chip 580 and may identify the memory module 500 based on the device information DI. The memory controller 100 may control the memory module 500 based on the device information DI from the SPD chip 580. For example, the memory controller 100 may identify the type of the semiconductor memory device included in the memory module 500 based on the device information DI from the SPD chip 580.

[0192] Here, the circuit board 501, which is a printed circuit board, may extend in a first direction D1 perpendicular to a second direction D2 between a first edge portion 503 and a second edge portion 505. The first edge portion 503 and the second edge portion 505 may extend in the second direction D2.

[0193] The RCD 590 may be disposed at the center of the circuit board 501. The plurality of semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d may be arranged in a plurality of rows between the RCD 590 and the first edge portion 503 and between the RCD 590 and the second edge portion 505.

[0194] In this case, the semiconductor memory devices 601a to 601e and 602a to 602e may be arranged along multiple rows between the RCD 590 and the first edge portion 503. The semiconductor memory devices 603a to 603d and 604a to 604d may be arranged along multiple rows between the RCD 590 and the second edge portion 505. The semiconductor memory devices 601a to 601d, 602a to 602d, 603a to 603d, and 604a to 604d may be referred to as data chips, and the semiconductor memory devices 601e and 602e may be referred to as a first parity chip and a second parity chip, respectively.

[0195] Each of the multiple semiconductor memory devices 601a to 601d, 602a to 602d, 603a to 603d, and 604a to 604d may be coupled to a corresponding one of the data buffers 541 to 544 and 551 to 554 through data transmission lines for receiving / sending data signals DQ and data strobe signals DQS. Each of the semiconductor memory devices 601e and 602e may be coupled to the data buffer 545 through data transmission lines for receiving / sending parity data PRTS and data strobe signals DQS.

[0196] The RCD 590 may provide command / address signals (e.g., CA) to the semiconductor memory devices 601a to 601e through the command / address transmission lines 561, and may provide command / address signals to the semiconductor memory devices 602a to 602e through the command / address transmission lines 563.

[0197] In addition, the RCD 590 may provide command / address signals to the semiconductor memory devices 603a to 603d through the command / address transmission lines 571, and may provide command / address signals to the semiconductor memory devices 604a to 604d through the command / address transmission lines 573.

[0198] The command / address transmission lines 561 and 563 may be commonly connected to a module resistor unit 560 set to be adjacent to the first edge portion 503, and the command / address transmission lines 571 and 573 may be commonly connected to a module resistor unit 570 set to be adjacent to the second edge portion 505.

[0199] Each of the module resistor units 560 and 570 may include a termination resistor Rtt / 2 connected to a termination voltage Vtt. In this case, the arrangement of the module resistor units 560 and 570 may reduce the number of module resistor units, thereby reducing the area for setting the termination resistors.

[0200] In addition, each of the plurality of semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d may be a DRAM device.

[0201] The SPD chip 580 may be arranged to be adjacent to the RCD 590, and the PMIC 585 may be arranged between the semiconductor memory device 603d and the second edge portion 505. The PMIC 585 may generate a power supply voltage VDD based on the input voltage VIN, and may supply the power supply voltage VDD to the semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d.

[0202] Although the PMIC 585 is shown in Figure 23 to be arranged adjacent to the second edge portion 505, in an exemplary embodiment, the PMIC 585 may be arranged in the central portion of the circuit board 501 to be adjacent to the RCD 590.

[0203] Figure 24 is a block diagram showing an example of a memory system having a four-rank memory module according to some embodiments. In Figure 24 the memory system 700 may include a memory controller 710 and at least one or more memory modules 720 and 730.

[0204] The memory controller 710 may control the memory modules 720 and / or 730 to execute commands provided from a processor or a host. The memory controller 710 may be implemented in the processor or the host, or may be implemented with an application processor or a system-on-chip (SoC). The memory controller 710 may include a transmitter 711 for sending signals to at least one or more memory modules 720 and 730, and a receiver 713 for receiving signals from at least one or more memory modules 720 and 730. For signal integrity, a resistor RTT on the bus 740 of the memory controller 710 may be used to implement a source terminal. The resistor RTT may be coupled to the power supply voltage VDDQ. The memory controller 710 may include an ECC engine 715, and the ECC engine 715 may employ Figure 6 the ECC engine 400 of

[0205] Accordingly, the ECC engine 715 may include an ECC encoder and an ECC decoder. The ECC decoder may perform the first ECC decoding and the second ECC decoding in parallel, and may share a part of the parity check matrix when performing the first ECC decoding and the second ECC decoding. The first ECC decoding is used to correct symbol errors, and the second ECC decoding is used to correct multi-bit errors. Accordingly, the ECC engine 715 may reduce the complexity and decoding latency of the ECC.

[0206] At least one or more memory modules 720 and 730 may be referred to as a first memory module 720 and a second memory module 730. The first memory module 720 and the second memory module 730 may be coupled to the memory controller 710 via a bus 740. Each of the first memory module 720 and the second memory module 730 may correspond to Figure 1 the memory module MM in. The first memory module 720 may include at least one or more memory banks RK1 and RK2, and the second memory module 730 may include one or more memory banks RK3 and RK4.

[0207] Each of the first memory module 720 and the second memory module 730 may include a plurality of data chips and at least one parity check chip.

[0208] Figure 25 is a block diagram showing an example of a mobile system including a memory module according to some embodiments. In Figure 25 the mobile system 800 may include an application processor (AP) 810, a connection module 820, a memory module MM 850, a non-volatile memory device (NVM) 840, a user interface 830, and a power supply 870. The application processor 810 may include a memory controller (MCT) 811. The memory controller 811 may include Figure 6 the ECC engine 400 of.

[0209] The application processor 810 may execute applications (such as a web browser, a game application, a video player, etc.). The connection module 820 may perform wired communication or wireless communication with an external device.

[0210] The memory module 850 may store data processed by the application processor 810 or operate as a working memory. The memory module 850 may include a plurality of semiconductor memory devices MD 851, 852, 853, and 85r (where r is a positive integer greater than 3) and an RCD 861.

[0211] The semiconductor memory devices 851, 852, 853, and 85r may include a plurality of data chips and at least one parity chip. Accordingly, the ECC engine in the memory controller 811 may perform first ECC decoding and second ECC decoding in parallel and may share a part of the parity matrix when performing the first ECC decoding and the second ECC decoding, the first ECC decoding for correcting symbol errors and the second ECC decoding for correcting multi-bit errors. Accordingly, the ECC engine may reduce the complexity and decoding latency of ECC.

[0212] The non-volatile memory device 840 may store a boot image for booting the mobile system 800. The user interface 830 may include at least one input device (such as, a keypad, a touch screen, etc.) and at least one output device (such as, a speaker, a display device, etc.). The power supply 870 may supply an operating voltage to the mobile system 800.

[0213] Various types of packages may be used to mount the mobile system 800 or components of the mobile system 800.

[0214] Figure 26 is a block diagram illustrating an example of a computing system according to some embodiments. In Figure 26 the computing system 30 may include a plurality of hosts 900a, 900b, ……, 900f and a memory system 1000, and the memory system 1000 may include a memory controller 1100 and a memory module 1200. Here, f is a natural number greater than two.

[0215] The memory module 1200 may include a plurality of data chips 1210a to 1210p and at least one parity chip 1220. The plurality of data chips 1210a to 1210p may be referred to as memory chips. The at least one parity chip 1220 may be referred to as an ECC chip.

[0216] The memory controller 1100 may apply a command CMD and an address ADDR to the memory module 1200 and may exchange a set of codewords SCW with the memory module 1200. The memory controller 1100 may include a processor 1110 and an ECC engine 1130.

[0217] The processor 1110 may control the overall operation of the memory controller 1100.

[0218] The ECC engine 1130 may perform ECC encoding on a user data set to generate a parity data set and may provide a set of codewords SCW including the user data set and the parity data set to the memory module 1200 in a write operation.

[0219] The ECC engine 1130 can perform the first ECC decoding and the second ECC decoding in parallel during a read operation, and can share a part of the parity check matrix when performing the first ECC decoding and the second ECC decoding. The first ECC decoding is used to correct symbol errors in the codeword set SCW, and the second ECC decoding is used to correct multiple-bit errors in the codeword set SCW. Therefore, the ECC engine 1130 can reduce the complexity and decoding latency of ECC.

[0220] The memory controller 1100 can be connected to a plurality of hosts 900a, 900b, ……, 900f via a Compute Express Link (CXL) bus 50, and can control a plurality of data chips 1210a to 1210p and at least one parity check chip 1220 by communicating with the plurality of hosts 900a, 900b, ……, 900f via the CXL interface.

[0221] In some embodiments, the CXL bus 50 can support multiple CXL protocols, and messages and / or data can be transmitted through the multiple CXL protocols. For example, the multiple CXL protocols can include a non-coherent protocol (or, I / O protocol CXL.io), a coherent protocol (or, cache protocol CXL.cache), and a memory access protocol (or, memory protocol CXL.memory). In some embodiments, the CXL bus 50 can support protocols such as Peripheral Component Interconnect (PCI), PCI Express (PCIe), Universal Serial Bus (USB), and Serial Advanced Technology Attachment (SATA). The protocols supported by the CXL bus 50 can be referred to as interconnect protocols.

[0222] The memory controller 1100 can represent a device that provides functions to a plurality of hosts 900a, 900b, ……, 900f. Based on the CXL specification 2.0, the memory controller 1100 can be an accelerator that supports the CXL specification. For example, at least some of the computing operations and I / O operations executed in the plurality of hosts 900a, 900b, ……, 900f can be offloaded to the memory controller 1100. In some embodiments, each of the plurality of hosts 900a, 900b, ……, 900f can include any one or any combination of programmable components (e.g., Graphics Processing Unit (GPU) and Neural Processing Unit (NPU)), components that provide fixed functions (e.g., Intellectual Property (IP) core), and reconfigurable components (e.g., Field Programmable Gate Array (FPGA)).

[0223] Figure 27 is a block diagram showing an example of one of the multiple hosts in a Figure 26 computing system according to some embodiments. In Figure 27Among them, the configuration of host 900a among multiple hosts 900a, 900b, ……, 900f and the configuration of each of hosts 900b, ……, 900f can be substantially the same as the configuration of host 900a. Host 900a may include a processor 910 and a host memory 940.

[0224] Processor 910 may be a central processing unit (CPU) of host 900a. In some embodiments, processor 910 may be a CXL-based processor. As Figure 27 shown, processor 910 may be connected to host memory 940, and may include a physical layer 917, a multi-protocol multiplexer 916, an interface circuit 915, a coherence / cache circuit 913, a bus circuit 914, at least one core 911, and an I / O device 912.

[0225] At least one core 911 may execute instructions and be connected to the coherence / cache circuit 913. The coherence / cache circuit 913 may include a cache hierarchy and may be referred to as coherence / cache logic. In Figure 27 this case, the coherence / cache circuit 913 may communicate with at least one core 911 and the interface circuit 915. For example, the coherence / cache circuit 913 may implement communication at least through a protocol including a coherence protocol and a memory access protocol. In some embodiments, the coherence / cache circuit 913 may include a direct memory access (DMA) circuit. The I / O device 912 may be used to communicate with the bus circuit 914. For example, the bus circuit 914 may be PCIe logic, and the I / O device 912 may be a PCIe I / O device.

[0226] The interface circuit 915 may implement communication between the components of the processor 910 (e.g., the coherence / cache circuit 913 and the bus circuit 914) and the memory system 1000. In some embodiments, the interface circuit 915 may implement communication between the components of the processor 910 and the memory system 1000 according to multiple protocols (e.g., a non-coherence protocol, a coherence protocol, and a memory access protocol). For example, the interface circuit 915 may determine one of the multiple protocols based on messages and data for communication between the components of the processor 910 and the memory system 1000.

[0227] The multi - protocol multiplexer 916 may include at least one protocol queue. The interface circuit 915 may be connected to at least one protocol queue and send messages and / or data to the memory system 1000 and receive messages and / or data from the memory system 1000 through at least one protocol queue. In some embodiments, the interface circuit 915 and the multi - protocol multiplexer 916 may be integrally formed as one component. In some embodiments, the multi - protocol multiplexer 916 may include multiple protocol queues corresponding to multiple protocols supported by the CXL bus 50 respectively. In some embodiments, the multi - protocol multiplexer 916 may arbitrate communications of different protocols and provide the selected communications to the physical layer 917.

[0228] Figure 28 Illustrates an example of a multi - protocol for communication in a Figure 26 computing system according to some embodiments. In Figure 28 this, the processor 910 and the memory controller 1100 may communicate with each other based on multiple protocols.

[0229] According to the above CXL example, the multiple protocols may include a memory protocol MEM, a coherence protocol CACHE, and a non - coherence protocol IO. The memory protocol MEM may define transactions from a master device to a slave device and from a slave device to a master device. The coherence protocol CACHE may define the interaction between the memory controller 1100 and the processor 910. For example, the interface of the coherence protocol CACHE may include three channels for requests, responses, and data. The non - coherence protocol IO may provide non - coherent load / store for I / O devices.

[0230] The memory controller 1100 may communicate with the memory module 1200, and the processor 910 may communicate with the host memory 940.

[0231] Figure 29 is an example of a computing system according to some embodiments when the memory system according to the example embodiment corresponds to a type 3 memory system defined by the CXL protocol. In Figure 29 this, the computing system 1300 may include a root complex 1310, a CXL memory expander 1320 connected to the root complex 1310, and a memory resource 1330.

[0232] The root complex 1310 may include a home agent 1311 and an I / O bridge 1313, and the home agent 1311 may communicate with the CXL memory expander 1320 based on the coherence protocol CXL.mem, and the I / O bridge 1313 may communicate with the CXL memory expander 1320 based on a non-coherence protocol (i.e., the I / O protocol CXL.io). Based on the CXL protocol, the home agent 1311 may correspond to an agent on the host side, and the agent on the host side is arranged to resolve the overall coherence of the computing system 1300 for a given address.

[0233] The CXL memory expander 1320 may include a memory controller 1321, and the memory controller 1321 may adopt Figure 26 the memory controller 1100 in. Additionally, the CXL memory expander 1320 may output data to the root complex 1310 based on the I / O protocol CXL.io or PCIe via the I / O bridge 1313.

[0234] The memory resources 1330 may include a plurality of memory regions MR1, MR2, ……, MRf, and each of the plurality of memory regions MR1, MR2, ……, MRf may be implemented as a memory of various units.

[0235] Figure 30 is a block diagram showing a data center including a computing system according to some embodiments. In Figure 30 this, the data center 2000 may be a facility that collects various types of data and provides various services, and may be referred to as a data storage center. The data center 2000 may be a system for operating a search engine and a database, and may be a computing system used by a company such as a bank or a government agency. The data center 2000 may include application servers 2100_1 (first application server) to 2100_U (Uth application server) and storage servers 2200_1 (first storage server) to 2200_V (Vth storage server). The number of application servers 2100_1 to 2100_U and the number of storage servers 2200_1 to 2200_V may be selected differently according to some embodiments, and the number of application servers 2100_1 to 2100_U and the number of storage servers 2200_1 to 2200_V may be different from each other.

[0236] Hereinafter, for ease of description, an example of the storage server 2200_1 will be described.

[0237] The storage server 2200_1 may include a processor 2210_1, a memory 2220_1, a switch 2230_1, a network interface controller (NIC) 2240_1, a storage device 2250_1, and a CXL interface 2260_1. The storage server 2200_V may include a processor 2210_v, a memory 2220_v, a switch 2230_v, a NIC 2240_v, a storage device 2250_v, and a CXL interface 2260_v.

[0238] The processor 2210_1 may control the overall operation of the storage server 2200_1. The memory 2220_1 may store various instructions or data under the control of the processor 2210_1. The processor 2210_1 may be configured to access the memory 2220_1 to execute various instructions or process data. In some embodiments, the memory 2220_1 may include at least one of various memory devices (such as double data rate synchronous DRAM (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, or non-volatile DIMM).

[0239] In some embodiments, the number of processors 2210_1 included in the storage server 2200_1 and the number of memories 2220_1 included in the storage server 2200_1 may be differently changed or modified. In one embodiment, the processors 2210_1 and memories 2220_1 included in the storage server 2200_1 may form a processor-memory pair, and the number of processor-memory pairs included in the storage server 2200_1 may be differently changed or modified. In one embodiment, the number of processors 2210_1 included in the storage server 2200_1 and the number of memories 2220_1 included in the storage server 2200_1 may be different. The processor 2210_1 may include a single-core processor and a multi-core processor.

[0240] Under the control of the processor 2210_1, the switch 2230_1 may selectively connect the processor 2210_1 and the storage device 2250_1 or may selectively connect the NIC 2240_1, the storage device 2250_1, and the CXL 2260_1.

[0241] The NIC 2240_1 can connect the storage server 2200_1 to the network NT. The NIC 2240_1 can include a network interface card, a network adapter, etc. The NIC 2240_1 can be connected to the network NT through a wired interface, a wireless interface, a Bluetooth interface, or an optical interface. The NIC 2240_1 can include an internal memory, a digital signal processor (DSP), a host bus interface, etc., and can be connected to the processor 2210_1 or the switch 2230_1 through the host bus interface. The host bus interface can include various interface schemes (such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVMe, Compute Express Link (CXL), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card interface, Multimedia Card (MMC) interface, Embedded MMC (eMMC) interface, Universal Flash Storage (UFS) interface, Embedded UFS (eUFS) interface, CompactFlash (CF) card interface, etc.) of at least one. In one embodiment, the NIC 2240_1 can be integrated with at least one of the processor 2210_1, the switch 2230_1, and the storage device 2250_1.

[0242] Under the control of the processor 2210_1, the storage device 2250_1 can store data or can output the stored data. The storage device 2250_1 can include a controller CTRL 2251_1, a non-volatile memory NAND 2252_1, a DRAM 2253_1, and an interface I / F 2254_1. In one embodiment, the storage device 2250_1 can further include a security element SE for security or privacy. The storage device 2250_v can include a controller CTRL 2251_v, a non-volatile memory NAND 2252_v, a DRAM 2253_v, and an interface I / F 2254_v. In one embodiment, the storage device 2250_v can further include a security element SE for security or privacy.

[0243] The controller 2251_1 can control the overall operation of the storage device 2250_1. The controller 2251_1 can include SRAM. In response to a signal received through the interface 2254_1, the controller 2251_1 can store data in the non-volatile memory 2252_1 or can output the data stored in the non-volatile memory 2252_1. The controller 2251_1 can be configured to control the non-volatile memory 2252_1 based on a switching interface or ONFI.

[0244] The DRAM 2253_1 can be configured to temporarily store data to be stored in the non-volatile memory 2252_1 or data read from the non-volatile memory 2252_1. The DRAM 2253_1 can be configured to store various data (e.g., metadata and mapping data) required for the operation of the storage controller 2251_1. The interface 2254_1 can provide a physical connection between the controller 2251_1 and the processor 2210_1, the switch 2230_1, or the NIC 2240_1. The interface 2254_1 can be implemented to support the direct-attached storage (DAS) mode, and the direct-attached storage (DAS) mode allows a direct connection to the storage device 2250_1 through a dedicated cable. The interface 2254_1 can be implemented based on at least one of the various above-mentioned interfaces through the host interface bus.

[0245] The above components of the storage server 2200_1 are provided as examples, and the present disclosure is not limited thereto. The above components of the storage server 2200_1 can be applied to each of other storage servers or to each of the application servers 2100_1 to 2100_U. In the application servers 2100_1 to 2100_U, the storage devices 2150_1 to 2150_u can be selectively omitted.

[0246] The application server 2100_1 can include a processor 2110_1, a memory 2120_1, a switch 2130_1, a NIC 2140_1, and a CXL interface 2160_1. The application server 2100_U can include a processor 2110_u, a memory 2120_u, a switch 2130_u, a NIC 2140_u, and a CXL interface 2160_u.

[0247] The application servers 2100_1 to 2100_U and the storage servers 2200_1 to 2200_V can communicate with each other through the network NT. The network NT can be implemented using Fibre Channel (FC) or Ethernet. FC can be a medium for relatively high-speed data transmission, and an optical switch providing high performance and / or high availability can be used. According to the access scheme of the network NT, the storage servers 2200_1 to 2200_V can be provided as file storage devices, block storage devices, or object storage devices.

[0248] In some embodiments, the network NT may be a storage-only network or a network dedicated to storage (such as a storage area network (SAN)). For example, the SAN may be a FC-SAN that uses a FC network and is implemented according to the FC protocol (FCP). For another example, the SAN may be an IP-SAN, which uses a Transmission Control Protocol / Internet Protocol (TCP / IP) network and is implemented according to the iSCSI (SCSI over TCP / IP or Internet SCSI) protocol. In some embodiments, the network NT may be a general network (such as a TCP / IP network). For example, the network NT may be implemented according to at least one of protocols such as Fibre Channel over Ethernet (FCoE), Network Attached Storage (NAS), Non-Volatile Memory Express over Fabrics (NVMe) (NVMe-oF), etc.

[0249] In some embodiments, at least one of the plurality of application servers 2100_1 to 2100_U may be configured to access at least one of the remaining application servers or at least one of the storage servers 2200_1 to 2200_V via the network NT. For example, the application server 2100_1 may store data requested by a user or a client in at least one of the storage servers 2200_1 to 2200_V via the network NT. Optionally, the application server 2100_1 may obtain data requested by a user or a client that is in at least one of the storage servers 2200_1 to 2200_V via the network NT. In this case, the application server 2100_1 may be implemented with a web server, a database management system (DBMS), etc.

[0250] The application server 2100_1 may access the memory 2120_1 or the storage device 2150_1 of the application server 2100_1 or the storage device 2250_1 of the storage server 2200_1 via the network NT. In this way, the application server 2100_1 may perform various operations on the data stored in the application servers 2100_1 to 2100_U and / or the storage servers 2200_1 to 2200_V. For example, the application server 2100_1 may execute commands for moving or copying data between the application servers 2100_1 to 2100_U and / or the storage servers 2200_1 to 2200_V. The data may be transferred from the storage devices 2250_1 to 2250_v of the storage servers 2200_1 to 2200_V to the memories 2120_1 to 2120_u of the application servers 2100_1 to 2100_U directly or through the memories 2220_1 to 2220_v of the storage servers 2200_1 to 2200_V. For example, for security or privacy, the data transmitted via the network NT may be encrypted data.

[0251] The storage servers 2200_1 to 2200_V and the application servers 2100_1 to 2100_U can be connected to the memory expander 2300 through the CXL interfaces 2260_1 to 2260_v and 2160_1 to 2160_u. The memory expander 2300 can be used as an extended memory for each of the storage servers 2200_1 to 2200_V and the application servers 2100_1 to 2100_U, or the virtualization components included therein can communicate with each other through the CXL interfaces 2260_1 to 2260_v and 2160_1 to 2160_u and the memory expander 2300.

[0252] The present disclosure can be applied to various electronic devices and systems including memory modules and memory systems. For example, the present disclosure can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, etc.

[0253] Although the present disclosure contains many specific implementation details, these should not be construed as limitations on the scope that can be claimed. The specific features described in the context of separate embodiments in the present disclosure can also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment can also be implemented separately or in any suitable sub-combination in multiple embodiments. In addition, although the features may be described above as acting in a specific combination, in some cases one or more features from the combination can be deleted from the combination, and the combination can relate to a sub-combination or a variation of the sub-combination.

Claims

1. A memory controller, comprising: Error correction code ECC engine; as well as A processor configured to control an ECC engine, The ECC engine includes an ECC decoder, and the ECC decoder is configured as follows: performing a first ECC decoding by using a first sub-check matrix and a second sub-check matrix of a parity check matrix to correct a symbol error in a read codeword set read from a memory module, the memory module including a plurality of data chips and at least one parity check chip; and In parallel with performing the first ECC decoding, performing a second ECC decoding by using a second sub-check matrix and a third sub-check matrix of the parity check matrix to correct a multi-bit error in the read codeword set and detect a triple-bit error in the read codeword set, Among them, the ECC decoder is configured as: generating a syndrome including a first sub-syndrome, a second sub-syndrome, and a third sub-syndrome based on the parity check matrix and the read codeword set; correcting the symbol error based on comparing the first sub-syndrome and the second sub-syndrome; and The multi-bit error is corrected and the triple error is detected based on a sum value obtained by summing the syndrome values ​​of the first sub-syndrome.

2. The memory controller according to claim 1, wherein: The ECC decoder is configured as: estimating a first error vector associated with the symbol error based on comparing the first subsyndrome and the second subsyndrome; generating a first error flag indicating a result of the first ECC decoding by performing a vector multiplication operation on an estimated first error vector and a transposed matrix of a parity check matrix; estimating a second error vector associated with the multi-bit error based on the summed value; and A second error flag associated with whether the multi-bit error is corrected is generated by performing a vector multiplication operation on the estimated second error vector and the transposed matrix.

3. The memory controller according to claim 1, wherein: The ECC decoder is configured as: estimating a first error vector associated with the symbol error based on comparing the first subsyndrome and the second subsyndrome; generating a first error flag indicating a result of the first ECC decoding by performing a vector multiplication operation on the estimated first error vector and a transposed matrix of the parity check matrix; and A second error flag indicating whether a single-bit error is detected or whether the triple-bit error is detected is generated based on the sum value, the second sub-syndrome, and the third sub-syndrome.

4. The memory controller according to claim 1, wherein: The first sub-check matrix includes a plurality of unit sub-matrices and a plurality of zero sub-matrices, wherein the plurality of unit sub-matrices correspond to a plurality of symbols in the read codeword set, and the plurality of zero sub-matrices correspond to the plurality of unit sub-matrices; The second sub-check matrix includes a first alpha matrix corresponding to the bits of the plurality of symbols, the first alpha matrix having sequentially increasing index values; and The third sub-check matrix includes a second alpha matrix obtained by cubing each of the first alpha matrices.

5. The memory controller according to claim 4, wherein: The ECC decoder includes: a syndrome generator configured to generate the syndrome by performing a vector multiplication operation on a read codeword set and a transposed matrix of a parity check matrix; a symbol error correction circuit configured to, in response to the syndrome having a non-zero value, perform a first ECC decoding on the read codeword set by using a first sub-check matrix and a second sub-check matrix, and generate a first error flag indicating whether the symbol error is corrected; a random error correction circuit configured to, in response to the syndrome having a non-zero value, perform a second ECC decoding on the read codeword set by using a second sub-check matrix and a third sub-check matrix, and generate a second error flag indicating at least one of whether the multi-bit error is corrected, whether the triple-bit error is detected, and whether a single-bit error is detected; and The decision circuit is configured to generate a decision signal indicating a result of the first ECC decoding and a result of the second ECC decoding based on the first error flag and the second error flag, and provide the decision signal to the processor.

6. The memory controller according to claim 5, wherein: The syndrome generator is configured as: generating a first sub-syndrome based on the read codeword set and a transpose of a first sub-check matrix included in the transposed matrix; generating a second sub-syndrome based on the read codeword set and the transposition of the second sub-check matrix included in the transposed matrix; and A third sub-syndrome is generated based on the read codeword set and the transposition of the third sub-check matrix included in the transposed matrix.

7. The memory controller according to claim 5, wherein: The symbol error correction circuit includes: an error size and error symbol position estimator configured to estimate the size of the symbol error and the position of the target symbol where the symbol error occurs based on a ratio of the second sub-syndrome to the first sub-syndrome; a symbol error corrector configured to generate a corrected user data set by correcting an error of a target symbol among a plurality of symbols of a read codeword set based on position information of the target symbol, and output an estimated first error vector based on the position information of the target symbol and a first sub-syndrome; and The error syndrome checker is configured to perform a first vector multiplication operation on the estimated first error vector and the transposed matrix, and to generate a first error flag based on a result of the first vector multiplication operation.

8. The memory controller according to claim 7, wherein: In response to the target alpha matrix not existing in the first alpha matrix, the error magnitude and error symbol location estimator is configured to output a first error flag indicating a first ECC decoding failure, the target alpha matrix matching a ratio of the second sub-syndrome to the first sub-syndrome.

9. The memory controller according to claim 7, in, In response to the presence of a target alpha matrix in the first alpha matrix, the error magnitude and error symbol location estimator is configured to estimate the symbol as a target symbol, the target alpha matrix matching a ratio of the second sub-syndrome to the first sub-syndrome, wherein the symbol corresponds to a value obtained by dividing an index of a target symbol by the number of bits in each of the plurality of symbols, and The symbol error corrector is configured to output an estimated first error vector by replacing a target symbol with a portion of the first sub-syndrome and setting each bit of the plurality of symbols except the target symbol to zero.

10. The memory controller according to claim 7, wherein: The error syndrome checker is configured to output a first error flag indicating that the first ECC decoding is successful in response to a result of the first vector multiplication operation matching the syndrome.

11. The memory controller according to claim 7, wherein: The error syndrome checker is configured to output a first error flag indicating a first ECC decoding failure in response to a result of the first vector multiplication operation being different from the syndrome.

12. The memory controller according to claim 5, wherein: Random error correction circuits include: a first syndrome value checker configured to determine whether a first summed value of syndrome values ​​of a first sub-syndrome is zero or two, and to generate a check signal indicative of a result of said determination; a second syndrome value checker configured to: in response to the first sum value being not zero and not two, determine whether the first sum value is one; in response to the first sum value being not one, output a second error flag indicating that the three-bit error is detected; and in response to the first sum value being one, output a second error flag indicating one of whether the three-bit error is detected and whether a single-bit error is detected based on the second sub-syndrome and the third sub-syndrome; a multi-bit error corrector configured to: estimate a location of the multi-bit error based on the second sub-syndrome and the third sub-syndrome in response to a check signal indicating that the first sum value is zero or two; generate a corrected user data set by correcting the multi-bit errors in the read codeword set based on the estimated location; estimate a second error vector based on the estimated location; and output the estimated second error vector; and The error syndrome checker is configured to perform a second vector multiplication operation on the estimated second error vector and the transposed matrix, and to generate a second error flag based on a result of the second vector multiplication operation.

13. The memory controller according to claim 12, wherein: The second syndrome value checker is configured to: In response to a result of cubing the second sub-syndrome matching the third sub-syndrome, outputting a second error flag indicating that the single bit error is detected; and In response to a result of cubing the second sub-syndrome being different from the third sub-syndrome, a second error flag indicating that the three-bit error is detected is output.

14. The memory controller according to claim 12, wherein: The multi-bit error corrector is configured to output an estimated second error vector by setting a first bit of a position corresponding to the multi-bit error in the read codeword set to a logic high level and by setting a second bit other than the first bit in the read codeword set to a logic low level.

15. The memory controller according to claim 12, wherein: The error correction subchecker is configured as: In response to a result of the second vector multiplication operation matching the syndrome, outputting a second error flag indicating that a two-bit error is corrected; and In response to a result of the second vector multiplication operation being different from the syndrome, a second error flag indicating that the three-bit error is detected is output.

16. The memory controller according to claim 1, wherein: The ECC engine also includes: an ECC encoder configured to generate parity data by performing ECC encoding on a user data set based on a parity generation matrix, and to send the user data set and the parity data to a memory module, The parity check generator matrix includes a first sub-generator matrix, a second sub-generator matrix and a third sub-generator matrix. The first sub-generator matrix includes a plurality of identity sub-matrices and a plurality of zero sub-matrices, the plurality of identity sub-matrices correspond to a plurality of symbols in the user data set, and the plurality of zero sub-matrices correspond to the plurality of identity sub-matrices. wherein the second sub-generator matrix includes a first alpha matrix corresponding to the bits of the plurality of symbols, the first alpha matrix having index values ​​that increase sequentially, and The third sub-generator matrix includes a second alpha matrix obtained by performing a cubing operation on each of the first alpha matrices.

17. A memory system comprising: A memory module comprising a plurality of data chips and at least one parity chip; as well as a memory controller configured to control the memory module, The memory controller includes: Error Correction Code (ECC) engine; and A processor configured to control an ECC engine, The ECC engine includes an ECC decoder, and the ECC decoder is configured as follows: performing a first ECC decoding to correct a symbol error in a read codeword set read from a memory module by using a first sub-check matrix and a second sub-check matrix of the parity check matrix; and In parallel with performing the first ECC decoding, performing a second ECC decoding by using a second sub-check matrix and a third sub-check matrix of the parity check matrix to correct a multi-bit error in the read codeword set and detect a triple-bit error in the read codeword set, Among them, the ECC decoder is configured as: generating a syndrome including a first sub-syndrome, a second sub-syndrome, and a third sub-syndrome based on a parity check matrix and a read codeword set; correcting the symbol error based on comparing the first sub-syndrome and the second sub-syndrome; and The multi-bit error is corrected and the triple error is detected based on a sum value obtained by summing the syndrome values ​​of the first sub-syndrome.

18. The memory system of claim 17, wherein: The ECC decoder is configured as: estimating a first error vector associated with the symbol error based on comparing the first subsyndrome and the second subsyndrome; generating a first error flag indicating a result of the first ECC decoding by performing a vector multiplication operation on an estimated first error vector and a transposed matrix of a parity check matrix; estimating a second error vector associated with the multi-bit error based on the summed value; and A second error flag associated with whether the multi-bit error is corrected is generated by performing a vector multiplication operation on the estimated second error vector and the transposed matrix.

19. The memory system of claim 17, wherein: The memory controller is configured to control the memory module by communicating with one or more hosts via a compute fast link interface, The first sub-check matrix and the second sub-check matrix are used to perform Reed-Solomon decoding corresponding to the first ECC decoding, and The second sub-check matrix and the third sub-check matrix are used to perform Bose-Chaudhuri-Hokkewenheim decoding corresponding to the second ECC decoding.

20. A memory controller configured to control a memory module including a plurality of data chips and at least one parity chip by communicating with one or more hosts via a computing fast link interface, the memory controller comprising: Error correction code ECC engine; as well as A processor configured to control an ECC engine, The ECC engine includes an ECC decoder, and the ECC decoder is configured as follows: performing a first ECC decoding to correct a symbol error in a read codeword set read from a memory module by using a first sub-check matrix and a second sub-check matrix of the parity check matrix; and In parallel with performing the first ECC decoding, performing a second ECC decoding by using a second sub-check matrix and a third sub-check matrix of the parity check matrix to correct a multi-bit error in the read codeword set and detect a triple-bit error in the read codeword set, Among them, the ECC decoder is configured as: generating a syndrome including a first sub-syndrome, a second sub-syndrome, and a third sub-syndrome based on the parity check matrix and the read codeword set; correcting the symbol error based on comparing the first sub-syndrome and the second sub-syndrome; and correcting the multi-bit error and detecting the triple error based on a sum value obtained by summing the syndrome values ​​of the first sub-syndrome, wherein the first ECC decoding corresponds to Reed-Solomon decoding, and Among them, the second ECC decoding corresponds to Bose-Chaudhuri-Hokwenheim decoding.

Images