PCIe endpoint device link debugging method and device based on FPGA

Abstract

The invention provides a PCIe (Peripheral Component Interconnect Express) endpoint equipment link debugging method and device based on an FPGA (Field Programmable Gate Array), a state machine, a thermal reset counter and a register are designed in the FPGA, and firmware of an upper computer initiates PCIe endpoint equipment link training; if the training fails, the upper computer initiates hot reset to the PCIe endpoint device; and when the state machine receives the hot reset signal, the configuration information of the register is adjusted according to the counting of the hot reset counter, and the PCIe endpoint equipment link is subjected to equalization, transmission rate adjustment and channel number adjustment. According to the method, the programmable characteristic of the FPGA is utilized, a state machine and a counter are designed in the FPGA, aiming at the signal integrity problem in the link, the signal integrity problem of the PCIe link is quickly positioned through the methods that the FPGA state machine sets a register and adjusts PCIe endpoint equipment balance, rate, channel number and the like, and the signal integrity problem of the PCIe link is quickly positioned in a mode of shielding part of problems. And the link system can be continuously debugged.

Description

Technical Field

[0001] The present invention relates to the field of communication link debugging, and more specifically, to a method and device for debugging a PCIe endpoint device link based on an FPGA. Background Art

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard, which is designed to replace the traditional PCI interface to provide higher bandwidth and speed while maintaining backward compatibility. PCIe adopts a point-to-point architecture to achieve high-speed data transmission. Each device has an independent channel and does not share the bus bandwidth, significantly improving the data transmission efficiency and the overall system performance. Currently, after years of development, the PCIe bus technology has evolved from the initial version 1.0 to version 6.0, and the transmission rate has increased from the initial 2.5 GT / s to 64 GT / s, and it is widely used in peripherals such as graphics cards, sound cards, and network cards.

[0003] Due to the point-to-point transmission method, PCIe devices are divided into Root Complex (root complex), Bridge (bridge device), Switch (PCIe-PCIe bridge), and EndPoint (endpoint device); different devices are connected through connectors (such as gold fingers) and cables (such as PCIe extension cables). As the transmission rate of PCIe becomes higher and higher, the signal integrity problem of the connection between PCIe devices becomes more prominent, and the debugging work of the PCIe link becomes more important accordingly. Summary of the Invention

[0004] The present invention provides a method and device for debugging a PCIe endpoint device link based on an FPGA to solve the technical problems existing in the prior art.

[0005] According to the first aspect of the present invention, there is provided a method for debugging a PCIe endpoint device link based on an FPGA. The PCIe endpoint device link refers to multiple links formed between a PCIe endpoint device and other PCIe devices. Both the PCIe endpoint device and other PCIe devices are integrated in the FPGA. A state machine, a thermal reset counter, and registers are designed in the FPGA. The method includes:

[0006] Step 1, the host computer firmware initiates the training of the PCIe endpoint device link;

[0007] Step 2, if the training of the PCIe endpoint device link fails, the host computer sends a thermal reset signal to the PCIe endpoint device;

[0008] Step 3, when the state machine of the PCIe endpoint device receives the thermal reset signal, adjust the configuration information of the register according to the number of thermal resets counted in the thermal reset counter. The configuration information includes equalization configuration information, transmission rate configuration information, or channel number configuration information for the PCIe endpoint device link, so as to adjust the PCIe endpoint device link according to the configuration information of the register.

[0009] Based on the above technical solution, the present invention can also be improved as follows.

[0010] Optionally, step 3 includes:

[0011] Step 31, when the state machine of the PCIe endpoint device receives the thermal reset signal, increment the thermal reset counter by 1;

[0012] Step 32, the state machine adjusts the equalization configuration information in the register according to the count in the thermal reset counter to perform equalization configuration on the PCIe endpoint device link. After the equalization configuration, return to step 1 and step 2;

[0013] Step 33, if the PCIe endpoint device link training still fails, the host computer sends a thermal reset signal to the PCIe endpoint device again, and the thermal reset counter is incremented by 1;

[0014] Step 34, the state machine adjusts the transmission rate configuration information in the register according to the count in the thermal reset counter to adjust the transmission rate of the PCIe endpoint device link. After the transmission rate adjustment, return to step 1 and step 2;

[0015] Step 35, if the PCIe endpoint device link training still fails, the host computer sends a thermal reset signal to the PCIe endpoint device again, and the thermal reset counter is incremented by 1;

[0016] Step 36, the state machine adjusts the channel number configuration information in the register according to the count in the thermal reset counter to adjust the channel number of the PCIe endpoint device link. After the channel number adjustment, return to step 1 and step 2 until the PCIe endpoint device link training is successful.

[0017] Optionally, in step 34, the state machine adjusts the transmission rate configuration information in the register according to the count in the thermal reset counter, including:

[0018] The state machine reduces the transmission rate of the PCIe endpoint device link through register configuration according to the count in the thermal reset counter.

[0019] Optionally, in step 36, the state machine adjusts the channel number configuration information in the register according to the count in the thermal reset counter, including:

[0020] The state machine reduces the number of channels in the PCIe endpoint device link according to the count in the thermal reset counter through register configuration.

[0021] According to a second aspect of the present invention, there is provided a PCIe endpoint device link debugging device based on FPGA. The device includes an FPGA, in which a PCIe endpoint device and other PCIe devices are integrated. The PCIe endpoint device link refers to multiple links formed between the PCIe endpoint device and other PCIe devices. The FPGA includes a state machine, a thermal reset counter, and a register;

[0022] The host computer firmware initiates the PCIe endpoint device link training;

[0023] If the PCIe endpoint device link training fails, the host computer sends a thermal reset signal to the PCIe endpoint device;

[0024] When the state machine of the PCIe endpoint device receives the thermal reset signal, it adjusts the configuration information of the register according to the number of thermal resets counted in the thermal reset counter. The configuration information includes equalization configuration information, transmission rate configuration information, or channel number configuration information for the PCIe endpoint device link, so as to adjust the PCIe endpoint device link according to the configuration information of the register.

[0025] A PCIe endpoint device link debugging method and device provided by the present invention design a state machine, a thermal reset counter, and a register in the FPGA. The host computer firmware initiates the PCIe endpoint device link training; if the training fails, the host computer sends a thermal reset to the PCIe endpoint device; when the state machine receives the thermal reset signal, it adjusts the configuration information of the register according to the count of the thermal reset counter, and adjusts the equalization, transmission rate, and channel number of the PCIe endpoint device link. The present invention utilizes the programmable characteristics of the FPGA, designs a state machine and a counter in the FPGA, and aims at the signal integrity problem in the link. By setting the register through the FPGA state machine, methods such as adjusting the equalization, rate, and channel number of the PCIe endpoint device are used to quickly locate the signal integrity problem of the PCIe link, and by shielding some problems, it is ensured that the link system can continue to be debugged. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the interconnection relationship between PCIe devices;

[0027] Figure 2 Flowchart of a PCIe endpoint device link debugging method based on FPGA provided by the present invention;

[0028] Figure 3 Overall flowchart for PCIe endpoint device link debugging;

[0029] Figure 4 Schematic diagram of a PCIe endpoint device link debugging device based on FPGA. Specific implementation manners

[0030] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. In addition, the technical features in each embodiment or a single embodiment provided by the present invention can be combined with each other arbitrarily to form a feasible technical solution. Such combination is not restricted by the order of steps and / or the mode of structural composition, but must be based on the fact that those of ordinary skill in the art can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0031] Refer to Figure 1 , which shows the interconnection relationship between PCIe devices. Among them, the PCIe endpoint device link is composed of multiple channels (Lanes). A Lane is a combination of a group of differential signals, including a transmit channel and a receive channel. The differential signals of the transmit channel include two signals, Tx+ and TX-, and the differential signals of the receive channel include two signals, RX+ and RX-. Transmission and reception are carried out simultaneously, that is, it supports the full-duplex working mode. The PCIe standard usually supports X1, X4, X8, X16 (i.e., 1 Lane, 4 Lanes, 8 Lanes, 16 Lanes). The more the number of Lanes, the higher the bandwidth. At the same time, the PCIe channel number is downward compatible. For example, an X16 device can be compatible with an X1 device, and so on.

[0032] The PCIe transmission rate has evolved from the early 2.5 GT / s to 64 GT / s in the 6.0 standard. With the increase in transmission rate, many signal integrity issues have become more prominent. There are much fewer signal integrity problems at low frequencies. At the same time, the PCIe standard organization has also realized the signal integrity problems brought about by the continuous increase in rate. Since the PICe 3.0 standard, an equalization process has been introduced and the corresponding standard register (Link Control Register 3) has been specified to alleviate the signal integrity problems after the rate exceeds 8 GT / s.

[0033] FPGA PCIe EndPoint devices usually need to adapt to different Root Complex / Bridge / Switch. There are significant differences in connectors, cables, and PCB layout and wiring. As the PCIe rate continues to climb, more and more signal integrity problems will be faced.

[0034] Currently, the most common debugging method for signal integrity problems encountered in PCIe link training is the eye diagram. Some PCIe-related integrated circuits integrate an eye diagram acquisition circuit inside. However, due to the limited acquisition depth of the internal circuit, it often cannot accurately reflect the actual situation, especially some occasional transmission errors. At the same time, there are significant differences between the internal electromagnetic environment and the external electromagnetic environment of the integrated circuit. Therefore, the internal eye diagram acquisition of PCIe-related integrated circuits is not completely reliable. In addition, most current FPGA chips do not integrate an eye diagram acquisition circuit. And external eye diagram acquisition is often achieved through a high-speed oscilloscope. There will also be corresponding problems with the high-speed oscilloscope collecting the eye diagram. For example, using an oscilloscope to collect the eye diagram often requires a PCIe adapter. Once the PCIe device uses a non-standard gold finger connector (such as CPCI-E or MXM, etc.), it will be very troublesome. Introducing an additional adapter board itself will exacerbate the signal integrity problem. Moreover, the eye diagram method can only assist in determining the eye diagram problem and cannot solve the FPGA PCIe link problem in a short time, and the system debugging still cannot proceed normally.

[0035] Based on this, the present invention provides a method for debugging the PCIe endpoint device link based on FPGA. Utilizing the programmable characteristics of FPGA, the problems of the PCIe link can be quickly determined by simply adjusting the PCIe path equalization, the number of channels, the link speed, etc. through a hardware state machine. And when the signal integrity problems of the FPGA PCIe link are not completely solved, it supports other function debugging of the link system.

[0036] See Figure 2, is a flowchart of a method for debugging the link of a PCIe endpoint device based on FPGA. Among them, the PCIe endpoint device and other PCIe devices are both integrated in the FPGA. A state machine, a thermal reset counter, and registers are designed in the FPGA. The debugging method mainly includes the following steps:

[0037] Step 1, the host computer firmware initiates the link training of the PCIe endpoint device;

[0038] Step 2, if the link training of the PCIe endpoint device fails, the host computer sends a thermal reset signal to the PCIe endpoint device;

[0039] Step 3, when the state machine of the PCIe endpoint device receives the thermal reset signal, according to the number of thermal resets counted in the thermal reset counter, adjust the configuration information of the register. The configuration information includes the equalization configuration information, the transmission rate configuration information, or the channel number configuration information of the PCIe endpoint device link, so as to adjust the PCIe endpoint device link according to the configuration information of the register.

[0040] It can be understood that due to signal integrity problems, involving multiple factors such as connectors, PCB design, and cables, the present invention can locate the signal problems caused by the above factors and avoid them to ensure the progress of system debugging. However, it cannot completely solve the signal integrity of the PCIe link. Completely solving the signal integrity problem of the PCIe link requires continuous system-level analysis and debugging.

[0041] In summary, the present invention aims at the link debugging problem of multi-link and high-rate PCIe endpoint devices. A state machine and a thermal reset counter are designed inside the FPGA. The current debugging state is confirmed through the thermal reset counter, and then the equalization, rate, and channel number of the FPGA PCIe endpoint device register are adjusted through the state machine to initially diagnose the signal integrity problem of the PCIe endpoint device link and mask the problem to ensure that the system can continue debugging.

[0042] Among them, the overall flowchart of the PCIe endpoint device link debugging can be seen in Figure 3 , and the specific steps include:

[0043] Step 1, the PCIe device link system is powered on and reset, and the host computer firmware initiates the link training of the PCIe endpoint device to establish a link between the PCIe endpoint device and other PCIe devices;

[0044] Step 2, if the link training of the PCIe endpoint device fails, the host computer sends a thermal reset signal to the PCIe endpoint device;

[0045] Step 31, when the state machine of the PCIe endpoint device receives a thermal reset signal, the thermal reset counter is incremented by 1, and the thermal reset counter counts the number of thermal reset signals sent by the host computer;

[0046] Step 32, the state machine adjusts the equalization configuration information in the register according to the count in the thermal reset counter to perform equalization configuration on the PCIe endpoint device link. After the equalization configuration, return to Steps 1 and 2 to continue training the PCIe endpoint device link;

[0047] Step 33, if the training of the PCIe endpoint device link still fails, the host computer sends a thermal reset signal to the PCIe endpoint device again, and the thermal reset counter is incremented by 1;

[0048] Step 34, the state machine adjusts the transmission rate configuration information in the register according to the count in the thermal reset counter to adjust the transmission rate of the PCIe endpoint device link. After the transmission rate adjustment, return to Steps 1 and 2 to continue training the PCIe endpoint device link;

[0049] Step 35, if the training of the PCIe endpoint device link still fails, the host computer sends a thermal reset signal to the PCIe endpoint device again, and the thermal reset counter is incremented by 1;

[0050] Step 36, the state machine adjusts the channel number configuration information in the register according to the count in the thermal reset counter to adjust the channel number of the PCIe endpoint device link. After the channel number adjustment, return to Steps 1 and 2, repeat the adjustment of equalization, transmission rate, and channel number of the PCIe endpoint device link, and continue to train the PCIe endpoint device link until the training of the PCIe endpoint device link is successful.

[0051] Among them, in Step 32, the state machine adjusts the equalization configuration information in the register according to the count in the thermal reset counter, mainly by configuring the Perform Equalization field of the Link Control 3 Register in the Secondary PCI Express Extended Capability of the PCIe EndPoint and Root Complex / Switch / Bridge to 1, aiming to adjust the equalization parameters of the sending end of the PCIe link brightness. It should be noted that equalization is only valid for links above PCIe 3.0.

[0052] Among them, in step 34, the state machine adjusts the transmission rate configuration information in the register according to the count in the thermal reset counter, mainly by reducing the transmission rate of the PCIe endpoint device link through register configuration. Reducing the transmission rate of the PCIe endpoint device can be achieved by configuring the Max Link Speed field of the LnkCap register of the PCIe EndPoint device. Some Root Complex / Switch / Bridge devices can also limit the maximum speed of the PCIe link through firmware configuration.

[0053] Among them, in step 36, the state machine adjusts the channel number configuration information in the register according to the count in the thermal reset counter, mainly by configuring the Maximum Link Width field of the LnkCap register of the PCIe EndPoint device. Some Root Complex / Switch / Bridge devices can also configure the number of channels of the PCIe link through firmware. In actual debugging, it can also be achieved by selecting a connector with only some channels (for example, selecting the gold finger slots of X1, X4, X8).

[0054] It should be noted that the thermal reset counter on the FPGA side is cleared to 0 during power-on reset and incremented by 1 each time the host computer sends a thermal reset. The state machine selects to configure balance, rate, or channel number and the specific configured values according to the value of the thermal reset counter.

[0055] The three methods of equalization, speed reduction, and channel number reduction in the present invention complement each other. In actual debugging, they can be flexibly used according to the situation, iterated repeatedly, and the equalization configuration, transmission rate, and link channel number of the link can be modified according to the debugging status of the PCIe endpoint device. It should be noted that in the foregoing embodiments, the order of adjusting the equalization information, transmission rate, and channel number of the PCIe endpoint device link is as follows. In practice, the order of adjusting the equalization information, transmission rate, and channel number is not limited. The idea of the present invention is to continuously adjust the equalization information, transmission rate, or channel number of the PCIe endpoint device link until the PCIe endpoint device link is successfully established. For example, when enabling equalization for a certain FPGA PCIe EndPoint device and reducing the transmission rate to PCIe Gen1 still fails, but reducing the PCIe channel number to 1 results in successful training. At this time, it can be generally judged that the link training failure is caused by the signal integrity of some channels. It is still possible to return to step 34 and try to increase the PCIe rate to a certain extent to facilitate further determination of the problem. At the same time, it can also improve the performance and efficiency of system debugging after masking the problem. And so on for others. For example, PCIe can be reduced in speed from 6.0, 5.0, 4.0, 3.0, 2.0, 1.0 in sequence, and the channel number can be reduced from X16, X8, X4, X1 in sequence, and so on. These debugging combinations can be iterated repeatedly to facilitate problem location.

[0056] See Figure 4 , a PCIe endpoint device link debugging device provided by the present invention. The debugging device includes an FPGA. The PCIe endpoint device and other PCIe devices are integrated in the FPGA. The PCIe endpoint device link refers to multiple links formed between the PCIe endpoint device and other PCIe devices. The FPGA includes a state machine, a thermal reset counter, and registers.

[0057] The working process of the PCIe endpoint device link debugging device is as follows: The host computer firmware initiates PCIe endpoint device link training; if the PCIe endpoint device link training fails, the host computer sends a thermal reset signal to the PCIe endpoint device; when the state machine of the PCIe endpoint device receives the thermal reset signal, according to the number of thermal resets counted in the thermal reset counter, the configuration information of the register is adjusted. The configuration information includes the equalization configuration information, transmission rate configuration information, or channel number configuration information of the PCIe endpoint device link, so as to adjust the PCIe endpoint device link according to the configuration information of the register.

[0058] It can be understood that the method of debugging the PCIe endpoint device link using the PCIe endpoint device link debugging device can refer to the PCIe endpoint device link debugging method provided in the foregoing embodiments, and will not be repeated here.

[0059] A method and device for link debugging of a PCIe endpoint device based on FPGA provided by an embodiment of the present invention utilize the programmable characteristics of the FPGA to implant a state machine and a thermal reset counter in the FPGA PCIe endpoint device. At the same time, the PCIe registers are configured through the state machine to adjust the equalization, transmission rate, and number of channels of the PCIe endpoint device link, so as to diagnose and shield signal integrity problems in the PCIe endpoint device link. The debugging method has the characteristics of simplicity, high efficiency, and automation; at the same time, by reducing the speed and the number of channels, the communication of the link is ensured, and the system can continue to conduct in-depth functional debugging without completely solving the signal integrity of the link (solving signal integrity problems often requires remaking the PCB board), which improves the efficiency of system debugging.

[0060] It should be noted that in the above embodiments, the descriptions of each embodiment have their own emphases. For parts not detailedly described in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0061] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can be implemented in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can be implemented in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0062] The present invention is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram, can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for realizing the functions specified in Figure 1 one or more flows and / or blocks Figure 1 one or more blocks.

[0063] These computer program instructions can also be stored in a computer-readable memory capable of guiding a computer or other programmable data processing devices to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device realizes the functions in Figure 1 one or more flows and / or blocks Figure 1The functions specified in one or more boxes.

[0064] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide for implementing the steps of the functions specified in one Figure 1 process or multiple processes and / or boxes Figure 1 or more boxes.

[0065] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concept. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0066] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A PCIe endpoint device link debugging method based on FPGA, characterized in that: The PCIe endpoint device link refers to a plurality of links formed between the PCIe endpoint device and other PCIe devices, the PCIe endpoint device and other PCIe devices are integrated into an FPGA, a state machine, a hot reset counter and a register are designed in the FPGA, and the method includes: Step 1, the host computer firmware initiates the PCIe endpoint device link training; Step 2: If the link training of the PCIe endpoint device fails, the host computer sends a hot reset signal to the PCIe endpoint device; Step 3, when the state machine of the PCIe endpoint device receives the hot reset signal, the configuration information of the register is adjusted according to the number of hot resets counted in the hot reset counter, and the configuration information includes the balance configuration information, transmission rate configuration information or channel quantity configuration information of the PCIe endpoint device link, so as to adjust the PCIe endpoint device link according to the configuration information of the register.

2. The PCIe endpoint device link debugging method according to claim 1, characterized in that: Step 3 includes: Step 31, when the state machine of the PCIe endpoint device receives the hot reset signal, the hot reset counter is incremented by 1; Step 32, the state machine adjusts the balancing configuration information in the register according to the count in the hot reset counter to perform balancing configuration on the PCIe endpoint device link, and after balancing configuration, returns to steps 1 and 2; Step 33, if the link training of the PCIe endpoint device still fails, the host computer sends a hot reset signal to the PCIe endpoint device again, and the hot reset counter increases by 1; Step 34, the state machine adjusts the transmission rate configuration information in the register according to the count in the hot reset counter to adjust the transmission rate of the PCIe endpoint device link, and after the transmission rate is adjusted, returns to step 1 and step 2; Step 35, if the link training of the PCIe endpoint device still fails, the host computer sends a hot reset signal to the PCIe endpoint device again, and the hot reset counter increases by 1; Step 36, the state machine adjusts the channel quantity configuration information in the register according to the count in the hot reset counter to adjust the channel quantity of the PCIe endpoint device link. After the channel quantity is adjusted, return to steps 1 and 2 until the PCIe endpoint device link training is successful.

3. The PCIe endpoint device link debugging method according to claim 2, characterized in that: In step 34, the state machine adjusts the transmission rate configuration information in the register according to the count in the hot reset counter, including: The state machine reduces the transmission rate of the PCIe endpoint device link through register configuration according to the count in the hot reset counter.

4. The PCIe endpoint device link debugging method according to claim 2, characterized in that: The step 36, wherein the state machine adjusts the channel quantity configuration information in the register according to the count in the hot reset counter, includes: The state machine reduces the number of channels in the PCIe endpoint device link through register configuration according to the count in the hot reset counter.

5. A PCIe endpoint device link debugging device based on FPGA, characterized in that: The device comprises an FPGA, in which a PCIe endpoint device and other PCIe devices are integrated, wherein the PCIe endpoint device link refers to a plurality of links formed between the PCIe endpoint device and other PCIe devices, and the FPGA comprises a state machine, a hot reset counter and a register; The host computer firmware initiates the PCIe endpoint device link training; If the link training of the PCIe endpoint device fails, the host computer sends a hot reset signal to the PCIe endpoint device; When the state machine of the PCIe endpoint device receives the hot reset signal, the configuration information of the register is adjusted according to the number of hot resets counted in the hot reset counter, and the configuration information includes the balance configuration information, transmission rate configuration information or channel quantity configuration information of the PCIe endpoint device link, so as to adjust the PCIe endpoint device link according to the configuration information of the register.

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