Software and hardware joint debugging method based on IPC, electronic equipment and medium

Abstract

The invention relates to the technical field of chips, in particular to an IPC-based software and hardware joint debugging method, electronic equipment and a medium, and the method comprises the following steps: S1, obtaining N software test case sets needing to run on a to-be-tested chip design in parallel; s2, allocating a corresponding process group (B1n, B2n) to each An, and allocating a corresponding interaction identifier Pn to each process group based on an IPC protocol; s3, all B1n are started in parallel, each B1n starts to execute the corresponding An, meanwhile, chip initialization operation is conducted through chip RTL codes, and the B1n generates register configuration instructions corresponding to the An based on the corresponding An and enters a waiting state; and S4, after chip initialization operation of the to-be-tested chip design is completed, B1n and B2n perform inter-process communication based on the corresponding Pn, and An runs on the to-be-tested chip design. According to the method, the cross-stage verification cost of the software test case is reduced, and the chip verification efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular, to a software and hardware co-verification method, an electronic device, and a medium based on IPC. Background Art

[0002] During the chip development process, different chip verification stages need to be experienced. Usually, hardware-level verification is first performed based on the chip RTL (Register Transfer Level) code. After basic hardware verification, a chip hardware accelerator or a physical chip will be obtained. Then, system-level verification is performed based on the hardware accelerator or the physical chip. After system-level verification passes, software-level verification is performed based on the accelerator or the physical chip. In the prior art, different verification platforms need to be developed for different stages. Only test cases for the corresponding stage can be verified between different verification platforms, and cross-stage test case verification cannot be achieved. However, there is a need to run software test cases on the chip RTL code during the chip development process. For example, when a problem occurs when a software test case is run on a software test platform, it is desired to run the same software test case on the chip RTL code for verification to facilitate debugging. Usually, software test cases may be very complex and there is a need for parallel operation. If the verification on the chip RTL code is achieved by writing corresponding hardware test cases for software test cases, it will cost a lot and the verification efficiency is low. It can be seen that how to directly run software test cases on the chip RTL code, reduce the cross-stage verification cost of software test cases, and improve the chip verification efficiency has become an urgent technical problem to be solved. Summary of the Invention

[0003] The purpose of the present invention is to provide a software and hardware co-verification method, an electronic device, and a medium based on IPC, which realize the running of software use cases on the chip RTL code through software and hardware co-verification, reduce the cross-stage verification cost of software test cases, and improve the chip verification efficiency.

[0004] According to the first aspect of the present invention, a software and hardware co-verification method based on IPC is provided, including:

[0005] Step S1, obtaining N software test case sets {A 1 , A 2 ,..., A n ,..., A N} that need to be run in parallel on the to-be-tested chip design, where A n is the nth software test case, and the value range of n is from 1 to N. The to-be-tested chip design is implemented based on RTL code;

[0006] Step S2, allocating a corresponding process group (B n for each A 1n , B 2 n ), B 1 n is A n corresponding first process, B 2 n is A n corresponding second process, and allocate corresponding interaction identifier P for each process group based on the IPC protocol n , where the IPC protocol is an inter - process communication protocol;

[0007] Step S3, start all Bs in parallel 1 n , each B 1 n starts to execute the corresponding A n , and at the same time, the chip RTL code performs chip initialization operations, B 1 n Based on the corresponding A n generate the register configuration instructions corresponding to A n and enter the waiting state;

[0008] Step S4, after the chip under test design completes the chip initialization operation, B 1 n , B 2 n Based on the corresponding P n perform inter - process communication and run A n on the chip under test design.

[0009] According to a second aspect of the present invention, there is provided an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the first aspect of the present invention.

[0010] According to a third aspect of the present invention, there is provided a computer - readable storage medium storing computer - executable instructions, and the computer instructions are used to execute the method described in the first aspect of the present invention.

[0011] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above - mentioned technical solutions, a software - hardware co - debugging method, an electronic device and a medium based on IPC provided by the present invention can achieve considerable technical progress and practicality, and have wide industrial utilization value. It has at least the following beneficial effects:

[0012] Based on dual - process communication, the present invention realizes directly running software test cases on the verification of the chip design to be tested implemented by RTL code, and through multiple groups of parallel dual - processes, realizes the parallel running of software test cases in the software test case set on the verification of the chip design to be tested without changing the software test cases, reducing the cross - stage verification cost of software test cases and improving the chip verification efficiency. Description of the Drawings

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for description in the embodiments. Obviously, the following - described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0014] Figure 1 It is a flowchart of the software - hardware co - debugging method based on IPC provided by the embodiment of the present invention. Detailed Embodiments

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0016] The embodiment of the present invention provides a software - hardware co - debugging method based on IPC, as Figure 1 shown, including:

[0017] Step S1, obtain N software test case sets {A 1 , A 2 ,..., A n ,..., A N} that need to be run in parallel on the chip design to be tested, where A n is the nth software test case, and the value range of n is from 1 to N. The chip design to be tested is implemented based on RTL code.

[0018] It should be noted that the software test case set can specifically be a software test case set for regression testing or a set composed of other software test cases with parallel running requirements. The RTL code can specifically be code generated based on Verilog language or SystemVerilog language.

[0019] Step S2, allocate a corresponding process group (B n , B 1 n , B2 n ) and B 1 n is A n the corresponding first process, B 2 n is A n the corresponding second process, and allocate a corresponding interaction identifier P for each process group based on the IPC protocol n , and the IPC protocol is the Inter-Process Communication protocol (IPC for short), which specifically refers to the protocol for data exchange and information transfer between different processes in a computer system.

[0020] It should be noted that each process group has a unique interaction identifier P n , and each process group binds two processes through the corresponding interaction identifier P n and realizes IPC communication between the two processes based on P n

[0021] Step S3: Start all Bs in parallel 1 n , and each B 1 n starts to execute the corresponding A n , and at the same time, the chip RTL code performs chip initialization operations, B 1 n generates the register configuration instruction corresponding to A based on the corresponding A n and enters the waiting state. n

[0022] It should be noted that B 1 n corresponds to pure software operations, B 2 n which is used to interact with the chip design under test and needs to be implemented based on hardware. When the system starts, the hardware usually needs to perform chip initialization operations first before subsequent interaction operations can be carried out. Chip initialization specifically includes hardware initialization, system power-on, reset release, etc. Therefore, B 1 n should execute faster than B 2 n . When each B 1 n starts, it begins to execute the corresponding A n , B 1 n generates the register configuration instruction corresponding to A based on the corresponding A n and n ​​The corresponding register configuration instruction requires implementing register configuration based on the chip under test. At this time, it is necessary to wait for the chip under test to complete chip initialization. Therefore, B 1 n Enter the waiting state.

[0023] Step S4: After the chip under test completes the chip initialization operation, B 1 n and B 2 n Based on the corresponding P n Perform inter-process communication to run A n on the chip under test design.

[0024] It should be noted that after the chip initialization operation is completed, B 1 n and B 2 n can generate interaction information carrying P n for inter-process communication, so as to realize running the software test case A n on the chip under test design for verification without changing the software test case.

[0025] As an embodiment, step S3 includes:

[0026] Step S31: B 1 n Parse the corresponding A n to obtain the operation parameters and operation logic corresponding to A n

[0027] It should be noted that the operation parameters can be the original operation parameters and original operation logic corresponding to the test case. The operation parameters can also be the original operation parameters and intermediate operation parameters obtained based on the original operation parameters, and the operation logic can be the original operation logic and intermediate operation logic obtained based on the original operation logic.

[0028] Step S32: B 1 n Obtain the memory information of the chip under test design, and allocate memory addresses for the operation parameters corresponding to A n based on the memory information of the chip under test design.

[0029] It should be noted that B 1 n can allocate corresponding memory addresses for each operation parameter based on the required memory size of the operation parameter and the current memory resources by calling the driver module. The driver module can obtain all resource information of the current chip under test design, such as memory size, register type, engine resources, etc.

[0030] ​Step S33, B 1 n Based on A n The corresponding operation parameters and A n Generate A based on the memory addresses allocated for the corresponding operation parameters n The corresponding register configuration instructions, and the A n The corresponding register configuration instructions include A n The interaction identifier P corresponding to the corresponding process group n .

[0031] As an embodiment, the step S4 includes:

[0032] Step S41, after the chip under test completes the chip initialization operation, B 1 n Send the A n The corresponding register configuration instructions to B through the IPC interface 2 n .

[0033] It should be noted that after the chip under test completes the chip initialization operation, it can interact with B 2 n with B 1 n for interaction

[0034] Step S42, B 2 n Based on A n The corresponding register configuration instructions perform register configuration operations on the chip under test

[0035] It should be noted that B 2 n Receives the A 1 n Sent by B n The corresponding register configuration instructions. The original A n The corresponding register configuration instructions are generated based on the software language and cannot be directly executed on the chip under test. Through language conversion, register configuration operations are implemented on the chip under test

[0036] Step S43, B 1 n After the execution of the A n The corresponding register configuration instructions are completed, based on each A n The corresponding operation parameters and register configuration information generate A n The corresponding data transfer instructions and send them to B through the IPC interface 2 n , A nThe corresponding data transfer instruction includes A n The interaction identifier P corresponding to the corresponding process group n 。

[0037] It should be noted that after the register configuration is completed, each A n The corresponding operation parameters need to be stored in the memory corresponding to the chip design under test. Therefore, based on each A n The corresponding operation parameters and register configuration information are used to generate A n The corresponding data transfer instruction, and sent to B through the IPC interface 2 n 。

[0038] Step S44, B 2 n Based on A n The corresponding data transfer instruction stores the corresponding operation parameters of A in the memory corresponding to the chip design under test on the chip design under test n 。

[0039] It should be noted that the original A n The corresponding data transfer instruction B 2 n Generated based on the software language and cannot be directly executed on the chip design under test. Through language conversion, the corresponding operation parameters of A are stored in the memory corresponding to the chip design under test n 。

[0040] Step S45, B 1 n After the execution of the corresponding data transfer instruction of A n Based on the corresponding operation logic of A n Generate the corresponding doorbell instruction of A n And send it to B through the IPC interface 2 n ,A n The corresponding doorbell instruction of A includes A n The interaction identifier P corresponding to the corresponding process group n 。

[0041] Step S46, B 2 n Based on the corresponding doorbell instruction of A and the corresponding operation parameters of A stored in the memory of the chip design under test n Execute the corresponding operation logic of A on the chip design under test n Generate A n The operation result running on the chip design under test n 。

[0042] It should be noted that the original An The corresponding doorbell instruction is generated based on a software language and cannot be directly executed on the chip design under test. Through language conversion, it is realized to execute A on the chip design under test. n The corresponding arithmetic logic.

[0043] As an embodiment, the step S42 includes:

[0044] Step S421, B 2 n Convert the register configuration instruction corresponding to A into a register configuration instruction implemented in SystemVerilog corresponding to A through the Direct Programming Interface (DPI for short). n The corresponding register configuration instruction is converted into a register configuration instruction implemented in SystemVerilog corresponding to A. n The corresponding register configuration instruction implemented in SystemVerilog.

[0045] Among them, DPI is a standard interface that allows SystemVerilog code to directly call C or C++ functions, and vice versa. DPI allows data and control information to be transferred between the two languages. Therefore, based on DPI, the conversion between the software language and the SystemVerilog language can be realized, which will not be elaborated here.

[0046] Step S422, B 2 n Based on the register configuration instruction implemented in SystemVerilog corresponding to A, perform a register configuration operation on the chip design under test. n The corresponding register configuration instruction implemented in SystemVerilog corresponding to A performs a register configuration operation on the chip design under test.

[0047] As an embodiment, the step S44 includes:

[0048] Step S441, B 2 n Convert the data transfer instruction corresponding to A into a data transfer instruction implemented in SystemVerilog corresponding to A through the direct programming interface. n The corresponding data transfer instruction is converted into a data transfer instruction implemented in SystemVerilog corresponding to A. n The corresponding data transfer instruction implemented in SystemVerilog.

[0049] Step S442, B 2 n Based on the data transfer instruction implemented in SystemVerilog corresponding to A, store the corresponding operation parameters of A in the memory corresponding to the chip design under test. n The corresponding data transfer instruction implemented in SystemVerilog corresponding to A stores the corresponding operation parameters of A in the memory corresponding to the chip design under test. n The corresponding operation parameters are stored in the memory corresponding to the chip design under test.

[0050] As an embodiment, the step S46 includes:

[0051] Step S461, B 2 nConvert A through a direct programming interface n The corresponding doorbell instruction into the A implemented in SystemVerilog n The corresponding doorbell instruction

[0052] Step S462, B 2 n Based on A n The corresponding doorbell instruction implemented in SystemVerilog and the A stored in the memory of the chip design under test n The corresponding operation parameters execute A on the chip design under test n The corresponding operation logic, generating A n The operation result running on the chip design under test

[0053] It should be noted that through the direct programming interface, the instructions implemented based on the software language can be converted into the instructions implemented in SystemVerilog that can be executed on the chip design under test. Conversely, if the chip design under test needs to generate instructions to be returned to B 1 n Since the instructions of the chip design under test are implemented based on the hardware language, they also need to be first converted into instructions implemented in the software language through the direct programming interface and then passed to B 1 n The software language can specifically be C language, C++ language, etc

[0054] B 1 n Judge whether the corresponding operation of B 2 n is completed, and there are at least the following two implementation methods

[0055] Implementation method 1

[0056] B 1 n Judge whether the corresponding operation is completed by obtaining the completion instruction sent by B 2 n The completion instruction includes the interaction identifier P corresponding to the process group corresponding to A n The completion instruction is the chip initialization operation completion instruction, the register configuration completion instruction, and the data transfer completion instruction. That is, after B n completes the operation, generates the corresponding operation completion instruction, converts it into the completion instruction implemented in the software language through the direct programming interface, and then feeds it back to B through the IPC interface 2 n After B 1 n receives the completion instruction, determines B 1 n After receiving the completion instruction, determine B 2n The corresponding operation is completed, B 1 n Continue to perform subsequent instruction generation operations.

[0057] Embodiment 2

[0058] Set the number of requests that can be sent in the IPC interface to 1, B 1 n After generating an instruction, store it in the IPC interface. When B 2 n After taking the currently stored instruction from the IPC interface, B 2 n Send the next instruction to the IPC interface.

[0059] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts depict the steps as sequential processes, many of the steps can be implemented in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0060] An embodiment of the present invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0061] An embodiment of the present invention also provides a computer-readable storage medium storing computer-executable instructions, and the computer instructions are used to execute the method described in the embodiment of the present invention.

[0062] Based on dual-process communication, the embodiment of the present invention realizes directly running software test cases on the verification of the chip design to be tested implemented by RTL code, and through multiple groups of parallel dual-processes, realizes the parallel running of software test cases in the software test case set on the verification of the chip design to be tested, without changing the software test cases, reduces the cross-stage verification cost of software test cases, and improves the chip verification efficiency.

[0063] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the above-disclosed technical content within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A software and hardware joint debugging method based on IPC, characterized in that: include: Step S1: Obtain N software test case sets {A1, A2, ..., A n ,...,A N }, A n is the nth software test case, where the value of n ranges from 1 to N, and the chip design to be tested is implemented based on RTL code; Step S2: for each A n Assign the corresponding process group (B1 n ,B2 n ), B1 n A n The corresponding first process, B2 n A n The corresponding second process assigns a corresponding interaction identifier P to each process group based on the IPC protocol n , the IPC protocol is an inter-process communication protocol; Step S3: Start all B1 in parallel n , each B1 n Start executing the corresponding A n At the same time, the chip RTL code performs chip initialization operations, B1 n Based on the corresponding A n Generate A n The corresponding register configuration instruction enters the waiting state; Step S4: After the chip under test is designed to complete the chip initialization operation, B1 n 、B2 n Based on the corresponding P n For inter-process communication, A n Run on the chip design under test.

2. The method according to claim 1, characterized in that The step S3 comprises: Step S31, B1 n Analyze the corresponding A n , get A n Corresponding operation parameters and operation logic; Step S32, B1 n Get the memory information of the chip design to be tested. The memory information of the chip design to be tested is A n The corresponding operation parameters are allocated memory addresses; Step S33, B1 n Based on A n The corresponding operation parameters and A n The memory address of the corresponding operation parameter allocation generates A n The corresponding register configuration instruction, the A n The corresponding register configuration instructions include A n The corresponding process group corresponding to the interaction identifier P n .

3. The method according to claim 2, characterized in that The step S4 comprises: Step S41: After the chip under test is designed to complete the chip initialization operation, B1 n A n The corresponding register configuration instructions are sent to B2 via the IPC interface n ; Step S42, B2 n Based on A n The corresponding register configuration instructions perform register configuration operations on the chip design under test; Step S43, B1 n In A n After the corresponding register configuration instruction is executed, based on each A n The corresponding operation parameters and register configuration information generate A n The corresponding data transfer instructions are sent to B2 through the IPC interface n , A n The corresponding data handling instructions include A n The corresponding process group corresponding to the interaction identifier P n ; Step S44, B2 n Based on A n The corresponding data handling instructions will be A in the chip under test design n The corresponding operation parameters are stored in the memory corresponding to the chip design under test; Step S45, B1 n In A n After the corresponding data handling instruction is executed, based on A n The corresponding operation logic generates A n The corresponding doorbell command is sent to B2 through the IPC interface n , A n The corresponding doorbell commands include A n The corresponding process group corresponding to the interaction identifier P n ; Step S46, B2 n Based on A n The corresponding doorbell command and the A stored in the memory of the chip under test n The corresponding operation parameters are executed on the chip design under test. n The corresponding operation logic generates A n The results of operations run on the chip design under test.

4. The method according to claim 3, characterized in that The step S42 comprises: Step S421, B2 n A n The corresponding register configuration instruction is converted to A n The corresponding register configuration instructions implemented by SystemVerilog; Step S422, B2 n Based on A n The corresponding SystemVerilog implemented register configuration instructions perform register configuration operations on the chip design under test.

5. The method according to claim 3, characterized in that: The step S44 comprises: Steps S441, B2 n A n The corresponding data handling instructions are converted to A n The corresponding SystemVerilog implementation of data handling instructions; Step S442, B2 n Based on A n The corresponding SystemVerilog implementation of the data handling instructions will be A in the chip under test design n The corresponding operation parameters are stored in the memory corresponding to the chip design under test.

6. The method according to claim 3, characterized in that The step S46 comprises: Step S461, B2 n A n The corresponding doorbell instructions are converted to SystemVerilog implementation A n Corresponding doorbell command; Step S462, B2 n Based on A n The corresponding SystemVerilog doorbell instruction and the A stored in the design memory of the chip under test n The corresponding operation parameters are executed on the chip design under test. n The corresponding operation logic generates A n The results of operations run on the chip design under test.

7. The method according to claim 3, characterized in that B1 n By obtaining B2 n The completion instruction sent determines whether the corresponding operation is completed. The completion instruction sent determines whether the corresponding operation is completed. The completion instruction includes A n The corresponding process group corresponding to the interaction identifier P n The completion instructions are chip initialization operation completion instructions, register configuration completion instructions, and data transfer completion instructions.

8. The method according to claim 3, characterized in that Set the number of requests that can be sent in the IPC interface to 1, B1 n After the instruction is generated, it is stored in the IPC interface. n After taking the currently stored instruction from the IPC interface, B2 n Send the next command to the IPC interface.

9. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method of any one of the preceding claims 1-8.

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