Hardware and software based register configuration method, electronic device and medium

Abstract

The application relates to the chip technical field, in particular to a register configuration method based on software and hardware, electronic equipment and medium, which comprises the following steps: S1, generating original register configuration instructions based on a software configuration module; S2, determining register addresses corresponding to register names based on a register address mapping table; S3, inputting the register names corresponding to the original register configuration instructions and the corresponding register addresses into a direct programming interface in a configuration interface module to generate target register configuration instructions based on a SystemVerilog language; S4, calling a test sequence module based on the target register configuration instructions to generate a test task sequence; and S5, calling a driving module to input the test task sequence into a chip design to be tested, and performing corresponding register configuration operations in the chip design to be tested based on the test task sequence. The application improves chip development efficiency and reduces chip development cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and particularly to a register configuration method based on software and hardware, an electronic device and a medium. BACKGROUND

[0002] In the chip development process, different chip verification stages need to be experienced, usually first based on the chip RTL (Register Transfer Level) code for hardware level verification, and the chip hardware accelerator or physical chip will be obtained after the basic hardware verification, and then the system level verification is carried out based on the hardware accelerator or physical chip. After the system level verification is passed, the software level verification is carried out based on the hardware accelerator or physical chip. The hardware accelerator or physical chip belongs to the real existing entity, if the problem is found in the software verification stage, a large amount of updating cost needs to be consumed, and the chip development efficiency is reduced. Therefore, the software engineer hopes to realize the register configuration based on the chip RTL code before the chip is taped out, and the software level verification is carried out in advance. However, the software engineer usually issues instructions based on software, and cannot directly interact with the chip RTL code, so the register configuration cannot be directly realized. Therefore, how to realize the register configuration based on the software instruction in advance based on the RTL code, improve the chip development efficiency, and reduce the chip development cost, becomes a technical problem to be solved. SUMMARY

[0003] The present application aims to provide a register configuration method based on software and hardware, an electronic device and a medium, which improves the chip development efficiency and reduces the chip development cost.

[0004] According to the first aspect of the present application, a register configuration method based on software and hardware is provided, comprising:

[0005] Step S1, generating an original register configuration instruction based on a software configuration module, and sending the original register configuration instruction to a configuration interface module, wherein the original register configuration instruction comprises a register name, and the original register configuration instruction is generated based on a software language;

[0006] Step S2, determining the register address corresponding to the register name in the original register configuration instruction based on a register address mapping table pre-stored in the configuration interface module, wherein the register address mapping table is used to store the mapping relationship information of the register name and the register address based on the chip design to be tested;

[0007] Step S3, inputting the register name corresponding to the original register configuration instruction and the corresponding register address into a direct programming interface in the configuration interface module to generate a target register configuration instruction based on a SystemVerilog language;

[0008] Step S4, calling a test sequence module based on the target register configuration instruction to generate a test task sequence;

[0009] Step S5, calling a driving module to input the test task sequence into a chip design to be tested, and performing a corresponding register configuration operation in the chip design to be tested based on the test task sequence, wherein the chip design to be tested is generated based on RTL code.

[0010] According to a second aspect of the present application, an electronic device is provided, comprising at least one processor, and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method according to the first aspect of the present application.

[0011] According to a third aspect of the present application, a computer readable storage medium is provided, which stores computer executable instructions for executing the method according to the first aspect of the present application.

[0012] Compared with the prior art, the present application has obvious advantages and beneficial effects. By the above technical solution, the register configuration method based on software and hardware, the electronic device and the medium provided by the present application can achieve considerable technical progress and practicality, and have wide industrial utilization value. At least the following beneficial effects are achieved:

[0013] The present application generates original register configuration instructions implemented by software code based on a software configuration module, and only the register name needs to be specified in the original register configuration instructions, without the need to specify the register address. Different register address mapping tables can be configured in the configuration interface module according to different application scenarios, and the register address is determined based on the register address mapping table. Then, the target register configuration instructions based on the SystemVerilog language are generated based on the preset direct programming interface, which realizes the interaction between the register configuration instructions issued based on software and the RTL code, so that software engineers can perform register configuration based on the chip RTL code before the chip is taped out, and perform software level verification in advance, thereby improving the chip development efficiency and reducing the chip development cost. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0015] Figure 1 The register configuration method based on software and hardware provided by the embodiments of the present application is shown in the flowchart. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0017] The embodiments of the present application provide a register configuration method based on software and hardware, as shown in the following formula (1), which comprises the following steps. Figure 1

[0018] Step S1, generating an original register configuration instruction based on a software configuration module, and sending the original register configuration instruction to a configuration interface module, wherein the original register configuration instruction comprises a register name, and the original register configuration instruction is generated based on a software language.

[0019] It should be noted that the software configuration module is implemented based on a software language to generate an original register configuration instruction based on the software language, and the software language can be C language, C++ language, etc. The software configuration module is used to simulate the behavior of a CPU (Central Processing Unit) in a register configuration process.

[0020] Step S2, determining a register address corresponding to the register name in the original register configuration instruction based on a register address mapping table pre-stored in the configuration interface module, wherein the register address mapping table is used to store mapping relationship information of register names and register addresses based on a chip design under test.

[0021] It should be noted that the register address mapping table can be flexibly set based on a specific chip design under test, and by setting the register address mapping table, an upper-layer software engineer only needs to input a register name, without frequently updating codes due to inputting different register addresses for different chip designs under test, thereby reducing the operation difficulty of the software engineer and enabling flexible adaptation to different chip designs under test.

[0022] Step S3, inputting the register name corresponding to the original register configuration instruction and the corresponding register address into a direct programming interface in the configuration interface module to generate a target register configuration instruction based on a SystemVerilog language.

[0023] ​It should be noted that the direct programming interface (DPI) is a standard interface, which allows SystemVerilog code to directly call C or C++ functions, and vice versa. DPI allows data and control information to be passed between the two languages, so based on DPI, conversion between software language and SystemVerilog language can be realized, which will not be described here. The target register configuration instruction is a register configuration instruction generated based on the PCIE protocol, and can also be a register configuration instruction generated based on the AXI protocol, and the corresponding protocol is configured according to the specific application scenario. The PCIE protocol and the AXI protocol are both existing bus protocols, which will not be described here.

[0024] Step S4, calling a test sequence module based on the target register configuration instruction to generate a test task sequence;

[0025] Step S5, calling a driving module to input the test task sequence into the chip design under test, and executing corresponding register configuration operations in the chip design under test based on the test task sequence, and the chip design under test is generated based on RTL code.

[0026] It should be noted that the test sequence module and the driving module are both modules on the verification platform, and the verification platform is used to verify the chip design under test. In addition, through the configuration and conversion of the configuration interface module, the register configuration instruction generated by the software engineer is converted into a target register configuration instruction that can interact with the chip design under test, so that the software engineer can perform register configuration based on the chip RTL code before chip tape-out, and perform software-level verification in advance, thereby improving the chip development efficiency and reducing the chip development cost.

[0027] As an embodiment, the original register configuration instruction can be an original register write instruction, or can be an original register read instruction.

[0028] If the original register configuration instruction is an original register write instruction, the step S1 includes:

[0029] Step S11, calling a register write function Reg write based on a software configuration module to generate an original register write instruction, and the original register write instruction includes a register name and a target write value.

[0030] If the original register configuration instruction is an original register read instruction, the step S1 includes:

[0031] Step C11, calling a register read function Reg read based on a software configuration module to generate an original register read instruction, and the original register write instruction includes a register name.

[0032] It should be noted that in step S1, the original register write instruction may be generated only through step S11; the original register read instruction may be generated only through step C11; or the original register write instruction may be generated through both step S11 and step C11.

[0033] As one embodiment, step S4 includes:

[0034] Step S41: Based on the target register configuration instruction, call the test sequence module to generate test tasks, and store them in a preset storage queue in sequence to generate a test task sequence.

[0035] It should be noted that tasks in the storage queue can be executed sequentially or skipped according to the execution strategy.

[0036] As one embodiment, the test task sequence = (A1, A2, ..., A n ,...,A N ), A n Configure the nth register, where n ranges from 1 to N, and N is the total number of register configuration tasks in the current test task sequence. n =(A1) n A2 n ),A1 n A1 is the task type identifier. n =0 means A n For register read task, A1 n =1 means A n Write task to register, A2 n For A n Task completion status indicator, A2 n =0 means A n Task not completed, A2 n =1 means A n Task completed.

[0037] As one embodiment, step S5 includes:

[0038] Step S51: Call the driver module to transfer (A1, A2, ..., A n ,...,A N (Input is being processed in the chip design process.)

[0039] Step S52: Extract (A1, A2, ..., A n ,...,A N A1 n =1 task, generate test write task sequence (B1,B2,...,B m ,...,BM ),{B1,B2,...,B m ,...,B M} is a subset of {A1,A2,...,A n ,...,A N}, B m is the mth register write task, m ranges from 1 to M, M is the total number of register write tasks in the test task sequence, B m =(B1 m ,B2 m ), B1 m is a task type identifier, B1 m =1, B2 m indicates the B m task completion status identifier.

[0040] It should be noted that the test write task sequence (B1,B2,...,B m ,...,B M ) is generated to facilitate the execution of subsequent register write tasks.

[0041] Step S53, extract the task A1 n =0 in (A1,A2,...,A N ,...,A n ), generate a test read task sequence (C1,C2,...,C k ,...,C K ), {C1,C2,...,C k ,...,C K} is a subset of {A1,A2,...,A n ,...,A N}, C k is the kth register read task, k ranges from 1 to K, K is the total number of register read tasks in the test task sequence, K+M=N, C k =(C1 k ,C2 k ), C1 k is a task type identifier, C1 k =2, C2 k indicates the C k task completion status identifier.

[0042] It should be noted that the test read task sequence is generated to facilitate the execution of subsequent register read tasks.

[0043] Step S54, based on (B1,B2,...,B m ,...,B M) in the chip design under test, based on (A1, A2,..., A n ,...,A N ) and (C1, C2,..., C k ,...,C K ) in the chip design under test.

[0044] It should be noted that different execution strategies of the register write task can be specified to meet different application requirements, which will be illustrated by two embodiments of executing the register write task.

[0045] Embodiment one,

[0046] In the step S54, the register write task is executed in the chip design under test based on (B1, B2,..., B m ,...,B M ), including:

[0047] Step S541, initially set m = 1.

[0048] Step S542, if m = 1, directly execute step S544, if m > 1, execute step S543.

[0049] It should be noted that if m = 1, it means that the current register write task is the first register write task in the test write task sequence, and there is no need to wait for the completion of other write tasks, so step S544 is directly executed, if m > 1, it is necessary to determine whether the register write task before B m is completed.

[0050] Step S543, judge whether B2 m-1 is equal to 1, if yes, execute step S544, otherwise, when B2 m-1 is equal to 1, execute step S544, wherein when B m-1 is executed, a corresponding write completion instruction is generated, and B2 m-1 is updated to 1 based on the corresponding write completion instruction of B m-1 .

[0051] It should be noted that through step S543, the register write task can be strictly executed according to the test write task sequence, avoiding writing errors, improving the accuracy of the execution of the register write task, and being suitable for application scenarios with high accuracy requirements for the execution of the write task.

[0052] Step S544, B m is issued to the chip design under test to execute the corresponding register write operation, if m < M, set m = m + 1, return to step S542, if m = M, wait for (A1, A2,..., An ..., A N All tasks in (B1, B2,..., B

[0053] It should be noted that, after B m is issued to the chip design to be tested, the chip design to be tested will execute B m according to the register address.

[0054] It should be noted that the execution strategy of the register write task in Embodiment 1 can ensure the accuracy of the execution of the register write task, but since each register write task needs to wait for the execution of the previous register write task before being issued, the execution efficiency is low. However, in some application scenarios, there may be no write sequence requirement for the register write task, or the execution efficiency requirement is higher, and the execution strategy of Embodiment 1 is obviously not applicable. Based on such application scenarios, Embodiment 2 is further proposed.

[0055] Embodiment 2,

[0056] In step S54, based on (B1, B2,..., B m ..., B M ), the test register write task is executed in the chip design to be tested, including:

[0057] Step C541, initially set m = 1, and set the write task count value R = 0.

[0058] The write task count value is used to record the number of register write tasks that have been issued and not yet executed in real time.

[0059] Step C542, issue B m to the chip design to be tested to execute the corresponding register write operation, and set R = R + 1.

[0060] Step C543, if m < M, set m = m + 1, and return to step C542; if m = M, all tasks in (A1, A2,..., A n ..., A N ) are executed, and the process is ended;

[0061] During the execution of steps C521 to C543, step C540 also needs to be executed, that is, when any one test write task is executed, a write completion instruction is generated, and R = R - 1 is set each time a write completion instruction is generated. When R = 0, all B1, B2,..., B m corresponding B2 m-1 are updated to 1.

[0062] It should be noted that through steps C541-C543 and step C540, the fast delivery of register write tasks is realized, and each register write task can be quickly delivered without waiting for the previous register write task to be executed. In addition, the number of currently delivered and not yet executed register write tasks is recorded in real time by the task count value R, and when R becomes 0, it means that all the currently delivered register write tasks have been executed, so B2 m-1 can be updated in batches, thereby improving the execution efficiency of the register write tasks.

[0063] As an embodiment, in step S54, the test register read tasks are executed in the chip design under test based on (A1, A2,..., A n ,...,A N ) and (C1, C2,..., C k ,...,C K ), including:

[0064] Step D541, initially set k = 1.

[0065] Step D542, judge whether all the task completion status identifiers corresponding to the register configuration tasks with task type identifiers of 1 before A k corresponding to C n are equal to 1, if yes, execute step D543, otherwise, wait until all the task completion status identifiers corresponding to the register configuration tasks with task type identifiers of 1 before A k corresponding to C n are equal to 1, then execute step D543.

[0066] It should be noted that if all the task completion status identifiers corresponding to the register configuration tasks with task type identifiers of 1 before A k corresponding to C n are equal to 1, it means that all the write tasks before A n corresponding to C N in (A1, A2,..., A k ,...,A n ) have been executed, and this condition is met to deliver C k to the chip design under test to execute the corresponding register read operation, ensuring the correct execution of the write operation. If not, it needs to wait until all the task completion status identifiers corresponding to the register configuration tasks with task type identifiers of 1 before A k corresponding to C n are equal to 1, then C k can be delivered to the chip design under test to execute the corresponding register read operation.

[0067] Step D543, deliver Ck The C2 register read operation is executed in the chip design to be tested, and when the C2 register read operation is completed, a read return instruction is generated, and the corresponding C2 register read operation is completed. k The C2 register read operation is executed in the chip design to be tested, and when the C2 register read operation is completed, a read return instruction is generated, and the corresponding C2 register read operation is completed. k The C2 register read operation is executed in the chip design to be tested, and when the C2 register read operation is completed, a read return instruction is generated, and the corresponding C2 register read operation is completed.

[0068] If k < K, k is set to k+1, and step D542 is returned, and if k = K, all tasks in (A1, A2,..., A n ,...,A N ) are executed, and the process is ended.

[0069] It should be noted that steps D541 to D544 can be used in combination with the processing mode of the register write task in Embodiment 1, or can be used in combination with the processing mode of the write task in Embodiment 2.

[0070] It should be noted that some example embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts depict the steps in a sequential order, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. The processes can be terminated when their operations are completed, but can also have additional steps not included in the figures. The processes can correspond to methods, functions, procedures, subroutines, subprograms, etc.

[0071] The embodiment of the application also provides an electronic device, comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the application.

[0072] The embodiment of the application also provides a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are used for executing the method described in the embodiment of the application.

[0073] The embodiment of the application generates the original register configuration instruction implemented by the software code based on the software configuration module, and only the register name needs to be specified in the original register configuration instruction, without specifying the register address. Different register address mapping tables can be configured in the configuration interface module according to different application scenarios, and the register address is determined based on the register address mapping table. Then, the target register configuration instruction based on the SystemVerilog language is generated based on the preset direct programming interface, the interaction between the register configuration instruction issued based on the software and the RTL code is realized, the software engineer can perform register configuration based on the chip RTL code before the chip is taped out, the software level verification is performed in advance, the chip development efficiency is improved, and the chip development cost is reduced.

[0074] The above merely describes preferred embodiments of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with the preferred embodiments as above, it is not intended to limit the present application. Any person skilled in the art, without departing from the technical solution of the present application, can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, as long as it does not deviate from the technical solution of the present application, still belongs to the scope of the technical solution of the present application.

Claims

1. A method of configuring a register based on hardware and software, comprising: The method comprises the following steps: Step S1, generating an original register configuration instruction based on a software configuration module, and sending the original register configuration instruction to a configuration interface module, wherein the original register configuration instruction comprises a register name, and the original register configuration instruction is generated based on a software language; Step S2, determining a register address corresponding to the register name in the original register configuration instruction based on a register address mapping table pre-stored in the configuration interface module, wherein the register address mapping table is used to store mapping relationship information of register names and register addresses based on a chip design to be tested; Step S3, inputting the register name corresponding to the original register configuration instruction and the corresponding register address into a direct programming interface in the configuration interface module to generate a target register configuration instruction based on a SystemVerilog language; Step S4, calling a test sequence module based on the target register configuration instruction to generate a test task sequence; Step S5, calling a driving module to input the test task sequence into the chip design to be tested, and performing a corresponding register configuration operation in the chip design to be tested based on the test task sequence, wherein the chip design to be tested is generated based on an RTL code; The test task sequence = (A1, A2,..., AN), AN is the nth register configuration task, n ranges from 1 to N, N is the total number of register configuration tasks in the current test task sequence, AN = (A1, A2), A1 is a task type identifier, A1 = 0 indicates that AN is a register read task, A1 = 1 indicates that AN is a register write task, A2 is an A task completion status identifier, A2 = 0 indicates that the A task is not executed completely, A2 = 1 indicates that the A task is executed completely n N n n n n n n n n n n n n n n n ​​​​​​​​​​​​​​​​​ extracting (A1, A2,..., A n ,...,A N ) of the tasks in which A1 n =1, generating a test write task sequence (B1, B2,..., B m ,...,B M ), (B1, B2,..., B m ,...,B M ) being a subset of (A1, A2,..., A n ,...,A N ), B m being the mth register write task, m ranging from 1 to M, M being the total number of register write tasks in the test task sequence, B m = (B1 m ,B2 m ), B1 m being a task type identifier, B1 m =1, B2 m representing a B m task completion status identifier; The step S5 comprises: performing a test register write task in the chip design to be tested based on (B1, B2,..., B m ,...,B M ), and specifically comprises: Step S541, initially setting m=1; Step S542, if m=1, directly executing step S544, and if m>1, executing step S543; Step S543, judging whether B2 m-1 is equal to 1, if yes, executing step S544, otherwise, waiting for B2 m-1 to be equal to 1, executing step S544, wherein, when B m-1 is equal to 1, executing step S544, wherein, when B m-1 is equal to 1, executing step S544, wherein, when B m-1 is equal to 1, executing step S544, wherein, when B Step S544, B m corresponding register write operation in the chip design under test, if m n ,...,A N all tasks in (A1, A2,..., A M are executed, the process ends.

2. The method of claim 1, wherein, if the original register configuration instruction is an original register write instruction, the step S1 comprises: Step S11, calling a register write function Reg write based on the software configuration module to generate an original register write instruction, wherein the original register write instruction comprises a register name and a target write value; if the original register configuration instruction is an original register read instruction, the step S1 comprises: Step C11, calling a register read function Reg read based on the software configuration module to generate an original register read instruction, wherein the original register read instruction comprises a register name.

3. The method of claim 2, wherein, the step S4 comprises: Step S41, calling a test sequence module based on the target register configuration instruction to generate a test task, and storing the test task in a preset storage queue in a sequence to generate a test task sequence.

4. The method of claim 2, wherein, the step S5 comprises: Step S51, calling the driving module to input (A1, A2,..., A n ,...,A N ) into the chip design under test; Step S53: Extract (A1, A2, ..., A n ,...,A N A1 in ) n For tasks with a value of 0, generate a test read task sequence (C1, C2, ..., C...). k ,...,C K (C1,C2,...,C) k ,...,C K ) is (A1,A2,...,A) n ,...,A N A subset of ), C k This is the k-th register read task, where k ranges from 1 to K, K is the total number of register read tasks in the test task sequence, K + M = N, and C k =(C1 k C2 k C1 k C1 is the task type identifier. k =2, C2 k C represents k Task completion status indicator; Step S54, performing the test register read task in the chip design under test based on (A1, A2,..., A n ,...,A N ) and (C1, C2,..., C k ,...,C K ). Step S54, performing the test register read task in the chip design under test based on (A1, A2,..., A n ,...,A N ) and (C1, C2,..., C k ,...,C K ).

5. The method of claim 4, wherein, performing a test register write task in a chip design under test based on (B1, B2,..., B m ,...,B M ) Step C541, initially setting m=1, and setting a write task count value R=0; Step C542, B m The corresponding register write operation is executed in the chip design to be tested, and R=R+1 is set. Step C543, if m < M, set m = m + 1, return to Step C542, if m = M, all tasks in (A1, A2,..., A n ,...,A N ) are executed, end the process; In the process of performing step C521 to step C543, step C540 is also performed, when any one test write task is performed, a write completion instruction is generated, R=R-1 is set every time a write completion instruction is generated, when R=0, the current B1, B2,..., B m Corresponding B2 m-1 All are updated to 1.

6. The method of claim 4, wherein, In step S54, based on (A1, A2,..., A n ,...,A N ) and (C1, C2,..., C k ,...,C K ), the test register reading task in the chip design under test is performed, including: Step D541, initially setting k=1; Step D 542, judging C k Corresponding A n If all the task completion status identifiers corresponding to the register configuration tasks of which the task type identifier is 1 are equal to 1, then execute Step D 543, otherwise, wait for C k Corresponding A n If all the task completion status identifiers corresponding to the register configuration tasks of which the task type identifier is 1 are equal to 1, then execute Step D 543, otherwise, wait for C Step D543, C k is issued to the chip design under test to perform a corresponding register read operation, and C k is generated after the execution is completed, and the corresponding C2 k is updated to 1. Step D 544, if k < K, set k = k + 1, return to step D 542, if k = K, all tasks in (A1, A2,..., AK) are executed, end the process. n N ​​ 7. An electronic device, comprising: The device comprises: at least one processor; and a memory connected in communication with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method of any one of the preceding claims 1-6.

8. A computer-readable storage medium, characterized in that, The computer executable instructions are stored in the memory, and the computer executable instructions are used to execute the method of any one of the preceding claims 1-6.

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