Multi-channel based direct memory access system, method, electronic device, medium and program product

Abstract

The present disclosure provides a multi-channel based direct memory access system, method, electronic device, medium and program product, relating to the fields of semiconductors and data processing. The system includes: a bandwidth change determination module configured to determine a first change trend of a read bandwidth for reading data and a second change trend of a write bandwidth for writing data in each of a plurality of transmission channels of the direct memory access system; a priority determination module configured to adjust values of data transmission priorities of at least one of the plurality of transmission channels based on the first change trend and the second change trend, where the values of data transmission priorities are used to indicate data transmission times to be allocated to the at least one transmission channel.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors and data processing, and in particular, to a multi-channel based direct memory access system, method, electronic device, computer-readable storage medium, and computer program product. Background Art

[0002] With the continuous enrichment of computer application scenarios, the requirements for data transmission speed and overall system performance are increasing day by day. In the initial stage of the development of computer systems, data transmission mainly relied on the central processing unit for control. This method was inefficient and seriously occupied its time and resources. Therefore, the multi-channel direct memory access (DMA) technology gradually emerged. This technology allows external devices to directly exchange data with the memory without the need for the central processing unit to control, enabling the central processing unit to focus on more complex operations and task processing. Therefore, how to improve the data transmission efficiency of multi-channel DMA has become one of the research hotspots and difficulties in the industry. Summary of the Invention

[0003] The present disclosure provides a multi-channel based direct memory access system, method, electronic device, computer-readable storage medium, and computer program product.

[0004] According to one aspect of the present disclosure, there is provided a multi-channel based direct memory access system, the system comprising: a bandwidth change determination module configured to determine a first change trend of a read bandwidth for reading data and a second change trend of a write bandwidth for writing data in each of a plurality of transmission channels of the direct memory access system; a priority determination module configured to adjust a value of a data transmission priority of at least one of the plurality of transmission channels based on the first change trend and the second change trend, the value of the data transmission priority being used to indicate a data transmission time to be allocated to at least one of the transmission channels, wherein the priority determination module includes: a first priority determination module configured to reduce the value of the data transmission priority of at least one of the transmission channels in response to the first change trend corresponding to at least one of the plurality of transmission channels being a decrease in the read bandwidth; a second priority determination module configured to reduce the value of the data transmission priority of at least one of the transmission channels in response to the second change trend corresponding to at least one of the plurality of transmission channels being a decrease in the write bandwidth; a third priority determination module configured to increase the value of the data transmission priority of at least one of the transmission channels in response to the first change trend corresponding to at least one of the plurality of transmission channels being an increase in the read bandwidth and the second change trend being an increase in the write bandwidth.

[0005] According to another aspect of the present disclosure, a multi-channel based direct memory access method is provided, including: determining a first change trend of a read bandwidth for each transmission channel among a plurality of transmission channels of a direct memory access system and a second change trend of a write bandwidth for writing data; based on the first change trend and the second change trend, adjusting a value of a data transmission priority of at least one transmission channel among the plurality of transmission channels, where the value of the data transmission priority is used to indicate a data transmission time to be allocated to at least one transmission channel, and where adjusting the value of the data transmission priority of at least one transmission channel among the plurality of transmission channels includes: in response to the first change trend corresponding to at least one transmission channel among the plurality of transmission channels being a decrease in the read bandwidth, reducing the value of the data transmission priority of at least one transmission channel; in response to the second change trend corresponding to at least one transmission channel among the plurality of transmission channels being a decrease in the write bandwidth, reducing the value of the data transmission priority of at least one transmission channel; and in response to the first change trend corresponding to at least one transmission channel among the plurality of transmission channels being an increase in the read bandwidth and the second change trend being an increase in the write bandwidth, increasing the value of the data transmission priority of at least one transmission channel.

[0006] According to another aspect of the present disclosure, an electronic device is provided, including the direct memory access system as described above in the present disclosure.

[0007] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, where the computer instructions are used to cause a computer to execute the method as described above in the present disclosure.

[0008] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, where the computer program, when executed by a processor, implements the method as described above in the present disclosure.

[0009] According to one or more embodiments of the present disclosure, the bandwidth utilization rate of multi-channel direct memory access can be improved.

[0010] According to the embodiments described below, these and other aspects of the present disclosure will be apparent and will be elucidated with reference to the embodiments described below. Description of the Drawings

[0011] The drawings exemplarily illustrate embodiments and form a part of the specification, and are used together with the written description of the specification to explain the exemplary embodiments of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of the claims. In all the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0012] Figure 1 is a schematic diagram illustrating traditional data transmission through software-controlled multi-channel DMA;

[0013] Figure 2 FIG. is a block diagram showing the structure of a multi-channel based DMA system according to an exemplary embodiment;

[0014] Figure 3 FIG. is a block diagram showing the structure of a bandwidth change determination module according to an exemplary embodiment of the present disclosure;

[0015] Figure 4 FIG. is a schematic diagram showing the determination of the change amount of the read delay count according to an exemplary embodiment;

[0016] Figure 5 FIG. is a block diagram showing the structure of a bandwidth change determination module according to another exemplary embodiment of the present disclosure;

[0017] Figure 6 FIG. is a schematic diagram showing the determination of the change amount of the backpressure count according to an exemplary embodiment;

[0018] Figure 7 FIG. is a block diagram showing the structure of a DMA system according to another exemplary embodiment of the present disclosure;

[0019] Figure 8 FIG. is a schematic diagram showing the determination of the data transfer time allocated to each transfer channel according to an exemplary embodiment;

[0020] Figure 9 FIG. is a schematic diagram of a multi-channel based DMA system according to another exemplary embodiment;

[0021] Figure 10 FIG. is a flowchart of a multi-channel based DMA method according to an exemplary embodiment;

[0022] Figure 11 FIG. is a flowchart of a method for adjusting the value of the data transfer priority of a transfer channel according to an exemplary embodiment;

[0023] Figure 12 FIG. is a block diagram of an exemplary electronic device that can be applied to an exemplary embodiment. Detailed Embodiments

[0024] The following describes exemplary embodiments of the present disclosure with reference to the accompanying drawings. Various details of the embodiments of the present disclosure are included to assist in understanding, and they should be considered merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of the present disclosure. Similarly, descriptions of well-known functions and structures are omitted for clarity and conciseness in the following description.

[0025] In the present disclosure, unless otherwise specified, the use of terms such as "first", "second", etc. to describe various elements does not intend to limit the positional relationship, timing relationship or importance relationship of these elements. Such terms are only used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of the element, and in certain cases, based on the context description, they may also refer to different instances.

[0026] In the description of various examples in the present disclosure, the terms used are only for the purpose of describing specific examples and are not intended to be limiting. Unless the context clearly indicates otherwise, if the number of elements is not specifically limited, the element may be one or more. As used herein, the term "plurality" means two or more, and the term "based on" should be interpreted as "at least partially based on". In addition, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations.

[0027] With the development of the computer field, Direct Memory Access (DMA) technology has been widely used, and generally DMA can be multi-channel.

[0028] When multi-channel DMA reads data from the memory, the overall bandwidth of the DMA will be affected by the channel with the minimum bandwidth. For example, when one channel is reading data from the memory, other devices are also reading data from the memory, causing the channel to wait until other devices have finished reading before it can continue to read. This will result in a reduction in the bandwidth of the channel, thereby affecting the overall data transfer efficiency of the DMA. Traditional multi-channel DMA adjusts the overall bandwidth of the DMA by setting the priority of each channel through software.

[0029] Figure 1 FIG. is a schematic diagram showing traditional data transfer by software-controlled multi-channel DMA.

[0030] As Figure 1As shown in the figure, the DMA can have two channels, such as channel 0 and channel 1, where channel 0 transfers data with DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), and channel 1 transfers data with local RAM (Random Access Memory). When the two channels request data transfer simultaneously, an order problem of sequential response processing will occur. The traditional method is to solve this problem by statically configuring the priorities of channel 0 and channel 1 through software. For example, the priority level of channel 0 can be set to high and the priority level of channel 1 can be set to low in the relevant registers. Then, when these two channels send requests simultaneously, channel 0 will be preferentially used to transfer data with the DDR. However, if the bandwidth for channel 0 to access the DDR is low at this time, while the bandwidth for channel 1 to access the local RAM is high, it will result in a low overall bandwidth utilization rate of the DMA. If we want to improve the overall bandwidth utilization rate of the DMA, we can only set the priority of channel 1 to be higher through software settings.

[0031] Therefore, the method of adjusting the overall bandwidth utilization rate of the DMA by statically controlling the priority of each channel through software is poor in terms of flexibility and response speed, and it is difficult to meet the requirements of efficient data transfer.

[0032] In order to improve the bandwidth utilization rate of the multi-channel DMA, the present disclosure provides a direct memory access system based on multiple channels.

[0033] The exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0034] Figure 2 FIG. is a block diagram showing the structure of a multi-channel based DMA system 200 according to an exemplary embodiment.

[0035] As Figure 2 shown, the DMA system 200 includes a bandwidth change determination module 201 and a priority determination module 202, where the priority determination module 202 includes a first priority determination module 2021, a second priority determination module 2022, and a third priority determination module 2023.

[0036] The bandwidth change determination module 201 is configured to determine a first change trend of the read bandwidth for reading data and a second change trend of the write bandwidth for writing data of each transmission channel among the multiple transmission channels of the DMA.

[0037] In the example, the bandwidth change determination module 201 can monitor in real time the bandwidth changes of each transmission channel in the DMA system when reading data and when writing data. The larger the read bandwidth of a transmission channel, the higher the efficiency of the transmission channel in reading data. The first change trend can refer to the increase or decrease of the read bandwidth over time. The bandwidth change determination module 201 can analyze its change trend by comparing the data amounts read from the memory by a single transmission channel at different time points. For example, a certain transmission channel can read 2 KB (kilobytes) of data at the first moment, and at a subsequent second moment, the data amount read by this transmission channel is 1 KB, which indicates that the read bandwidth of this transmission channel may be restricted, so the first change trend is a decrease.

[0038] In the example, the higher the write bandwidth of a transmission channel, the higher the efficiency of the transmission channel in writing data. Similar to the first change trend, the second change trend can refer to the increase or decrease of the write bandwidth over time. The bandwidth change determination module 201 can analyze its change trend by comparing the data amounts written to the memory by a single transmission channel at different time points. For example, a certain transmission channel can write 1 KB of data at the first moment, and at a subsequent second moment, the data amount written by this transmission channel is 2 KB, which indicates that the write bandwidth of this transmission channel increases, so the second change trend is an increase.

[0039] Therefore, by monitoring in real time the bandwidth changes of each transmission channel during read and write operations, the change trends of the read bandwidth and write bandwidth of each transmission channel can be judged, providing a basis for the dynamic management of the DMA system.

[0040] The priority determination module 202 is configured to adjust the value of the data transmission priority of at least one transmission channel among the multiple transmission channels based on the first change trend and the second change trend. The value of the data transmission priority is used to indicate the data transmission time to be allocated to the at least one transmission channel.

[0041] As shown above, the priority determination module 202 includes a first priority determination module 2021, a second priority determination module 2022, and a third priority determination module 2023.

[0042] The first priority determination module 2021 is configured to, in response to the first change trend corresponding to the at least one transmission channel among the multiple transmission channels being a decrease in the read bandwidth, reduce the value of the data transmission priority of the at least one transmission channel.

[0043] The second priority determination module 2022 is configured to, in response to the second change trend corresponding to the at least one transmission channel among the multiple transmission channels being a decrease in the write bandwidth, reduce the value of the data transmission priority of the at least one transmission channel.

[0044] The third priority determination module 2023 is configured to increase the value of the data transmission priority of the at least one transmission channel in response to the first change trend corresponding to the at least one transmission channel among the multiple transmission channels being an increase in read bandwidth and the second change trend being an increase in write bandwidth.

[0045] In an example, the value of the data transmission priority can be used to measure the amount of resources obtained by each channel during data transmission. The higher the value of the data transmission priority of a transmission channel, the more data transmission opportunities the transmission channel can obtain in the total resource allocation. This data transmission opportunity can be reflected by the data transmission time. Therefore, the channel with a higher value of the data transmission priority can be allocated a longer data transmission time.

[0046] In an example, the priority determination module 202 can dynamically adjust the priority of the transmission channels with changing bandwidths according to the trends of bandwidth changes when reading and writing data for each transmission channel, so that the channels with higher read and write bandwidths can occupy more time for data transmission, thereby improving the overall bandwidth utilization of the DMA.

[0047] In an example, the DMA system can continuously monitor the read bandwidth and write bandwidth of each transmission channel and determine their respective change trends based on the monitoring results. When the first change trend of a certain transmission channel shows that its read bandwidth is decreasing, it means that the efficiency of reading data from this transmission channel becomes lower. Then the DMA system can reduce the value of the data transmission priority of this channel, that is, reduce the data transmission time it obtains in the DMA system, to ensure that resources can be more effectively allocated to those channels with higher current transmission efficiency.

[0048] In an example, when the second change trend of a certain transmission channel shows that its write bandwidth is decreasing, it means that the efficiency of writing data to this transmission channel becomes lower. Similarly, the value of the data transmission priority of this channel can be reduced to reduce the data transmission time it obtains in the DMA system.

[0049] In an example, when the first change trend of a certain transmission channel shows that its read bandwidth is increasing and the second change trend shows that its write bandwidth is also increasing, it means that the efficiency of both reading data and writing data from this transmission channel becomes higher. The DMA system can accordingly increase the value of the data transmission priority of this transmission channel to obtain more data transmission time, thereby improving the overall bandwidth utilization of the DMA system.

[0050] In an example, the priority adjustment can be applied to a transmission channel whose read bandwidth and write bandwidth change. During the adjustment process, the priority value can be increased or decreased. For example, it can be linearly increased or decreased, or dynamically changed according to a set weighting strategy. No matter which adjustment method is used, its essence is to reallocate the priority value of the transmission channel in real time based on the change trend of the read / write bandwidth.

[0051] Therefore, by adopting this method of dynamically adjusting the priority of each channel in the DMA system in real time according to the change trend of the read / write bandwidth, the problem that the overall transmission efficiency decreases due to the performance degradation of some channels in the multi-channel DMA system can be effectively solved, enabling channels with higher read / write bandwidth efficiency to obtain more transmission time in a timely manner, thereby improving the overall bandwidth utilization rate of the DMA system. At the same time, it can also reduce the dependence of the DMA system on software adjustment, reduce the configuration complexity, and improve the operating efficiency of the system.

[0052] In some embodiments, the first change trend can be determined based on the change amount of the read latency count. The read latency count can represent the number of time intervals of delay when each transmission channel in a plurality of transmission channels reads data.

[0053] In an example, the read latency count can be a quantitative metric used to measure situations such as waiting or blocking during the data reading process of a transmission channel. It can be expressed as the number of time intervals of delay detected by the DMA system during the reading process. For example, at a certain moment, a certain channel is delayed by 3 clock signals during the data reading process, then the read latency count of this channel at this moment can be 3. Therefore, by monitoring the change amount of the read latency count of the transmission channel, the change trend of the read bandwidth of this channel can be indirectly judged. For example, if the read latency count of a certain transmission channel increases, it means that the efficiency of this channel to read data decreases, that is, the first change trend is a decrease in the read bandwidth; if the read latency count decreases, it means that the read efficiency of this channel improves, that is, the first change trend is an increase in the read bandwidth.

[0054] Therefore, the method of determining the first change trend according to the change amount of the read latency count can effectively and accurately reflect the dynamic change situation of the real-time read efficiency of the transmission channel.

[0055] Figure 3 FIG. shows a structural block diagram of a bandwidth change determination module 300 according to an exemplary embodiment of the present disclosure.

[0056] In some embodiments, the bandwidth change determination module 300 may further include a delay change amount determination module 301. The delay change amount determination module 301 may include a first delay count determination module 3011, a second delay count determination module 3012, and a first change amount determination module 3013.

[0057] The first delay count determination module 3011 is configured to determine a first delay count corresponding to each of a plurality of transmission channels when reading data at a first moment.

[0058] The second delay count determination module 3012 is configured to determine a second delay count corresponding to each of the plurality of transmission channels when reading data at a second moment, where the second moment is the moment after the first moment.

[0059] The first change amount determination module 3013 is configured to, for each transmission channel, determine a change amount of the read delay count of the transmission channel based on a difference between the second delay count and the first delay count.

[0060] In an example, the change amount of the read delay count of a transmission channel can be obtained by calculating the difference between the read delay counts of the channel at different moments. For example, the read delay count of each transmission channel can be counted at the first moment, i.e., the first delay count; similarly, the read delay count of each transmission channel can be counted at the subsequent second moment, i.e., the second delay count, and the interval between these two moments can be set to a fixed period or dynamically adjusted according to the operating state of the DMA system. After obtaining the first delay count and the second delay count of each channel, the difference between the delay counts of each channel can be calculated respectively to determine the change amount of the read delay count of each transmission channel, so as to determine the first change trend. For example, if the result of subtracting the first delay count from the second delay count of a certain transmission channel is positive, it means that the read delay of the transmission channel is increasing, and the data reading efficiency of the channel is decreasing, that is, the first change trend is that the read bandwidth decreases; conversely, if the result of subtracting the first delay count from the second delay count of a certain transmission channel is negative, it means that the data reading efficiency of the channel is improving, that is, the first change trend is that the read bandwidth increases.

[0061] Therefore, by calculating the difference between the read delay counts at two moments, the change amount of the read delay count can be determined in real time, providing a basis for judging the change trend of the read bandwidth.

[0062] Figure 4 FIG. is a schematic diagram showing the determination of the change amount of the read delay count according to an exemplary embodiment.

[0063] As Figure 4 shown, the first delay count 401 when channel 0 reads data can be obtained at time t1, and the second delay count 402 when channel 0 reads data can be obtained at time t2, and the difference between the two can be calculated, which is the change amount 403 of the read delay count of channel 0.

[0064] In some embodiments, the second change trend may be determined based on the change amount of the number of backpressures for each of the multiple transmission channels. The number of backpressures may represent the number of times the memory is occupied by other master devices outside the system when each of the multiple transmission channels writes data to the memory.

[0065] In an example, backpressure may refer to the situation where when a transmission channel writes data to the memory, due to the memory being occupied by other system master devices, the transmission channel is unable to access the memory for the write operation. When the transmission channel is backpressured, its bandwidth will decrease accordingly, and the more the number of backpressures, the more its bandwidth will decrease. Therefore, by monitoring the change amount of the number of backpressures of the transmission channel, the change trend of the write bandwidth of the channel can be indirectly determined. For example, if the number of backpressures of a certain transmission channel increases, it indicates that the efficiency of writing data to this channel decreases, that is, the second change trend is a decrease in the write bandwidth; if the number of backpressures decreases, it indicates that the write efficiency of this channel improves, that is, the second change trend is an increase in the write bandwidth.

[0066] Therefore, the method of determining the second change trend based on the change amount of the number of backpressures can effectively and accurately reflect the dynamic change of the real-time write efficiency of the transmission channel.

[0067] Figure 5 FIG. shows a block diagram of a bandwidth change determination module 500 according to another exemplary embodiment of the present disclosure.

[0068] In some embodiments, the bandwidth change determination module 500 may further include a backpressure change amount determination module 501. The backpressure change amount determination module 501 may include a first backpressure number determination module 5011, a second backpressure number determination module 5012, and a second change amount determination module 5013.

[0069] The first backpressure number determination module 5011 is configured to determine the corresponding first backpressure number for each of the multiple transmission channels when writing data to the memory at a first moment.

[0070] The second backpressure number determination module 5012 is configured to determine the corresponding second backpressure number for each of the multiple transmission channels when writing data to the memory at a second moment, where the second moment is a moment after the first moment.

[0071] The second change amount determination module 5013 is configured to, for each of the multiple transmission channels, determine the change amount of the number of backpressures of the transmission channel based on the difference between the second backpressure number and the first backpressure number.

[0072] In the example, the change amount of the backpressure times of the transmission channel can be obtained by calculating the difference between the backpressure times of the channel at different times. For example, the backpressure times of each transmission channel can be counted at the first moment, that is, the first backpressure times; similarly, the backpressure times of each transmission channel can be counted at the subsequent second moment, that is, the second backpressure times, and the interval between these two moments can be set to a fixed period or dynamically adjusted according to the operating state of the DMA system. After obtaining the first backpressure times and the second backpressure times of each channel, the difference between the backpressure times of each channel can be calculated respectively to determine the change amount of the backpressure times of each transmission channel, so as to determine the second change trend. For example, if the result of subtracting the first backpressure times from the second backpressure times of a certain transmission channel is positive, it means that the backpressure times of this transmission channel are increasing, and the efficiency of writing data to this channel decreases, that is, the second change trend is a decrease in the write bandwidth; on the contrary, if the result of subtracting the first backpressure times from the second backpressure times of a certain transmission channel is negative, it means that the efficiency of writing data to this channel is improving, that is, the second change trend is an increase in the write bandwidth.

[0073] Therefore, by calculating the difference between the backpressure times at two moments, the change amount of the backpressure times can be determined in real time, providing a basis for judging the change trend of the write bandwidth.

[0074] Figure 6 FIG. shows a schematic diagram of determining the change amount of the backpressure times according to an exemplary embodiment.

[0075] As Figure 6 shown, the first backpressure times 601 when channel 0 writes data can be obtained at time t1, and the second backpressure times 602 when channel 0 writes data can be obtained at time t2, and the difference between the two can be calculated, which is the change amount 603 of the backpressure times of channel 0.

[0076] Figure 7 FIG. shows a block diagram of a DMA system 700 according to another exemplary embodiment of the present disclosure.

[0077] In some embodiments, the DMA system 700 may further include a transmission time determination module 701. The transmission time determination module 701 may include a total priority determination module 7011, a ratio calculation module 7012, and a time determination module 7013.

[0078] The total priority determination module 7011 is configured to add up the data transmission priority values of each transmission channel among a plurality of transmission channels to determine the sum of the total priorities.

[0079] The ratio calculation module 7012 is configured to calculate, for at least one transmission channel whose data transmission priority value is adjusted among multiple transmission channels, the ratio of the data transmission priority value of the at least one transmission channel to the sum of the total priorities.

[0080] The time determination module 7013 is configured to determine the data transmission time to be allocated to the at least one transmission channel based on the ratio.

[0081] In the example, the data transmission time of each channel can be determined by performing a weighted calculation on the data transmission priority value of the transmission channel. First, after the priority value is adjusted, the data transmission priority values of all transmission channels can be added together to obtain the sum of the total priorities. Then, for the transmission channels whose priority values are adjusted, calculate the ratio of the priority values of these transmission channels to the sum of the total priorities. Therefore, the higher the ratio of the priority value to the sum of the total priorities. At the same time, since the sum of the total priorities may change after the priority adjustment, other transmission channels whose priority values have not changed also need to recalculate the corresponding ratio. For example, in a DMA system, there are two channels, channel 0 and channel 1. The priority values of channel 0 and channel 1 at the first moment are both 2. Therefore, the ratio of these two channels to the total priority is 50% each. Assume that at the second moment, channel 0 has a reduced write bandwidth due to backpressure, while the read and write bandwidth of channel 1 has not changed. Therefore, the priority value of channel 0 is adjusted to 1, and the priority value of channel 1 remains unchanged. Then, the sum of the total priorities after adjustment is 3. The ratio of the priority value of channel 0 to the sum of the total priorities drops to 33.3%, and the ratio of the priority value of channel 1 to the sum of the total priorities increases to 66.7%.

[0082] In the example, according to the ratio of the priority value of each channel to the sum of the total priorities, the data transmission time to be allocated to each channel can be determined. For example, if the ratio of the priority value of a certain channel to the sum of the total priorities is 40%, then that channel will be allocated 40% of the data transmission time. This method can ensure that each channel in the DMA system is allocated an appropriate time according to its actual needs, avoiding the situation where a low-bandwidth channel occupies too much time and results in low overall bandwidth utilization of the DMA system.

[0083] Therefore, through this priority calculation and time allocation method, the DMA system can dynamically adjust the data transmission time of each channel, thereby maximizing the overall bandwidth utilization of the DMA system.

[0084] Figure 8 FIG. shows a schematic diagram of determining the data transmission time allocated to each transmission channel according to an exemplary embodiment.

[0085] As Figure 8As shown, the values of the priorities of channel 0, 801, channel 1, 802, and channel 2, 803, in the DMA system are shown. The sum of these three priority values can be added to obtain the total priority sum 810. Then, the proportions of the priority values of channel 0, channel 1, and channel 2 in the total priority sum 810 can be calculated respectively, that is, the proportion 811 of the priority value of channel 0, the proportion 812 of the priority value of channel 1, and the proportion 813 of the priority value of channel 2. Finally, based on the calculated proportions, the data transfer times 821, 822, and 823 allocated to channel 0, channel 1, and channel 2 can be determined respectively.

[0086] It should be understood that Figure 8 For the sake of convenience of description, taking the DMA system including three channels as an example, in actual applications, the number of channels of the DMA may not be limited to three.

[0087] Figure 9 FIG. shows a schematic diagram of a multi-channel-based DMA system according to another exemplary embodiment.

[0088] As Figure 9 shown, the DMA system may include two channels, channel 0 and channel 1, and a priority determination module 901, a delay variation determination module 902, a buffer 903, and a backpressure variation determination module 904. The buffer 903 can be used to store the data read by each channel.

[0089] When data is read, the delay variation determination module 902 can obtain the read delay counts 9021 of channel 0 and 9022 of channel 1 at two different times, and determine the delay variation between channel 0 and channel 1 at these two times by calculating the difference in the read delay counts. Similarly, when data is written, the backpressure variation determination module 904 can obtain the backpressure counts 9041 of channel 0 and 9042 of channel 1 at two different times, and determine the backpressure variation between channel 0 and channel 1 at these two times by calculating the difference in the backpressure counts.

[0090] Further, the delay change amount and backpressure change amount of channel 0 and channel 1 can be fed back to the priority determination module 901. The priority determination module 901 can adjust the priority values of channel 0 and channel 1 according to the fed-back data, so that the overall bandwidth utilization rate of the DMA system is in a relatively high state. For example, when the read and write bandwidths of channel 0 become lower and the read and write bandwidths of channel 1 become higher, the delay change amount and backpressure change amount of channel 0 will both increase, while the delay change amount and backpressure change amount of channel 1 will both decrease. Then, the results of the delay change amount and backpressure change amount of channel 0 and channel 1 can be fed back to the priority determination module 901 to reduce the priority value of channel 0 and increase the priority value of channel 1, so that channel 1 can obtain more transmission time, thereby improving the overall bandwidth utilization rate of the DMA.

[0091] In the example, when the read and write bandwidths of channel 0 change from low to high and finally become the same as those of channel 1, and the read and write bandwidths of channel 1 remain unchanged, the delay change amount and backpressure change amount of channel 0 will both decrease, while the delay change amount and backpressure change amount of channel 1 remain unchanged. Then, the results of the delay change amount and backpressure change amount of channel 0 and channel 1 can be fed back to the priority determination module 901 to increase the priority value of channel 0, and finally, data can be transmitted fairly between the two channels.

[0092] In the example, when the bandwidth of reading data of channel 0 becomes lower while the bandwidth of writing data remains unchanged, and the read and write bandwidths of channel 1 remain unchanged, the delay change amount of channel 0 will increase and the backpressure change amount remains unchanged, while the delay change amount and backpressure change amount of channel 1 both remain unchanged. Then, the results of the delay change amount and backpressure change amount of channel 0 and channel 1 can be fed back to the priority determination module 901 to reduce the priority value of channel 0, so that channel 1 occupies a longer transmission time and the overall bandwidth utilization rate of the DMA is improved.

[0093] Figure 10 The figure shows a flowchart of a multi-channel based DMA method 1000 according to an exemplary embodiment.

[0094] As Figure 10 shown, the method 1000 includes step S1001 and step S1002.

[0095] In step S1001, determine the first change trend of the read bandwidth for reading data and the second change trend of the write bandwidth for writing data of each transmission channel in the direct memory access system.

[0096] In step S1002, based on the first change trend and the second change trend, the value of the data transmission priority of at least one of the multiple transmission channels is adjusted, and the value of the data transmission priority is used to indicate the data transmission time to be allocated to at least one of the transmission channels.

[0097] According to the multi-channel-based DMA method of embodiments of the present disclosure, it is possible to monitor in real time the bandwidth changes of each transmission channel in the DMA system during read and write operations, and dynamically adjust the value of the priority of each channel, so that the channels with higher read and write bandwidth efficiency can obtain more transmission time in a timely manner, thereby improving the overall bandwidth utilization rate of the DMA system.

[0098] Figure 11 FIG. shows a flowchart of a method 1100 for adjusting the value of the data transmission priority of a transmission channel according to an exemplary embodiment.

[0099] As Figure 11 shown, method 1100 includes step S1101, step S1102, and step S1103.

[0100] In step S1101, in response to the first change trend corresponding to at least one of the multiple transmission channels being a decrease in read bandwidth, the value of the data transmission priority of at least one of the transmission channels is decreased.

[0101] In step S1102, in response to the second change trend corresponding to at least one of the multiple transmission channels being a decrease in write bandwidth, the value of the data transmission priority of at least one of the transmission channels is decreased.

[0102] In step S1103, in response to the first change trend corresponding to at least one of the multiple transmission channels being an increase in read bandwidth and the second change trend being an increase in write bandwidth, the value of the data transmission priority of at least one of the transmission channels is increased.

[0103] It should be understood that Figure 10 steps S1001 and S1002 shown in can correspond to the bandwidth change determination module 201 and the priority determination module 202 in the DMA system 200 described with reference to Figure 2 Method 1100 is a sub-step of step S1002, and steps S1101, S1102, and S1103 can correspond to the first priority determination module 2021, the second priority determination module 2022, and the third priority determination module 2023 in the DMA system 200 described with reference to Figure 2 Thus, the operations, features, and advantages described above for the DMA system 200 also apply to method 1000 and method 1100. For the sake of brevity, some operations, features, and advantages are not described herein again.

[0104] Although specific functions have been discussed above with reference to specific modules, it should be noted that the functions of the various modules discussed herein can be divided into multiple modules, and / or at least some of the functions of multiple modules can be combined into a single module. The actions performed by a specific module discussed herein include the specific module itself performing the action, or alternatively the specific module invoking or otherwise accessing another component or module that performs the action (or performs the action in combination with the specific module). Thus, a specific module that performs an action can include the specific module itself that performs the action and / or another module that the specific module invokes or otherwise accesses and that performs the action.

[0105] It should also be understood that the various techniques herein can be described in the general context of software or program modules. The various modules described above with respect to Figure 2 can be implemented in hardware or in hardware in combination with software and / or firmware. For example, these modules can be implemented as computer program code / instructions that are configured to execute in one or more processors and stored in a computer-readable storage medium. Alternatively, these modules can be implemented as hardware logic / circuits. For example, in some embodiments, one or more of the bandwidth change determination module 201 and the priority determination module 202 as Figure 2 shown can be implemented together in a system on a chip (SoC). The SoC can include an integrated circuit chip (which includes one or more components such as a processor (e.g., a central processing unit (CPU), a microcontroller, a microprocessor, a digital signal processor (DSP), etc.), a memory, one or more communication interfaces, and / or other circuits), and can optionally execute the received program code and / or include embedded firmware to perform functions.

[0106] According to an embodiment of the present disclosure, an electronic device is further provided, including the DMA system as described above in the present disclosure.

[0107] According to an embodiment of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is further provided, wherein the computer instructions are used to cause a computer to execute the method as described above.

[0108] According to an embodiment of the present disclosure, a computer program product is further provided, including a computer program, wherein the computer program, when executed by a processor, implements the method as described above.

[0109] Hereinafter, illustrative examples of such an electronic device will be described in conjunction with Figure 12 description.

[0110] Figure 12 FIG. Figure 12 illustrates an example configuration of an electronic device 1200 that may include the multi-channel-based DMA system described herein. It should be noted that Figure 12 the structure shown is merely an example, and according to specific implementation manners, the electronic device of the present disclosure may include only Figure 12 one or more of the components shown.

[0111] The electronic device 1200 may be various different types of devices. Examples of the electronic device 1200 include but are not limited to: desktop computers, server computers, laptop or netbook computers, mobile devices (e.g., tablet computers, cellular or other wireless telephones (e.g., smart phones), notepad computers, mobile stations), wearable devices (e.g., glasses, watches), entertainment devices (e.g., entertainment appliances, set-top boxes communicatively coupled to display devices, gaming consoles), televisions or other display devices, automotive computers, and so on.

[0112] The electronic device 1200 may include at least one processor 1202, a memory 1204, (multiple) communication interfaces 1206, a display device 1208, other input / output (I / O) devices 1210, one or more mass storage devices 1212, and one or more of the multi-channel-based DMA systems 1224 described herein that can communicate with each other, such as via a system bus 1214 or other suitable connections.

[0113] The processor 1202 may be a single processing unit or multiple processing units, and all processing units may include a single or multiple computing units or multiple cores. The processor 1202 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuits, and / or any device that manipulates signals based on operation instructions. In addition to other capabilities, the processor 1202 may be configured to obtain and execute computer-readable instructions stored in the memory 1204, the mass storage device 1212, or other computer-readable media, such as program code of an operating system 1216, program code of an application 1218, program code of other programs 1220, and so on.

[0114] Memory 1204 and mass storage device 1212 are examples of computer-readable storage media for storing instructions that are executed by processor 1202 to implement the various functions described above. For example, memory 1204 generally can include both volatile and non-volatile memory (e.g., RAM, ROM, etc.). In addition, mass storage device 1212 generally can include a hard disk drive, a solid state drive, removable media, including external and removable drives, memory cards, flash memory, floppy disks, optical disks (e.g., CD, DVD), storage arrays, network-attached storage, storage area networks, and the like. Memory 1204 and mass storage device 1212 can both be collectively referred to herein as memory or computer-readable storage media, and can be non-transitory media capable of storing computer-readable, processor-executable program instructions as computer program code that can be executed by processor 1202 as a particular machine configured to implement the operations and functions described in the examples herein.

[0115] Multiple programs can be stored on mass storage device 1212. These programs include operating system 1216, one or more application programs 1218, other programs 1220, and program data 1222, and they can be loaded into memory 1204 for execution. Examples of such application programs or program modules can include, for example, computer program logic (e.g., computer program code or instructions) for implementing method 1000 and / or additional embodiments described herein.

[0116] Although illustrated as being stored in memory 1204 of electronic device 1200 in Figure 12 the modules 1216, 1218, 1220, and 1222 or portions thereof can be implemented using any form of computer-readable medium accessible by electronic device 1200. As used herein, "computer-readable medium" includes at least two types of computer-readable media, namely computer-readable storage media and communication media.

[0117] A computer-readable storage medium includes volatile and non-volatile, removable and non-removable media implemented by any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer-readable storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVDs), or other optical storage devices, magnetic cassettes, magnetic tapes, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory medium that can be used to store information for access by an electronic device. In contrast, a communication medium can embody computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism. The computer-readable storage media as defined herein do not include a communication medium.

[0118] One or more communication interfaces 1206 are used to exchange data with other devices, such as via a network, a direct connection, and the like. Such communication interfaces can be one or more of the following: any type of network interface (e.g., network interface card (NIC)), wired or wireless (such as IEEE 802.11 wireless LAN (WLAN)) wireless interfaces, Worldwide Interoperability for Microwave Access (Wi-MAX) interfaces, Ethernet interfaces, Universal Serial Bus (USB) interfaces, cellular network interfaces, Bluetooth TM interfaces, Near Field Communication (NFC) interfaces, and the like. The communication interface 1206 can facilitate communication within a variety of network and protocol types, including wired networks (e.g., LAN, cable, etc.) and wireless networks (e.g., WLAN, cellular, satellite, etc.), the Internet, and the like. The communication interface 1206 can also provide communication with external storage devices (not shown) such as in storage arrays, network-attached storage, storage area networks, and the like.

[0119] In some examples, a display device 1208, such as a monitor, can be included for displaying information and images to a user. Other I / O devices 1210 can be devices that receive various inputs from a user and provide various outputs to the user, and can include touch input devices, gesture input devices, cameras, keyboards, remote controls, mice, printers, audio input / output devices, and the like.

[0120] The techniques described herein may be supported by these various configurations of the electronic device 1200 and are not limited to the specific examples of the techniques described herein. For example, the functionality may also be implemented in whole or in part on a “cloud” using a distributed system. The cloud comprises and / or represents a platform for resources. The platform abstracts the underlying functionality of the hardware (e.g., servers) and software resources of the cloud. The resources may include applications and / or data that may be used when performing computational processing on servers remote from the electronic device 1200. The resources may also include services provided over the Internet and / or over a subscriber network such as a cellular or Wi-Fi network. The platform may abstract the resources and functionality to connect the electronic device 1200 with other electronic devices. Accordingly, the implementation of the functionality described herein may be distributed across the entire cloud. For example, the functionality may be implemented in part on the electronic device 1200 and in part via a platform that abstracts the functionality of the cloud.

[0121] Although the present disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative and exemplary, and not restrictive; the present disclosure is not limited to the disclosed embodiments. Variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed subject matter, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps not listed, the indefinite article “a” or “an” does not exclude a plurality, the term “plural” means two or more, and the term “based on” shall be construed as “at least partially based on”. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A multi-channel based direct memory access system, comprising: A bandwidth change determination module, configured to determine a first change trend of a read bandwidth for reading data and a second change trend of a write bandwidth for writing data in each of a plurality of transmission channels of the direct memory access system; And A priority determination module, configured to adjust a value of a data transmission priority of at least one of the plurality of transmission channels based on the first change trend and the second change trend, where the value of the data transmission priority is used to indicate a data transmission time to be allocated to the at least one transmission channel, and wherein the priority determination module includes: A first priority determination module, configured to reduce the value of the data transmission priority of the at least one transmission channel in response to the first change trend corresponding to the at least one transmission channel among the plurality of transmission channels being a decrease in the read bandwidth; A second priority determination module, configured to reduce the value of the data transmission priority of the at least one transmission channel in response to the second change trend corresponding to the at least one transmission channel among the plurality of transmission channels being a decrease in the write bandwidth; and A third priority determination module, configured to increase the value of the data transmission priority of the at least one transmission channel in response to the first change trend corresponding to the at least one transmission channel among the plurality of transmission channels being an increase in the read bandwidth and the second change trend being an increase in the write bandwidth.

2. The system according to claim 1, wherein The first change trend is determined based on a change amount of a read delay count, and the read delay count represents a number of time intervals of delay when each of the plurality of transmission channels reads data.

3. The system according to claim 2, wherein, The bandwidth change determination module further includes a delay change amount determination module, including: A first delay count determination module, configured to determine a first delay count corresponding to each of the plurality of transmission channels when reading data at a first moment; A second delay count determination module, configured to determine a second delay count corresponding to each of the plurality of transmission channels when reading data at a second moment, where the second moment is a moment after the first moment; and A first change amount determination module, configured to determine a change amount of the read delay count of the transmission channel for each transmission channel based on a difference between the second delay count and the first delay count.

4. The system according to any one of claims 1 to 3, wherein The second change trend is determined based on a change amount of a backpressure count of each of the plurality of transmission channels, and the backpressure count represents a number of times the memory is occupied by other master devices outside the system when each of the plurality of transmission channels writes data to the memory.

5. The system according to claim 4, wherein, The bandwidth change determination module further includes a backpressure change amount determination module, including: A first backpressure count determination module, configured to determine a first backpressure count corresponding to each of the plurality of transmission channels when writing data to the memory at a first moment; A second backpressure count determination module, configured to determine a second backpressure count corresponding to each of the plurality of transmission channels when data is to be written to the memory at a second moment, where the second moment is the moment after the first moment; and A second change amount determination module, configured to, for each of the plurality of transmission channels, determine a change amount of the backpressure count of the transmission channel based on a difference between the second backpressure count and the first backpressure count.

6. The system according to any one of claims 1 to 3, wherein, The system further includes a transmission time determination module, including: A total priority determination module, configured to add up the data transmission priority values of each of the plurality of transmission channels to determine a sum of total priorities; A ratio calculation module, configured to, for at least one of the plurality of transmission channels whose data transmission priority values are adjusted, calculate a ratio of the data transmission priority value of the at least one transmission channel to the sum of the total priorities; and A time determination module, configured to determine the data transmission time to be allocated to the at least one transmission channel based on the ratio.

7. A multi-channel based direct memory access method, including: Determining a first change trend of a read bandwidth for reading data and a second change trend of a write bandwidth for writing data for each of the plurality of transmission channels of a direct memory access system; And Based on the first change trend and the second change trend, adjusting data transmission priority values of at least one of the plurality of transmission channels, where the data transmission priority values are used to indicate data transmission time to be allocated to the at least one transmission channel, and where adjusting the data transmission priority values of at least one of the plurality of transmission channels includes: In response to the first change trend corresponding to the at least one of the plurality of transmission channels being a decrease in the read bandwidth, reducing the data transmission priority value of the at least one transmission channel; In response to the second change trend corresponding to the at least one of the plurality of transmission channels being a decrease in the write bandwidth, reducing the data transmission priority value of the at least one transmission channel; and In response to the first change trend corresponding to the at least one of the plurality of transmission channels being an increase in the read bandwidth and the second change trend being an increase in the write bandwidth, increasing the data transmission priority value of the at least one transmission channel.

8. An electronic device, including the direct memory access system according to any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause a computer to execute the method according to claim 7.

10. A computer program product comprising a computer program, wherein, The computer program, when executed by a processor, implements the method according to claim 7.

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