Application method and device of switch compatible with interconnection, storage medium and electronic equipment

Abstract

The invention discloses an application method and device of a switch compatible with interconnection, a storage medium and electronic equipment, and relates to the technical field of servers, and the method comprises the steps: determining the input signal level of a target port through detecting the connection state of the target port; further, under the condition that the input signal level is the first level value, it can be determined that an input and output assembly in the switch control panel is in an equipment connection mode, and a semi-interconnection architecture mode of mounting equipment can be configured for the switch; and under the condition that the input signal level is the second level value, determining that the input and output components in the switch control panel are in the switch connection mode, thereby being capable of configuring a full interconnection architecture mode for the switches, solving the technical problem of insufficient compatibility of high-speed interconnection and flexible configuration of mounting equipment between the switches, and improving the switching efficiency. The technical effects that the port configuration can be adaptively switched according to the level of the input signal, and the semi-interconnection architecture of the mounting equipment and the full interconnection architecture between the switches are compatible are achieved.

Description

Technical Field

[0001] This application relates to the technical field of servers, and particularly to an application method and device, a storage medium, and an electronic device for a switch with compatible interconnection. Background Art

[0002] With the surging demand for artificial intelligence computing, the interconnection technology between GPUs (Graphics Processing Units) and NICs (Network Interface Controllers) in high-performance computing servers has become the key to improving the overall system efficiency. In the traditional interconnection architecture, GPUs and NICs are connected to the CPU (Central Processing Unit) through the PCIe bus (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard), but this architecture has communication bottlenecks and latency problems in large-scale parallel processing. The full interconnection architecture forms a PCIe Fabric network by directly interconnecting SWs (Switches, switch chips), greatly improving the communication efficiency and data processing speed between devices.

[0003] However, in the standard full interconnection architecture, to ensure high-speed communication between any two devices, a large number of downstream ports originally used to connect devices are converted into fabric ports for interconnection between SWs, restricting the number of GPUs and NICs that can be mounted. In addition, different customers have different configuration requirements for GPUs and NICs, and it is necessary to realize that while maintaining the interconnection between some SWs, other SW ports are allowed to mount more NICs to meet their specific requirements for network communication capabilities. That is, there is a technical problem of insufficient compatibility between high-speed interconnection between SWs and flexible configuration of mounted devices (such as GPUs and NICs) in the prior art. Summary of the Invention

[0004] This application provides an application method and device, a storage medium, and an electronic device for a switch with compatible interconnection, so as to at least solve the technical problem of insufficient compatibility between high-speed interconnection between SWs and flexible configuration of mounted devices (such as GPUs and NICs) in a full interconnection architecture AI server in the related art.

[0005] This application provides an application method for a switch with compatible interconnection, including: detecting the connection status of a target port on the switch control board; determining the input signal level of the target port based on the detected connection status of the target port; when the input signal level is a first level value, determining that the input / output component in the switch control board is in the device connection mode, and performing management configuration on the target device connected to the target port, where the target device is connected to the switch control board through a target connection device; when the input signal level is a second level value, determining that the input / output component in the switch control board is in the switch connection mode, and the switch control board and the reference switch control board communicate through their respective target ports.

[0006] The present application also provides an application device for a compatible and interconnected switch, including: a detection module for detecting the connection status of a target port on the switch control board; a first determination module for determining the input signal level of the target port based on the detected connection status of the target port; a second determination module for, when the input signal level is a first level value, determining that the input / output component in the switch control board is in the device connection mode and managing and configuring the target device connected to the target port, where the target device is connected to the switch control board through a target connection device; a third determination module for, when the input signal level is a second level value, determining that the input / output component in the switch control board is in the switch connection mode, and the switch control board and a reference switch control board communicate with each other through their respective target ports.

[0007] The present application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any one of the above application methods of the compatible and interconnected switch when executing the computer program.

[0008] The present application also provides a computer-readable storage medium storing a computer program, where the computer program implements the steps of any one of the above application methods of the compatible and interconnected switch when executed by a processor.

[0009] The present application also provides a computer program product including a computer program, where the computer program implements the steps of any one of the above application methods of the compatible and interconnected switch when executed by a processor.

[0010] Through the present application, since the input signal level of the target port is determined by detecting the connection status of the target port; furthermore, when the input signal level is a first level value, it can be determined that the input / output component in the switch control board is in the device connection mode, and a semi-interconnected architecture mode for the switch to configure the mounted device can be provided; when the input signal level is a second level value, it can be determined that the input / output component in the switch control board is in the switch connection mode, and a full-interconnected architecture mode can be provided for the switch, solving the technical problem of insufficient compatibility between high-speed interconnection between switches and flexible configuration of mounted devices, and achieving the technical effect of being able to adaptively switch port configuration according to the input signal level and being compatible with the semi-interconnected architecture of the mounted device and the full-interconnected architecture between switches. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0012] Figure 1 Schematic diagram of the connection of the switch chip for an application method of a compatible and interconnected switch provided by an embodiment of the present application;

[0013] Figure 2 Flowchart of an application method of a compatible and interconnected switch provided by an embodiment of the present application;

[0014] Figure 3 Schematic diagram of a semi - interconnected architecture for an application method of a compatible and interconnected switch provided by an embodiment of the present application;

[0015] Figure 4 Schematic diagram of a fully - interconnected architecture for an application method of a compatible and interconnected switch provided by an embodiment of the present application;

[0016] Figure 5 Circuit diagram of the connection between the switch and the device under the semi - interconnected architecture for an application method of a compatible and interconnected switch provided by an embodiment of the present application;

[0017] Figure 6 Circuit diagram of the interconnection between switches under the fully - interconnected architecture for an application method of a compatible and interconnected switch provided by an embodiment of the present application;

[0018] Figure 7 Flowchart of another application method of a compatible and interconnected switch provided by an embodiment of the present application;

[0019] Figure 8 Logical relationship diagram of an application method of a compatible and interconnected switch provided by an embodiment of the present application;

[0020] Figure 9 Logical relationship diagram of another application method of a compatible and interconnected switch provided by an embodiment of the present application;

[0021] Figure 10 Schematic diagram of a hardware interconnection topology provided by an embodiment of the present application;

[0022] Figure 11 Schematic diagram of the structure of an application device of a compatible and interconnected switch according to an embodiment of the present application;

[0023] Figure 12 Schematic diagram of the structure of an application electronic device of a compatible and interconnected switch according to an embodiment of the present application. Detailed implementation manners

[0024] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0025] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0026] In order to enable those skilled in the art of this technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0027] As Figure 1 shown, a connection schematic diagram of a PCIe Switch chip includes an access device 130, which represents an external device connected to the PCIe switching system. The device can be a graphics card, a network interface card, a storage device, etc. The connector 160 is the physical connection point between the access device and the switching chip 110, and is responsible for transmitting the data of the access device to the switching chip. Figure 1 There are two connectors 160, which are respectively located on the connection lines of the access device 130 and the processor 120, indicating that these two components are both connected to the switching chip through their respective connectors. The switching chip 110 is the central component of the entire system and is responsible for managing and controlling the flow of data between different devices. It can forward data from the input device to the output device as needed, such as the processor or the memory; the switching chip 110 is connected to different components through multiple ports, including the connector 160, the memory 140, and the controller 150.

[0028] The memory 140 is a component in the system for storing data, and is connected to other parts of the system through the switching chip 110, allowing read and write operations of data. The processor 120 is a component that executes computing tasks, and is connected to other parts of the system through the switching chip 110, and can access the data in the memory and perform processing operations. The controller 150 is a component in the system responsible for managing and controlling operations, and communicates with the switching chip 110 and the access device through port information to coordinate the transmission and processing of data.

[0029] Embodiments of the present application provide an application method for a compatible interconnection switch, and the method is described in detail in combination with the execution process of the application method for the compatible interconnection switch.

[0030] To more clearly understand the technical solutions provided by the embodiments of the present application, the key terms related to the embodiments of the present application are introduced herein:

[0031] Switch: In the present application, it can be expressed as a switch or an exchanger.

[0032] MCIO: Multi-Channel Input / Output, a high-speed signal connector used for PCIe signal transmission inside the chassis.

[0033] PCIe: Peripheral Component Interconnect Express, a high-speed signal used for high-speed transmission of I0 data within a computer system.

[0034] PCIe Switch: An I / O chip used to expand a group of PCIe signals into multiple groups of PCIe signals for expanding CPU I / O resources.

[0035] PCIe Fabric interconnection: A technical means to realize the transfer of PCIe data between SWs.

[0036] SW: In the present application, it refers to PCIe Switch.

[0037] PCBA: Printed Circuit Board Assembly, a circuit board.

[0038] CXL Switch: Compute Express Link Switch, an SW chip based on the CXL protocol.

[0039] FRU: Field Replaceable Unit, a field replaceable unit.

[0040] Riser Card: An expansion card.

[0041] CPLD (Complex Programmable Logic Device) is a complex digital integrated circuit and belongs to a type of programmable logic device (PLD).

[0042] BMC (Baseboard Management Controller) is a microcontroller, usually integrated on the server motherboard.

[0043] A MUX (Multiplexer), that is, a multiplexer, is an electronic component or integrated circuit that can selectively switch multiple input signals to a single output channel.

[0044] CEM (Common Expansion Module), a standard module interface design, especially suitable for expansion modules in high-performance computing and data center environments.

[0045] The CEM SLOT in this application refers to the slot on the Riser card, which is used to install or connect external devices (such as GPUs, NICs) to the PCIe bus of the server.

[0046] PERST (Peripheral Reset): Peripheral reset signal.

[0047] CLK BUFFER, clock buffer. CLK OE_N: Clock output enable signal. The Output Enable (OE) signal is a control signal used to turn on or off signal output. O1 (Output 1) is an output signal or pin of the CLKBUFFER, which represents the first output signal channel.

[0048] 100M Clock: 100 MHz clock signal, DP (Data Positive): Represents the positive phase signal line in the differential pair, which carries the positive phase information of the 100M Hz clock signal, DN (Data Negative): Represents the negative phase signal line in the differential pair, which carries the inverted phase signal of the clock signal.

[0049] I2C (Inter-Integrated Circuit): It is a serial bus protocol for simple two-way communication between microcontrollers and microprocessors. In this application, I2C is used to transmit control information, status information or perform device management, such as transmitting device configuration information between the Riser card and the SW board.

[0050] BMC_I2C_FRU_SCL: The clock signal line for the BMC to communicate with the FRU device through the I2C bus.

[0051] BMC_I2C_FRU_SDA: It is the data signal line for the BMC to communicate with the FRU device through the I2C bus.

[0052] I2C_FRU_SCL / SDA is a set of I2C signal lines used to communicate with the Field Replaceable Unit (FRU).

[0053] The I2C_SLOT_SCL / SDA signal is associated with the I2C communication interface on the PCIe slot in the server hardware and is used for the server system (such as BMC or CPLD) to communicate with the devices (such as GPU, NIC card) installed on the PCIe slot.

[0054] Slot Present signal (SLOT_PRSNT): A signal for detecting whether a PCIe device (such as GPU or NIC) is correctly inserted into the slot on the motherboard.

[0055] Riser Present signal (RISER_PRSNT): Used to detect whether the Riser card is inserted into a specific position on the SW board.

[0056] THROTTLE: Throttle signal. Used to control the data transfer rate of the device.

[0057] Bandwidth ID (BW_ID): Bandwidth identification signal, a signal for identifying the PCIe bandwidth level supported by the device.

[0058] SW_MODE: Mode signal selected by the switch. Used to indicate whether the SW port should be configured as a fabric mode or a downstream port mode.

[0059] MUX_SEL: Multiplexer selection signal. Used to control the signal selection of the MUX (multiplexer). According to the MUX_SEL signal, the MUX can switch different signal paths to ensure that the correct signal reaches the target port and avoid signal short - circuit or conflict.

[0060] BW_MODE: Bandwidth mode signal. Used to notify the SW how to configure its port bandwidth, such as x8 or x16.

[0061] Surelink Cable is a connection cable specifically designed for high - reliability and high - performance computing environments, mainly used for high - speed signal transmission inside or between servers.

[0062] As an alternative implementation, as Figure 2 shown, the application method of the above - mentioned compatible and interconnected switch includes:

[0063] S202, detecting the connection status of the target port on the switch control board;

[0064] Optionally, the above - mentioned switch control board can specifically be a PCIe Switch. The connection status of the above - mentioned target port includes idle (not connected) or non - idle (connected state), and it can be used to detect the devices connected to the switch.

[0065] S204. Determine the input signal level of the target port based on the detected connection status of the target port.

[0066] Optionally, once a physical connection to the target port is detected, the system further checks the level status of the input signal. By judging the level of the input signal, the system can distinguish whether the device is a Riser card, NIC, GPU, or another switch control board.

[0067] S206. When the input signal level is the first level value, determine that the input / output component in the switch control board is in the device connection mode, and perform management configuration on the target device connected to the target port, where the target device is connected to the switch control board through a target connection device.

[0068] Optionally, if the input signal shows the first level value (e.g., low level L), the system will determine that the target port is in the device mounting state, and the above target device is, for example, a GPU or NIC. Further, the MUX will be configured in the A = C mode (signal conduction) to allow the device and its functional signals (such as PERST, 100M CLOCK, etc.) to interact with the switch control board.

[0069] As Figure 3 shown in the "semi-interconnected" topology schematic diagram of GPU:NIC = 2:1, each switch SW consumes 2 x16 Ports for interconnection between SWs (shown as F ports in the figure). After removing one uplink port (shown as H port in the figure) for connection to the CPU, 6 x16 Ports in a 144-lane SW chip can be used for mounting GPUs / NICs (shown as D ports in the figure), achieving 2 ports for mounting NICs and 4 ports for mounting GPUs.

[0070] S208. When the input signal level is the second level value, determine that the input / output component in the switch control board is in the switch connection mode, and the switch control board and the reference switch control board communicate through their respective target ports.

[0071] Optionally, if the input signal is the second level value (e.g., high level H), the system will determine that the target port is in the inter-SW interconnection state (Fabric mode). Further, the configuration of the MUX will be set to the B = C mode (signal truncation) to ensure that only PCIe high-speed signals can be transmitted through the interconnection cable, avoiding interference from other auxiliary signals.

[0072] As Figure 4A data bridge is built between any two SWs in the shown topology, avoiding the P2P performance loss caused by data detouring through the CPU. Specifically, 3 x16 Ports are consumed for SW interconnection (as shown by the F ports in the figure), and then, excluding one uplink port (as shown by the H port in the figure) for connection to the CPU, 5 x16 Ports in a 144-lane SW chip can be used to mount GPUs / NICs (as shown by the D ports in the figure).

[0073] Through the above-described embodiments recorded in this application, by detecting the connection state of the target port, the input signal level of the target port is determined; furthermore, when the input signal level is the first level value, it can be determined that the input / output component in the switch control board is in the device connection mode, and a semi-interconnection architecture mode for mounting devices can be configured for the switch; when the input signal level is the second level value, it can be determined that the input / output component in the switch control board is in the switch connection mode, and a full-interconnection architecture mode can be configured for the switch, solving the technical problem of insufficient compatibility between high-speed interconnection between switches and flexible configuration of mounted devices, and achieving the technical effect of being able to adaptively switch port configuration according to the input signal level and being compatible with the semi-interconnection architecture of mounted devices and the full-interconnection architecture between switches.

[0074] In an alternative embodiment, determining the input signal level of the target port based on the detected connection state of the target port includes:

[0075] S1, when the on-board detection circuit is detected to be conducting by the level signal detection pin, determining that the input signal level of the target port is the first level value, where the level signal detection pin is inside the target port, and the on-board detection circuit is used to detect the on-board state of the target connection device;

[0076] S2, when the on-board detection circuit is detected to be disconnected by the level signal detection pin, determining that the input signal level of the target port is the second level value.

[0077] In the above step S1, as Figure 5 shown, MCIO is a signal definition based on the requirements of the downstream Riser, mainly including: PCIe x16 high-speed signals, PERST, 100M CLOCK, two I2Cs, Slot on-board, Riser on-board, bandwidth ID, Throttle, and many other signals. Each signal is defined on the corresponding connector pins (as shown by MCIO in the figure). It should be noted that the riser card is a wire-bonded board, and the signal correspondence when the board-end MCIO is connected to the wire-end MCIO is A to A and B to B.

[0078] The above-mentioned level signal detection pin is the MCIO A9 pin, which is used to monitor whether the signal pins of the Riser card or Device (such as GPU, NIC) are truly inserted into the target port (such as PE2 of SW0).

[0079] The above-mentioned presence detection circuit is used to identify the physical presence state of the target connection device (Riser card or Device). When the connection device is inserted, the circuit will conduct, pulling the level of the level signal detection pin down to the first level value (such as low level L). For example Figure 5 After the presence detection circuit in the figure conducts, the Riser Card sends the RISER_PRSNT signal to the CPLD of the SW board through the A9 pin. That is, when the Riser card is inserted, the above input signal level is a low-level signal.

[0080] Further, in the above step S2, as Figure 6 shown, the signal definition of the internal MCIO is the same as that defined in Figure 5 In the configuration mode of Figure 6 , both SW0 PE2 and SW1 PE1 are fabric ports, and SW0 PE2 needs to be interconnected with SW3PE1 in another layer of SW, and SW1 PE1 needs to be interconnected with SW2 PE2 in another layer of SW board, so as to realize a full-interconnection topology. When the MCIO at both ends of the two boards is interconnected through a cable, the signal corresponding relationship is A connected to B, and B connected to A.

[0081] The above-mentioned level signal detection pin A9 is connected to the suspended B9, and it is detected that the above-mentioned presence detection circuit is disconnected, and then the above input signal level is a high-level signal.

[0082] Through the above-mentioned implementation manners described in this application, when the level signal detection pin detects that the presence detection circuit is conducting, it is determined that the input signal level of the target port is the first level value; when the level signal detection pin detects that the presence detection circuit is disconnected, it is determined that the input signal level of the target port is the second level value; that is, by obtaining the riser presence signal from the MCIO A9 pin for configuration judgment and then executing the control of CLK and MUX, determining the signal output of the CPDL under different configurations, and controlling the on and off of the circuits transmitting relevant signals under different configurations, the technical effect of ensuring the normal operation of the system without adding special cables and being compatible with different configurations is achieved.

[0083] In an alternative implementation manner, when the level signal detection pin detects that the presence detection circuit is conducting, determining that the input signal level of the target port is the first level value includes:

[0084] S1. When it is detected that the pin connected to the level signal detection pin is the first pin, it is determined that the in-position detection circuit is conducting, where one end of the first pin is grounded.

[0085] S2. The input signal level received by the target port is the first level value.

[0086] In the above step S1, as Figure 5 shown, the pin connected to the level signal detection pin is A9 in the Riser Card, that is, the above-mentioned first pin, and one end of A9 is grounded.

[0087] Further in the above step S2, when the in-position detection circuit is conducting due to the insertion of the device, the level of the level signal detection pin will change from high level to low level, that is, the above-mentioned first level value can be low level.

[0088] Through the above-described embodiments recorded in the present application, when it is detected that the signal on the first pin (i.e., the MCIO A9 pin) connected to the level signal detection pin is conducting (i.e., the Riser card is in position and one end of the pin is grounded through the Riser card), the system can immediately recognize that the Riser card has been correctly inserted, thereby determining that the in-position detection circuit is in a conducting state, and further entering the device connection mode. In this mode, the CPLD automatically executes the control logic to configure components such as the MUX and CLK to ensure the correct conduction of signals and the normal operation of the device, avoiding the need for additional hardware adjustment or special cables when switching between different configurations, simplifying the system design, and improving the flexibility of mode switching.

[0089] In an alternative embodiment, when it is detected that the in-position detection circuit is disconnected at the level signal detection pin, it is determined that the input signal level of the target port is the second level value, including:

[0090] S1. When it is detected that the pin connected to the level signal detection pin is the second pin, it is determined that the in-position detection circuit is disconnected, where one end of the second pin is floating.

[0091] S2. The input signal level received by the target port is the second level value.

[0092] In the above step S1, as Figure 6 shown, the pin connected to the level signal detection pin in SW Board 1 is B9 in SW Board 2, that is, the above-mentioned second pin, and one end of B9 is set to be floating.

[0093] Further in the above step S2, the pull-up resistor inside the SW board will stabilize the level of the level signal detection pin at a high level, that is, the above-mentioned second level value can be high level.

[0094] Through the above-described embodiments recorded in the present application, it is immediately recognized that the Riser card is not inserted or has been removed, thereby determining that the in-position detection circuit is in an open state, entering the switch full-interconnection mode, simplifying the system design, and improving the flexibility of mode switching.

[0095] In an alternative embodiment, after determining that the input signal level of the target port is the first level value, it includes:

[0096] S1, the controller in the switch control board outputs a first strobe signal, where the first strobe signal is used to indicate the connection strategy of the pins in the input / output component;

[0097] S2, determine that the input / output component in the switch control board is in the device connection mode according to the first strobe signal;

[0098] S3, configure the target port as the downstream port mode based on the device connection mode, where the target port in the downstream port mode is used to connect to the target device.

[0099] In the above step S1, the controller may be, for example, the CPLD (Complex Programmable Logic Device) in the Figure 5 SW board in, the relevant CPLD input signal is default pull-up processed inside the board, the first strobe signal may be used to indicate the selection of the signal path in the MUX1 in the Figure 5 SW board in, and the input / output component may be MUX1. By outputting the first strobe signal, the system can enable a specific signal path to ensure that only the signals related to device interaction can be correctly transmitted.

[0100] Further in the above step S2, for example, in the above device connection mode, such as Figure 5 the type A pins and type C pins in MUX1 are connected in the

[0101] to make MUX1 internally conducting, and the same applies to MUX2; ensure that after the device (such as GPU, NIC) is connected to the target port, it can receive all necessary control and clock signals, realize the plug-and-play of the device, and improve the flexibility of system configuration and the usage efficiency of the device.

[0102] In an alternative embodiment, after determining that the input signal level of the target port is the second level value, it includes:

[0103] S1, the controller in the switch control board outputs a second strobe signal, where the second strobe signal is used to indicate the connection strategy of the pins in the input / output component;

[0104] S2. Determine that the input / output component in the switch control board is in the switch connection mode according to the second strobe signal;

[0105] S3. Configure the target port as the interconnection port mode based on the switch connection mode, where the target port in the interconnection port mode is used to connect to the reference switch control board.

[0106] In the above step S1, the above controller can be, for example, the CPLD (Complex Programmable Logic Device) in the SW board as in Figure 6 The above second strobe signal can indicate the selection of the signal path in MUX1 in the SW board as in Figure 6 The above input / output component can be MUX1.

[0107] In the above step S2, for example, in the above switch connection mode, as in Figure 6 In MUX1, the C-type pin is connected to the B-type pin to disconnect the inside of MUX1, and the same applies to MUX2; that is, except for the necessary high-speed data signals, the connections of the remaining signals will be isolated or blocked to adapt to the characteristics of the interconnection between SWs, and the relevant possible short-circuit signals can be isolated.

[0108] Optionally, in the above step S3, the controller (CPLD) can notify the SW0 chip through the SW_MODE signal to configure the target port as the interconnection port mode. That is, the target port will be specifically used for point-to-point communication with other switch control boards (such as SW3) to achieve smooth data flow under the full interconnection architecture.

[0109] Through the above implementation manners recorded in this application, when it is detected that the target port will be used for the interconnection between SWs, the CPLD will output a second strobe signal to indicate the MUX to switch to the corresponding signal isolation mode. In this mode, the MUX only allows PCIe high-speed signals to pass through, while truncating other control signals (such as PERST, 100M CLOCK, I2C, etc.) that may cause short circuits, avoiding the short-circuit risk caused by the connection of different types of signals through the cable during the interconnection between SWs. This dynamic signal isolation and management mechanism effectively ensures the stable operation and efficient communication of the full interconnection architecture AI server under different configurations, avoids signal conflicts at the hardware level, and improves the compatibility and flexibility of the system.

[0110] In an optional implementation manner, after configuring the target port as the downstream port mode based on the device connection mode, it includes:

[0111] S1. The controller on the switch control board detects the online state of the target device through the first conduction circuit, where the target connection device on the first conduction circuit is conducted with the controller through the input / output component;

[0112] S2. When the controller receives the device online signal, it outputs a clock enable signal, where the clock enable signal is used to provide a data transmission synchronization signal for the target device.

[0113] An optional implementation manner is used to illustrate the above steps S1 - S2. As Figure 5 shown, SLOT_PRSNT is in position, and the BW_ID (bandwidth ID) is sent by the Riser Card, led to the SW board through pins B11 and B8, and finally sent to the CPLD through MUX1, that is, when the controller receives the device online signal.

[0114] Once the CPLD detects the device online signal, that is, the device is in position and active, it sends a clock enable signal to the CLK buffer (clock buffer). The 100M differential clock is sent by Figure 5 the CLK BUFFER shown, connected to pins A11 / A12, and the port enable state of the CLK BUFFER is controlled by the CPLD.

[0115] Through the above implementation manner described in this application, the CPLD uses the first conduction circuit to detect the device in - position situation, and then outputs a clock enable signal according to the detection result, realizing the precise control of the signal and the synchronous activation of the device.

[0116] In an optional implementation manner, after outputting the clock enable signal when the controller receives the device online signal, it includes:

[0117] S1. The reset signal output by the controller is transmitted to the third pin on the switch control board through the first conduction circuit, and is transmitted to the target device through the reference third pin of the same type as the third pin on the target connection device, where the target device performs a reset operation according to the reset signal;

[0118] S2. The function signal output by the controller is transmitted to the fourth pin on the switch control board through the first conduction circuit, and is transmitted to the target device through the reference fourth pin of the same type as the fourth pin on the target connection device, where the function signal is used to reduce the power consumption of the target device;

[0119] S3. The reference controller on the switch control board transmits the target connection device communication signal to the fifth pin on the switch control board through the second conduction circuit, and is transmitted to the target connection device through the reference fifth pin of the same type as the fifth pin on the target connection device, where the target connection device on the second conduction circuit is conducted with the reference controller through the reference input - output component, and the target connection device communication signal is used to read the target connection device information of the target connection device;

[0120] S4, the reference controller on the switch control board transmits the device communication signal to the sixth pin of the switch control board through the second conduction circuit, and transmits it to the target device through the reference sixth pin of the same type as the sixth pin on the target connection device, where the device communication signal is used to read the device information of the target device.

[0121] An optional implementation manner is used to illustrate the above steps S1 - S4. As Figure 5 shown, the PERST signal is sent by the CPLD, passes through MUX1, and then is sent to the MCIO A8 pin, and finally reaches the CEM SLOT in the Riser Card, which is used to reset the above-mentioned target device connected to the slot; the THROTTLE signal is sent by the CPLD, passes through MUX1, and then is sent to the MCIO B12 pin, and finally reaches the CEM SLOT in the Riser Card, which is used to reduce the frequency and power consumption of the above-mentioned target device. One of the two I2C lines is connected to the FRU in the RiserCard to read the FRU information on the board, and the other is connected to the CEM SLOT to read the device information, which is sent by the BMC. That is, the above-mentioned reference controller can be the BMC, which is connected to the MCIO A29 / A30 and B29 / B30 pins after passing through MUX2, and finally reaches the Riser Card.

[0122] Through the above implementation manner, the device enters a stable state after reset, and its power consumption settings can be further adjusted without causing system instability. After reading the information of the target connection device, the system can manage the device communication signal more accurately, ensure the accuracy and integrity of the information, and thus optimize the device configuration and resource allocation.

[0123] In an optional implementation manner, the switch control board and the reference switch control board communicate with each other through their respective target ports, including:

[0124] S1, send a target data packet to the target port matching the reference switch control board through the target port matching the switch control board;

[0125] S2, determine the target receiving device based on the parsing result of the address identification information in the target data packet by the reference switch control board;

[0126] S3, forward the target data packet to the target receiving device through the receiving port matching the target receiving device on the reference switch control board.

[0127] The following uses a complete implementation manner to illustrate the above steps S1 - S3. The above data packet contains the destination address, control information, and actual data. Assume that Figure 4The GPU0 on SW-0 as shown needs to send data to GPU4 on SW-3. The target data packet will be sent from the downstream port of SW-0 connected to GPU0 to the fabric port on the SW board, and then transmitted to the fabric port of SW-3 through the Surelink cable.

[0128] When the target data packet arrives at SW-3, SW-3 will parse the address identification information (such as MAC address, IP address or device ID) in the data packet, and then determine which device is the final destination of the data packet according to the parsing result. For example, it is parsed that the above target receiving device is GPU4; the target data packet is transmitted to GPU4 through the downstream port corresponding to GPU4.

[0129] In an alternative embodiment, after determining that the input / output component in the switch control board is in the device connection mode, it includes:

[0130] S1. When it is detected that the bandwidth identifier of the target device corresponds to the first configuration condition, it is determined that the target device and the switch control board perform signal transmission through the first signal link;

[0131] S2. When it is detected that the bandwidth identifier of the target device corresponds to the second configuration condition, it is determined that the target device and the switch control board perform signal transmission through the second signal link, where the number of data channels in the second signal link is greater than the number of data channels in the first signal link.

[0132] Optionally, in the above step S1, the above first configuration condition may be the case where the target device requires x8 bandwidth. When the CPLD detects that the above bandwidth identifier (such as BW ID) signal meets the first configuration condition, it can configure the port of the SW (switch) as an x8 signal link through control signals such as MUX_SEL and OE_N to adapt to the lower bandwidth requirements of the device. The system automatically adjusts the width of the signal link to match the electrical characteristics of the x8 bandwidth. For example, it reduces the frequency of the clock signal and isolates unnecessary signal lines.

[0133] Optionally, in the above step S2, the above second configuration condition may be the case where the target device requires x16 bandwidth. When the CPLD detects that the above bandwidth identifier (such as BW ID) signal indicates that the device requires x16 bandwidth, it will configure the port of the SW as an x16 signal link. That is, all 16 data channels of the SW are activated to provide a higher data transmission rate. At the same time, the CLKBUFFER of the SW will output a clock signal that matches the x16 bandwidth requirement to ensure the integrity and synchronization of data transmission.

[0134] Through the above-described embodiments recorded in this application, triggered by the BW ID signal of the target device, the CPLD automatically selects the configuration steps based on the high or low level state of the signal, thereby adapting to the bandwidth requirements of the device. This dynamic configuration ability enables the system to intelligently adapt to the performance requirements of different devices without manual intervention or physical layer changes, greatly enhancing the flexibility and configuration compatibility of the system.

[0135] The following describes this application in a complete embodiment:

[0136] As shown in the flowchart Figure 7 shown: First, execute S702. Is RISER_PRSNT low?

[0137] When RISER_PRSNT is a low-level signal, RISER_PRSNT = L indicates that the Riser is present. Execute S704, the output of SW_MODE is low; the output of MUX_SEL is low. S706, SW0_PE2 is configured as a downstream port; MUX: A = C (signal conduction).

[0138] Further execute S708. Is SLOT_PRSNT low? If SLOT_PRSNT is high, it means that no device is mounted, and the step ends.

[0139] If SLOT_PRSNT is low, it means that a device is mounted. Continue to execute S710, the output of CLK_OE_N is low, specifically 100M CLK Enable. Judge S712. Is BW_ID low? If BW_ID is low, execute S714-1, the output of BW_MODE is low; SW0_PE2 is configured as x16. Otherwise, execute S714-2, the output of BW_MODE is high; SW0_PE2 is configured as x8x8. The corresponding logical relationship is as Figure 8 shown.

[0140] When RISER_PRSNT is a high-level signal, execute S716, the output of SW_MODE is high; the output of MUX_SEL is high. S718, SW0_PE2 is configured as Fabric; MUX: B = C (signal truncation). It should also be noted that the output of CLK_OE_N is high, specifically 100M CLK Disable. The corresponding logical relationship is as Figure 9 shown.

[0141] A schematic diagram of a hardware interconnection topology corresponding to the embodiment of this application is as Figure 10As shown in the figure, there are two PCIe Switches (SW0 and SW1) in the figure. Each is respectively connected to a CPU and multiple MCIO modules for signal transmission. It can be connected to a Slot for mounting devices, or used for high-speed and low-latency PCIe Fabric interconnection between the motherboard and the PCIe Switch (SW) board, and between SW boards through the Surelink Cable.

[0142] Each CPU is connected to a SW, forming an uplink port. For example, CPU0 is connected to the PE0 port of SW0, while CPU1 is connected to the PE3 port of SW1. This ensures that the CPU can directly interact with the SW and control the global resource allocation of the AI server.

[0143] SW0 and SW1 are interconnected with each other and with the SWs (SW2 and SW3) at another level through Fabric ports. The PE1, PE2, and PE3 ports of SW0 are respectively connected to the PE1 of SW2, the PE1 of SW3, and the PE0 of SW1, while the PE0, PE1, and PE2 ports of SW1 are respectively connected to the PE3 of SW0, the PE2 of SW2, and the PE2 of SW3. The above cross-interconnection method forms an efficient fully interconnected network, allowing direct communication between any two GPUs or NICs, significantly reducing data transmission latency, and improving P2P communication performance.

[0144] The downlink ports of the SW (such as PE4 to PE8 of SW0 and PE4 to PE8 of SW1) are used to mount GPUs and NICs. Each port can carry a x16 device, such as a GPU or NIC, and is connected to the corresponding Riser board through the MCIO module, thus realizing flexible expansion and signal adaptation of the device.

[0145] The Riser board serves as a bridge between the SW and the device, receives signals from the SW through the MCIO module, and transfers them to the GPU or NIC. The MCIO ports inside the Riser board are signal-matched with the MCIO ports at the device end, ensuring the correct transmission of signals.

[0146] The Fabric ports only transmit PCIe high-speed signals, while the uplink and downlink ports contain more functional signals, such as PERST, 100M CLOCK, I2C, presence signals, etc. Through signal processing on the MCIO module and the Riser board, it is ensured that under different configurations (such as Figure 3 the semi-interconnected architecture shown, Figure 4The compatibility and correctness of the signals in the fully interconnected architecture shown). In addition, through the slot presence and BW ID signals in this application, the SW can synchronously support x8x8 class devices (network cards / GPUs), further expanding the configuration compatibility.

[0147] Through the above implementation manners of this application, the MCIO signals are arranged. The CPLD makes configuration judgments based on the high and low levels of the Riser presence signal, and controls the MUX and buffer through the MUX_SEL and OE_N signals to physically isolate the MCIO-related signals. And the CPLD notifies the SW to synchronously execute the FW switch through the SW_MODE signal (when switching the SW Port attributes such as fabric or downstream, the corresponding FW file needs to be used), realizing the switching and compatibility of the configuration of the PE2 port, so as to select the PE2 port for connecting to the device or interconnecting with the switch. It should be noted that the same settings can also be made for multiple ports in the same way to increase the flexibility and diversity of the topology structure.

[0148] According to another aspect of the embodiments of this application, a compatible and interconnected switch is further provided, including:

[0149] Inside the switch control board, there are a connector, a controller, a reference controller, input / output components, reference input / output components, a clock buffer, and at least one port. Among them, the connector is used to transmit signals to the devices connected to the switch control board, the controller is used to output corresponding control signals according to the received signal levels, and the input / output components, reference input / output components, and clock buffer respectively determine their output signals according to the control signals;

[0150] Optionally, as Figure 5 shown in a switch control board (SW board), the above connector can be MCIO, the above controller can be CPLD, the above reference controller can be BMC, the above input / output components can be MUX1, the above reference input / output components can be MUX2, the above clock buffer can be CLK BUFFER, and at least one port, Figure 5 taking the PE2 port on SW0 as an example.

[0151] The connector is respectively connected to the controller through the input / output components, the target port, and the clock buffer;

[0152] Optionally, as Figure 5 shown in the SW board, the pins on the MCIO are connected to the pins on one side of the MUX1, and the pins on the other side of the MUX1 are connected to the pins on the CPLD; similarly, the MCIO can also be connected to the CPLD through the PE2, and the MCIO can also be connected to the CPLD through the CLK BUFFER.

[0153] The reference controller is connected to the connector through the reference input / output component.

[0154] Optionally, as Figure 5 shown in the SW board, the pins of the BMC are connected to the pins on one side of the MUX2, and the pins on the other side of the MUX2 are connected to the pins on the MCIO.

[0155] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0156] According to another aspect of the embodiments of the present application, there is also provided an application device of a compatible interconnection switch for implementing the application method of the above compatible interconnection switch. As Figure 11 shown, the device includes:

[0157] A detection module 1102, configured to detect the connection status of a target port on the switch control board;

[0158] A first determination module 1104, configured to determine the input signal level of the target port based on the detected connection status of the target port;

[0159] A second determination module 1106, configured to determine that the input / output component in the switch control board is in the device connection mode when the input signal level is a first level value, and manage and configure the target device connected to the target port, where the target device is connected to the switch control board through a target connection device;

[0160] A third determination module 1108, configured to determine that the input / output component in the switch control board is in the switch connection mode when the input signal level is a second level value, and the switch control board and the reference switch control board communicate with each other through their respective target ports.

[0161] Optionally, the above first determination module includes: a fourth determination unit, configured to determine that the input signal level of the target port is a first level value when the on-site detection circuit is detected to be conducting by the level signal detection pin, where the level signal detection pin is inside the target port, and the on-site detection circuit is used to detect the on-site status of the target connection device; and determine that the input signal level of the target port is a second level value when the on-site detection circuit is detected to be disconnected by the level signal detection pin.

[0162] Optionally, the above-mentioned fourth determination unit includes: a first detection unit, configured to determine that the in-position detection circuit is turned on when it is detected that the pin connected to the level signal detection pin is the first pin, where one end of the first pin is grounded; and the input signal level received by the target port is the first level value.

[0163] Optionally, the above-mentioned fourth determination module further includes: a second detection unit, configured to determine that the in-position detection circuit is turned off when it is detected that the pin connected to the level signal detection pin is the second pin, where one end of the second pin is floating; and the input signal level received by the target port is the second level value.

[0164] Optionally, the above-mentioned first detection unit includes: a first output unit, configured to output a first gating signal by a controller in the switch control board, where the first gating signal is used to indicate the connection strategy of the pins in the input / output component; determine that the input / output component in the switch control board is in the device connection mode according to the first gating signal; and configure the target port as the downlink port mode based on the device connection mode, where the target port in the downlink port mode is used to connect to the target device.

[0165] Optionally, the above-mentioned second detection unit includes: a second output unit, configured to output a second gating signal by a controller in the switch control board, where the second gating signal is used to indicate the connection strategy of the pins in the input / output component; determine that the input / output component in the switch control board is in the switch connection mode according to the second gating signal; and configure the target port as the interconnection port mode based on the switch connection mode, where the target port in the interconnection port mode is used to connect to the reference switch control board.

[0166] Optionally, the above-mentioned first output unit is further configured to detect the online status of the target device by a controller on the switch control board through a first conduction circuit, where the target connection device on the first conduction circuit is conducted with the controller through the input / output component; and output a clock enable signal when the controller receives the device online signal, where the clock enable signal is used to provide a data transmission synchronization signal for the target device.

[0167] Optionally, the above first output unit is further configured to transmit the reset signal output by the controller to the third pin on the switch control board through the first conduction circuit, and transmit it to the target device through the reference third pin of the same type as the third pin on the target connection device, where the target device performs a reset operation according to the reset signal; the function signal output by the controller is transmitted to the fourth pin on the switch control board through the first conduction circuit, and transmitted to the target device through the reference fourth pin of the same type as the fourth pin on the target connection device, where the function signal is used to reduce the power consumption of the target device; the reference controller on the switch control board transmits the target connection device communication signal to the fifth pin of the switch control board through the second conduction circuit, and transmits it to the target connection device through the reference fifth pin of the same type as the fifth pin on the target connection device, where the target connection device on the second conduction circuit is conducted with the reference controller through the reference input / output component, and the target connection device communication signal is used to read the target connection device information of the target connection device; the reference controller on the switch control board transmits the device communication signal to the sixth pin of the switch control board through the second conduction circuit, and transmits it to the target device through the reference sixth pin of the same type as the sixth pin on the target connection device, where the device communication signal is used to read the device information of the target device.

[0168] Optionally, the above third determination module includes a communication unit, configured to send a target data packet to a target port matching the reference switch control board through a target port matching the switch control board; determine a target receiving device based on the parsing result of the address identification information in the target data packet by the reference switch control board; and forward the target data packet to the target receiving device through a receiving port matching the target receiving device on the reference switch control board.

[0169] Optionally, the above second determination module is further configured to determine that the target device and the switch control board perform signal transmission through a first signal link when it is detected that the bandwidth identifier of the target device corresponds to a first configuration condition; determine that the target device and the switch control board perform signal transmission through a second signal link when it is detected that the bandwidth identifier of the target device corresponds to a second configuration condition, where the number of data channels in the second signal link is greater than the number of data channels in the first signal link.

[0170] For the description of the features corresponding to the embodiments of the application device of the compatible interconnected switch, reference may be made to the relevant description of the embodiments corresponding to the application method of the compatible interconnected switch, which will not be elaborated here one by one.

[0171] An embodiment of the present application further provides an electronic device, including a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above embodiments of the application method of the compatible interconnected switch.

[0172] The electronic device to which this application is applied can be a terminal device or a server. In this embodiment, the electronic device is taken as an example of a mobile phone and a computer. As Figure 12 shown, the electronic device includes a memory 1202 and a processor 1204. A computer program is stored in the memory 1202, and the processor 1204 is configured to execute the steps in any of the above method embodiments through the computer program.

[0173] Optionally, in this embodiment, the above electronic device can be at least one network device among multiple network devices in a computer network.

[0174] Optionally, those of ordinary skill in the art can understand that Figure 12 the structure shown is only schematic. The electronic device can also be a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a handheld computer, and a mobile Internet device (Mobile Internet Devices, MID), a PAD and other terminal devices. Figure 12 It does not limit the structure of the above electronic device. For example, the electronic device may further include more or fewer components (such as a network interface, etc.) than those shown in Figure 12 , or have a different configuration from that shown in Figure 12 .

[0175] Among them, the memory 1202 can be used to store software programs and modules, such as the program instructions / modules corresponding to the application method and device of the compatible interconnection switch in the embodiments of this application. The processor 1204 executes various functional applications by running the software programs and modules stored in the memory 1202, that is, to implement the application method of the above compatible interconnection switch. The memory 1202 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, a flash memory, or other non-volatile solid-state memories. In some instances, the memory 1202 may further include a memory remotely provided relative to the processor 1204, and these remote memories can be connected to the terminal through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof. Among them, the memory 1202 can specifically but not limitedly be used to store information such as signals and data. As an example, as Figure 12 shown, the above memory 1202 may include but are not limited to the detection module 1102, the first determination module 1104, the second determination module 1106, and the third determination module 1108 in the application device of the above compatible interconnection switch. In addition, it may further include but are not limited to other module units in the application device of the above compatible interconnection switch, which will not be elaborated in this example.

[0176] Optionally, the above-mentioned transmission device 1206 is used to receive or send data via a network. Specific examples of the above-mentioned network may include a wired network and a wireless network. In one example, the transmission device 1206 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices and routers through a network cable, so as to communicate with the Internet or a local area network. In one example, the transmission device 1206 is a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0177] In addition, the above-mentioned electronic device further includes: a display 1208; and a connection bus 1210 for connecting each module component in the above-mentioned electronic device.

[0178] In other embodiments, the above-mentioned terminal device or server may be a node in a distributed system. Among them, the distributed system may be a blockchain system, and the blockchain system may be a distributed system formed by connecting the multiple nodes through network communication. Among them, the nodes can form a point-to-point network, and any form of computing device, such as servers, terminals and other electronic devices, can become a node in the blockchain system by joining the point-to-point network.

[0179] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. Among them, the computer program is set to execute the steps in any of the above-mentioned application method embodiments of the compatible interconnection switch when running.

[0180] In an exemplary embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memory (Read-Only Memory, abbreviated as ROM), random access memory (Random Access Memory, abbreviated as RAM), mobile hard disks, magnetic disks or optical discs and other various media that can store computer programs.

[0181] An embodiment of the present application further provides a computer program product. The above-mentioned computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-mentioned application method embodiments of the compatible interconnection switch.

[0182] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-mentioned application method embodiments of the compatible interconnection switch.

[0183] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0184] The above has introduced in detail an application method, device, storage medium, and electronic device of a compatible and interconnected switch provided by this application. Specific examples are used herein to elaborate on the principles and implementation manners of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An application method of a compatible interconnection switch, characterized in that: include: Check the connection status of the target port on the switch control board; Determining an input signal level of the target port based on the detected connection status of the target port; When the input signal level is a first level value, determining that the input and output components in the switch control board are in device connection mode, and managing and configuring the target device connected to the target port, wherein the target device is connected to the switch control board through a target connection device; When the input signal level is a second level value, the input and output components in the switch control board are determined to be in switch connection mode, and the switch control board and the reference switch control board communicate with each other through their respective target ports.

2. The application method of the compatible interconnection switch according to claim 1, characterized in that: The step of determining the input signal level of the target port based on the detected connection state of the target port comprises: In the case where the level signal detection pin detects that the in-position detection circuit is turned on, determining that the input signal level of the target port is a first level value, wherein the level signal detection pin is inside the target port, and the in-position detection circuit is used to detect the in-position state of the target connection device; In a case where the level signal detection pin detects that the presence detection circuit is disconnected, it is determined that the input signal level of the target port is a second level value.

3. The application method of the compatible interconnection switch according to claim 2, characterized in that: The step of determining that the input signal level of the target port is a first level value when the level signal detection pin detects that the presence detection circuit is turned on comprises: In the case where it is detected that the pin connected to the level signal detection pin is a first pin, determining that the presence detection circuit is turned on, wherein one end of the first pin is grounded; The level of the input signal received by the target port is the first level value.

4. The application method of the compatible interconnection switch according to claim 2, characterized in that: When the level signal detection pin detects that the presence detection circuit is disconnected, determining that the input signal level of the target port is a second level value includes: In the case where it is detected that the pin connected to the level signal detection pin is the second pin, determining that the presence detection circuit is disconnected, wherein one end of the second pin is suspended; The level of the input signal received by the target port is the second level value.

5. The application method of the compatible interconnection switch according to claim 3, characterized in that: After determining that the input signal level of the target port is a first level value, the method further comprises: The controller in the switch control board outputs a first selection signal, wherein the first selection signal is used to indicate a connection strategy of pins in the input and output components; Determining, according to the first selection signal, that the input-output component in the switch control board is in the device connection mode; The target port is configured as a downstream port mode based on the device connection mode, wherein the target port in the downstream port mode is used to connect with the target device.

6. The application method of the compatible interconnection switch according to claim 4, characterized in that: After determining that the input signal level of the target port is a second level value, the method further comprises: The controller in the switch control board outputs a second selection signal, wherein the second selection signal is used to indicate a connection strategy of the pins in the input-output component; determining, according to the second selection signal, that the input-output component in the switch control board is in the switch connection mode; The target port is configured as an interconnect port mode based on the switch connection mode, wherein the target port in the interconnect port mode is used to connect to the reference switch control board.

7. The application method of the compatible interconnection switch according to claim 5, characterized in that: After configuring the target port as a downlink port mode based on the device connection mode, the method includes: The controller on the switch control board detects the online state of the target device through a first conduction circuit, wherein the target connection device on the first conduction circuit is connected to the controller through the input-output component; When the controller receives a device online signal, the controller outputs a clock enable signal, wherein the clock enable signal is used to provide a data transmission synchronization signal for the target device.

8. The application method of the compatible interconnection switch according to claim 7, characterized in that: After the controller receives the device online signal and outputs the clock enable signal, the method includes: The reset signal output by the controller is transmitted to the third pin on the switch control board through the first conduction circuit, and is transmitted to the target device through a reference third pin of the same type as the third pin on the target connection device, wherein the target device performs a reset operation according to the reset signal; The function signal output by the controller is transmitted to the fourth pin on the switch control board through the first conduction circuit, and is transmitted to the target device through the reference fourth pin of the same type as the fourth pin on the target connection device, wherein the function signal is used to reduce power consumption for the target device; The reference controller on the switch control board transmits the target connection device communication signal to the fifth pin of the switch control board through the second conduction circuit, and transmits it to the target connection device through the reference fifth pin of the target connection device of the same type as the fifth pin, wherein the target connection device on the second conduction circuit is connected to the reference controller through the reference input and output component, and the target connection device communication signal is used to read the target connection device information of the target connection device; The reference controller on the switch control board transmits the device communication signal to the sixth pin of the switch control board through the second conduction circuit, and transmits it to the target device through a reference sixth pin of the same type as the sixth pin on the target connection device, wherein the device communication signal is used to read the device information of the target device.

9. The application method of the compatible interconnection switch according to claim 1, characterized in that: The switch control board and the reference switch control board communicate with each other through their respective target ports, including: Sending a target data packet to the target port matching the reference switch control board through the target port matching the switch control board; Determine a target receiving device based on the parsing result of the reference switch control board on the address identification information in the target data packet; The target data packet is forwarded to the target receiving device through a receiving port on the reference switch control board that matches the target receiving device.

10. The application method of the compatible interconnection switch according to claim 1, characterized in that: After determining that the input and output components in the switch control board are in device connection mode, the method includes: In the case where it is detected that the bandwidth identifier of the target device corresponds to the first configuration condition, determining that the target device and the switch control board perform signal transmission through the first signal link; When it is detected that the bandwidth identifier of the target device corresponds to the second configuration condition, it is determined that the target device and the switch control board transmit signals through a second signal link, wherein the number of data channels in the second signal link is greater than the number of data channels in the first signal link.

11. A switch compatible with interconnection, characterized in that: include: The switch control board includes a connector, a controller, a reference controller, an input-output component, a reference input-output component, a clock buffer and at least one port, wherein the connector is used to transmit a signal to a device connected to the switch control board, the controller is used to output a corresponding control signal according to a received signal level, and the input-output component, the reference input-output component and the clock buffer respectively determine their own output signals according to the control signal; The connector is connected to the controller through the input and output components, the target port and the clock buffer respectively; The reference controller is connected to the connector via the reference input and output component.

12. An application device of a switch compatible with interconnection, characterized in that: include: A detection module, used to detect the connection status of a target port on a switch control board; A first determination module determines an input signal level of the target port based on the detected connection state of the target port; A second determination module is used to determine that the input and output components in the switch control board are in device connection mode when the input signal level is a first level value, and manage and configure the target device connected to the target port, wherein the target device is connected to the switch control board through a target connection device; The third determination module is used to determine that the input and output components in the switch control board are in switch connection mode when the input signal level is a second level value, and the switch control board and the reference switch control board communicate through their respective target ports.

13. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the application method of the compatible interconnection switch according to any one of claims 1 to 10 when executing the computer program.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the application method of the compatible interconnection switch according to any one of claims 1 to 10.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the application method of the compatible interconnection switch according to any one of claims 1 to 10 are implemented.

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