Method for forming product identification number of system on chip
By reading the initial storage value of the static random storage unit as the product identification number during wafer testing of SoC products, the problem of increasing chip area and testing time when writing the unique identification number is solved, and the effect of saving costs and ensuring uniqueness is achieved.
Patent Information
- Application Number
- CN202510034439.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-09
- Publication Date
- 2025-05-30
AI Technical Summary
When writing a unique identification number to each product in SoC products, a write circuit needs to be added, resulting in an increase in chip area, an increase in test write time and an increase in cost.
By powering on the system on chip during wafer testing and performing a read operation on the static random storage unit, its initial stored value is obtained as the product identification number.
There is no need to add an identification number writing circuit, which reduces the chip area and test writing time, while saving costs, and ensures the uniqueness of each product through the randomness of the initial storage value of the static random storage unit.
Smart Images
Figure CN120067041A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and particularly relates to a method for forming a product identification number of a system-on-chip. Background Art
[0002] A system-on-chip (SoC), also known as a system-level chip, refers to a product, which is an integrated circuit with a dedicated target, including a complete system and all the content of the embedded software. At the same time, it is also a technology used to realize the entire process from determining the system function, to software and hardware partitioning, and to completing the design. A system-on-chip generally includes a CPU, a memory, an instruction cache, a data cache, and various interface circuits.
[0003] For mass-produced SoC products to ensure the traceability of failures after packaging, it is necessary to write a unique identification number for each product. To achieve this function, additional writable circuits such as eFuses need to be added in the design.
[0004] An electronic fuse (eFuse) is a programmable electronic fuse. Due to its non-volatile storage and one-time programmable characteristics, it is widely used in chip design and verification. Since the eFuse technology is mature, there are already various semiconductor intellectual properties (IP or IP cores) on the market. In the chip design stage, only need to purchase the eFuse IP as needed and add the corresponding control module, then the eFuse IP can be quickly applied to the self-developed chip.
[0005] However, when using writable circuits such as eFuses to write a unique identification number for each product of mass-produced SoC products, the writable circuits such as eFuses not only increase the chip area, but also increase the additional test writing time and increase the IP cost. Summary of the Invention
[0006] The purpose of the present invention is to provide a method for forming a product identification number of a system-on-chip to solve at least one of the problems of increasing the writable circuit in the design, increasing the chip area, increasing the test writing time, and increasing the cost when writing a unique identification number for products in SoC products.
[0007] To solve the above technical problems, the present invention provides a method for forming a product identification number of a system-on-chip, including:
[0008] Providing a system-on-chip, the system-on-chip including a chip and a plurality of static random access memory units located on the chip;
[0009] During wafer testing, power on the system-on-chip and perform a read operation on the static random access memory unit in the system-on-chip to obtain the initial stored value of the static random access memory unit, and the initial stored value of the static random access memory unit constitutes the product identification number of the system-on-chip.
[0010] Optionally, the initial stored value of the static random access memory unit is 0 or 1.
[0011] Optionally, after powering on the system-on-chip, affected by the initial disturbance signal, the probability that the initial stored value of the static random access memory unit is 0 or 1 is 50% each.
[0012] Optionally, the layout arrangements of adjacent static random access memory units are symmetric to each other.
[0013] Optionally, adjacent static random access memory units include left-right adjacent and up-down adjacent.
[0014] Optionally, the initial stored values of the static random access memory units are randomly distributed.
[0015] Optionally, the number of the read results of the initial stored values of the static random access memory units is at least greater than 10 3 times the number of the product identification numbers of the system-on-chip.
[0016] Optionally, the number of the read results of the initial stored values of the static random access memory units is:
[0017] N = ab2 n
[0018] Wherein, n is the number of static random access memory units in each logical address, a is the number of logical addresses in a block area, b is the number of block areas in the array area of the entire memory unit, and a, b, and n are natural numbers greater than 0.
[0019] Optionally, after obtaining the product identification number of the system-on-chip, record the product identification number of the system-on-chip and the corresponding information of the system-on-chip.
[0020] Optionally, the corresponding information of the system-on-chip includes the manufacturer of the product, the production time of the product, and the production process of the product.
[0021] In the method for forming the product identification number of the system-on-chip provided by the present invention, during wafer testing, the system-on-chip is powered on, and a read operation is performed on the static random access memory cells in the system-on-chip to obtain the initial stored value of the static random access memory cells. The initial stored value of the static random access memory cells constitutes the product identification number of the system-on-chip. Due to the randomness of the initial stored value of the static random access memory cells, the uniqueness of the sequence of memory cells corresponding to each logical address is caused. Therefore, the initial stored value of the static random access memory cells can be used as a characteristic value representing each logical address. Since the system-on-chip in the present invention includes static random access memory cells, only by adding a read program for a partial length of the static random access memory cells during wafer testing, a unique identification number can be assigned to each product, avoiding the additional increase in chip area due to adding an identification number writing circuit and the additional test writing time, and saving costs. That is, compared with the prior art, no additional one-time programmable memory writing circuit needs to be added in the present invention. Therefore, the chip area occupied by the one-time programmable memory is reduced. At the same time, in the present invention, the identification number does not need to be read separately. Therefore, the test time for reading the identification number is saved. And the cost of the one-time programmable memory writing circuit is saved. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:
[0023] Figure 1 is a flowchart of the method for forming the product identification number of the system-on-chip according to an embodiment of the present invention.
[0024] Figure 2 is a layout schematic diagram of the static random access memory cells in the system-on-chip according to an embodiment of the present invention.
[0025] Figure 3 is a butterfly curve diagram of the static random access memory cells in the system-on-chip according to an embodiment of the present invention.
[0026] Figure 4 is a schematic diagram of the storage area in the system-on-chip according to an embodiment of the present invention.
[0027] In the drawings:
[0028] 10 - static random access memory cells; 20 - logical address. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0029] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in a very simplified form and are not drawn to scale, and are only used to facilitate and clearly assist in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the accompanying drawings need to show different emphases and sometimes use different scales.
[0030] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features. In addition, as used in the present invention, an element being disposed on another element generally only means that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the two elements may be directly or indirectly connected, coupled, cooperated or transmitted through an intermediate element, and cannot be construed as indicating or implying the spatial position relationship between the two elements, that is, an element may be inside, outside, above, below or on one side of another element, etc. in any orientation, unless otherwise explicitly specified in the content. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0031] Figure 1 It is a flowchart of a method for forming a product identification number of a system-on-chip according to an embodiment of the present invention. As Figure 1 shown, this embodiment provides a method for forming a product identification number of a system-on-chip, including:
[0032] Step S10, providing a system-on-chip, the system-on-chip including a chip and a plurality of static random access memory units located on the chip;
[0033] Step S20, when performing wafer testing, powering on the system-on-chip and performing a read operation on the static random access memory units in the system-on-chip to obtain an initial stored value of the static random access memory units, and the initial stored value of the static random access memory units constitutes the product identification number of the system-on-chip.
[0034] Figure 2It is a layout schematic diagram of a static random access memory unit in a system-on-chip according to an embodiment of the present invention. A system-on-chip generally includes a CPU, a memory, an instruction cache, a data cache, and various interface circuits. The memory in the system-on-chip includes an array area of memory cells. Specifically, the array area of memory cells is divided into multiple block areas; each block area includes multiple logical addresses, and each logical address includes multiple bit cells, and the bit cells are, for example, static random access memory units 10. As Figure 2 shown, in the layout of the chip, the layout arrangements of adjacent static random access memory units 10 are symmetric to each other. Specifically, adjacent static random access memory units 10 include the static random access memory units 10 adjacent left and right and the static random access memory units 10 adjacent up and down. That is, any one of the static random access memory units 10 is symmetric with the static random access memory units 10 on its left and right sides, and any one of the static random access memory units 10 is symmetric with the static random access memory units 10 on its upper and lower sides. In other words, any one of the static random access memory units 10 is symmetric with the four surrounding static random access memory units 10.
[0035] Figure 3 It is a butterfly curve graph of a static random access memory unit in a system-on-chip according to an embodiment of the present invention. As Figure 3 shown, in the ideal case without process deviation, the left and right structures of the static random access memory unit 10 are completely symmetric. After power-on and affected by the initial disturbance signal, the probability of the stable state of the static random access memory unit 10 being 0 or 1 is 50% each. That is, the initial stored value of the static random access memory unit 10 is 0 or 1. After the system-on-chip is powered on and affected by the initial disturbance signal, the probability that the initial stored value of the static random access memory unit 10 is 0 or 1 is 50% each. In the actual situation, each independent static random access memory unit 10 has a process deviation. After power-on and affected by the initial disturbance signal, an initial stored value of 0 or 1 will stably appear. For adjacent static random access memory units 10, due to the layout arrangements being symmetric up and down and left and right, the differences in the static random access memory units 10 caused by the process deviation are different. After power-on and affected by the initial disturbance signal, the stable state of the static random access memory unit 10 is 0 or 1, showing a random distribution. That is, the initial stored values of the static random access memory units are randomly distributed. Based on the randomness of the initial stored values of the static random access memory units, the uniqueness of the sequence of static random access memory units corresponding to each logical address can be obtained, which can be used as a characteristic value representing each logical address. Therefore, the initial stored values of the static random access memory units corresponding to each logical address can be used as the identification number of the chip, that is, the identification number of the system-on-chip, and can also be called the serial number or identification code of the chip, so that when there are quality problems in the chip in the subsequent system-on-chip, such as chip failure, the system-on-chip has traceability to find the cause of chip failure in the system-on-chip.
[0036] The initial stored value of the static random access memory cell, which serves as the identification number of the chip, must satisfy that the number of permutations and combinations of the initial stored values of the static random access memory cells is much larger than the number of chips in this batch. That is to say, the number of permutations and combinations of the initial stored values of the static random access memory cells is much larger than the number of systems on a chip, so as to ensure that the probability of the same identification number of the system on a chip appearing is 0.
[0037] Specifically, the number of the read results of the initial stored values of the static random access memory cells is at least 10 times greater than the number of the product identification numbers of the systems on a chip. 3 times.
[0038] The number of the read results of the initial stored values of the static random access memory cells 10 is:
[0039] N = ab2 n
[0040] Wherein, n is the number of static random access memory cells in each logical address, a is the number of logical addresses in a block area, b is the number of block areas in the array area of the entire memory cell, and a, b, and n are natural numbers greater than 0.
[0041] Figure 4 is a schematic diagram of the storage area in the system on a chip according to an embodiment of the present invention. In this embodiment, the number of static random access memory cells 10 in each logical address 20 is 32, that is, DQ0, DQ1... DQ31. That is to say, 32 static random access memory cells 10 constitute a logical address 20. Block1 includes 32 logical addresses 20, that is, each Block includes 32 logical addresses. The array area (Array) of the entire memory cell includes 64 Blocks, that is, the array area of the entire memory cell includes Block1, Block2... Block64. Since each logical address 20 includes 32 static random access memory cells 10, the 32-bit output of reading the 32 static random access memory cells 10 in one logical address 20 is, for example, 0xF161B453 (hexadecimal), which is converted to binary as 1110001011000011011010001010011, corresponding to the initial stored values of DQ31... DQ1, DQ0. The number of the read results of the initial stored values of the static random access memory cells 10 in this embodiment is:
[0042] N = ab2 n = 64 * 32 * 2 32 = 8.79 * 10 12
[0043] That is to say, the number of products of the system on a chip does not exceed 8.79 * 10 9In the case of [quantity], the probability that the product identification numbers of two system-on-chips are the same is 0. Those skilled in the art can select the read length of the static random access memory according to the quantity of system-on-chips in this batch. When using the initial stored value of a partial length of the static random access memory as the product identification number of the system-on-chip, generally start reading from the static random access memory at the beginning to the static random access memory with a preset length.
[0044] In another embodiment, due to the randomness of the initial stored value of the static random access memory, it results in the uniqueness of the storage unit sequence corresponding to each logical address. By reading a part of the storage units of the embedded SRAM, an SoC product serial number can be formed. Generally, the packaging batch will be printed on the packaged IC, that is, the in-chip product serial number only needs to be unique within the packaging batch. Assume that during wafer testing, the first 20 bits of the static random access memory embedded in the SoC product are read. This sequence can distinguish more than one million products at most (2 20 ), which is sufficient to accommodate the total quantity of a batch of packaged SoC products.
[0045] After obtaining the product identification number of the system-on-chip, record the product identification number of the system-on-chip and the corresponding information of the system-on-chip. The corresponding information of the system-on-chip includes the manufacturer of the product, the production time of the product, and the production process of the product. In this embodiment, using the initial stored value of the static random access memory as the product identification number of the system-on-chip avoids adding a one-time programmable memory writing circuit. Therefore, it reduces the chip area occupied by the one-time programmable memory. At the same time, in this embodiment, there is no need to separately read the identification number. The method for forming the product identification number of the system-on-chip in this embodiment only needs to add a read test of the SRAM during wafer-level testing to obtain the initial stored value of the static random access memory as the product identification number of the system-on-chip. Therefore, it saves the test time for reading the identification number of the system-on-chip. Also, without adding a one-time programmable memory writing circuit, it saves the intellectual property cost of the one-time programmable memory writing circuit. It is worth emphasizing that the method for forming the product identification number of the system-on-chip in this embodiment is applicable to SoC products including SRAM at any process node.
[0046] In subsequent processes, if problems such as chip failure occur in the chip in the system-on-chip, the corresponding process and production time of the chip in the system-on-chip can be traced to determine the cause of the failure of the system-on-chip.
[0047] In summary, in the method for forming the product identification number of the system-on-chip provided in the embodiment of the present invention, when performing wafer testing, the system-on-chip is powered on, and a read operation is performed on the static random access memory unit in the system-on-chip to obtain the initial stored value of the static random access memory unit, and the initial stored value of the static random access memory unit constitutes the product identification number of the system-on-chip. Based on the randomness of the initial stored value of the static random access memory unit, the uniqueness of the storage unit sequence corresponding to each logical address is caused. Therefore, the initial stored value of the static random access memory unit can be used as a characteristic value representing each logical address. Since the system-on-chip in the present invention includes a static random access memory unit, only by adding a read program for a partial length of the static random access memory unit during wafer testing, a unique identification number can be assigned to each product, avoiding the additional increase in chip area due to adding an identification number writing circuit and the additional test writing time, and saving costs. That is, compared with the prior art, no additional one-time programmable memory writing circuit needs to be added in the present invention. Therefore, the chip area occupied by the one-time programmable memory is reduced. At the same time, since the present invention does not need to separately read the identification number, the test time for reading the identification number is saved. And the cost of the one-time programmable memory writing circuit is saved.
[0048] It should be noted that the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same and similar parts among the various embodiments can be referred to each other. In addition, the different parts among the various embodiments can also be combined and used with each other. The present invention does not limit this.
[0049] In addition, it should also be recognized that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belong to the scope of protection of the technical solution of the present invention.
Claims
1. A method for forming a product identification number of a system on chip, characterized in that: include: Provide a system on a chip, the system on a chip comprising a chip and a plurality of static random access memory cells located on the chip; During wafer testing, the system on chip is powered on, and a read operation is performed on the static random access memory cells in the system on chip to obtain initial storage values of the static random access memory cells, which constitute a product identification number of the system on chip.
2. The method for forming a system-on-chip product identification number according to claim 1, characterized in that: The initial storage value of the static random access memory cell is 0 or 1.
3. The method for forming a system-on-chip product identification number according to claim 1, characterized in that: After the system on chip is powered on, under the influence of the initial disturbance signal, the probability that the initial storage value of the static random access memory cell is 0 or 1 is 50%.
4. The method for forming a system-on-chip product identification number according to claim 1, characterized in that: The layouts of adjacent static random access memory cells are symmetrical to each other.
5. The method for forming a system-on-chip product identification number according to claim 4, characterized in that: The adjacent static random access memory cells include left-right adjacent and top-bottom adjacent.
6. The method for forming a system-on-chip product identification number according to claim 1, characterized in that: The initial storage values of the static random storage units are randomly distributed.
7. The method for forming a system-on-chip product identification number according to claim 1, characterized in that: The number of the initial storage value reading results of the static random access memory cell is at least greater than 10 times the number of the product identification number of the system on chip 3 times.
8. The method for forming a system-on-chip product identification number according to claim 7, characterized in that: The number of initial storage value reading results of the static random access memory cell is: N=ab2 n Wherein, n is the number of static random storage units in each logical address, a is the number of logical addresses in a block area, b is the number of block areas in the array area of the entire storage unit, and a, b and n are natural numbers greater than 0.
9. The method for forming a system-on-chip product identification number according to claim 1, characterized in that: After obtaining the product identification number of the system on chip, the product identification number of the system on chip and corresponding information of the system on chip are recorded.
10. The method for forming a system-on-chip product identification number according to claim 9, characterized in that: The corresponding information of the system on chip includes the manufacturer of the product, the production time of the product and the production process of the product.