Data verification method and device, electronic equipment, storage medium and chip

Abstract

The invention provides a data verification method, which comprises the steps of transmitting target data to a secure storage area, generating a first verification code corresponding to the target data in the process of transmitting the target data, and verifying the target data after the target data is transmitted. And determining the integrity of the target data according to a comparison result of the first check code and a pre-recorded second check code. According to the embodiment, data transmission and check code generation can be completed in a parallel mode, and the data check efficiency is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of data verification, and in particular, to a method and apparatus for verifying data, an electronic device, a storage medium, and a chip. Background Art

[0002] Data integrity is one of the three basic elements of information security; during the process of transmitting and storing data, it is ensured that the data is not tampered with without authorization or can be quickly detected after being tampered with. Summary of the Invention

[0003] The present disclosure provides a method and apparatus for verifying data, an electronic device, a storage medium, and a chip to solve the problems in the related art, and can complete data transmission and generation of verification codes in a parallel manner, improving the data verification efficiency.

[0004] A first aspect embodiment of the present disclosure proposes a method for verifying data, the method comprising:

[0005] Transmitting target data to a secure storage area;

[0006] Generating a first verification code corresponding to the target data during the transmission of the target data;

[0007] After the transmission of the target data is completed, determining the integrity of the target data according to the comparison result between the first verification code and the recorded second verification code.

[0008] In some embodiments of the present disclosure, before generating the first verification code corresponding to the target data during the transmission of the target data, the method further comprises:

[0009] Configuring a generator of the first verification code.

[0010] In some embodiments of the present disclosure, the configuring of the generator of the first verification code comprises:

[0011] Configuring whether to enable the generator of the first verification code;

[0012] Configuring the type of the first verification code to be generated.

[0013] In some embodiments of the present disclosure, the transmitting the target data to the secure storage area comprises:

[0014] Sending a transmission instruction to a direct memory access controller DMAC so that the DMAC transfers the target data from a non-secure storage area to the secure storage area.

[0015] In some embodiments of the present disclosure, generating a first check code corresponding to the target data during the transmission of the target data includes:

[0016] After transmitting the target data based on the DMAC and configuring the generator for enabling the generation of the first check code, generating the first check code corresponding to the target data based on the generator, wherein the generator is configured in the DMA C;

[0017] Storing the first check code in a check code register, where the check code register is configured in the DMAC.

[0018] In some embodiments of the present disclosure, determining the integrity of the target data according to the comparison result between the first check code and the second check code includes:

[0019] Reading the first check code from the check code register;

[0020] Reading the second check code from a preset memory or register;

[0021] Comparing the first check code with the second check code;

[0022] If it is determined that the first check code is consistent with the second check code, it is determined that the target data is not damaged during transmission;

[0023] If it is determined that the first check code is inconsistent with the second check code, it is determined that the target data is damaged during transmission.

[0024] In some embodiments of the present disclosure, the second check code is pre-recorded in a certificate.

[0025] A second aspect embodiment of the present disclosure provides a data verification device, and the device includes:

[0026] A transmission unit, configured to transmit target data to a secure storage area;

[0027] A generation unit, configured to generate a first check code corresponding to the target data during the transmission of the target data;

[0028] A verification unit, configured to determine the integrity of the target data according to the comparison result between the first check code and the second check code after the transmission of the target data is completed.

[0029] In some embodiments of the present disclosure, the device further includes:

[0030] A configuration unit, configured to configure the generator for the first check code before generating the first check code corresponding to the target data during the transmission of the target data.

[0031] In some embodiments of the present disclosure, the configuration unit is further configured to:

[0032] Configure whether to enable the generator of the first check code;

[0033] Configure the type of the first check code to be generated.

[0034] In some embodiments of the present disclosure, the transmission unit is further configured to send a transmission instruction to a direct memory access controller (DMAC), so that the DMAC transfers the target data from a non-secure storage area to the secure storage area.

[0035] In some embodiments of the present disclosure, the generation unit is further configured to:

[0036] After the target data is transferred based on the DMAC and the generator of the first check code is configured to be enabled, generate a first check code corresponding to the target data based on the generator, wherein the generator is configured in the DMAC;

[0037] Store the first check code in a check code register, and the check code register is configured in the DMAC.

[0038] In some embodiments of the present disclosure, the verification unit is further configured to:

[0039] Read the first check code from the check code register;

[0040] Read the second check code from a preset memory or register;

[0041] Compare the first check code with the second check code;

[0042] If it is determined that the first check code is consistent with the second check code, it is determined that the target data is not damaged during transmission;

[0043] If it is determined that the first check code is inconsistent with the second check code, it is determined that the target data is damaged during transmission.

[0044] In some embodiments of the present disclosure, the second check code is pre-recorded in a certificate.

[0045] A third aspect embodiment of the present disclosure provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method described in the first aspect embodiment of the present disclosure.

[0046] A fourth aspect embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the method described in the first aspect embodiment of the present disclosure.

[0047] A fifth aspect embodiment of the present disclosure provides a chip, including one or more interface circuits and one or more processors; the interface circuit is used to receive a signal and send the signal to the processor, and the signal includes computer instructions; when the processor executes the computer instructions, an electronic device is caused to execute the method described in the first aspect embodiment of the present disclosure.

[0048] In summary, according to the data verification method proposed by the present disclosure, the method includes transmitting target data to a secure storage area, generating a first verification code corresponding to the target data during the transmission of the target data, and determining the integrity of the target data according to the comparison result between the first verification code and the recorded second verification code after the transmission of the target data is completed. This embodiment can complete data transmission and generation of verification codes in a parallel manner, improving the data verification efficiency.

[0049] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure, and do not constitute an improper limitation to the present disclosure.

[0051] Figure 1 It is a flowchart of a data verification method provided by an embodiment of the present disclosure;

[0052] Figure 2 It is a schematic diagram of the principle of a data verification method provided by an embodiment of the present disclosure;

[0053] Figure 3 It is a flowchart of a data verification method provided by an embodiment of the present disclosure;

[0054] Figure 4 It is a schematic diagram of the principle of a data verification method provided by an embodiment of the present disclosure;

[0055] Figure 5 It is a schematic structural diagram of a data verification device provided by an embodiment of the present disclosure;

[0056] Figure 6 It is a schematic structural diagram of a data verification device provided by an embodiment of the present disclosure;

[0057] Figure 7 A structural schematic diagram of an electronic device provided by an embodiment of the present disclosure;

[0058] Figure 8 A structural schematic diagram of a chip provided by an embodiment of the present disclosure. Detailed implementation manners

[0059] The embodiments of the present disclosure will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, but should not be construed as limiting the present disclosure.

[0060] Data integrity is one of the three basic elements of information security; during the process of transmitting and storing data, it is ensured that the data is not tampered with without authorization or can be quickly detected after being tampered with.

[0061] In the related art, data is transmitted from a non-secure storage area to a secure storage area through a Direct Memory Access Controller (DMAC). After the transmission is completed, a checksum of the data is calculated. Finally, the calculated checksum is compared with the known checksum, and the integrity of the data is determined according to the comparison result. The above solution adopts a serial method, first transmitting the data and then calculating the checksum, and the check efficiency is relatively low.

[0062] Therefore, in order to solve the problems existing in the related art, the present disclosure proposes a method for verifying data. The target data is transmitted to a secure storage area. During the transmission of the target data, a first checksum corresponding to the target data is generated. After the transmission of the target data is completed, the integrity of the target data is determined according to the comparison result between the first checksum and the recorded second checksum.

[0063] This solution can complete data transmission and checksum generation in a parallel manner, improving the data verification efficiency.

[0064] The embodiments of the present disclosure are not exhaustive. They are only illustrations of some embodiments and do not constitute specific limitations on the protection scope of the present disclosure. Without contradiction, each step in a certain embodiment can be implemented as an independent embodiment, and the steps can be combined arbitrarily. For example, the solution after removing some steps in a certain embodiment can also be implemented as an independent embodiment, and the order of the steps in a certain embodiment can be exchanged arbitrarily. In addition, the optional implementation manners in a certain embodiment can be combined arbitrarily; furthermore, the embodiments can be combined arbitrarily. For example, some or all of the steps of different embodiments can be combined arbitrarily, and a certain embodiment can be combined arbitrarily with the optional implementation manners of other embodiments.

[0065] In each embodiment of the present disclosure, without special instructions and logical conflicts, the terms and / or descriptions among the embodiments are consistent and can be cited from each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0066] The terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments and do not constitute a limitation on the present disclosure.

[0067] In the embodiments of the present disclosure, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above-mentioned", "said", "afore-mentioned", "this", etc., can mean "one and only one", or can also mean "one or more", "at least one", etc. For example, in the case of using articles such as "a", "an", "the" in English translation, the noun after the article can be understood as a singular expression or a plural expression.

[0068] In some embodiments, terms such as "in response to...", "in response to determining...", "in the case of...", "when...", "while...", "if...", etc. can be replaced with each other.

[0069] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not lower than", "above", etc. can be replaced with each other, and terms such as "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "not more than", "lower than", "lower than or equal to", "not higher than", "below", etc. can be replaced with each other.

[0070] In the embodiments of the present disclosure, prefix words such as "first" and "second" are only used to distinguish different described objects, and do not impose limitations on the position, order, priority, quantity, content, etc. of the described objects. The description of the described objects shall refer to the description in the claims or the context of the embodiments, and no redundant limitations shall be constituted due to the use of prefix words.

[0071] In the embodiments of the present disclosure, "a plurality of" means two or more.

[0072] In the embodiments of the present disclosure, terms such as "import", "input", "read in" can be replaced with each other.

[0073] In some embodiments, a device, etc. can be interpreted as physical or virtual, and its name is not limited to the name recorded in the embodiments. Terms such as "device", "equipment", "device", "circuit", "network element", "node", "function", "unit", "section", "system", "network", "chip", "chip system", "entity", "subject" can be replaced with each other.

[0074] In some embodiments, terms such as "terminal", "terminal device", "user equipment (UE)", "user terminal", "mobile station (MS)", "mobile terminal (MT)", subscriber station, mobile unit, subscriber unit, wireless unit, remote unit, mobile device, wireless device, wireless communication device, remote device, mobile subscriber station, access terminal, mobile terminal, wireless terminal, remote terminal, handset, user agent, mobile client, client can be replaced with each other.

[0075] Figure 1 The flowchart of a data verification method provided by an embodiment of the present disclosure. This method can be applicable to application scenarios such as processors. For example, it can be executed by a processor integrated with data transmission and data verification functions or a terminal including a processor, or by other devices suitable for data transmission and verification, which is not limited in the present disclosure. As Figure 1 shown, this data verification method includes steps 101-103.

[0076] Step 101: Transmit the target data to the secure storage area.

[0077] The method described in the embodiment of the present disclosure is applicable to the secure verification scenario of any type of data.

[0078] The target data is any type of data used for secure verification, such as application data, image data, etc., which is not limited.

[0079] In some embodiments, obtaining data, information, etc. may comply with the laws and regulations of the country where it is located.

[0080] In some embodiments, data, information, etc. may be obtained after obtaining user consent.

[0081] Please refer to Figure 2 , Figure 2 which is a schematic diagram of the principle of a data verification method provided by an embodiment of the present disclosure. The target data is usually stored in a non-volatile memory (such as a flash memory). When performing a security verification, it is necessary to first read the target data from the flash memory to the non-secure storage area, and then read the target data from the non-secure storage area to the secure storage area.

[0082] The secure storage area and the non-secure storage area described in the embodiment of the present disclosure are hardware partitions of the chip's memory address space. The memory address space of the chip can be its own memory address space or can include an external memory. The storage area of this memory is divided into a secure storage area and a non-secure storage area. Specifically, the present disclosure does not specifically limit the secure storage area and the non-secure storage area.

[0083] Step 102: Generate a first check code corresponding to the target data during the transmission of the target data.

[0084] In the embodiment of the present disclosure, while performing the transmission of the target data, it is also necessary to generate the first check code in parallel. By executing the data transmission and the generation of the check code in parallel, the time consumed for verification is shortened and the verification efficiency is improved.

[0085] In some embodiments, the first check code can be generated by controlling a generator. The specific process of generating the check code can refer to any implementation method in the related art, so it will not be elaborated here.

[0086] Step 103. After the target data transmission is completed, determine the integrity of the target data according to the comparison result between the first check code and the recorded second check code.

[0087] In one embodiment of the present disclosure, the second check code may be recorded in a certificate.

[0088] The processor reads the second check code recorded in the certificate, compares the first check code with the second check code. If it is determined that the first check code is consistent with the second check code, it is determined that the target data is not damaged during transmission, that is, it indicates that the target data meets the integrity; if it is determined that the first check code is inconsistent with the second check code, it is determined that the target data is damaged during transmission, that is, it indicates that the integrity of the target data is damaged or tampered with.

[0089] In summary, according to the data verification method proposed by the present disclosure, the method includes transmitting target data to a secure storage area. During the transmission of the target data, a first check code corresponding to the target data is generated. After the target data transmission is completed, determine the integrity of the target data according to the comparison result between the first check code and the second check code, where the second check code is recorded in a certificate. This embodiment can complete data transmission and generation of check codes in parallel, improving the data verification efficiency.

[0090] To achieve parallel execution of data transmission and check code generation, the present disclosure embodiment configures the generator of the first check code to configure whether to enable the generator during data transmission. If the generator is configured to execute in parallel with data transmission, that is, the generator is enabled, then when executing data transmission, generate the first check code based on the generator in parallel.

[0091] In some embodiments, the generator may also be configured to disable the generator, that is, when data is transmitted, the generator does not execute to generate the first check code.

[0092] In the specific application process, configuring the generator of the first check code includes two aspects. In addition to the above embodiment of configuring whether to enable the generator of the first check code; the other aspect also includes: configuring the type of the first check code generated. When configuring the type of the first check code, it is necessary to know the type of the second check code in advance, and configure the type of the first check code based on the type of the second check code to ensure that the first check code and the second check code can be compared. In the present disclosure embodiment, the type of the first check code may include but is not limited to sha1 / sha2 / crc, etc. Specifically, the present disclosure embodiment does not limit the type of the check code.

[0093] Figure 3Further shows a flowchart of a data verification method proposed by the present disclosure.

[0094] Step 301: Send a transfer instruction to the Direct Memory Access Controller (DMAC) so that the DMAC transfers the target data from the non-secure storage area to the secure storage area.

[0095] The processor (taking the CPU as an example) sends a transfer instruction to the Direct Memory Access Controller (DMAC). In the embodiments of the present disclosure, the DMAC is usually included in the processor or is part of the processor. When a large amount of data needs to be transferred, the processor sends a transfer request to the DMAC, and then the DMAC takes over the bus control right to perform data transfer.

[0096] Reference can continue to Figure 3 , the processor sends a transfer instruction to the generator configuration register, the DMAC reads and executes the transfer instruction, and transfers the target data from the non-secure storage area to the secure storage area. For the process of the DMAC transferring the target data, reference can be made to the detailed description in the related art, so it will not be elaborated here.

[0097] Step 302: After the DMAC transfers the target data and the generator for enabling the first check code is configured and enabled, generate the first check code corresponding to the target data based on the generator, where the generator is configured in the DMAC.

[0098] It can be seen from step 301 that the processor sends a transfer instruction to the generator configuration register to control the transfer of the target data. In addition, an instruction to enable the generator is also sent to the generator configuration register, so that when the DMAC transfers the target data, the generator synchronously generates the first check code corresponding to the target data, improving the efficiency of data verification.

[0099] Please refer to Figure 4 , the DMAC is configured with a generator configuration register: used to configure the generator, which can configure whether to enable the generator and the type of check code to be generated; it is configured with a generator for generating the first check code; it is configured with a check code register: used to store the generated first check code.

[0100] Step 303: Store the first check code in the check code register, and the check code register is configured in the DMAC.

[0101] Step 304: Read the first check code from the check code register, and read the second check code from a preset memory or register.

[0102] After the DMAC generates the first check code, it stores the first check code in the check code register. When the processor performs the comparison, it reads the first check code in the check code register, and reads the certificate stored in the preset memory space or register, and obtains the second check code recorded in the certificate.

[0103] Step 305: Compare the first check code with the second check code.

[0104] If it is determined that the first check code is consistent with the second check code, execute step 306; if it is determined that the first check code is inconsistent with the second check code, execute step 307.

[0105] Step 306: Determine that the target data is not damaged during transmission.

[0106] Step 307: Determine that the target data is damaged during transmission.

[0107] Corresponding to the above data verification method, the present invention also provides a data verification device. Since the device embodiment of the present invention corresponds to the above method embodiment, for the details not disclosed in the device embodiment, reference may be made to the above method embodiment, and details will not be repeated in the present invention.

[0108] Figure 5 FIG. 600 is a schematic structural diagram of a data verification device provided by an embodiment of the present disclosure. The data verification device includes:

[0109] A transmission unit 61, configured to transmit target data to a secure storage area;

[0110] A generating unit 62, configured to generate a first check code corresponding to the target data during the transmission of the target data;

[0111] A verification unit 63, configured to determine the integrity of the target data according to the comparison result of the first check code and the second check code after the transmission of the target data is completed, where the second check code is recorded in a certificate.

[0112] In summary, according to the data verification device proposed by the present disclosure, the device includes transmitting target data to a secure storage area, generating a first check code corresponding to the target data during the transmission of the target data, and determining the integrity of the target data according to the comparison result of the first check code and the second check code after the transmission of the target data is completed, where the second check code is recorded in a certificate. This embodiment can complete data transmission and generation of check codes in parallel, improving data verification efficiency.

[0113] Further, in a possible implementation manner of an embodiment of the present disclosure, as Figure 6As shown, the device further includes:

[0114] A configuration unit 64, configured to configure a generator of the first check code before generating the first check code corresponding to the target data during the transmission of the target data.

[0115] Further, in a possible implementation manner of the embodiment of the present disclosure, as Figure 6 shown, the configuration unit 64 is further configured to:

[0116] Configure whether to enable the generator of the first check code;

[0117] Configure the type of the first check code to be generated.

[0118] Further, in a possible implementation manner of the embodiment of the present disclosure, as Figure 6 shown, the transmission unit 61 is further configured to send a transmission instruction to a direct memory access controller DMAC, so that the DMAC transfers the target data from a non-secure storage area to the secure storage area.

[0119] Further, in a possible implementation manner of the embodiment of the present disclosure, as Figure 6 shown, the generating unit 62 is further configured to:

[0120] After the target data is transferred based on the DMAC and the generator of the first check code is configured to be enabled, generate the first check code corresponding to the target data based on the generator, wherein the generator is configured in the DMA C;

[0121] Store the first check code in a check code register, and the check code register is configured in the DMAC.

[0122] Further, in a possible implementation manner of the embodiment of the present disclosure, as Figure 6 shown, the checking unit 63 is further configured to:

[0123] Read the first check code from the check code register;

[0124] Read the second check code from a preset memory or register;

[0125] Compare the first check code with the second check code;

[0126] If it is determined that the first check code is consistent with the second check code, it is determined that the target data is not damaged during transmission;

[0127] If it is determined that the first check code is inconsistent with the second check code, it is determined that the target data is damaged during transmission.

[0128] Further, in a possible implementation manner of the embodiments of the present disclosure, the second check code is pre-recorded in the certificate.

[0129] Since the device provided by the embodiments of the present disclosure corresponds to the methods provided by the above several embodiments, the implementation manners of the methods are also applicable to the device provided by this embodiment and will not be described in detail in this embodiment.

[0130] In the above embodiments provided by the present application, the methods and devices provided by the embodiments of the present application are introduced. To implement the various functions in the methods provided by the embodiments of the present application, an electronic device may include a hardware structure and software modules, and implement the above various functions in the form of a hardware structure, software modules, or a combination of a hardware structure and software modules. A certain function among the above various functions may be executed in the form of a hardware structure, software module, or a combination of a hardware structure and software module.

[0131] Figure 7 FIG. is a block diagram of an electronic device 800 for implementing the above data verification method according to an exemplary embodiment. For example, the electronic device 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0132] Refer to Figure 7 , the electronic device 800 may include one or more of the following components: a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0133] The processing component 802 generally controls the overall operation of the electronic device 800, such as operations associated with display, telephone calls, data communication, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the above methods. In addition, the processing component 802 may include one or more modules to facilitate the interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate the interaction between the multimedia component 808 and the processing component 802.

[0134] The memory 804 is configured to store various types of data to support the operation of the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phone book data, messages, pictures, videos, and the like. The memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disk.

[0135] The power supply component 806 provides power to various components of the electronic device 800. The power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 800.

[0136] The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can sense not only the boundaries of touch or swipe actions but also detect the duration and pressure associated with the touch or swipe operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have focal length and optical zoom capabilities.

[0137] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC) that is configured to receive external audio signals when the electronic device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals can be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, the audio component 810 further includes a speaker for outputting audio signals.

[0138] The I / O interface 812 provides an interface between the processing component 802 and a peripheral interface module, which can be a keyboard, a click wheel, buttons, etc. These buttons can include, but are not limited to: a home button, a volume button, a start button, and a lock button.

[0139] The sensor assembly 814 includes one or more sensors for providing status assessment of various aspects of the electronic device 800. For example, the sensor assembly 814 can detect the on / off state of the electronic device 800, the relative positioning of components, such as components for the display and keypad of the electronic device 800. The sensor assembly 814 can also detect a change in the position of the electronic device 800 or a component of the electronic device 800, the presence or absence of user contact with the electronic device 800, the orientation or acceleration / deceleration of the electronic device 800, and the temperature change of the electronic device 800. The sensor assembly 814 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 814 can also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 can also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0140] The communication component 816 is configured to facilitate communication between the electronic device 800 and other devices in a wired or wireless manner. The electronic device 800 can access a wireless network based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (New Radio), or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 further includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0141] In an exemplary embodiment, the electronic device 800 can be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for performing the above method.

[0142] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, and the above instructions can be executed by a processor 820 of the electronic device 800 to complete the above method in image processing. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0143] Embodiments of the present disclosure also provide a non-transitory computer-readable storage medium storing computer instructions, where the computer instructions are used to cause a computer to execute the methods described in the above embodiments of the present disclosure.

[0144] For the case where the electronic device can be a chip or a chip system, reference can be made to Figure 8 the schematic structural diagram of the chip shown. Figure 8 The chip shown includes a processor 901 and an interface 902. Among them, the number of processors 901 can be one or more, and the number of interfaces 902 can be multiple.

[0145] Optionally, the chip further includes a memory 903, and the memory 903 is used to store necessary computer programs and data.

[0146] Those skilled in the art can also understand that the various illustrative logical blocks and steps listed in the embodiments of the present application can be implemented by electronic hardware, computer software, or a combination of both. Whether such a function is implemented by hardware or software depends on the specific application and the design requirements of the entire system. Those skilled in the art can use various methods to implement the functions for each specific application, but such implementation should not be construed as exceeding the scope of protection of the embodiments of the present application.

[0147] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present disclosure described herein can be implemented in an order different from those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0148] In the description of this specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0149] Any process or method description represented in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a specific logical function or process, and the scope of the preferred embodiments of the present invention includes additional implementations, where functions may be executed in a manner substantially simultaneous or in an order opposite to that shown or discussed, according to the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0150] The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered a sequenced list of executable instructions for implementing a logical function, and can be embodied specifically in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, a system including a processing module, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection having one or more wires (control method), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable medium on which a program can be printed, as the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpretation, or other suitable processing as necessary, and then stored in a computer memory.

[0151] It should be understood that various parts of the embodiments of the present invention can be implemented with hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented with software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented with hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0152] Those of ordinary skill in the art can understand that all or part of the steps carried out in the method of the above embodiments can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0153] In addition, each functional unit in the various embodiments of the present invention can be integrated in a processing module, or each unit can exist physically alone, or two or more units can be integrated in a module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disc, etc.

[0154] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A data verification method, characterized in that: The method comprises: Transferring target data to a secure storage area; During the transmission of the target data, generating a first check code corresponding to the target data; After the target data transmission is completed, the integrity of the target data is determined according to the comparison result between the first verification code and the recorded second verification code.

2. The method according to claim 1, characterized in that: During the transmission of the target data, before generating a first check code corresponding to the target data, the method further includes: The generator of the first verification code is configured.

3. The method according to claim 2, characterized in that The configuring the generator of the first verification code includes: Configure whether to enable the generator of the first verification code; Configure the type of generating the first verification code.

4. The method according to claim 3, characterized in that The transferring of the target data to the secure storage area comprises: A transfer instruction is sent to a direct memory access controller DMAC so that the DMAC transfers the target data from the non-secure storage area to the secure storage area.

5. The method according to claim 4, characterized in that In the process of transmitting the target data, generating a first check code corresponding to the target data includes: After transmitting the target data based on the DMAC and configuring and enabling the generator of the first check code, generating a first check code corresponding to the target data based on the generator, wherein the generator is configured in the DMAC; The first check code is stored in a check code register, and the check code register is configured in the DMAC.

6. The method according to claim 5, characterized in that The determining the integrity of the target data according to the comparison result of the first check code and the second check code comprises: Reading the first check code from the check code register; Reading the second verification code from a preset memory or register; Comparing the first verification code with the second verification code; If it is determined that the first verification code is consistent with the second verification code, it is determined that the target data is not damaged during transmission; If it is determined that the first verification code is inconsistent with the second verification code, it is determined that the target data is damaged during transmission.

7. The method according to claim 1, characterized in that The second verification code is pre-recorded in the certificate.

8. A data verification device, characterized in that: The device comprises: A transmission unit, used for transmitting target data to a secure storage area; A generating unit, configured to generate a first check code corresponding to the target data during the transmission of the target data; The verification unit is used to determine the integrity of the target data according to the comparison result between the first verification code and the recorded second verification code after the transmission of the target data is completed.

9. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-7.

11. A chip, characterized in that: The chip comprises one or more interface circuits and one or more processors; the interface circuit is used to receive a signal and send the signal to the processor, wherein the signal comprises a computer instruction; when the processor executes the computer instruction, the chip executes the method described in any one of claims 1 to 7.

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