Data processing method and device, storage medium and electronic equipment

Abstract

The embodiment of the invention provides a data processing method and device, a storage medium and electronic equipment, and relates to the technical field of computers, and the device comprises a data filling module which is used for carrying out data filling on received first data to obtain second data; splitting the second data to obtain at least one block message; the message word extension module is used for performing message word extension on each block message to obtain a message word for compression calculation; the compression function module is used for performing compression calculation on the message word to obtain a calculation result; the compression function module adopts an assembly line calculation framework formed based on a compressor and a working variable register, calculation variables required by compression calculation are stored in the compression function module, and the calculation variables change along with the change of the round number. In this way, the problem that in the prior art, a cryptographic chip is low in large-scale data safety calculation efficiency is solved through a pipeline calculation architecture, and the data calculation efficiency is improved in combination with the pre-stored calculation variables.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a data processing method, apparatus, storage medium, and electronic device. Background Art

[0002] The cryptographic chip is an important solution for the secure startup and data encryption of host devices to ensure the stable operation of the system and data security. As the only hashing algorithm in the national cryptographic algorithms, the SM3 algorithm is widely used in data security. Therefore, developing a high-performance and low-complexity SM3 hardware accelerator is of great significance for enhancing the national information security and the independent innovation ability of cryptographic technologies.

[0003] Currently, many cryptographic chips based on the SM3 algorithm still adopt the traditional serial computing architecture. When implementing the algorithm in hardware, the complex compression function calculation path is not optimized, but the RTL description of combinational logic is directly used. The traditional serial architecture has low throughput and cannot meet the encryption and decryption requirements of large-scale data streams; the complex compression function calculation path limits the working frequency of the SM3 algorithm and reduces the calculation efficiency. In addition, in the technical solutions implemented by a small amount of parallel computing hardware, the problem of resource utilization rate is not considered, resulting in excessive consumption of logic resources and low performance and efficiency. Summary of the Invention

[0004] The present disclosure provides a data processing method, apparatus, storage medium, and electronic device to at least solve the above technical problems existing in the prior art.

[0005] The technical solution of the embodiment of the present disclosure is implemented as follows: In a first aspect, the embodiment of the present disclosure provides a data processing apparatus, where the apparatus includes: A data padding module, configured to perform data padding on the received first data to obtain second data; and split the second data to obtain at least one block message; A message word expansion module, configured to perform message word expansion on each block message to obtain message words for compression calculation; A compression function module, configured to perform compression calculation on the message words to obtain a calculation result; the compression function module adopts a pipeline calculation architecture based on a compressor and working variable registers, and calculation variables required for compression calculation are stored in the compression function module, and the calculation variables change with the number of rounds.

[0006] In the above solution, the compressor in the compression function module includes: a first CSA (Carry-Save Adder), a second CSA, and a third CSA; The first CSA is used to perform a first addition operation, which is an addition operation on a first specific operation result, a first register value, and a first message word; The second CSA is used to perform a second addition operation, which is an addition operation on a first shift result, the calculation variable, and a second register value; The third CSA is used to perform a third addition operation, which is an addition operation on a second specific operation result, a third register value, and a second message word; wherein, the second message word is a processing result of the first message word.

[0007] In the above solution, the compression function module includes: a memory, which is used to receive the number of rounds and output the calculation variable corresponding to the number of rounds.

[0008] It is also used to receive and store at least one number of rounds required for compression calculation and the calculation variable corresponding to each number of rounds.

[0009] In the above solution, the memory adopts a dual-port mode and supports simultaneous read and write operations on the memory within the same clock.

[0010] In the above solution, the compression function module further includes: 8 working variable registers; The first register value is the value of the eighth working variable register; The second register value is the value of the fifth working variable register; The third register value is the value of the fourth working variable register.

[0011] In the above solution, the compression function module includes 64 compression units, and each compression unit includes: a compressor and 8 working variable registers, and the compressor includes: a first CSA, a second CSA, and a third CSA.

[0012] In the above solution, the message word expansion module includes: An expander, which is used to receive the block message and expand the block message into a message word for compression calculation; A message word register group, which is used to store the message word and update the message word in each round; and send the message words of the first message word and the second message word to the compressor in the compression function module.

[0013] In the above solution, a register is defined in the expander for storing the second message word.

[0014] In the above solution, after each round of iterative calculation is completed, the message word register group is used to update the message word with the smallest serial number to the message word corresponding to the current iterative calculation.

[0015] In the above solution, the message word register group includes 16 message word registers for storing the message words that change with iterative calculation.

[0016] In the above solution, the compression function module adopts the SM3 hashing algorithm.

[0017] In a second aspect, an embodiment of the present disclosure provides a data processing method, the method including: Performing data padding on the received first data to obtain second data; splitting the second data to obtain at least one block message; Performing message word expansion on each of the block messages to obtain message words for compression calculation; Performing compression calculation on the message words to obtain a calculation result; wherein, a pipeline calculation architecture composed of a compressor and working variable registers is adopted to perform compression calculation on the message words, calculation variables required for the compression calculation are pre-stored in a memory, and the calculation variables change with the number of rounds.

[0018] In a third aspect, an embodiment of the present disclosure provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute any one of the data processing methods.

[0019] In a fourth aspect, an embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, the computer instructions being used to cause a computer to execute the data processing method according to any one of the above.

[0020] The embodiments of the present disclosure have the following beneficial effects: By applying the data processing method, device, storage medium and electronic device provided by the embodiments of the present disclosure, a data padding module is used to perform data padding on the received first data to obtain second data; splitting the second data to obtain at least one block message; a message word expansion module is used to perform message word expansion on each of the block messages to obtain message words for compression calculation; a compression function module is used to perform compression calculation on the message words to obtain a calculation result; the compression function module adopts a pipeline calculation architecture composed of a compressor and working variable registers, and calculation variables required for compression calculation are stored in the compression function module, and the calculation variables change with the number of rounds. In this way, the problem of low efficiency of large-scale data security calculation by a cryptographic chip in the prior art is solved through the pipeline calculation architecture, and the data calculation efficiency is improved by combining pre-stored calculation variables.

[0021] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 FIG. 1 is a schematic structural diagram of a data processing device provided by an embodiment of the present disclosure; Figure 2 FIG. 2 is a schematic structural diagram of a compressor provided by an embodiment of the present disclosure; Figure 3 FIG. 3 is a schematic structural diagram of a BRAM provided by an embodiment of the present disclosure; Figure 4 FIG. 4 is a schematic structural diagram of a message word register bank provided by an embodiment of the present disclosure; Figure 5 FIG. 5 is a schematic structural diagram of a hardware accelerator based on the SM3 hashing algorithm provided by an embodiment of the present disclosure; Figure 6 FIG. 6 is a schematic structural diagram of a high-speed pipelined computing module provided by an embodiment of the present disclosure; Figure 7 FIG. 7 is a schematic flowchart of a data processing method provided by an embodiment of the present disclosure; Figure 8 FIG. 8 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] In order to make the objectives, features, and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of the present disclosure.

[0024] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0025] If similar descriptions such as "first / second" appear in the application documents, the following explanations shall be added. In the following descriptions, the terms "first / second / third" involved are only used to distinguish similar objects and do not represent a specific order for the objects. Understandably, "first / second / third" can be interchanged with a specific order or sequence under allowable circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0027] Before further elaborating on the embodiments of the present disclosure, the nouns and terms involved in the embodiments of the present disclosure are described. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations.

[0028] SM3 is an encryption standard released by the State Cryptography Administration of China. It belongs to the cryptographic hash algorithm and is used to generate the digest value (i.e., hash value) of a message. It has a fixed output length (256 bits) and a specific operation process.

[0029] The SM3 algorithm is similar to common hash algorithms (such as SHA-256) and is mainly used to generate a message digest with a length of 256 bits. Its design goal is to ensure data integrity and it is widely used in fields such as digital signatures and identity authentication. Generally speaking, the length of its output digest value is 256 bits, and the message block length is 512 bits, that is, the size of the block message processed each time is 512 bits. The number of iterative compressions is 64 times. When the algorithm performs hash calculation, 64 rounds of compression and iteration operations will be carried out.

[0030] The main steps of the SM3 algorithm include 64 rounds of function iterative compression. In each round of iteration, the message words need to go through multiple logical operations (such as AND, OR, NOT, etc.) and permutations to gradually update a 256-bit hash value.

[0031] In hardware implementation, the calculation process of the SM3 algorithm faces problems such as computational complexity, resource consumption, and time delay. For example, most of the current secure calculations based on the SM3 hash algorithm in cryptographic chips still adopt the traditional serial computing architecture. During the hardware implementation of the algorithm, the calculation path of the complex compression function is not optimized, but the complex combinational logic is directly described at the register-transfer level (RLT). In addition, in the technical solutions of a small amount of parallel computing hardware implementation, the issue of resource utilization is not considered.

[0032] In summary, in the current solution, there are problems of excessive consumption of logical resources, low performance and efficiency.

[0033] Based on this, the embodiments of the present disclosure provide a data processing device, including: a data filling module, configured to perform data filling on the received first data to obtain second data; split the second data to obtain at least one block message; a message word expansion module, configured to perform message word expansion on each block message to obtain a message word for compression calculation; a compression function module, configured to perform compression calculation on the message word to obtain a calculation result; the compression function module adopts a pipeline calculation architecture based on a compressor and working variable registers, and calculation variables required for compression calculation are stored in the compression function module, and the calculation variables change with the number of rounds. The pipeline calculation architecture is used to solve the problem of low efficiency of large-scale data security calculation by a cryptographic chip in the prior art, and the data calculation efficiency is improved by combining pre-stored calculation variables.

[0034] Figure 1 It is a schematic structural diagram of a data processing device provided by an embodiment of the present disclosure; as Figure 1 shown, the device includes: a data filling module, a message word expansion module, and a compression function module; The data filling module is configured to perform data filling on the received first data to obtain second data; split the second data to obtain at least one block message; The message word expansion module is configured to perform message word expansion on each block message to obtain a message word for compression calculation; The compression function module is configured to perform compression calculation on the message word to obtain a calculation result; the compression function module adopts a pipeline calculation architecture based on a compressor and working variable registers, and calculation variables required for compression calculation are stored in the compression function module, and the calculation variables change with the number of rounds.

[0035] Here, the data processing module may be a hardware accelerator based on the SM3 hashing algorithm; the data filling module, the message word expansion module, and the compression function module may be component modules in the accelerator.

[0036] The data filling module first fills the received input data (i.e., the first data) to obtain a format that meets the requirements of the SM3 hashing algorithm (i.e., the second data). For example, the SM3 hashing algorithm needs to fill the input data to a specific length to adapt to algorithm processing. After data filling, the second data is split into multiple block messages, and each block message needs to be processed independently. By splitting, the input long data stream is segmented into block messages suitable for algorithm processing, and each block message contains data of a fixed size. For example, the block message size of the SM3 hashing algorithm is 512 bits (64 bytes). When a group of data is received, data filling processing is required, and the result of filling is a multiple of 512 bits. Regarding the filling method, assume that the length of a certain received message m is l bits. First, the bit "1" can be added to the end of the message m, and then x "0"s are added, where x satisfies that the remainder of ( l +1+x) modulo 512 is equal to 448. Finally, a 64-bit bit string representing the data length is added to make the bit length of the filled data a multiple of 512 bits, and then grouped to obtain 512-bit block messages.

[0037] The message word expansion module is used to expand each block message to generate the message words required for compression calculation, that is, to obtain W j and . The message words W j and are the inputs of the compression function module of the algorithm. Message word expansion is to perform a certain transformation and expansion on the data for subsequent compression calculation.

[0038] The compression function module is the core module of the SM3 hashing algorithm and is responsible for performing compression calculation on the message words to obtain the final result. The compression function is a key step in the SM3 hashing algorithm, involving multiple steps and calculations. The compression process will compress the data of each input message word into an output of a fixed length. Here, the compression function module provided in the embodiments of the present disclosure adopts a pipeline calculation architecture based on a compressor and working variable registers, which can decompose the complex calculation process into multiple stages, perform different calculations simultaneously in different stages, that is, multiple calculation steps can be processed in parallel through pipeline technology, improving the calculation efficiency and enhancing the overall performance.

[0039] Moreover, the calculation variables required by the compression function module provided in the embodiments of the present disclosure during the compression calculation process change with the number of rounds of the algorithm (it can be understood that the specific values of the calculation variables are different in different rounds). This change is part of the algorithm design and is used to enhance security. Here, by pre-storing the calculation variables required for calculation in the compression calculation module, a good benefit can be obtained through the area-for-time strategy with relatively small overhead, improving the calculation efficiency.

[0040] In some embodiments, the compressor in the compression function module includes: a first CSA, a second CSA, and a third CSA; The first CSA is used to perform a first addition operation, and the first addition operation is an addition operation for a first specific operation result, a first register value, and a first message word; The second CSA is used to perform a second addition operation, and the second addition operation is an addition operation for a first shift result, the calculation variable, and a second register value; The third CSA is used to perform a third addition operation, and the third addition operation is an addition operation for a second specific operation result, a third register value, and a second message word; wherein, the second message word is the processing result of the first message word.

[0041] Here, the compressor in the compression function module includes three CSAs, and each CSA is responsible for performing different addition operations and processing different input data.

[0042] The first CSA performs the first addition operation, and the goal of this operation is to perform an addition calculation on the first specific operation result, the first register value, and the first message word; wherein, the first specific operation result is a specific operation in the SM3 hashing algorithm, denoted as GGj (j represents the current operation round); the first register value is a register state in the hashing algorithm, used to store the result of the previous calculation, here it is the value of a certain working variable register in the compression function module, denoted as H; the first message word refers to the message word input to the compression function module for compression, denoted as W.

[0043] The second CSA performs the second addition operation, and the goal of this operation is to perform an addition calculation on the first shift result, the calculation variable, and the second register value; wherein, the first shift result is a certain shift processing of the first-step calculation result, and usually the hashing algorithm will perform a certain form of displacement or rotation operation on the message, denoted as (A <<< 12). The calculation variable is a predefined variable in the hashing algorithm, used to increase the complexity of the algorithm and prevent attacks, and this calculation variable also undergoes a shift operation, and the calculation variable is denoted as (Tj <<< j). The second register value is another hash state register value, used to store the result of the previous round of calculation, here it is the value of a certain working variable register in the compression function module, denoted as E.

[0044] The third CSA performs a third addition operation, the goal of which is to add the second specific operation result, the third register value, and the second message word; wherein, the second specific operation result is a calculation result related to data or hash state, denoted as FFj; the third register value is the third state register in the algorithm, used to store the intermediate result of the current step, denoted as D; the second message word is the message word obtained by processing the first message word W, denoted as W', and the processing of the first message word W here includes an exclusive OR operation.

[0045] Here is an example, such as Figure 2 shown Figure 2 is a schematic structural diagram of a compressor provided by an embodiment of the present disclosure; Figure 2 Among them, CSA1 is the first CSA, CSA2 is the second CSA, and CSA3 is the third CSA; as Figure 2 shown, A, B, C, D, E, F, G, H respectively represent working variable registers, and a pipeline computing architecture is formed by the compressor and the working variable registers to achieve compression computing.

[0046] In each compressor, CSA1 is used to perform GG j + H + W j addition, CSA2 is used to perform (A <<< 12)+ calculation variable + E addition, wherein the calculation variable is ([[]] T j <<< j), recorded in BRAM. Then, the results of CSA1 and CSA2 are added to obtain TT the value of 2, and finally the register PP is calculated through the permutation function E t+1 The critical path of register E, and its calculation delay includes three adders, some Boolean functions, and a permutation function.

[0047] Since the calculation path in register A t+1 also includes the addition of A <<< 12, Tj <<< j, and E, so only one CSA3 is used to perform FF + D + W the addition of the three numbers ', after CSA1 finishes the calculation, it is XORed with A <<< 12 to obtain SS the value of 2, and finally the value of SS 2 is added to the result of CSA3 to complete the operation. For register A t+1The calculation path has its calculation delay reduced to that of three adders plus the delay of some Boolean functions. Among them, the permutation function and the Boolean function mainly contribute to the wiring delay, which can be ignored compared to the adder delay.

[0048] Through the above path, the combinational logic delay of the output register A t+1 and the output register E t+1 is reduced, improving the system operating frequency.

[0049] In some embodiments, the compression function module includes: a memory for receiving the number of rounds and outputting the calculation variables corresponding to the number of rounds.

[0050] The memory is further configured to receive and store at least one iteration round number required for compression calculation and the calculation variables corresponding to each iteration round number.

[0051] Here, the memory is a hardware component for storing relevant data (such as the number of rounds and calculation variables).

[0052] The number of rounds indicates how many rounds the compression function will process the data. Each round of calculation will use different calculation variables, register values, and input data to update the final result.

[0053] For each round of calculation, the algorithm uses a specific calculation variable, denoted as ( T j <<<j), where T j represents a variable value corresponding to the iteration round number j, and <<< represents a circular left shift operation, that is, ( T j <<<j) represents the result of circularly shifting the variable T j by j bits, and this result is used for compression calculation. This calculation variable plays a role in increasing the complexity and security in the encryption algorithm, preventing attackers from cracking the encryption algorithm by predicting fixed patterns.

[0054] The memory stores at least one iteration round number and the calculation variables corresponding to each iteration round number, and it can output a corresponding calculation variable ( T j <<<j) for compression calculation according to the received iteration round number (such as which round).

[0055] Provide an example, as Figure 3 shown, Figure 3Among them, clk_a represents the write clock, clk_b represents the read clock, w_addr represents the write address, r_addr represents the read address, wea represents the write enable, w_data represents the write data, and r_data represents the read data; BRAM (Block RAM) represents a memory resource in the FPGA, which is used to store data, that is, a kind of memory; CF represents the compression function, that is, it represents compressing T in the BRAM. 1 <<<1, T 2 <<<2... T 64 <<<64 is applied to compression calculation, such as provided to the second addition operation. Figure 3 The BRAM in it is configured as a simple dual-port mode (Dual Port BRAM). In the simple dual-port mode, it is allowed to perform read and write operations on the BRAM simultaneously within the same clock. T j Calculation is performed in the first cycle of clock reset, and the value is written into the BRAM. When each valid clock comes, the address will be incremented by 1, and the latest T j value will be written to the adjacent position of the BRAM. The pipelined calculation starts in the next clock cycle after the BRAM write operation. The index value of the pipeline is used as the read address (r_addr), and the value read from the BRAM ( T j <<<j) participates in the calculation of the compression function. In the figure, T 1 <<<1, T 2 <<<2... T 64 <<<64 respectively represent the corresponding results stored in the BRAM ( T j <<<j).

[0056] In the embodiments of the present disclosure, considering that in the calculation logic of the Boolean function, the shift logic (T j <<<j) occupies a relatively long path, and there are a total of 64 rounds of iterations in the SM3 architecture. Therefore, it is proposed to exhaustively T j write all shift cases into a memory (i.e., BRAM), which uses a total of 64×32bit space. Then, using the number of iteration rounds as the read address, the result of (T j <<<j) can be directly read from the memory. In the case of relatively small overhead, good benefits can be achieved through the area-for-time strategy. Moreover, by using BRAM addressing to replace part of the shift logic (Tj<<<j) in the compression function, the lookup table (LUT) resources of the FPGA can also be saved.

[0057] In some embodiments, the memory adopts a dual-port mode and supports simultaneous read and write operations on the memory within the same clock.

[0058] In some embodiments, the compression function module further includes: eight working variable registers; The value of the first register is the value of the eighth working variable register; The value of the second register is the value of the fifth working variable register; The value of the third register is the value of the fourth working variable register.

[0059] In one example, the eighth working variable register can be Figure 2 register H in Figure 2 the fifth working variable register can be Figure 2 register E in

[0060] Correspondingly, Figure 2 A in

[0061] is the first working variable register, B is the second working variable register, C is the third working variable register, F is the sixth working variable register, and G is the seventh working variable register. Figure 2 The compression calculation is implemented according to the calculation process shown in

[0062] Combined with Figure 2 shown, the compression function performs 64 rounds of compression calculations, and iterative operations are carried out based on eight working variable registers A, B, C, D, E, F, G, H to update the working variable registers.

[0063] Figure 2 In SS1 = , where is read from the memory ( Figure 2 BRAM in SS2 =

[0064] TT1 =

[0065] TT2 =

[0066] D = C C = B 9 B = A A = TT1 H = G G = F 19 F = E E = P 0 (TT2) Wherein, A, B, C, D, E, F, G, H respectively represent working variable registers; SS1, SS2, TT1, TT2 are intermediate variables respectively; FF j , GG j , P 0 All represent different specific operations, which are not limited here.

[0067] The compression function includes two critical paths, which are the calculation paths of register A t+1 and register E t+1 respectively. The calculation paths of register A t+1 and register E t+1 are as follows:

[0068]

[0069] Combined with Figure 2 it can be seen that the embodiment of the present disclosure uses CSA to optimize the critical path. When CSA processes consecutive operations of multiple additions, only the addition operation is performed in the last step, and the others can be implemented through bit operations. Therefore, the delay is approximately the delay of the last adder.

[0070] In addition, enumerate T j all shift cases and write all possible shift results (T j <<<j) into the memory, that is, BRAM. When in use, the iteration count is used as the read address, and the result of (T j <<<j) can be directly read from BRAM. In the case of relatively small overhead, although the area of the memory (BRAM) is increased, through pre-computation and direct reading, the same calculation for each iteration is avoided, and the calculation time for each iteration can be significantly reduced, thereby optimizing the running efficiency of the encryption algorithm in hardware implementation.

[0071] In some embodiments, the compression function module includes 64 compression units, and each compression unit includes: a compressor and 8 working variable registers, and the compressor includes: a first CSA, a second CSA, and a third CSA.

[0072] Here, the working variable register refers to the storage unit used in the compressor for temporarily storing intermediate calculation results. In an encryption algorithm, working variables are typically used to hold data that is continuously updated during multiple calculation steps. In each round of calculation, data is passed through these working variable registers and used in the next round.

[0073] The compressor can also be described as a compression operation unit or a compression function unit. The compressor processes and calculates data through the CSA and working variable registers, and finally completes the data compression task.

[0074] It should be noted that Figure 2 the FF in j 、GG j 、P 0 and other operations can also be considered as part of the compressor or compression function.

[0075] In some embodiments, the message word expansion module includes: An expander for receiving the block message and expanding the block message into message words for compression calculation; A message word register group for storing the message words, updating the message words in each round; and sending the message words of the first message word and the second message word to the compressor in the compression function module.

[0076] In some embodiments, the message word register group includes: 16 message word registers for storing the message words that change with iterative calculation.

[0077] Here, the expander can receive a block message and expand it into message words for subsequent compression calculation. In some encryption algorithms, messages are divided into blocks of a fixed size, and expansion refers to transforming these blocks into message words suitable for the compression function.

[0078] The message word register group stores the message words, and during each round of calculation, these message words are updated. Message word registers are usually modified in each round of encryption operation to ensure that each round of calculation is based on the previous state. The message word register group may specifically include 16 message word registers.

[0079] Provide an example, as Figure 4 shown, Figure 4 is a schematic structural diagram of a message word register group provided by an embodiment of the present disclosure; the message register group has 16 message word registers for storing message words (denoted as W ) that change with iterative calculation. The initial values of the 16 registers are obtained by grouping the block message (Message), and the subsequent message wordsW 16 ~ W 67 Calculated from the extension of the previously generated message word, i.e., the extension calculates to obtain W new (For example, according to W 0 to W 15 obtain W 16 , as W new is updated; according to W 1 to W 16 obtain W 17 , as W new is updated; and so on, not elaborated here), W 16 ~ W 67 The extension method of Figure 4 is as shown.

[0080] When the extension of the new message word is completed, the new message word is stored in the register W 15 . Originally, W 15 ~ W 1 The values of the registers are shifted in sequence and stored in W 14 ~ W 0 registers to complete the update of the values of 16 registers. The value in the originally W 0 register is passed to the compression function for compression calculation.

[0081] The specific extension process can be as follows: The calculation method of

[0082] and, The calculation method is:

[0083] Among them, is the permutation function specified by the SM3 algorithm; is the 32-bit bitwise exclusive OR operator; <<< is the 32-bit bitwise cyclic left shift operator.

[0084] In some embodiments, a register is defined in the extender for storing the second message word.

[0085] Here, an additional register is defined in the architecture of the extender for storing the message word W ', combined with Figure 4 shown, based on the message word W0 ~ W 67 , it is possible to obtain W 0 '~ W 63 ', The calculation method is as follows: , these message words sequentially update the register storing the message words and are synchronously transmitted to the compression function module.

[0086] In some embodiments, after each round of iterative calculation is completed, the message word register group is used to update the message word with the smallest serial number to the message word corresponding to the current iterative calculation.

[0087] Here, considering that as the iterative calculation of the compression function progresses, the message words stored in the message word register are also constantly updated, and the data dependency of the message word expansion calculation only exists between every n (n is 16) consecutive message words. Therefore, after each round of iterative calculation is completed, updating the message word with the smallest serial number in the message word register to the message word corresponding to the current iterative calculation can achieve the reuse of the register. Adopting the technology of register reuse can greatly save the consumption of hardware resources.

[0088] In some embodiments, the initial values of the 16 message word registers are obtained based on the block message grouping; the 17th to 68th words are obtained based on the extended calculation of the generated message words.

[0089] In some embodiments, the device further includes: a central processing unit, and the data filling module receives the first data from the central processing unit.

[0090] In one example, the data processing device is a hardware accelerator based on the SM3 hashing algorithm, such as Figure 5 shown, providing a structural schematic diagram of a hardware accelerator based on the SM3 hashing algorithm; the hardware accelerator may include: a central processing unit (CPU), a double data rate synchronous dynamic random access memory (DDR), a 32-bit data bus, an SM3 algorithm core module (SM3 Core), an AHB (Advanced High-performance Bus) interface (represented as AHB Inf in the figure), a Register register bank (represented as Register in the figure), a DMA (Direct Memory Access), and a FIFO (First Input First Output) memory (represented as FIFO in the figure).

[0091] Among them, the core module of the SM3 algorithm includes: a data padding module and a high-speed pipelined computing module; the high-speed pipelined computing module includes: a message word expansion module and a compression function module.

[0092] The CPU places DMA configuration information, keys, etc. in the Register register bank through the AHB interface. After the DMA receives the configuration signal from the CPU and completes the startup, it fetches data from the DDR through the AHB interface, then writes it into the subsequent FIFO. Finally, the core module of the SM3 algorithm fetches data from the FIFO for compression calculation. After the compression calculation is completed, the core module of the SM3 algorithm stores the digest value in the Register register bank and waits for the CPU to read.

[0093] The compression function module may include: m compressors; the message word expansion module includes: n expanders, k message word registers, and i groups of working variable registers. Among them, the compressor is used to perform compression calculation on the message, and the working variable register is used to store the intermediate value after the compressor calculation. The m compressors and the i groups of working variable registers together constitute the pipelined calculation of the compression function. The expander is used to expand the message to generate the message words required by the compression function. The message word register is used to store the expanded message words and update them in each round of pipelined calculation. In one example, m is 64, n is 1, k is 16, i is 64, and each group of working variable registers includes 8 registers.

[0094] Figure 6 The structural schematic diagram of a high-speed pipelined computing module provided by an embodiment of the present disclosure is as Figure 6 shown, the high-speed pipelined computing module includes: a message word expansion module and a compression function module; The compression function module includes: 64 compressors (i.e., Figure 6 Compressor in) and 64 groups of working variable registers; the 64 compressors have the same computing architecture and perform 64 rounds of compression calculation on the message respectively.

[0095] The message word expansion module includes: one expander (i.e., Figure 6 Expander in) and 16 message word registers.

[0096] Figure 6 In, W represents the message word register, W 0 to W 15 、W 15 to W 30 etc. respectively represent the message words stored in 16 message word registers. Here, the message word register can adopt Figure 4The shown design realizes register reuse; a~h Register represents each group of working variable registers, including 8 working variable registers. The compressor and its corresponding working variable registers can adopt Figure 2 The shown design realizes compression calculation.

[0097] The Expander receives the block Message, expands the block Message into message words for compression calculation. 16 message word registers are used to store the message words, and are updated in each round, and the message words of the next round W , W ' are passed to the Compressor. As Figure 6 in, W 0 , W ’ 0 are passed to the Compressor, W 15 , W ’ 15 are passed to the Compressor, W 16 , W ’ 16 are passed to the Compressor, etc.

[0098] When large-scale data needs to be processed, a 512-bit message is input in each clock cycle. The first group of messages are sequentially subjected to 64 rounds of compression function calculations after entering the pipeline. When the first message finishes the first round of compression function calculation, its result enters the second round of compression function calculation. At this time, the second message can enter the pipeline for the first round of compression function calculation.

[0099] In this order, after 64 clock cycles, the first group of messages complete the compression function calculation, and the result of the last round of compression function calculation is XORed with the initial variables H 0 ~ H 7 to output the final hash digest value. In each subsequent clock cycle, a new digest value will be output until the entire pipeline computing architecture processes the last block message.

[0100] The device provided by the embodiments of the present disclosure adopts a high-speed pipeline parallel computing architecture, which improves the algorithm throughput and greatly improves the efficiency of secure computing. Moreover, message word register reuse is adopted, and the relevant combinational logic adopts BRAM addressing design, which saves hardware resources and improves resource utilization.

[0101] It should be noted that the device provided in the embodiments of the present disclosure can perform parallel processing of multiple file integrity verification or digital signature tasks in a pipeline, which can greatly improve the computing speed and shorten the task completion time; the high-performance computing ability can complete more work in the same time, reducing the time cost and opportunity cost.

[0102] Figure 7 It is a schematic flowchart of a data processing method provided by an embodiment of the present disclosure; as Figure 7 shown, the method can be applied to the data processing device described above, and the method includes: Step 701: Perform data padding on the received first data to obtain second data; split the second data to obtain at least one block message; Step 702: Perform message word expansion on each block message to obtain message words for compression calculation; Step 703: Perform compression calculation on the message words to obtain a calculation result; wherein, a pipeline calculation architecture composed of a compressor and working variable registers is used to perform compression calculation on the message words, and the calculation variables required for the compression calculation are pre-stored in a memory, and the calculation variables change with the number of rounds.

[0103] In some embodiments, a compression function module performs compression calculation on the message words to obtain a calculation result, wherein the compressor in the compression function module includes: a first CSA, a second CSA, and a third CSA; The first CSA is used to perform a first addition operation, and the first addition operation is an addition operation for a first specific operation result, a first register value, and a first message word; The second CSA is used to perform a second addition operation, and the second addition operation is an addition operation for a first shift result, the calculation variable, and a second register value; The third CSA is used to perform a third addition operation, and the third addition operation is an addition operation for a second specific operation result, a third register value, and a second message word; wherein, the second message word is the processing result of the first message word.

[0104] Here, the first CSA performs the first addition operation, and the goal of this operation is to perform an addition calculation on the first specific operation result, the first register value, and the first message word; wherein, the first specific operation result is a specific operation in the SM3 hashing algorithm, denoted as GGj (j represents the current operation round); the first register value is a register state in the hashing algorithm, used to save the result of the previous calculation, here it is the value of a certain working variable register in the compression function module, denoted as H; the first message word refers to the message word input to the compression function module for compression, denoted as W.

[0105] The second CSA performs a second addition operation, the goal of which is to add the first shift result, the computational variable, and the second register value; where the first shift result is a certain shift process of the first step calculation result. Usually, the hash algorithm will perform a certain form of displacement or rotation operation on the message, denoted as (A <<< 12). The computational variable is a predefined variable in the hash algorithm, used to increase the complexity of the algorithm and prevent attacks. This computational variable also undergoes a shift operation, denoted as (Tj <<< j). The second register value is another hash state register value, used to store the result of the previous round of calculation. Here, it is the value of a certain working variable register in the compression function module, denoted as E.

[0106] The third CSA performs a third addition operation, the goal of which is to add the second specific operation result, the third register value, and the second message word; where the second specific operation result is a calculation result related to the data or hash state, denoted as FFj; the third register value is the third state register in the algorithm, used to store the intermediate result of the current step, denoted as D; the second message word is the message word obtained by processing the first message word W, denoted as W', and the processing of the first message word W here includes an exclusive - or operation.

[0107] The second message word is the processing result of the first message word, and the processing can be an exclusive - or operation, such as the formula , represents a first message word, represents the second message word obtained after processing the first message word.

[0108] In some embodiments, the compression function module includes: a memory, configured to receive the number of rounds and output the computational variable corresponding to the number of rounds.

[0109] The memory is further configured to receive and store at least one number of rounds required for compression calculation and the computational variable corresponding to each number of rounds.

[0110] Correspondingly, the compression calculation of the message word to obtain a calculation result includes: Query the memory according to the number of rounds to determine the computational variable required for the current round of compression calculation.

[0111] Here, the number of rounds indicates how many rounds the compression function will process the data. Each round of calculation will use different computational variables, register values, and input data to update the final result.

[0112] For each round of calculation, the algorithm uses a specific computational variable, denoted as ( T j<<<j). This computational variable plays a role in increasing the complexity and security of the encryption algorithm, preventing attackers from cracking the encryption algorithm by predicting fixed patterns. At least one number of iteration rounds and the computational variables corresponding to each iteration round are stored in the memory, and it can output a corresponding computational variable according to the received number of iteration rounds (such as which round). T j <<<j) is used for compression calculation.

[0113] Here, considering that in the computational logic of the Boolean function, the shift logic (T j <<<j) occupies a relatively long path, and there are a total of 64 rounds of iteration in the SM3 architecture. Therefore, an exhaustive search T j All shift cases are written into a memory, which uses a total of 64×32bit space. Then, using the number of iteration rounds as the read address, the result of (T j <<<j) can be directly read from the memory. In the case of relatively small overhead, good benefits can be achieved through the area-for-time strategy. Moreover, by using BRAM addressing to replace part of the shift logic (Tj<<<j) in the compression function, the lookup table (LUT) resources of the FPGA can also be saved.

[0114] In some embodiments, the memory adopts a dual-port mode and supports simultaneous read and write operations on the memory within the same clock.

[0115] In some embodiments, the compression function module further includes: 8 working variable registers; The value of the first register is the value of the eighth working variable register; The value of the second register is the value of the fifth working variable register; The value of the third register is the value of the fourth working variable register.

[0116] In an example, the eighth working variable register can be Figure 2 register H in Figure 2 the fifth working variable register can be Figure 2 register E in

[0117] register D in Figure 2

[0118] Figure 2 Accordingly, A in Figure 2 is the first working variable register, B is the second working variable register, C is the third working variable register, F is the sixth working variable register, and G is the seventh working variable register.

[0118] The state changes of each working variable register have been described in the Figure 2 relevant description and will not be elaborated here.

[0119] In some embodiments, the compression function module includes 64 compression units, and each compression unit includes: a compressor and eight working variable registers, and the compressor includes: a first CSA, a second CSA, and a third CSA.

[0120] Here, the compressor can also be used to perform operations including FF j , GG j , P 0 and so on.

[0121] In some embodiments, the message word expansion module expands each block message to obtain message words for compression calculation. The message word expansion module includes: an expander and a message word register group.

[0122] Correspondingly, the step of expanding each block message to obtain message words for compression calculation includes: The expander receives the block message and expands the block message into message words for compression calculation; The message word register group stores the message words and updates the message words in each round; and, sends the message words of the first message word and the second message word to the compressor in the compression function module.

[0123] In some embodiments, registers are defined in the expander for storing the second message word.

[0124] In some embodiments, after each round of iterative calculation is completed, the message word register group updates the message word with the smallest serial number to the message word corresponding to the current iterative calculation.

[0125] In some embodiments, the message word register group includes 16 message word registers for storing the message words that change with iterative calculation.

[0126] Here, considering that as the iterative calculation of the compression function progresses, the message words stored in the message word registers are constantly updated, and the data dependency of the message word expansion calculation only exists between every n (n is 16) consecutive message words. Therefore, after each round of iterative calculation is completed, updating the message word with the smallest serial number in the message word register to the message word corresponding to the current iterative calculation can achieve the reuse of registers. The technology of register reuse can greatly save the consumption of hardware resources.

[0127] In an example, the message word register group adopts the Figure 4 shown structure, where the message register group has 16 message word registers for storing the message words that change with iterative calculation (denoted as W ), and the initial values of the 16 registers are obtained by grouping the block message (Message). The subsequent message wordsW 16 ~ W 67 It is calculated by extending the message words generated previously, that is, W is obtained by extended calculation new (for example, according to W 0 to W 15 to obtain W 16 , which is used as W new for updating; according to W 1 to W 16 to obtain W 17 , which is used as W new for updating; and so on, which will not be elaborated here), W 16 ~ W 67 The extension method of ~ Figure 4 is as shown. When the extension of the new message words is completed, the new message words are stored in the register W 15 . Originally W 15 ~ W 1 The values of the registers are shifted in sequence and stored in W 14 ~ W 0 registers to complete the update of the values of 16 registers. The values in the originally W 0 register are passed to the compression function for compression calculation.

[0128] An additional register is defined in the architecture of the extender to store the message word W '. Combining Figure 4 as shown, based on the message words W 0 ~ W 67 , W 0 '~ W 63 ' can be obtained The calculation method is as follows: , and these message words update the register storing the message word in sequence and are synchronously transmitted to the compression function module.

[0129] In this way, the update of each message word register is realized, and the message word extension result is synchronously transmitted to the compression function module.

[0130] In some embodiments, the compression function module adopts the SM3 hashing algorithm.

[0131] Here, the working principle of the data processing device can be based on the operation process of the SM3 hashing algorithm.

[0132] Combined with its data padding module, message word expansion module, and compression function module, each step of the SM3 hashing algorithm is executed respectively based on the method provided in the embodiments of the present disclosure.

[0133] In one example, the data processing device is a hardware accelerator based on the SM3 hashing algorithm, and data processing is realized through the various hardware components of the data processing device. Implementing the SM3 hashing algorithm through a hardware accelerator can significantly improve the computing performance, reduce power consumption, and enhance the efficiency and concurrent processing ability of the system. This is of great significance for scenarios such as processing large amounts of data, performing encryption verification, or digital signatures.

[0134] In some embodiments, the method further includes: receiving first data from a central processing unit.

[0135] It can be understood that the method provided in the above embodiments and the embodiments of the corresponding device belong to the same concept. For the specific implementation process, please refer to the method embodiments and will not be elaborated here.

[0136] The embodiments of the present application provide a computer program product or a computer program. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the data processing method.

[0137] The embodiments of the present application provide a computer-readable storage medium storing executable instructions, where the executable instructions are stored. When the executable instructions are executed by a processor, the processor will be caused to execute the data processing method provided in the embodiments of the present application.

[0138] In some embodiments, the computer-readable storage medium can be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disc, or CD-ROM; or it can be various devices including one or any combination of the above memories.

[0139] In some embodiments, the executable instructions can be in the form of a program, software, software module, script, or code, and can be written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and can be deployed in any form, including being deployed as an independent program or being deployed as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0140] As an example, the executable instructions may or may not correspond to files in a file system, and may be stored as part of a file that stores other programs or data. For example, they may be stored in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program being discussed, or in multiple cooperating files (e.g., files that store one or more modules, subroutines, or code portions).

[0141] As an example, the executable instructions may be deployed to execute on one computing device, or on multiple computing devices located at one location, or on multiple computing devices distributed across multiple locations and interconnected by a communication network.

[0142] Figure 8 Schematic diagram of the structure of an electronic device provided by an embodiment of the present disclosure; as Figure 8 shown, the electronic device 80 includes: a processor 801, and a memory 802 communicatively connected to the processor 801; the memory 802 stores instructions executable by the processor 801. The instructions are executed by the processor 801 to enable the processor 801 to perform: Perform data filling on the received first data to obtain second data; split the second data to obtain at least one block message; Perform message word expansion on each of the block messages to obtain message words for compression calculation; Perform compression calculation on the message words to obtain a calculation result; wherein, a pipeline calculation architecture composed of a compressor and working variable registers is used to perform compression calculation on the message words, and the calculation variables required for the compression calculation are pre-stored in the memory, and the calculation variables change with the number of rounds.

[0143] The electronic device provided in the above embodiment and the embodiment of the corresponding data processing method belong to the same concept. For the specific implementation process, please refer to the method embodiment, which will not be elaborated here.

[0144] In practical applications, the electronic device 80 may further include: at least one network interface 803. Each component in the electronic device 80 is coupled together through a bus system 804. It can be understood that the bus system 804 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 804 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, in Figure 8Various buses are labeled as bus system 804. Among them, the number of the processors 801 can be at least one, and the number of the memories 802 can be at least one. The network interface 803 is used for wired or wireless communication between the electronic device 80 and other devices.

[0145] The memory 802 in the embodiments of the present disclosure is used to store various types of data to support the operation of the electronic device 80.

[0146] The methods disclosed in the above embodiments of the present disclosure can be applied to or implemented by the processor 801. The processor 801 may be an integrated circuit chip with signal processing capabilities. In the implementation process, the steps of the above methods can be completed by the integrated logic circuit in hardware or instructions in software form in the processor 801. The above-mentioned processor 801 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 801 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present disclosure. The general-purpose processor may be a microprocessor or any conventional processor, etc. Combining the steps of the methods disclosed in the embodiments of the present disclosure, it can be directly embodied as being executed and completed by a hardware decoding processor, or executed and completed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, and this storage medium is located in the memory 802. The processor 801 reads the information in the memory 802 and combines its hardware to complete the steps of the foregoing data processing method.

[0147] In some embodiments, the electronic device 80 may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontroller units (MCUs), microprocessors, or other electronic components, and is used to execute the foregoing methods.

[0148] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this is not limited herein.

[0149] In the above description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0150] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure pertains. The terms used in this disclosure are only for the purpose of describing the embodiments of this disclosure and are not intended to limit this disclosure.

[0151] It should be understood that in the various embodiments of this disclosure, the magnitude of the serial numbers of the respective implementation processes does not imply the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation processes of the embodiments of this disclosure.

[0152] In addition, the terms "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of this disclosure, "a plurality" means two or more, unless otherwise specifically defined.

[0153] As described above, the above is only the specific implementation manner of this disclosure, but the protection scope of this disclosure is not limited thereto. Any person skilled in the technical field, within the technical scope disclosed by this disclosure, can easily think of changes or substitutions, which should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be subject to the protection scope of the claims.

Claims

1. A data processing device, characterized in that: The device comprises: A data filling module, configured to fill the received first data with data to obtain second data; and to split the second data to obtain at least one block message; A message word expansion module, used for performing message word expansion on each of the block messages to obtain a message word for compression calculation; A compression function module is used to perform compression calculation on the message word to obtain a calculation result; the compression function module adopts a pipeline calculation architecture based on a compressor and a working variable register, and the compression function module stores calculation variables required for compression calculation, and the calculation variables change with the number of rounds.

2. The device according to claim 1, characterized in that The compressor in the compression function module includes: a first CSA, a second CSA, and a third CSA; The first CSA is used to perform a first addition operation, where the first addition operation is an addition operation on a first specific operation result, a first register value, and a first message word; The second CSA is used to perform a second addition operation, where the second addition operation is an addition operation on the first shift result, the calculation variable, and the second register value; The third CSA is used to perform a third addition operation, where the third addition operation is an addition operation on the second specific operation result, the third register value and the second message word; wherein the second message word is the processing result of the first message word.

3. The device according to claim 1, characterized in that The compression function module includes: a memory for receiving a round number and outputting a calculation variable corresponding to the round number.

4. The device according to claim 3, characterized in that The memory is further used to receive and store at least one round number required for compression calculation and calculation variables corresponding to each round number.

5. The device according to claim 3, characterized in that The memory adopts a dual-port mode and supports simultaneous reading and writing operations on the memory within the same clock.

6. The device according to claim 2, characterized in that The compression function module also includes: 8 working variable registers; The first register value is the value of the eighth working variable register; The second register value is the value of the fifth working variable register; The third register value is the value of the fourth working variable register.

7. The device according to claim 1, characterized in that The compression function module includes 64 compression units, each of which includes a compressor and 8 working variable registers, and the compressor includes a first CSA, a second CSA, and a third CSA.

8. The device according to claim 1, characterized in that The message word expansion module comprises: An expander, used for receiving the block message and expanding the block message into a message word for compression calculation; A message word register group is used to store the message words and update the message words in each round; and send the message words of the first message word and the second message word to the compressor in the compression function module.

9. The device according to claim 8, characterized in that A register is defined in the expander for storing the second message word.

10. The device according to claim 8, characterized in that After each round of iterative calculation, the message word register group is used to update the message word with the smallest sequence number to the message word corresponding to the current iterative calculation.

11. The device according to claim 8, characterized in that The message word register group includes: 16 message word registers, which are used to store the message words that change with iterative calculation.

12. The device according to claim 1, characterized in that The compression function module adopts the SM3 hash algorithm.

13. A data processing method, characterized in that: The method comprises: Performing data padding on the received first data to obtain second data; splitting the second data to obtain at least one block message; Performing message word expansion on each of the block messages to obtain a message word for compression calculation; The message word is compressed and calculated to obtain a calculation result; wherein, the message word is compressed and calculated using a pipeline calculation architecture based on a compressor and a working variable register, and the calculation variables required for the compression calculation are pre-stored in a memory, and the calculation variables change with the number of rounds.

14. An electronic device, characterized in that: include: at least one processor; And, a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method of claim 13.

15. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause a computer to execute the method according to claim 13.

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