Verification system based on reuse of verification platform

Abstract

The invention relates to the technical field of chips, in particular to a verification system based on verification platform multiplexing, which comprises a software case issuing module used for issuing a software test case to an application development interface module; the application development interface module is used for calling the driving module to generate an original register type instruction, an original memory type instruction and an original doorbell type instruction; the conversion interface module is used for converting the original register type instruction, the original memory type instruction and the original doorbell type instruction into a target register type instruction, a target memory type instruction and a target doorbell type instruction which are realized by a SystemVerilog language; and the RTL module is used for executing the software test case based on the target register type instruction, the target memory type instruction and the target doorbell type instruction to generate an operation result. According to the invention, system-level verification and software verification can be realized in advance based on the RTL code, the chip development cost is reduced, and the chip development efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a verification system based on the reuse of verification platforms. Background Art

[0002] During the chip development process, different chip verification stages need to be experienced. Usually, hardware-level verification is first performed based on the chip RTL (Register Transfer Level) code. After hardware-level verification, a chip hardware accelerator or a physical chip will be obtained. Then, system-level verification is performed based on the hardware accelerator or the physical chip. After the system-level verification passes, software-level verification is performed based on the accelerator or the physical chip. The hardware accelerator or the physical chip is a real entity. If problems are found again during the system-level verification stage and the software verification stage, a large amount of update costs will be incurred, reducing the chip development efficiency. If some system-level verification and / or software-level verification can be performed in advance based on the chip RTL code, and some problems existing in the RTL code are solved before the generation of the hardware accelerator or the physical chip, the chip development efficiency can be improved and the chip development cost can be reduced. Therefore, how to implement system-level verification and / or software verification in advance based on the RTL code, improve the chip development efficiency, and reduce the chip development cost has become a technical problem to be solved urgently. Summary of the Invention

[0003] The purpose of the present invention is to provide a verification system based on the reuse of verification platforms, which can realize system-level verification and software verification in advance based on the RTL code, reduce the chip development cost, and improve the chip development efficiency.

[0004] The present invention provides a verification system based on the reuse of verification platforms, including: a software test case distribution module, an application development interface module, a driver module, a conversion interface module, and an RTL module. The software test case distribution module, the application development interface module, and the driver module are implemented based on software languages. The conversion interface module is implemented based on software languages and hardware languages. The RTL module is implemented based on hardware languages. The RTL module is used to store the RTL code of the chip design to be tested, and the RTL module is a component module of the hardware verification platform;

[0005] Among them, the software test case distribution module is connected to the application development interface library, the application development interface module is connected to the driver module, the driver module is connected to the conversion interface module, and the conversion interface module is connected to the RTL module;

[0006] The software test case distribution module is used to distribute software test cases to the application development interface module;

[0007] The application development interface module is used to call the driver module based on the received software test cases to generate original register type instructions, original memory type instructions, and original doorbell type instructions;

[0008] The conversion interface module is used to convert the original register type instructions, original memory type instructions, and original doorbell type instructions into target register type instructions, target memory type instructions, and target doorbell type instructions implemented in SystemVerilog language;

[0009] The RTL module is used to execute the software test cases based on the target register type instructions, target memory type instructions, and target doorbell type instructions to generate operation results.

[0010] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solutions, a verification system based on verification platform reuse provided by the present invention can achieve considerable technical progressiveness and practicality, and has wide industrial utilization value. It has at least the following beneficial effects:

[0011] The system of the present invention can reuse the chip RTL code in the RTL module of the hardware verification platform, execute system test cases and software test cases, and can perform some system-level verification and / or software-level verification in advance, so as to solve some problems existing in the RTL code before the hardware accelerator or physical chip is generated, improve the chip development efficiency, and reduce the chip development cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0013] Figure 1 Schematic diagram of a verification system based on verification platform reuse provided by an embodiment of the present invention;

[0014] Figure 2 Schematic diagram of another verification system based on verification platform reuse provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0016] An embodiment of the present invention provides a verification system based on verification platform reuse, as Figure 1 shown, including: a software test case distribution module, an application development interface module, a driver module, a conversion interface module, and an RTL module. The software test case distribution module, the application development interface module, and the driver module are implemented based on a software language, and the software language can specifically be C language, C++ language, etc. The conversion interface module is implemented based on a software language and a hardware language, and the hardware language corresponding to the conversion interface module is SystemVeriliog language. The RTL module is implemented based on a hardware language, and the RTL code for storing the design of the chip under test is in the RTL module. The RTL module is a component module of the hardware verification platform. The hardware language corresponding to the RTL module can specifically be Verilog language, SystemVeriliog language, etc.

[0017] Among them, the software test case distribution module is connected to the application development interface library, the application development interface module is connected to the driver module, the driver module is connected to the conversion interface module, and the conversion interface module is connected to the RTL module.

[0018] The software test case distribution module is used to distribute software test cases to the application development interface module. It should be noted that software engineers can write and generate software test cases based on the software test case distribution module according to the writing rules of software test cases for distribution. That is, without software engineers modifying the original software test cases, the system of the present invention can be used to run software test cases on the RTL code of the chip.

[0019] The application development interface module is used to call the driver module based on the received software test cases to generate original register type instructions, original memory type instructions, and original doorbell type instructions. It should be noted that the driver module can obtain all resource information of the current RTL chip design, such as memory size, register type, engine resources, etc. Therefore, by calling the driver module, original register type instructions, original memory type instructions, and original doorbell type instructions can be generated. The original register type instructions, original memory type instructions, and original doorbell type instructions are still implemented based on a software language and cannot directly interact with the RTL module. Therefore, conversion is required through the conversion interface module.

[0020] The conversion interface module is used to convert the original register type instructions, original memory type instructions, and original doorbell type instructions into target register type instructions, target memory type instructions, and target doorbell type instructions implemented in SystemVerilog language. Specifically, it can be implemented through the existing Direct Programming Interface (DPI for short). DPI is a standard interface that allows SystemVerilog code to directly call C or C++ functions, and vice versa. DPI allows data and control information to be transferred between the two languages. Therefore, based on DPI, the conversion between software languages and SystemVerilog language can be achieved, which will not be elaborated here.

[0021] The RTL module is used to execute the software test cases based on the target register type instructions, target memory type instructions, and target doorbell type instructions, and generate operation results. It should be noted that each test case is set with a corresponding target result. Finally, the operation result is compared with the target result. If they are consistent, the test passes; if not, the test fails.

[0022] As an embodiment, the application development interface module is used to parse the received software test cases, obtain operation parameters and operation logics, and call the driver module to obtain the memory address corresponding to each operation parameter based on the operation parameters. Among them, the operation parameters can be the original operation parameters and original operation logics corresponding to the test cases. The operation parameters can also be the original operation parameters and intermediate operation parameters obtained based on the original operation parameters, and the operation logics can be the original operation logics and intermediate operation logics obtained based on the original operation logics. The driver module allocates the corresponding memory address for each operation parameter based on the required memory size of the operation parameter and the current memory resources.

[0023] The system of the present invention can also run system test cases, such as Figure 2 As shown, as an embodiment, the system further includes a system use case distribution module, and the driver module further includes a Virtual Function I / O (VFIO for short). VFIO is a user-state driver framework that can directly interact with the libraries at the Linux bottom layer and then interact with the RTL module. The system use case distribution module is connected to the application development interface module.

[0024] The system use case distribution module is used to distribute system test cases to the application development interface module. It should be noted that system engineers can write and generate system test cases according to the writing rules of system test cases based on the software use case distribution module for distribution. That is, without system engineers modifying the original system test cases, the system of the present invention can be used to run system test cases on the chip RTL code.

[0025] As an embodiment, the application development interface module is used to call the virtual function interface in the driver module based on the received system test case to generate original register type instructions, original memory type instructions and original doorbell type instructions. The application development interface module is also used to parse the received system test case, obtain operation parameters and operation logic, and call the virtual function interface in the driver module to obtain the memory address corresponding to each operation parameter based on the operation parameters. It should be noted that the virtual function interface is only enabled when the test case is a system test case. When it is a software test case, it is not necessary to use the virtual function interface, and the corresponding operation is only implemented through the basic driver unit in the driver module. The granularity of the operation logic of the system test case is finer than that of the software test case. The system test case is undertaken through the virtual function interface, so that the system has better compatibility.

[0026] As an embodiment, the application development interface module is used to call the driver module to generate an original register configuration instruction based on each operation parameter and the memory address corresponding to each operation parameter, and send the original register configuration instruction to the conversion interface. The original register configuration instruction is an instruction generated based on the software language and cannot be directly used with the RTL module, so a conversion interface is required for conversion. The conversion interface is used to convert the original register configuration instruction into a target register configuration instruction implemented based on the SystemVerilog language, and send the target register configuration instruction to the RTL module. The RTL module is used to configure the registers in the chip design to be tested based on the target register configuration instruction, and after the configuration is completed, the register configuration completion instruction is returned to the application development interface module through the conversion interface and the driver module. The conversion interface is used to convert the register configuration completion instruction into a target register configuration completion instruction implemented in the software language, and send it to the application development interface module through the driver module. It should be noted that the register configuration completion instruction is an instruction generated based on the SystemVerilog language. When passing through the conversion interface, it needs to be converted by the conversion interface into an instruction implemented based on the software language before it can be returned to the application development interface module through the driver module.

[0027] As an embodiment, after receiving the register configuration completion instruction, the application development interface module is used to call the driver module to generate an original data transfer instruction based on each operation parameter and the register configuration information, and send the original data transfer instruction to the conversion interface. The original data transfer instruction is an instruction generated based on a software language and cannot be directly associated with the RTL module. Therefore, a conversion interface is required for conversion. The conversion interface is used to convert the original data transfer instruction into a target data transfer instruction implemented based on the SystemVerilog language, and send the target data transfer instruction to the RTL module. The RTL module is used to store the original data in the corresponding memory based on the target data transfer instruction. After the storage is completed, a data transfer completion instruction is returned to the application development interface module through the conversion interface and the driver module. The conversion interface is used to convert the data transfer completion instruction into a target data transfer completion instruction implemented based on a software language, and send it to the application development interface module through the driver module. It should be noted that the data transfer completion instruction is an instruction generated based on the SystemVerilog language. When passing through the conversion interface, it needs to be converted by the conversion interface into an instruction implemented based on a software language before it can be returned to the application development interface module through the driver module.

[0028] As an embodiment, after receiving the data transfer completion instruction, the application development interface module calls the driver module to generate an original doorbell instruction based on the operation logic, and send the original doorbell instruction to the conversion interface. The original doorbell instruction is an instruction generated based on a software language and cannot be directly associated with the RTL module. Therefore, a conversion interface is required for conversion. The conversion interface is used to convert the original doorbell instruction into a target doorbell instruction implemented based on the SystemVerilog language, and send the target doorbell instruction to the RTL module. The RTL module is used to execute the operation logic based on the target doorbell instruction and the original data stored in the memory to generate an operation result. The conversion interface is used to convert the operation result into a target operation result implemented based on a software language, and send it to the application development interface module through the driver module. It should be noted that the operation result is an instruction generated based on the SystemVerilog language. When passing through the conversion interface, it needs to be converted by the conversion interface into an instruction implemented based on a software language before it can be returned to the application development interface module through the driver module. Finally, the target operation result is compared with the target result to determine whether the test passes.

[0029] The system described in the embodiments of the present invention can reuse the chip RTL code in the RTL modules of the hardware verification platform, execute system test cases and software test cases, and can perform some system-level verifications and / or software-level verifications in advance, so as to solve some problems existing in the RTL code before the hardware accelerator or physical chip is generated, improve the chip development efficiency, and reduce the chip development cost.

[0030] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the equivalent embodiments by using the disclosed technical content within the scope of the technical solution of the present invention. However, as long as the content does not depart from the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A verification system based on verification platform reuse, characterized in that: include: A software use case sending module, an application development interface module, a driver module, a conversion interface module and an RTL module. The software use case sending module, the application development interface module and the driver module are implemented based on software language. The conversion interface module is implemented based on software language and hardware language. The RTL module is implemented based on hardware language. The RTL module is used to store the RTL code of the chip design to be tested. The RTL module is a component module of the hardware verification platform. The software use case issuing module is connected to the application development interface library, the application development interface module is connected to the driver module, the driver module is connected to the conversion interface module, and the conversion interface module is connected to the RTL module; The software test case sending module is used to send software test cases to the application development interface module; The application development interface module is used to call the driver module to generate original register type instructions, original memory type instructions and original doorbell type instructions based on the received software test case; The conversion interface module is used to convert the original register type instruction, the original memory type instruction and the original doorbell type instruction into the target register type instruction, the target memory type instruction and the target doorbell type instruction implemented by the SystemVerilog language; The RTL module is used to execute the software test case based on the target register type instruction, the target memory type instruction and the target doorbell type instruction to generate a calculation result.

2. The system according to claim 1, characterized in that The application development interface module is used to parse the received software test case, obtain operation parameters and operation logic, and call the driver module to obtain the memory address corresponding to each operation parameter based on the operation parameters.

3. The system according to claim 1, characterized in that The system further includes a system use case sending module, the driving module further includes a virtual function interface, the system use case sending module is connected to the application development interface module, The system test case sending module is used to send system test cases to the application development interface module; The application development interface module is used to call the virtual function interface in the driver module based on the received system test case to generate original register type instructions, original memory type instructions and original doorbell type instructions.

4. The system according to claim 3, characterized in that The application development interface module is also used to parse the received system test cases, obtain operation parameters and operation logic, and call the virtual function interface in the driver module to obtain the memory address corresponding to each operation parameter based on the operation parameters.

5. The system according to claim 2 or 4, characterized in that: The application development interface module is used to call the driver module to generate an original register configuration instruction based on each operation parameter and the memory address corresponding to each operation parameter, and send the original register configuration instruction to the conversion interface; The conversion interface is used to convert the original register configuration instruction into a target register configuration instruction implemented based on the SystemVerilog language, and send the target register configuration instruction to the RTL module; The RTL module is used to configure registers in the chip design to be tested based on target register configuration instructions, and after configuration is completed, returns a register configuration completion instruction to the application development interface module through a conversion interface and a driver module.

6. The system according to claim 5, characterized in that After receiving the register configuration completion instruction, the application development interface module is used to call the driver module to generate an original data handling instruction based on each operation parameter and the register configuration information, and send the original data handling instruction to the conversion interface; The conversion interface is used to convert the original data handling instruction into a target data handling instruction implemented based on the SystemVerilog language, and send the target data handling instruction to the RTL module; The RTL module is used to store the original data in the corresponding memory based on the target data transfer instruction, and after the storage is completed, returns the data transfer completion instruction to the application development interface module through the conversion interface and the driver module.

7. The system according to claim 6, characterized in that After receiving the data transfer completion instruction, the application development interface module calls the driver module to generate an original doorbell instruction based on the operation logic, and sends the original doorbell instruction to the conversion interface; The conversion interface is used to convert the original doorbell instruction into a target doorbell instruction implemented based on the SystemVerilog language, and send the target doorbell instruction to the RTL module; The RTL module is used to execute operation logic based on the target doorbell instruction and the original data stored in the memory to generate an operation result.

8. The system according to claim 7, characterized in that The RTL module is used to send the original completion instruction to the conversion interface; The conversion interface is used to convert the original completion instruction into a target completion instruction implemented by a software language, and send it to the application development interface module through the driver module; The original completion instruction is a register configuration completion instruction, a data transfer completion instruction or a calculation result.

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