A method and device for generating simulation excitation, electronic equipment and storage medium

Abstract

This application discloses a method, apparatus, electronic device, and storage medium for generating simulation stimuli, relating to the field of storage technology. The method includes: acquiring a first transmission transaction, which simulates a host storing data to be transmitted in host memory; determining M first half-storage blocks from multiple half-storage blocks based on the occupancy status and address representation of each half-storage block; generating N address entries based on the M first half-storage blocks, with the N address entries bound to the addresses of the M first half-storage blocks; determining at least one address identifier based on the N and the addresses of the N address entries; generating a simulation stimuli containing at least one address identifier; and sending the simulation stimuli to a storage controller, whereby the simulation stimuli are used to test the storage controller's transmission function for the data to be transmitted. This application solves the problem in related technologies of being unable to generate simulation stimuli corresponding to data transmission in discontinuous scenarios, improving the accuracy of testing the transmission function of the storage controller.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a method, apparatus, electronic device, and storage medium for generating simulation stimuli. Background Technology

[0002] With the rapid development of integrated circuit technology, the complexity and integration level of integrated circuits are constantly increasing, highlighting the growing importance of front-end verification. In the integrated circuit design process, front-end verification is a crucial step in ensuring design correctness and reliability. Front-end verification can be performed during the Hardware Description Language (HDL) code design phase, applying stimuli to the design through software simulation to test its functional correctness. In the storage field, the storage controller (also known as the host controller) serves as a key node connecting the user host and the storage medium. To better realize its functions, the industry has specified the Non-Volatile Memory Express (NVMe) protocol. Data interaction between the storage controller and the host must comply with the NVMe protocol. Front-end verification of the storage controller requires simulating the host to apply simulation stimuli to the host controller.

[0003] During the relevant front-end verification process, only data structures with different address representations matching each other are forcibly partitioned within the contiguous storage area after a specified address to generate simulation stimuli, in order to realize a scenario where data location is described by address entries with different address representations matching each other. However, this method of generating simulation stimuli cannot generate simulation stimuli corresponding to data transmission in non-contiguous scenarios, resulting in low accuracy in testing the transmission function of the storage controller. Summary of the Invention

[0004] This application provides a method, apparatus, electronic device, and storage medium for generating simulation stimuli, in order to at least solve the problem in related technologies that the inability to generate simulation stimuli corresponding to data transmission in discontinuous scenarios leads to low accuracy in testing the transmission function of the storage controller.

[0005] This application provides a method for generating simulation stimuli, comprising: acquiring a first transmission transaction, the first transmission transaction being used to simulate a host storing data to be transmitted in host memory, the first transmission transaction carrying an address representation, the address representation being used to indicate the storage distribution of the data to be transmitted in host memory, the host memory being divided into multiple half-storage blocks; determining M first half-storage blocks from the multiple half-storage blocks according to the occupancy status and address representation of each half-storage block, the M first half-storage blocks being used to store the data to be transmitted, the distribution of the M first half-storage blocks matching the address representation; generating N address entries based on the M first half-storage blocks, the N address entries being bound to the addresses of the M first half-storage blocks, N≤M, where N and M are both positive integers; determining at least one address identifier based on N and the addresses of the N address entries, the at least one address identifier being used to identify the addresses of the N address entries in host memory; generating a simulation stimuli containing at least one address identifier; and sending the simulation stimuli to a storage controller, the simulation stimuli being used to test the storage controller's transmission function of the data to be transmitted.

[0006] This application also provides a simulation stimulus generation device, including: an acquisition module for acquiring a first transmission transaction, the first transmission transaction being used to simulate the host storing data to be transmitted in the host memory, the first transmission transaction carrying an address representation method, the address representation method being used to indicate the storage distribution method of the data to be transmitted in the host memory, the host memory being divided into multiple half-storage blocks.

[0007] The processing module is used to determine M first half-storage blocks from multiple half-storage blocks according to the occupancy status and address representation of each half-storage block. The M first half-storage blocks are used to store the data to be transmitted, and the distribution of the M first half-storage blocks matches the address representation.

[0008] The processing module is also used to generate N address entries based on M first half-blocks of storage, and the N address entries are bound to the addresses of the M first half-blocks of storage, where N≤M and N and M are both positive integers.

[0009] The processing module is used to determine at least one address identifier based on the addresses of N and N address entries, wherein the at least one address identifier is used to identify the addresses of the N address entries in the host memory.

[0010] The processing module is used to generate a simulation stimulus containing at least one address identifier and send the simulation stimulus to the storage controller. The simulation stimulus is used to test the storage controller's ability to transmit data to be transmitted.

[0011] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above-described methods for generating simulation stimuli.

[0012] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described methods for generating simulation stimuli.

[0013] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described methods for generating simulation stimuli.

[0014] According to this application, the transport transaction generator obtains a first transport transaction, determines M first half-storage blocks from multiple half-storage blocks based on the occupancy status and address representation of each half-storage block, generates N address entries based on the M first half-storage blocks, determines at least one address identifier based on the N and the addresses of the N address entries, generates a simulation stimulus containing at least one address identifier, and sends the simulation stimulus to the storage controller.

[0015] Since host memory can be divided into multiple half-blocks, host memory space can be allocated according to the user's required transmission transactions. Based on the distribution range of these memory spaces, the data to be stored can be stored and multiple address entries can be generated according to the space occupancy status and the selected address representation method. Then, based on these multiple address entries, simulation stimuli corresponding to data transmission in non-contiguous scenarios can be generated, improving the accuracy of testing the transmission function of the storage controller. Furthermore, this application saves the time of allocating address ranges corresponding to half-blocks for the data to be transmitted. By grouping and planning address entries according to different address representation methods, it controls the distribution of the data to be transmitted and the number and distribution of corresponding address entries, providing flexibility and richness in simulation stimuli. Attached Figure Description

[0016] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A topology diagram of a simulation stimulus generation system provided in this application embodiment;

[0018] Figure 2 A flowchart illustrating a method for generating simulation stimuli provided in an embodiment of this application;

[0019] Figure 3 A schematic diagram illustrating the partitioning of a host memory into multiple HKBs, provided for an embodiment of this application;

[0020] Figure 4 This is a schematic diagram of the address entry distribution in the host memory provided in an embodiment of this application;

[0021] Figure 5 This is a schematic diagram of the PRP-List item distribution provided in the embodiments of this application;

[0022] Figure 6 This is a schematic diagram of the SGL entry distribution provided in the embodiments of this application;

[0023] Figure 7 A structural block diagram of a simulation stimulus generation device provided in an embodiment of this application;

[0024] Figure 8 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0026] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0027] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] The specific application environment architecture or specific hardware architecture on which the execution of the simulation stimulus generation method depends is described here.

[0029] The embodiments of this application are applied to the front-end verification of the storage controller (also known as the main controller / main control integrated circuit), in a scenario where it is necessary to simulate the user host to apply simulation stimuli to the storage controller.

[0030] In the NVMe protocol, data transmission can be non-contiguous. The protocol typically uses Physical Region Page (PRP) or Scatter / Gather List (SGL) data pointers to represent non-contiguous or fragmented data distribution. This requires the model simulating the user host to place the data to be transmitted in the host memory in a non-contiguous or fragmented manner and generate PRP and SGL address entries.

[0031] PRP is a physical page-based data transfer method in the NVMe protocol used to describe the transfer of data between host memory and storage devices (such as solid-state drives). It is mainly used to describe contiguous memory space.

[0032] SGL is a more flexible data transfer method in NVMe that can describe memory spaces of arbitrary size and non-contiguous nature.

[0033] In related technologies, the method of generating simulation stimuli by forcibly dividing data structures with different address representations in a contiguous storage area after a specified address by simulating the host has two drawbacks. First, it cannot generate simulation stimuli corresponding to data transmission in non-contiguous scenarios. Second, there is a risk of data overlap when multiple transmission transactions are initiated in parallel, which is not conducive to the parallel execution of multiple stimuli.

[0034] To address the aforementioned technical problems, this application provides a method for generating simulation stimuli. The method divides user memory into several minimum space units. Based on the total amount of data to be transmitted and the selected address representation method, a sufficient number of minimum space units are selected. Utilizing the characteristics of a simulated backdoor-readable and writable memory, these minimum space unit sets are read and written. Based on the selection results, simulation stimuli corresponding to several PRP and SGL entries are generated and sent to the storage controller to transmit the address information of the minimum space unit set to the storage controller, thereby testing the storage controller's data transmission function. This method can generate simulation stimuli corresponding to data transmission in discontinuous scenarios, thereby improving the accuracy of testing the storage controller's transmission function.

[0035] The following is based on Figure 1 Taking the simulation stimulus generation system shown as an example, the method provided in the embodiments of this application will be described.

[0036] like Figure 1 As shown, Figure 1 This is a topology diagram of a simulation stimulus generation system provided in an embodiment of this application. Figure 1 In the simulation stimulus generation system 100, there are a transmission transaction generator 101, a storage controller 102, a host memory 103, and a controller memory 104.

[0037] The transaction generator 101 in this embodiment can be any device with communication and computing capabilities, abbreviated as Trans-Gen. The transaction generator is built using a syntax structure such as classes, properties, and methods, based on SystemVerilog Object-Oriented Programming (SV-OOP), an important programming paradigm for hardware verification and design. The transaction generator can also be referred to as a simulation stimulus generation device.

[0038] The storage controller 102 in this embodiment can manage data transmission between host memory and controller memory, ensuring data storage reliability and read / write performance.

[0039] Host memory 103 can be random access memory (RAM) in the host computer, which is a component used to temporarily store data and program instructions during computer operation.

[0040] The controller memory 104 can be the memory provided by the main controller / storage controller itself, used to assist the main controller in completing specific tasks.

[0041] Figure 1 The simulation stimulus generation system shown is for illustrative purposes only and is not intended to limit the technical solutions of this application. Those skilled in the art should understand that, in specific implementations, the simulation stimulus generation system may include more devices, without limitation.

[0042] Embodiments of this application provide a method for generating simulation stimuli, applied to a transport transaction generator, such as... Figure 2 As shown, Figure 2 The flowchart illustrates a method for generating simulation stimuli according to an embodiment of this application. The method includes the following steps:

[0043] S201: Acquire the first transport transaction.

[0044] The first transmission transaction simulates the host storing the data to be transmitted in the host memory. The first transmission transaction carries the address representation, the length of the data to be transmitted, and the data to be transmitted.

[0045] The address representation method is used to indicate the storage distribution of the data to be transferred in the host memory. Address expressions include Physical Region Page (PRP) representation and Scatter / Gather List (SGL) representation.

[0046] Host memory (also known as Host-mem) is divided into multiple half-kilobytes (HKBs). A half-kilobyte (HKB) is also called a minimum unit of storage. Each half-kilobyte can be 512 bytes in size. Each half-kilobyte corresponds to an index or number, which is used to identify each HKB.

[0047] Understandably, in the NVMe protocol, the smallest unit of data transfer is a logical block, and a logical block is at least 512 bytes. Therefore, in this application, the host-mem space is divided into multiple half-blocks with a size and boundary of 512 bytes. For example, when the host memory is 1024KB, it can be divided into 2048 HKBs.

[0048] S202: Based on the occupancy status and address representation of each half-block, determine M first half-blocks among the multiple half-blocks.

[0049] Of these, M first-half storage blocks are used to store the data to be transmitted. The distribution of the M first-half storage blocks matches the address representation method.

[0050] In some optional implementations, the transport transaction generator obtains the static attributes of the multi-bit portion of the host memory and the size of each half-block; calculates the sum of the data length and the size of each half-block to obtain the total number M of half-blocks required for the data to be transmitted; and determines M first half-blocks among the multiple half-blocks based on the address representation, static attributes, and total number M, wherein the occupancy status of each of the M first half-blocks is unoccupied.

[0051] The static attribute consists of multiple bits. Each bit indicates the occupancy status of each half-block of storage. The static attribute is named allocated_hkb. Each bit of the static attribute represents the occupancy status of each HKB in host memory.

[0052] Specifically, setting a bit to a preset value indicates that the HKB corresponding to that bit's index is in an occupied state. The preset value is used to indicate whether the occupancy status of the half-block corresponding to each bit is occupied. For example, the preset value can be 1. Conversely, setting a bit to 0 indicates that the HKB corresponding to that bit's index is in an unoccupied or idle state.

[0053] Understandably, static properties ensure that space management information can be shared among multiple Trans-Gen objects (i.e., multiple transport transactions), meaning that this static property is used by all Trans-Gen objects. This static property allows the occupancy information to be shared among all transport transactions, ensuring that data overlap does not occur between multiple transport transactions.

[0054] In one example, when the address representation is physical page representation, the transport transaction generator determines M first half-blocks from multiple half-blocks that match the physical page representation based on static attributes and the total number M. These M first half-blocks are distributed across N memory pages.

[0055] In another example, when the address representation is a scatter-cluster list representation, the transport transaction generator determines M first half-blocks from multiple half-blocks that match the scatter-cluster list representation, based on static attributes and the total number M. These M first half-blocks correspond to N memory segments.

[0056] For example, with Figure 3 For example, Figure 3 This is a schematic diagram illustrating how a host memory is divided into multiple HKBs, as provided in an embodiment of this application. Figure 3 In the diagram, the shaded HKB indicates that it is occupied by other ongoing transmission transactions and is in a state of being occupied. The size of each memory page corresponding to this host memory is 4KB (therefore the aligned address should be 0x1000), which means that the maximum storage space that a PRP entry can represent is 4KB. Figure 3 Each line in the table represents a MemoryPage.

[0057] Taking a data length of 12*512 bytes and 12 HBK bytes required for transmission as an example, the transmission transaction generator determines 12 first half-blocks from multiple half-blocks under different address representation methods, including:

[0058] Example 1: When the address representation is PRP, the Trans-Gen generator searches for an idle HKB in the host memory based on static attributes. It first finds HKB4 in the first line. However, since PRP is used, if the starting address of HKB4 (0x0800) is taken as the first PRP entry, according to the NVMe protocol's definition of PRP, it will cover the address space 0x0800~0x0fff. In the diagram, 0x0a00~0x0fff is occupied by other PRP entries. Since the first half of the storage block is occupied by a transfer transaction, HKB4 cannot be used as the first half of the storage block. Next, HKB14 and HKB15 in the second row are found. If the starting address of HKB14, 0x1c00, is taken as the first PRP entry, according to the NVMe protocol's definition of a PRP, it will cover 0x1c00~0x1fff. The HKBs corresponding to 0x1c00~0x1fff are all unoccupied, meaning this storage space is available. Therefore, HKB14~HKB15, a total of 2 HKBs, can be used as the first half of the storage block. Next, the eight HKBs in the third row, HKB16~HKB23, are found. These eight HKBs form a single storage page and are not occupied by other transfer transactions (all are in an unoccupied state). Therefore, HKB16~HKB23, a total of 8 HKBs, can be used as the first half of the storage block. Finally, the two HKBs in the fifth row, HKB32~HKB33, are found. Thus far, 12 first half-blocks that match the physical page representation method have been identified from multiple half-blocks, including HKB14, HKB15, HKB16~HKB23, and HKB32~HKB33.

[0059] Example 2: When the address representation is SGL, the Trans-Gen generator searches for free HKBs in the host memory based on static attributes. First, it finds HKB4. Since it uses SGL address representation, according to the definition of SGL in the NVMe protocol, it can accurately represent the HKB4 space without worrying about covering other spaces. Therefore, HKB4 can be used as the first half-block. Next, it searches for HKB14~HKB23 and HKB32, all of which are unoccupied. Therefore, HKB14~HKB23 and HKB32 can be used as the first half-block. Thus, the 12 first half-blocks matching the scatter-cluster list representation are determined from multiple half-blocks: HKB4, HKB14~HKB23, and HKB32.

[0060] In some optional implementations, after the transport transaction generator determines M first half-blocks among multiple half-blocks, it can also look up the M bits corresponding to the M first half-blocks in the static attributes; and update each bit in the M bits of the static attributes to a preset value to obtain the first static attributes. For example, the transport transaction generator can update each bit in the M bits of the static attributes to 1 to indicate locking the M first HKBs.

[0061] Optionally, the transport transaction generator can record the indices of M first HKBs into a queue variable (udata_hkb_q).

[0062] In one example, when the transport transaction generator first locks M HKBs via allocated_hkb, it can set a semaphore in the transport transaction generator's class definition and make that semaphore a static attribute. This semaphore is also called alloc_chg_sema.

[0063] For example, before modifying allocated_hkb, the transport transaction generator needs to request modification rights from the sema (alloc_chg_sema), modify allocated_hkb after obtaining the modification rights, and return the modification rights after the modification is completed.

[0064] Understandably, the transport transaction generator sets this flag as a static attribute to ensure that any transport transaction requests the same flag. Furthermore, since the allocated_hkb variable is a static attribute, multiple transport transactions modify the same variable, thus preventing read / write conflicts between multiple concurrent transport transactions.

[0065] S203: Generate N address entries based on M first half-blocks of storage.

[0066] In this system, N address entries are bound to the addresses of M first half-blocks of storage, where N ≤ M and both N and M are positive integers.

[0067] In some optional implementations, when the address representation is a physical page representation, the transport transaction generator generates N address entries based on the starting address of the first first half-block distributed on each of the N storage pages corresponding to the M first half-blocks.

[0068] For example, when the address representation is physical page representation, the transport transaction generator generates N PRP address entries based on the starting address of the first first HKB in udata_hkb_q (the first first HKB distributed among the first storage pages corresponding to the M first half-blocks) and the starting addresses of the first first HKBs of the other storage pages among the N storage pages excluding the first storage page.

[0069] Example 3, taking Example 1 as an example, shows that the M first half-memory blocks are HKB14~15, HKB16~23, and HKB32~33. The transport transaction generator uses the starting address 0x1c00 of the first first HKB in the first row (HKB14) to create a PRP address entry; it uses the starting address 0x2000 of the first first HKB in the third row to create another PRP address entry; and it uses the starting address 0x400 of the first first HKB in the fifth row to create yet another PRP address entry, thus generating three PRP address entries. It can be understood that these three PRP entries can represent the complete data location of the data to be transmitted.

[0070] Optionally, the transport transaction generator can write N PRP address entries into a queue (prp_list).

[0071] In some optional implementations, when the address representation is a distributed aggregated list representation, the transport transaction generator generates N address entries based on the starting address of the first first half-block in each of the N storage segments corresponding to the M first half-blocks, and the data length of at least one first half-block included in each storage segment. Each address entry is also referred to as an SGL Data Block descriptor.

[0072] For example, when the address representation is a distributed aggregated list representation, the transport transaction generator generates N SGL Data Block descriptors based on the N consecutive storage segments corresponding to the M first half-storage blocks in udata_hkb_q.

[0073] Example 4, taking Example 2 as an example, has M first-half storage blocks: HKB4, HKB14~23, and HKB32. These M first-half storage blocks are distributed across three contiguous memory segments, meaning they correspond to three memory segments. The transaction generator uses the starting address 0x0800 of HKB4 and a data length of 512 bytes for one first-half storage block to create an SGL Data Block descriptor; it uses the starting address 0x1c00 of HKB14~23 and a data length of 5120 bytes for ten first-half storage blocks to create an SGL Data Block descriptor; and it uses the starting address 0x4000 of HKB32 and a data length of 512 bytes for one first-half storage block to create an SGL Data Block descriptor, thus generating three SGL Data Block descriptors (i.e., three SGL address entries). It can be understood that these three SGL Data Block descriptors can represent the complete data location of the data to be transmitted.

[0074] Optionally, the transport transaction generator can write N SGL address entries into a queue (sgl_dscrps).

[0075] S204: Determine at least one address identifier based on N and the addresses of N address entries.

[0076] Among them, at least one address identifier is used to identify the address of N address entries in the host memory.

[0077] In some optional implementations, when the address representation is a physical page representation and N is greater than a first value, the transport transaction generator obtains the entry size of each address entry and the storage page size of each storage page; calculates the ratio between the storage page size and the entry size to obtain the maximum number of entries allowed per storage page; calculates the ratio between N and the maximum number, and rounds the ratio up to obtain the first number of storage pages required for N-1 address entries; calculates the sum of the first number and N-2 to obtain the second number L of second half-blocks required for N address entries; determines L second half-blocks among multiple half-blocks based on the first static attribute and L; and determines at least one address identifier based on the starting address corresponding to the L second half-blocks and the first address corresponding to the first address entry.

[0078] Among them, N-1 address entries are the other N-1 address entries besides the first address entry.

[0079] L second half-blocks are used to store N address entries. The L second half-blocks are the remaining unoccupied half-blocks after the M first half-blocks among the multiple half-blocks, and L≥N are positive integers.

[0080] The occupancy status of each of the L second half storage blocks is unoccupied.

[0081] When N is greater than the first value, at least one address identifier includes the starting address and the first address.

[0082] The first value can be set according to the storage protocol between the host and the storage controller. For example, when the storage protocol is NVMe, the first value is 2.

[0083] Understandably, when there are more than two PRP address entries, the remaining PRP address entries after the first one need to be organized into a PRP-List. The PRP-List is divided into memory pages. For example, in the 4KB memory page space shown in Example 1, one memory page can store 512 PRP entries of length 8 bytes. When N is greater than the number of address entries that a memory page (PRP-List Page) can store, the remaining PRP address entries need to be stored in another memory page (PRP-List Page), and the last PRP entry of the previous PRP-List Page should be the starting address of the next PRP-List Page. This means that not only do we need to store N PRP address entries describing the location of all the data, but we also need to store N entries in the Host-mem that point to different PRP-List Pages. Therefore, the transport transaction generator needs to determine how many Memory Pages are needed based on the total number of PRP entries N and the number of entries pointing to the PRP-List Page that may need to be inserted, and select a sufficient number of HKBs from the Host-mem to generate entries pointing to the PRP-List Page.

[0084] For example, taking N address entries as an example, resulting in 521 PRP address entries, such as... Figure 4 As shown, Figure 4This is a schematic diagram of the address entry distribution in the host memory provided in this application embodiment; the transport transaction generator obtains that the entry size of each address entry is 8B and the storage page size of each storage page is 4KB; calculates the ratio between the storage page size and the entry size to obtain the maximum number of entries that can be stored in each storage page, 512; calculates the ratio between N and the maximum number, and performs an up-rounding operation on the ratio to obtain the first number of storage pages required for N-1 address entries, which is 2 (that is, it is determined that 2 PRP-List Pages are needed to store 520 PRP address entries); calculates the sum of the first number and N-2 to obtain the second number L of the second half storage block required for N address entries, which is 521, that is, it indicates that 1 entry pointing to the PRP-List Page needs to be inserted, for a total of 521 PRP address entries of size 8B.

[0085] The transport transaction generator searches for free HBKs in the host memory, finds HKB40~47 in line 6 and HKB40 and HKB48 in line 7, and records the indices of HKB40~47, HKB40, and HKB48 into a queue variable (udptr_hkb_q). Optionally, the transport transaction generator sets the bits corresponding to the indices of HKB40~47, HKB40, and HKB48 in allocated_hkb to 1 to indicate that HKB40~47, HKB40, and HKB48 are locked.

[0086] Furthermore, such as Figure 5 As shown, Figure 5 This is a schematic diagram of the PRP-List entry distribution provided in the embodiments of this application. The transport transaction generator traverses all HKB indices in udptr_hkb_q. When it finds that the current HKB index and the next HKB index are not in the same PRP-List Page range, it considers that the PRP-List Page needs to be switched. At the end of the entries that the first PRP-List Page can carry, a blank PRP address entry (blank entry) is inserted and the position of the PRP address entry is recorded. When traversing to the beginning of the next PRP-List Page, the blank PRP entry is assigned a value, which is the starting address of the new PRP-List Page.

[0087] Optionally, when the address representation is a physical page representation and N is less than or equal to a first value, the transport transaction generator determines at least one address identifier based on the address corresponding to each of the N address entries. In this case, the at least one address identifier includes the address corresponding to each of the N address entries.

[0088] In some optional implementations, when the address representation is a distributed aggregated list representation and N is greater than a second value, the transport transaction generator determines a first storage segment among multiple half-blocks based on a first static attribute. If the first storage segment can store N address entries, the starting address corresponding to the first storage segment is determined as at least one address identifier. If the first storage segment cannot store N address entries, a second storage segment is determined among multiple half-blocks based on the first static attribute. If the second storage segment can store N address entries and the starting address corresponding to the first storage segment, the starting address corresponding to the second storage segment is inserted into the last address entry of the first storage segment, and the starting address corresponding to the first storage segment is determined as at least one address identifier. If the second storage segment cannot store N address entries, the starting address corresponding to the first storage segment is determined as at least one address identifier, and multiple storage segments are determined among multiple half-blocks based on the first static attribute until multiple storage segments can store N address entries, and the starting address of the next storage segment is stored in the previous storage segment.

[0089] The second value can be set according to the storage protocol between the host and the storage controller. For example, when the storage protocol is NVMe, the second value is 1.

[0090] Understandably, when there are more than one SGL Data Block descriptor, these N SGL Data Block descriptors need to be organized into SGL segments (also called storage segments). An SGL segment is a contiguous storage space. When the first SGL segment is insufficient to hold N SGL Data Block descriptors, a second SGL segment needs to be determined from the next contiguous space. The last SGL address entry of the previous SGL segment should point to the SGL segment descriptor or the end segment descriptor of the next SGL segment. This necessitates not only storing N SGL Data Block descriptors containing all the data locations, but also storing the SGL segment descriptors in the Host-mem storage that point to multiple SGL segments when stored in different storage segments.

[0091] The SGL segment descriptor includes the size of each storage segment and the starting address of multiple SGL Data Block descriptors within the storage segment.

[0092] In one example, when the address representation is a scatter-cluster list representation and N is greater than a second value, the transport transaction generator obtains the entry size of each address entry; calculates the product of N and the entry size of each address entry to obtain the amount of memory space required for N address entries; calculates the ratio between the amount of memory space and the size of each half-block, adds 1 to this ratio and rounds it to obtain the number of class blocks required for N address entries. Based on the number of class blocks required for N address entries, the number of storage segments required for N address entries is determined.

[0093] For example, taking N address entries as 64 SGL Data Block descriptors, with each SGL Data Block descriptor being 16 bytes, the transport transaction generator calculates the product of N and the size of each address entry to obtain the amount of memory space required for N address entries (16 * 64 = 1024 bytes). It then calculates the ratio between the amount of memory space and the size of each half-block (1024 bytes / 512 bytes = 2), adds 1 to this ratio, and rounds it down to obtain the number of half-blocks required for N address entries as 3, which is 3 HKB of storage. Therefore, it is necessary to insert 1 SGL segment descriptor and 1 SGL end segment descriptor, for a total of 66 SGL entries of size 16 bytes each. Figure 4 As shown, the transport transaction generator searches for free HBKs in the host memory, finds HKB34, HKB37, and HKB40, and records their indices in a queue variable (udptr_hkb_q). Optionally, the transport transaction generator sets the bits corresponding to the indices of HKB34, HKB37, and HKB40 in allocated_hkb to 1 to indicate that HKB34, HKB37, and HKB40 are locked.

[0094] Furthermore, such as Figure 6 As shown, Figure 6 This is a schematic diagram of the SGL entry distribution provided in the embodiments of this application. The transport transaction generator traverses all HKB indices in udptr_hkb_q. When it finds that the current HKB index is not continuous with the next HKB index, it considers that the SGL segment needs to be switched. Then, at the end of the address entries that the first SGL segment can carry, a blank SGL segment descriptor (i.e., a blank entry) is inserted and the position of the SGL segment descriptor is recorded. When traversing to the HKB at the beginning of the next SGL segment, the address (i.e., the starting address) part of the previously inserted blank SGL segment descriptor is assigned a value. When traversing to the HKB that is determined to be the beginning of the next two SGL segments or the last HKB, the length (i.e., the size of each storage segment) part of the previously inserted blank SGL segment descriptor is assigned a value.

[0095] In some optional implementations, when the address representation is a distributed aggregated list representation and N is less than or equal to a second value, the transport transaction generator determines at least one address identifier based on the address corresponding to each of the N address entries. In this case, the at least one address identifier includes the address corresponding to each of the N address entries.

[0096] Optionally, the transport transaction generator uses the static attribute `allocated_hkb` as a storage unit lock. Besides modifying the lock value when allocating host memory space for the data to be transferred and its corresponding address entries, the lock information can also be modified independently by the user to customize the data distribution. For example, in a contiguous range of available HKB0~HKB15, taking N address entries of 3KB each as an example, if the range is directly allocated to N address entries within HKB0~15, only one SGL Data Block descriptor with address 0x0, length 3KB, and containing HKB0~5 will be obtained. However, if more address entries are desired, the user can modify `allocated_hkb` to lock HKB2 and HKB5 before allocation. The final allocated HKBs will then be HKB0, HKB1, HKB3, HKB4, HKB6, and HKB7, thus generating three SGL Data Block descriptors. Similarly, taking N address entries as examples of 40 SGL Data Block descriptors, if the range is directly allocated to N address entries in HKB0~15, the allocation will be to HKB0 and HKB1, resulting in an SGL segment with a starting address of 0x0 and a length of 40 SGL Data Block descriptors. However, if more SGL segments are desired, the user can manually modify allocated_hkb to lock HKB1 before allocation, resulting in allocation to HKB0 and HKB2, forming an SGL segment containing 31 SGL Data Block descriptors and an SGL end segment containing 9 SGL Data Block descriptors.

[0097] Understandably, when there are more than 2 PRP entries or more than 1 SGL entries (SGL Data Block descriptors), since the simulation stimulus (the IO command of the NVMe protocol) cannot accommodate more address entries, it is necessary to place each entry in the host memory and transmit only the starting position of these entries in the host memory (i.e., at least one address identifier) ​​in the simulation stimulus.

[0098] S205: Generate a simulation stimulus containing at least one address identifier, and send the simulation stimulus to the memory controller.

[0099] The simulation stimulus is used to test the storage controller's ability to transmit data.

[0100] In one example, after the transport transaction generator determines the required half-block of storage in the host memory for the data to be transferred and the corresponding address entries, it backdoors the data to be transferred and the corresponding address entries into the host memory sequentially according to the recorded HKB index. The backdoor writing is implemented using the `deposit` system task in the SystemVerilog language.

[0101] In one example, the transport transaction generator generates a simulation stimulus containing at least one address identifier based on at least one address identifier and an address representation, and sends the simulation stimulus to the storage controller so that the storage controller can transport the data to be transported based on at least one address identifier.

[0102] Understandably, upon receiving the simulation stimulus, the storage controller, based on at least one address identifier and address representation, transfers the data to be transmitted from the host memory to the controller memory. If the storage controller can successfully transfer the data from the host memory to the controller memory, it indicates that the storage controller's transmission function is normal.

[0103] Optionally, after the first transmission transaction is completed, the half-block of storage occupied by the first transmission transaction is released, and the corresponding bits of the half-block of storage occupied by the first transmission transaction are updated.

[0104] Understandably, after the first transmission transaction is completed, the HKBs occupied and locked by the first transmission transaction can be released through the queues that record the HKB index numbers udata_hkb_q and udptr_hkb_q occupied by the first transmission transaction. When releasing the HKBs occupied by the first transmission transaction, it is only necessary to traverse each index value in these two queues and reset the corresponding bit in the allocated_hkb attribute to 0 to unlock them.

[0105] based on Figure 2 The method shown involves a transport transaction generator acquiring a first transport transaction, determining M first half-blocks from multiple half-blocks based on the occupancy status and address representation of each half-block, generating N address entries based on the M first half-blocks, determining at least one address identifier based on the addresses of the N and N address entries, generating a simulation stimulus containing at least one address identifier, and sending the simulation stimulus to the storage controller.

[0106] Since host memory can be divided into multiple half-blocks, host memory space can be allocated according to the user's required transmission transactions. Based on the distribution range of these memory spaces, the data to be stored can be stored and multiple address entries can be generated according to the space occupancy status and the selected address representation method. Then, based on these multiple address entries, simulation stimuli corresponding to data transmission in non-contiguous scenarios can be generated, improving the accuracy of testing the transmission function of the storage controller. Furthermore, this application saves the time of allocating address ranges corresponding to half-blocks for the data to be transmitted. By grouping and planning address entries according to different address representation methods, it controls the distribution of the data to be transmitted and the number and distribution of corresponding address entries, improving the flexibility and richness of the simulation stimuli.

[0107] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0108] Embodiments of this application also provide a device for generating simulation stimuli, such as... Figure 7 As shown, Figure 7 The present application provides a structural block diagram of a simulation stimulus generation device; the device includes: an acquisition module 701, used to acquire a first transmission transaction, the first transmission transaction being used to simulate the host storing data to be transmitted in the host memory, the first transmission transaction carrying an address expression method, the address expression method being used to indicate the storage distribution method of the data to be transmitted in the host memory, the host memory being divided into multiple half-storage blocks.

[0109] The processing module 702 is used to determine M first half-storage blocks from multiple half-storage blocks according to the occupancy status and address expression method of each half-storage block. The M first half-storage blocks are used to store the data to be transmitted, and the distribution method of the M first half-storage blocks matches the address expression method.

[0110] The processing module 702 is used to generate N address entries based on M first half-storage blocks. The N address entries are bound to the addresses of the M first half-storage blocks, where N ≤ M and N and M are both positive integers.

[0111] The processing module 702 is used to determine at least one address identifier based on N and the addresses of N address entries, wherein the at least one address identifier is used to identify the addresses of N address entries in the host memory.

[0112] The processing module 702 is used to generate a simulation stimulus containing at least one address identifier and send the simulation stimulus to the storage controller. The simulation stimulus is used to test the storage controller's ability to transmit data to be transmitted.

[0113] In some optional implementations, the first transmission transaction also carries the data length of the data to be transmitted; the processing module 702 is specifically used to obtain the static attributes of the multi-bit corresponding to the host memory, and the size of each half-block, the static attributes including multiple bits, each bit being used to indicate the occupancy status of each half-block; calculate the sum of the data length and the size of each half-block to obtain the total number M of half-blocks required for the data to be transmitted; based on the address representation method, static attributes and the total number M, determine M first half-blocks among the multiple half-blocks, the occupancy status of each of the M first half-blocks is an unoccupied state.

[0114] In some optional implementations, after determining M first half-blocks among multiple half-blocks, the processing module 702 is further configured to find the M bits corresponding to the M first half-blocks in the static attributes; update each bit in the M bits in the static attributes to a preset value to obtain the first static attribute, wherein the preset value is used to indicate that the occupancy status of the half-block corresponding to each bit is occupied.

[0115] In some optional implementations, the processing module 702 has the function of determining, based on static attributes and a total number M, M first half-blocks that match the physical page representation when the address representation is physical page representation, and the M first half-blocks are distributed on N memory pages.

[0116] In some optional implementations, the processing module 702 further includes the function of determining, based on static attributes and the total number M, M first half-blocks that match the scatter-cluster list representation when the address representation is a scatter-cluster list representation, such that the M first half-blocks correspond to N storage segments.

[0117] In some optional implementations, the processing module 702 is further configured to generate N address entries based on the starting address of the first first half-block distributed on each of the N storage pages corresponding to the M first half-blocks when the address representation method is physical page representation method.

[0118] In some optional implementations, the processing module 702 is further configured to generate N address entries based on the starting address of the first first half-block in each of the N storage segments corresponding to the M first half-blocks, and the data length of at least one first half-block included in each storage segment, when the address representation is a distributed aggregated list representation.

[0119] In some optional implementations, the processing module 702 is further configured to obtain the entry size of each address entry and the storage page size of each storage page when the address representation is a physical page representation and N is greater than a first value. Calculate the ratio between the storage page size and the entry size to obtain the maximum number of entries that can be stored per storage page; calculate the ratio between N and the maximum number, and round up the ratio to obtain the first number of storage pages required for N-1 address entries, where N-1 address entries are the other N-1 address entries besides the first address entry; calculate the sum of the first number and N-2 to obtain the second number L of second half-storage blocks required for N address entries, where L second half-storage blocks are used to store N address entries, and L second half-storage blocks are the remaining unoccupied half-storage blocks after the M first half-storage blocks among multiple half-storage blocks, where L≥N and is a positive integer; based on the first static attribute and L, determine L second half-storage blocks among the multiple half-storage blocks, where the occupancy status of each of the L second half-storage blocks is unoccupied; based on the starting address corresponding to the L second half-storage blocks and the first address corresponding to the first address entry, determine at least one address identifier, where the at least one address identifier includes the starting address and the first address.

[0120] In some optional implementations, the processing module 702 further comprises determining at least one address identifier based on the address corresponding to each of the N address entries when the address representation is a physical page representation and N is less than or equal to a first value. The at least one address identifier includes the address corresponding to each of the N address entries.

[0121] In some optional implementations, the processing module 702 further comprises: when the address representation is a distributed aggregated list representation and N is greater than a second value, determining a first storage segment among multiple half-storage blocks based on a first static attribute; if the first storage segment can store N address entries, determining the starting address corresponding to the first storage segment as at least one address identifier; if the first storage segment cannot store N address entries, determining a second storage segment among multiple half-storage blocks based on the first static attribute; if the second storage segment can store N address entries and the starting address corresponding to the first storage segment, inserting the starting address corresponding to the second storage segment into the last address entry of the first storage segment, and determining the starting address corresponding to the first storage segment as at least one address identifier; if the second storage segment cannot store N address entries, determining the starting address corresponding to the first storage segment as at least one address identifier, and determining multiple storage segments among multiple half-storage blocks based on the first static attribute, until multiple storage segments can store N address entries, and the starting address of the next storage segment is stored in the previous storage segment.

[0122] In some optional implementations, the processing module 702 is further configured to determine at least one address identifier based on the address corresponding to each of the N address entries when the address representation is a distributed aggregated list representation and N is less than or equal to a second value. The at least one address identifier includes the address corresponding to each of the N address entries.

[0123] In some optional implementations, the processing module 702 is further configured to release the half-storage block occupied by the first transmission transaction after the first transmission transaction is completed, and update the bits corresponding to the half-storage block occupied by the first transmission transaction.

[0124] For a description of the features in the embodiment corresponding to the simulation stimulus generation device, please refer to the relevant description in the embodiment corresponding to the simulation stimulus generation method, which will not be repeated here.

[0125] Embodiments of this application also provide an electronic device, such as... Figure 8 As shown, Figure 8 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. The electronic device may be... Figure 1 The transmission transaction generator 101 shown; the electronic device includes a processor 10 and a memory 20, the memory 20 storing a computer program, the processor 10 being configured to run the computer program to perform the steps in any of the above-described simulation stimulus generation method embodiments.

[0126] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described simulation stimulus generation method embodiments at runtime.

[0127] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0128] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described simulation stimulus generation method embodiments.

[0129] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described simulation stimulus generation method embodiments.

[0130] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0131] The foregoing has provided a detailed description of a method, apparatus, electronic device, and storage medium for generating simulation stimuli, as provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for generating simulation stimuli, characterized in that, The method includes: A first transmission transaction is obtained. The first transmission transaction is used to simulate the host storing the data to be transmitted in the host memory. The first transmission transaction carries an address expression and the data length of the data to be transmitted. The address expression is used to indicate the storage distribution of the data to be transmitted in the host memory. The host memory is divided into multiple half-storage blocks. Based on the occupancy status of each half-block and the address representation method, M first half-blocks are determined from the plurality of half-blocks. The M first half-blocks are used to store the data to be transmitted, and the distribution of the M first half-blocks matches the address representation method. Based on the M first half-storage blocks, N address entries are generated, and the N address entries are bound to the addresses of the M first half-storage blocks, where N ≤ M, and N and M are both positive integers; Based on the N and the addresses of the N address entries, at least one address identifier is determined, the at least one address identifier being used to identify the addresses of the N address entries in the host memory; A simulation stimulus containing at least one address identifier is generated, and the simulation stimulus is sent to the storage controller, the simulation stimulus being used to test the storage controller's transmission function of the data to be transmitted; The step of determining M first half-blocks from the plurality of half-blocks based on the occupancy status of each half-block and the address representation method includes: Obtain the static attributes of the host memory corresponding to multiple bits, and the size of each half-block of storage. The static attributes include multiple bits, and each bit is used to indicate the occupancy status of each half-block of storage. Calculate the sum of the data length and the size of each half-block to obtain the total number M of half-blocks required for the data to be transmitted; Based on the address representation method, the static attributes, and the total number M, M first half-storage blocks are determined from the plurality of half-storage blocks, and the occupancy status of each of the M first half-storage blocks is an unoccupied state; when the address representation method is a physical page representation method, the M first half-storage blocks are distributed on N storage pages; Determining at least one address identifier based on the N and the addresses of the N address entries includes: When the address representation method is physical page representation method, and N is greater than the first value, obtain the entry size of each address entry and the storage page size of each storage page; Calculate the ratio between the storage page size and the entry size to obtain the maximum number of entries that can be stored in each storage page; Calculate the ratio between N and the maximum number, and round the ratio up to obtain the first number of storage pages required for N-1 address entries, where the N-1 address entries are the other N-1 address entries excluding the first address entry; Calculate the sum of the first quantity and N-2 to obtain the second quantity L of the second half-storage blocks required for the N address entries. The L second half-storage blocks are used to store the N address entries. The L second half-storage blocks are the remaining unoccupied half-storage blocks after the M first half-storage blocks among the plurality of half-storage blocks. L≥N and is a positive integer. Based on the first static attribute and the L, L second half-storage blocks are determined among the plurality of half-storage blocks, and the occupancy status of each of the L second half-storage blocks is the unoccupied status, and the first static attribute is obtained by updating each bit of the M bits in the static attribute; Based on the starting addresses corresponding to the L second half-blocks and the first address corresponding to the first address entry, at least one address identifier is determined, wherein the at least one address identifier includes the starting address and the first address.

2. The method according to claim 1, characterized in that, After determining M first half-blocks among the plurality of half-blocks, the method further includes: Find the M bits corresponding to the M first half-blocks in the static attributes; The first static attribute is obtained by updating each of the M bits in the static attribute to a preset value. The preset value is used to indicate that the occupancy status of the half-block corresponding to each bit is occupied.

3. The method according to claim 2, characterized in that, The step of determining the M first half-blocks from the plurality of half-blocks based on the address representation method, the static attributes, and the total number M includes: When the address representation method is the physical page representation method, based on the static attributes and the total number M, M first half-storage blocks that match the physical page representation method are determined from the plurality of half-storage blocks, and the M first half-storage blocks are distributed on N storage pages.

4. The method according to claim 2, characterized in that, The step of determining the M first half-blocks from the plurality of half-blocks based on the address representation method, the static attributes, and the total number M includes: When the address representation is a distributed clustered list representation, based on the static attribute and the total number M, M first half-storage blocks that match the distributed clustered list representation are determined from the plurality of half-storage blocks, and the M first half-storage blocks correspond to N storage segments.

5. The method according to claim 3, characterized in that, The step of generating N address entries based on the M first half-memory blocks includes: When the address representation method is the physical page representation method, the N address entries are generated based on the starting address of the first first half-block distributed on each of the N storage pages corresponding to the M first half-blocks.

6. The method according to claim 4, characterized in that, The step of generating N address entries based on the M first half-memory blocks includes: When the address representation method is the scattered cluster list representation method, the N address entries are generated based on the starting address of the first first half storage block in each of the N storage segments corresponding to the M first half storage blocks, and the data length of at least one first half storage block included in each storage segment.

7. The method according to claim 1, characterized in that, Determining at least one address identifier based on the N and the addresses of the N address entries includes: When the address representation method is the physical page representation method, and N is less than or equal to the first value, the at least one address identifier is determined based on the address corresponding to each of the N address entries, and the at least one address identifier includes the address corresponding to each of the N address entries.

8. The method according to claim 5, characterized in that, Determining at least one address identifier based on the N and the addresses of the N address entries includes: When the address representation is the scatter-aggregate list representation and N is greater than the second value, the first storage segment is determined among the plurality of half-storage blocks based on the first static attribute; If the first storage segment can store the N address entries, then the starting address corresponding to the first storage segment is determined as the at least one address identifier; If the first storage segment cannot store the N address entries, then based on the first static attribute, a second storage segment is determined from the plurality of half-storage blocks; If the second storage segment can store the N address entries and the starting address corresponding to the first storage segment, then the starting address corresponding to the second storage segment will be inserted into the last address entry of the first storage segment, and the starting address corresponding to the first storage segment will be determined as the at least one address identifier. If the second storage segment cannot store the N address entries, then the starting address corresponding to the first storage segment is determined as the at least one address identifier, and based on the first static attribute, multiple storage segments are determined in the multiple half-storage blocks until the multiple storage segments can store the N address entries, and the starting address of the next storage segment is stored in the previous storage segment.

9. The method according to claim 8, characterized in that, Determining at least one address identifier based on the N and the addresses of the N address entries includes: When the address representation is the dispersed aggregation list representation and N is less than or equal to the second value, the at least one address identifier is determined based on the address corresponding to each of the N address entries. The at least one address identifier includes the address corresponding to each of the N address entries.

10. The method according to claim 1, characterized in that, The method further includes: After the first transmission transaction is completed, the half-block of storage occupied by the first transmission transaction is released, and the corresponding bits of the half-block of storage occupied by the first transmission transaction are updated.

11. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the simulation stimulus generation method as described in any one of claims 1 to 10 when executing the computer program.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the simulation stimulus generation method as described in any one of claims 1 to 10.

13. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the simulation stimulus generation method as described in any one of claims 1 to 10.

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