A layout legalization method for mixed row height circuit design using legalization framework and bitmaps

Abstract

This invention proposes a layout legalization method for mixed row-height circuit design using a legalization framework and bitmap, relating to the field of mixed row-height circuit design. This invention employs a legalization framework and bitmap data structures to construct the layout legalization of mixed row-height circuits and to perform bitmap representation of the mixed row-height circuits. An algorithm is developed to quickly legalize circuits with complex constraints by searching for placeable positions within the mixed row-height circuit. Furthermore, this method can be improved based on existing algorithms for mixed row-height circuits. It features an algorithm module compatible with most legalization algorithms and provides highly efficient basic operation modules for the algorithm module to call.

Description

Technical Field

[0001] This invention proposes a layout legalization method for hybrid row height circuit design using a legalization framework and bitmap, which relates to the field of hybrid row height circuit design. Background Technology

[0002] In traditional circuits, standard cells are typically designed with the same height for ease of design and optimization. However, with the increasing complexity of modern circuit designs, standard cells have begun to have different heights to better balance power consumption, area, routerbility, and performance. Previous research on hybrid cell height legalization algorithms can be divided into two categories. The first category addresses hybrid cell height legalization problems with only basic constraints, primarily aiming to minimize cell displacement and trace length. These basic constraints include cell overlap, power / ground (VDD / VSS) alignment, and site alignment. However, this category lacks consideration for the additional constraints introduced by advanced technology nodes. The second category considers some additional constraints, such as minimum injection area (MIA), drain-to-drain docking (DDA), routerbility issues, and neighboring diffusion effects (NDE). However, neither category comprehensively addresses all constraints. With increasing design constraint complexity, combining many different design constraints and proposing a single legalization algorithm to solve them becomes nearly impossible. Summary of the Invention

[0003] To address the aforementioned issues, this invention proposes a layout legalization method for mixed-height circuit designs using a legalization framework and bitmap. This method can be used to quickly legalize circuits with mixed-height cells. Based on a bitmap, it can legalize layouts while considering dozens of layout constraints and minimizing cell displacement. Furthermore, this paper proposes an acceleration technique based on interval mapping, which can further speed up the search for legalization locations that do not violate design rules.

[0004] A layout legalization method for hybrid row height circuit design using a legalization framework and bitmap is characterized in that, in the design of the hybrid row height circuit, a bitmap data structure is used to construct the layout legalization of the hybrid row height circuit, and standard cells in the hybrid row height circuit that do not overlap with already placed standard cells or pre-placed obstacles are selected for placement; wherein the steps of the layout legalization method for hybrid row height circuit design using a legalization framework and bitmap include:

[0005] Step 1: Construct a legalization framework for hybrid row height circuit design, including establishing the constraints of the legalization framework for hybrid row height circuit unit design, completing the standardization of hybrid row height circuit to obtain standard units of hybrid row height circuit, and establishing basic operation modules for units that satisfy the legalization framework constraints and complete the standardization of hybrid row height circuit.

[0006] Step 2: Construct a bitmap-based mathematical expression for the mixed row height circuit layout using a bitmap;

[0007] Step 3: Based on the mixed row height circuit after bitmap processing, write the algorithm steps to find the standard cell where it can be placed;

[0008] Step 4: After completing Steps 1, 2, and 3, perform compatibility improvements based on the original algorithm used in the hybrid row height circuit.

[0009] Furthermore, the legitimization framework for constructing the hybrid row height circuit in step 1 includes the following:

[0010] Step 1.1: Establish the constraints of the legalization framework for the hybrid row height circuit design; the constraints of the legalization framework include the following: 1) cells must not overlap, 2) cells must be placed within the chip area, 3) cells must be located in a placeable position on the row, 4) cells must satisfy power / ground alignment constraints, 5) fence area constraints, 6) orientation constraints, and 7) pin mask alignment constraints.

[0011] Furthermore, the standard cell for the hybrid row height circuit obtained by standardizing the hybrid row height circuit in step 1 includes the following:

[0012] Step 1.2: Perform mathematical modeling on the hybrid row height circuit to obtain the global layout mathematical expression C for a hybrid row height circuit with n standard cells:

[0013] C = {c1,...,c} n};

[0014] Where c i This represents a single standard element, each of which has two attributes: coordinates and orientation. The standard element c... i The width, height, initial bottom-left corner coordinates, and single-row height are represented by w. i h i 、(x i ′,y i ′) and H.

[0015] Furthermore, the basic operational modules for constructing cells that satisfy the legalization framework constraints and complete the standardization of hybrid row height circuits in step 1 include the following:

[0016] Step 1.3: Cell operations for non-standardized mixed-row-height circuits include cell movement, cell merging, cell separation, and cell deformation; after standardizing the mixed-row-height circuit, the basic operation module includes the following:

[0017] Standardized movement of standard units: This includes the following:

[0018] A1. Move to the right: Given a coordinate, maximum displacement, and standard element c. i The goal is to place the standard cell in the nearest valid position on the right side of the coordinate system.

[0019] A2. Move to the left: Given a coordinate, maximum displacement, and standard element c. i The goal is to place the standard cell in the nearest valid position on the left side of the coordinate system.

[0020] A3. Same-line movement: Given a coordinate system, maximum displacement, and standard element c. i The goal is to place the standard cell in the nearest valid position on the same row of coordinates;

[0021] A4. Circumferential Movement: Given a coordinate system, maximum displacement, and standard element c. i The goal is to place the standard cell in the nearest valid location to the coordinates;

[0022] Standard unit c i Standardized merging and separation: Creating directed connections between cells of a mixed row height circuit with two different coordinates;

[0023] Standard unit c i Standardized variations include swapping the coordinates of cells in two mixed row height circuits, flipping cells in a mixed row height circuit, and extending cells in a mixed row height circuit.

[0024] Furthermore, the mathematical expression for constructing the hybrid row height circuit layout in step 2 includes the following:

[0025] Step 2.1: The layout legalization region of the hybrid row height circuit under the legalization framework consists of rows, and each row consists of many sites; the layout legalization region is defined as a grid, with all standard cells c i All elements must be positioned on the grid after the layout is completed;

[0026] Step 2.2: Use a bitmap data structure to represent the two-dimensional grid of the layout legalization region of the hybrid row height circuit under the legalization framework; use one bit to indicate whether the site is included by the standard cell c. i Sites are marked as occupied, with unoccupied sites marked as 0 and occupied sites marked as 1.

[0027] Construct a bitmap with n rows and m columns, where the mathematical notation for a bitmap in programming is defined as bitmap. In this bitmap, each cell of a mixed row-height circuit is represented by one bit. The mathematical expression for the bitmap of a mixed row-height circuit is as follows:

[0028]

[0029] Where z represents the total number of units, P k cell k The set of the coordinates of the four corners, (x ij ,y ij ) represents site ij The coordinates of the lower left corner, w ij and h ij These represent the site. ij Width and height;

[0030] The mathematical expression for the bitmap of a hybrid row height circuit is applicable not only to hybrid row height circuits with a single row height, but also to hybrid row height circuits with multiple row heights.

[0031] Furthermore, step 3, based on the hybrid row height circuit algorithm after bitmap processing, includes the following:

[0032] Step 3.1.1: Establish a standard element displacement algorithm; taking rightward displacement as an example, define the initial position (x', y') and the standard element c. i Width w, maximum displacement d max 、line r j The x-coordinate of the right boundary of the map r Site width w site ;

[0033] Step 3.1.2: To ensure the standard unit c i Define the maximum displacement d without exceeding the chip area. max The program expression is:

[0034] d max =min(d max ,x r -x'-w);

[0035] Step 3.1.3: Place the standard unit c i With line r j Align with the nearest site (x', y);

[0036] Step 3.1.4: Traverse coordinates between x' and x'+d max The site between the site and the standard unit ci When there is no overlap, call the function isPlaceable(c i ,x site ,y),

[0037] The isPlaceAble function is an interface provided by the design rule checking module. The isPlaceAble function calls the various design constraint checking functions encapsulated in the design rule checking module to determine whether the coordinates of the site meet the constraints under the legalization framework. If the constraints under the legalization framework are met, the nearest placeable position (x, y) is output.

[0038] Furthermore, step 3, based on the hybrid row height circuit algorithm after bitmap processing, includes the following:

[0039] Step 3.2.1: Initialize the function bitOr, which converts a multi-row bitmap into a single-row bitmap using a bitwise OR operation;

[0040] Step 3.2.2: Use n0 and n1 to record the number of leading consecutive 0 bits and 1 bits of the bitmap, respectively;

[0041] Step 3.2.3: Calculate the number of consecutive leading bits using the function getLeadingOneBitNum, and set them all to 0 using the function setLeadingZero;

[0042] Step 3.2.4: After completing step 3.2.3, calculate the number of leading consecutive 0 bits using the getLeadingZeroBitNum function, and set them all to 1 using the setLeadingOne function;

[0043] Step 3.2.5: The loop ends when n0-n1≥w, resulting in the first unit with a quantity greater than or equal to the standard unit c. i Find the consecutive 0 bits of width w, i.e., find the standard cell c that is multiple times the row height. i The right side is a standard placement location where it will not overlap with other units or obstacles.

[0044] Furthermore, the compatibility improvement operation in step 4 based on the original algorithm used in the hybrid row height circuit includes the following:

[0045] When the mixed row height circuit design uses the Abacus algorithm, the Abacus algorithm takes the PlaceRow function as its core and implements the function's functionality through the row-shifting, right-shifting, and merging operations in the combination operation module.

[0046] When the legalization of a mixed-row height circuit design is performed using the Tetris algorithm, the Tetris algorithm is implemented by calling the four-way shift function of the basic operation module.

[0047] In addition to using bitmaps for hybrid row height circuit design, an IntervalMap data structure is added to speed up the search for placeable cell locations.

[0048] The present invention has the following advantages:

[0049] 1) This method can be used to quickly legalize circuits with mixed-height cells. Based on bitmaps, it can legalize layouts while minimizing cell displacements, taking into account dozens of layout constraints.

[0050] 2) Significantly reduce the time required to search for the placement of cells when considering these design rules. Attached Figure Description

[0051] Figure 1 This is a flowchart of the algorithm system of the present invention.

[0052] Figure 2 This is a schematic diagram illustrating the legal framework of the present invention.

[0053] Figure 3 This is an example diagram of the mixed height unit represented by a bitmap according to the present invention.

[0054] Figure 4 This is an example diagram of a double row height cell represented by a bitmap according to the present invention. Detailed Implementation

[0055] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings.

[0056] like Figure 1 As shown, a layout legalization method for hybrid row height circuit design using a legalization framework and bitmap includes the following steps:

[0057] Step 1: Construct a legalization framework for hybrid row height circuit design, including establishing the constraints of the legalization framework for hybrid row height circuit unit design, completing the standardization of hybrid row height circuit to obtain standard units of hybrid row height circuit, and establishing basic operation modules for units that satisfy the legalization framework constraints and complete the standardization of hybrid row height circuit.

[0058] Step 2: Construct a bitmap-based mathematical expression for the mixed row height circuit layout using a bitmap;

[0059] Step 3: Based on the mixed row height circuit after bitmap processing, write the algorithm steps to find the standard cell where it can be placed;

[0060] Step 4: After completing steps 1, 2, and 3, perform compatibility improvements based on the original algorithm used in the hybrid row height circuit, and use acceleration technology to speed up the search for placeable locations.

[0061] like Figure 2 As shown in the embodiments of the present invention, the top-level module in the legalization framework is the legalization algorithm module. Since the legalization algorithm module is decoupled from the design rule checking module, it has strong compatibility and can port many classic legalization algorithms, such as Abacus, Tetris, MGL, and MrDP, to this module. This module adjusts the legalization order of cells, minimizes cell displacement, optimizes line length, and calculates cell layout costs based on the legalization algorithm used. When it is necessary to enhance the algorithm or use a better legalization algorithm, this module can be easily modified.

[0062] The basic operation module decouples the design rule checking module from the algorithm module. When designing the legalization algorithm, there is no need to consider how to check the design rules; it is only necessary to call the basic operation module to implement various operations on the units. This is because the basic operation module provided by this invention automatically calls the design rule checking module to determine whether the operation violates a certain design rule. If a design rule violation is found, the basic operation module will cancel the operation and continue to find the next position through the calculation method of the legalization algorithm used.

[0063] In embodiments of the present invention, the middle-level module of the legalization framework is the basic operation module, which can be called by the top-level legalization algorithm module. Almost all legalization algorithms can be implemented by calling the basic operation module. The basic operations provided by this module will be described in detail below:

[0064] a) Movement: The basic operation module includes four types of movement unit operations, each with different search ranges and directions. To avoid large displacements of units during the legalization process, the maximum range of possible placement locations searched by these four movement operations can be limited in practice. These four movement operations can meet the needs of most algorithms for movement units. These four movement operations are described below:

[0065] a.1) Move to the right (placeRight): Given a coordinate (x, y) and a maximum displacement d max and standard unit c i The goal is to make the standard unit c i Place it at the nearest valid position to the right of coordinates (x, y).

[0066] a.2) Move left (placeLeft): Given a coordinate (x, y) and a maximum displacement dmax and standard unit c i The goal is to make the standard unit c i Place it at the nearest valid position to the left of coordinates (x, y).

[0067] a.3) Place X: Given a coordinate (x, y), the maximum displacement d max and standard unit c i The goal is to make the standard unit c i Place it at the nearest valid position on the same row as the coordinates (x, y).

[0068] a.4) Place Around: Given a coordinate (x, y), the maximum displacement d max and standard unit c i The goal is to make the standard unit c i Place it at the nearest valid position to the coordinates (x, y).

[0069] Algorithm 1 illustrates the implementation details of the right-moving algorithm. Line 1 ensures the cell doesn't exceed the chip area, and line 2 ensures the cell is located at a placeable site on the row. Lines 3-9 search to the right from the cell's starting position to find the nearest placeable location. Line 3 iterates through coordinates between x' and x'+d. max The function `isPlaceable(c)` will be called in line 4 to ensure that placing items on these sites will not cause any overlap. i ,x site ,y), this is an interface provided by the design rule checking module, which can determine whether the location meets all considered design rules and constraints. Once the standard element c i If a cell can be placed in its current position, the rightward movement algorithm will report the position to the top-level legalization algorithm module. The top-level module will then decide whether to place the cell in that position based on the algorithm used.

[0070]

[0071] Moving to the left is implemented similarly to moving to the right, differing only in the search direction. Moving within the same row can be achieved by alternately calling move to the right and move to the left, typically requiring restrictions on the search range of each movement. Moving to all four directions can be achieved by calling move to the same row.

[0072] The basic operation module will query the design rule check module to understand whether the found location violates the considered design rules.

[0073] b) Merging and Separating

[0074] Some algorithms, such as Abacus, require the ability to create directed connections between two objects (cells or clusters), where the coordinates of one object are determined by the coordinates of the other. Therefore, a merge operation is provided in the basic operations module to achieve this functionality. If, after the merge operation, the design rule checking module determines that an illegal layout has occurred, the basic operations module also provides a detach operation for the algorithm module to call to undo the merge.

[0075] c) Flipping, swapping, and extending

[0076] Because elements have both coordinate and orientation attributes, some design rule violations can be resolved by flipping elements; therefore, element movement alone is insufficient. Thus, the basic operation module provides a flipping operation. Furthermore, some legalization algorithms optimize maximum displacement, line length, etc., by swapping elements, while others handle certain design rule violations. Therefore, the basic operation module provided in this invention also provides a swapping operation. Since some specific design rules, such as minimum implantation area (MIA) constraints, can be satisfied by extending elements, the basic operation module provided in this invention also introduces an extension operation.

[0077] In embodiments of the present invention, the underlying module of the legalization framework is a design rule checking module. The basic operation module can access the design rule checking module to determine whether a new position or orientation to be assigned to a cell will violate certain design rules that need to be considered. If the design rule checking module determines that the operation of the basic operation module will trigger a design rule violation, then the basic operation module will cancel the operation and continue searching for the next possible position for the target cell; otherwise, the basic operation module will complete the operation.

[0078] Figure 3 An example of using a bitmap to represent a layout is shown. Each grid in the diagram represents a site; unoccupied sites are marked as 0, and occupied sites are marked as 1. This invention provides a method where obstacles, fixed macrocells, and other similar areas are marked as 1 during the preprocessing stage. During the validation process, when a cell finds a placeable location, that location is marked as 1.

[0079] Based on bitmaps, this invention provides a way to quickly identify placement locations for units of various heights that do not overlap with other placed units or obstacles. Figure 4 This invention demonstrates a method for applying a bitmap to a double-row-height cell. Based on the starting position and height of the target cell, the invention provides a method to obtain a two-row bitmap, which is then converted into a single-row bitmap via a bitwise OR operation. Assuming the target cell has a width of 2 sites, then... Figure 4The yellow position represents the nearest non-overlapping location to the right of the target cell. If the yellow position violates other design rules, the search will continue to the right for the next non-overlapping location. Figure 4 The green area in the text. Other height cells are handled similarly to double-height cells.

[0080] Algorithm 2 provides a method for quickly implementing the above operations. In line 2, this invention provides the use of the function `bitOr` to convert a multi-row bitmap into a single-row bitmap through a bitwise OR operation. Lines 3-8 continuously search for a number of elements greater than or equal to the standard cell `c`. i Similarly, this invention provides methods to record the number of leading consecutive 0 bits and 1 bits of the bitmap bm using n0 and n1, respectively. In line 4, this invention provides a method to calculate the number of leading consecutive 1 bits using the function getLeadingOneBitNum, and then set them all to 0 using the function setLeadingZero in line 5. Then, in line 6, the number of leading consecutive 0 bits is calculated using the function getLeadingZeroBitNum, and then set them all to 1 using the function setLeadingOne in line 7. The loop ends when n0 - n1 ≥ w, which means that the first unit with a quantity greater than or equal to c has been found. i A series of consecutive 0 bits of width w, i.e., multiple times the row height unit c i The nearest position on the right that will not overlap with other units or obstacles. This invention provides a method to calculate the number of consecutive leading 0 bits and 1 bits in O(1) time using a built-in function. Therefore, this invention provides a method to quickly find the nearest non-overlapping position on the right side of the target unit using Algorithm 2.

[0081]

[0082] In one embodiment of the invention, Algorithm 3 details how the classic Abacus algorithm is run through a framework. The PlaceRow function is the core of the Abacus algorithm, and its functionality can be achieved by combining the same-line move (placeX), right move (placeRight), and merge operations in the operation module. In line 17, if cell c... i Since the cluster C on the far right of the current cell's row does not overlap, this invention provides a method to find the nearest valid position in that row using a row-shift function. In rows 19-21, the standard cell c... i With standard unit c iThe rightmost cluster C in the current row is merged, and the coordinates of the new cluster are calculated according to the method provided in the Abacus algorithm. If the new coordinates violate the design constraints, the merging is undone using the split operation of the basic operation module, and then the rightward shift function is used to continue searching for the next nearest legal position to the right.

[0083]

[0084] In one embodiment of the present invention, when the legalization of the hybrid row height circuit design is carried out using the Tetris algorithm, the Tetris algorithm is implemented by calling the four-way shift function of the basic operation module.

[0085]

[0086] In embodiments of this invention, to further accelerate the search for legal locations without violating design rules, this invention provides a data structure called Interval Map. This structure significantly reduces the search space of the hybrid row height circuit algorithm, thereby enabling the finding of the nearest feasible solution more quickly. Furthermore, the Interval Map proposed in this invention pre-considers design rules associated with continuous intervals, which reduces the number of rules that must be considered during the placement operation.

[0087] Interval Map is a data structure graph created based on the rows of a bitmap-based hybrid row-height circuit. It represents a region that is impossible to place standard cells. This region corresponds to an interval on the row of the hybrid row-height circuit and will be removed from the data structure graph of Interval Map.

[0088] By utilizing interval mapping, this invention provides a method to obtain intervals corresponding to specific positions using a binary search algorithm during the layout phase. It is important to note that not all intervals in the interval mapping represent valid positions, but it guarantees that positions not within any interval of the interval graph are invalid. Therefore, this invention provides a method to skip these regions and search for valid positions only within the remaining intervals of the interval graph.

[0089] The present invention has the following advantages:

[0090] 1) A legalization framework with strong compatibility and scalability with existing legalization algorithms is proposed. This invention provides a complete basic operation module that decouples the legalization algorithm module and the design rule checking module, making it easier to apply different legalization algorithms to the framework provided by this invention when considering multiple complex design rules.

[0091] 2) Simultaneously, to significantly reduce the search time required to find placeable locations in the basic operation module, this invention provides an innovative acceleration technology that can substantially reduce the time required to search for placeable locations of units in the basic operation module. In practical circuit design, the framework provided by this invention can be used to apply more legalization algorithms to the placement stage. In summary, the compatibility and scalability of this invention's framework make it an efficient solution to various legalization problems in electronic design automation.

[0092] The above are preferred embodiments of the present invention. Any changes made to the technical solution of the present invention that do not exceed the scope of the technical solution of the present invention shall fall within the protection scope of the present invention.

Claims

1. A layout legalization method for hybrid row height circuit design using a legalization framework and bitmap, characterized in that, In the design of hybrid row height circuits, a legalization framework and bitmap data structure are used to construct the hybrid row height circuit through layout legalization and to perform bitmap transformation on the hybrid row height circuit. An algorithm for searching for placeable positions in the hybrid row height circuit is written. The steps of the layout legalization method for hybrid row height circuit design using a legalization framework and bitmap include: Step 1: Construct a legalization framework for hybrid row height circuit design, including establishing the constraints of the legalization framework for hybrid row height circuit unit design, completing the standardization of hybrid row height circuit to obtain standard units of hybrid row height circuit, and establishing basic operation modules for units that satisfy the legalization framework constraints and complete the standardization of hybrid row height circuit. Step 2: Construct a bitmap-based mathematical expression for the mixed row height circuit layout using a bitmap; Step 3: Based on the mixed row height circuit after bitmap processing, write the algorithm steps to find the placeable positions of the standard cells; Step 4: After completing steps 1, 2, and 3, perform compatibility improvements based on the original algorithm used in the hybrid row height circuit, and use acceleration techniques to speed up the search for placeable locations. The mathematical expression for the bitmap-based construction of the hybrid row height circuit layout in step 2 includes the following: Step 2.1: The layout legalization region of the hybrid row height circuit under the legalization framework consists of rows, and each row consists of many sites; the layout legalization region is defined as a grid, with all standard cells c i All elements must be positioned on the grid after the layout is completed; Step 2.2: Use a bitmap data structure to represent the two-dimensional grid of the layout legalization region of the hybrid row height circuit under the legalization framework; use one bit to indicate whether the site is included by the standard cell c. i Sites are marked as occupied, with unoccupied sites marked as 0 and occupied sites marked as 1. Construct a bitmap with n rows and m columns, where the mathematical notation for a bitmap in programming is defined as bitmap. In this bitmap, each cell of a mixed row-height circuit is represented by one bit. The mathematical expression for the bitmap of a mixed row-height circuit is as follows: ； ； Where z represents the total number of units, P k cell k The set of coordinates of the four corners, site ij The coordinates of the lower left corner, w ij and h ij These represent the site. ij Width and height; The mathematical expression for the bitmap of a hybrid row height circuit is applicable not only to hybrid row height circuits with a single row height, but also to hybrid row height circuits with multiple row heights.

2. The layout legalization method for hybrid row height circuit design using a legalization framework and bitmap as described in claim 1, characterized in that, The legitimation framework for constructing the hybrid row height circuit in step 1 includes the following: Step 1.1: Establish the constraints of the legalization framework for the hybrid row height circuit design; the constraints of the legalization framework include the following: 1) cells must not overlap, 2) cells must be placed within the chip area, 3) cells must be located in a placeable position on the row, 4) cells must satisfy power / ground alignment constraints, 5) fence area constraints, 6) orientation constraints, and 7) pin mask alignment constraints.

3. The layout legalization method for hybrid row height circuit design using a legalization framework and bitmap as described in claim 2, characterized in that, Step 1, which completes the standardization of the hybrid row height circuit, yields the following standard cells for the hybrid row height circuit: Step 1.2: Perform mathematical modeling on the hybrid row height circuit to obtain the global layout mathematical expression C for a hybrid row height circuit with n standard cells: ； Where c i This represents a single standard element, each of which has two attributes: coordinates and orientation. The standard element c... i The width, height, initial bottom-left corner coordinates, and single-row height are represented by w. i h i , And H.

4. The layout legalization method for hybrid row height circuit design using a legalization framework and bitmap as described in claim 3, characterized in that, The basic operational modules for constructing cells that satisfy the legalization framework constraints and complete the standardization of hybrid row height circuits in step 1 include the following: Step 1.3: Cell operations for non-standardized mixed-row-height circuits include cell movement, cell merging, cell separation, and cell deformation; after standardizing the mixed-row-height circuit, the basic operation module includes the following: Standardized movement of standard units: This includes the following: A1. Move to the right: Given a coordinate, maximum displacement, and standard element c. i The goal is to place the standard cell in the nearest valid position on the right side of the coordinate system. A2. Move to the left: Given a coordinate, maximum displacement, and standard element c. i The goal is to place the standard cell in the nearest valid position on the left side of the coordinate system. A3. Same-line movement: Given a coordinate system, maximum displacement, and standard element c. i The goal is to place the standard cell in the nearest valid position on the same row of coordinates; A4. Circumferential Movement: Given a coordinate system, maximum displacement, and standard element c. i The goal is to place the standard cell in the nearest valid location to the coordinates; Standard unit c i Standardized merging and separation: Creating directed connections between cells of a mixed row height circuit with two different coordinates; Standard unit c i Standardized variations include swapping the coordinates of cells in two mixed row height circuits, flipping cells in a mixed row height circuit, and extending cells in a mixed row height circuit.

5. The layout legalization method for hybrid row height circuit design using a legalization framework and bitmap as described in claim 4, characterized in that, Step 3, based on the hybrid row height circuit algorithm after bitmap processing, includes the following: Step 3.1.1: Establish the standard element displacement algorithm; define the initial position. Standard unit c i Width w, maximum displacement d max 、line r j The x-coordinate of the right boundary of the bitmap r Site width w site ; Step 3.1.2: To ensure the standard unit c i Define the maximum displacement d without exceeding the chip area. max The program expression is: ； Step 3.1.3: Place the standard unit c i With line r j Go to the nearest site Alignment; Step 3.1.4: Traverse coordinates at... and The site between the site and the standard unit c i Call the function when there is no overlap. , The `isPlaceable` function is an interface provided by the design rule checking module. It calls various design constraint checking functions encapsulated in the module to determine whether the coordinates of the site satisfy the constraints under the legalization framework. If they do, it outputs the nearest available placement location. .

6. The layout legalization method for hybrid row height circuit design using a legalization framework and bitmap as described in claim 5, characterized in that, Step 3, which involves validating the mixed row height circuit after bitmap processing, includes the following algorithm: Step 3.2.1: Initialize the function bitOr, which converts a multi-row bitmap into a single-row bitmap using a bitwise OR operation; Step 3.2.2: Use n0 and n1 to record the number of leading consecutive 0 bits and 1 bits of the bitmap, respectively; Step 3.2.3: Calculate the number of consecutive leading bits using the function getLeadingOneBitNum, and set them all to 0 using the function setLeadingZero; Step 3.2.4: After completing step 3.2.3, calculate the number of leading consecutive 0 bits using the getLeadingZeroBitNum function, and set them all to 1 using the setLeadingOne function; Step 3.2.5: When When the loop ends, the first number of units greater than or equal to the standard unit c is obtained. i A series of consecutive zero bits of width w yields a standard cell c with multiple row heights. i The right side will not be different from other standard units c i Placement locations that overlap with obstacles.

7. The layout legalization method for hybrid row height circuit design using a legalization framework and bitmap as described in claim 6, characterized in that, Step 4, which involves compatibility improvements based on the original algorithm used in the hybrid row height circuit, includes the following: When the legalization of mixed row height circuit design adopts the Abacus algorithm, the Abacus algorithm realizes its own functions through the row shift, right shift and merge operations in the basic operation module.

8. The layout legalization method for hybrid row height circuit design using a legalization framework and bitmap as described in claim 7, characterized in that, Step 4, which involves compatibility improvements based on the original algorithm used in the hybrid row height circuit, includes the following: When the legalization of mixed-row height circuit design adopts the Tetris algorithm, the Tetris algorithm realizes its own function by calling the four-way shift function of the basic operation module.

9. The layout legalization method for hybrid row height circuit design using a legalization framework and bitmap as described in claim 1, characterized in that, The technical methods for speeding up the search for standard cells that can be placed in step 4 also include adding a data structure for interval mapping.

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