Graph arrangement optimization algorithm and system, equipment and storage medium

Abstract

A graph arrangement optimization algorithm and system, device and storage medium, the algorithm comprising: repeatedly performing a graph arrangement assignment operation algorithm for multiple times, the graph arrangement assignment operation algorithm comprising: selecting any cross point for placing a graph, and changing an initial value of the cross point for placing the graph into a first assignment; obtaining a graph forbidding area surrounding the graph, and changing an initial value of an intersection point in the graph forbidding area into a second assignment value; and selecting any cross point at the periphery of the graph prohibited area, and using the selected cross point at the periphery of the graph prohibited area as a cross point for placing the graph in the next graph arrangement assignment operation algorithm until the initial values are all changed into the first assignment value and the second assignment value. According to the arrangement condition of the first assignment value and the second assignment value in the two-dimensional grid, the optimal arrangement of the graph in the two-dimensional grid is obtained, so that the accuracy and the reliability are improved for the performance improvement of a subsequently formed semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and particularly to a graphic arrangement optimization algorithm, system, device, and storage medium. Background Art

[0002] In the development process of semiconductor technology, as the technology node continues to advance. As the number of transistors increases and the critical dimension continues to shrink, the contact resistance increases in the overall device resistance ratio, and the high resistance of the middle-section metal connection will directly affect the device performance. The via layer is generally used for device connection and metal connection. The factors affecting the conductor resistance size include material, length, cross-sectional area, and temperature. When the connection material, temperature, and length are fixed, the larger the cross-sectional area, the smaller the resistance value.

[0003] The placement position of the interconnection via is affected by the upper and lower layer environments and has a direct relationship with the width and spacing of the upper and lower layers. Therefore, the resistance value of the interconnection via is positively correlated with the cross-sectional area and placement density of the via itself. However, the via spacing is also limited by the lithography technology process capabilities.

[0004] However, currently, how to make the most efficient use of the area within a limited area is very crucial. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a graphic arrangement optimization algorithm, system, device, and storage medium to improve the efficiency of the semiconductor manufacturing process.

[0006] To solve the above problems, embodiments of the present invention provide a graphic arrangement optimization algorithm, including: establishing a two-dimensional grid, the two-dimensional grid includes a plurality of first grid lines extending along a first direction and a plurality of second grid lines extending along a second direction, the first direction is perpendicular to the second direction, and the first grid lines and the second grid lines intersect pairwise to form intersection points; performing a first assignment process on the intersection points, and using the assignment of the intersection points as the initial value; repeating the graphic arrangement assignment operation algorithm multiple times, the graphic arrangement assignment operation algorithm includes: selecting any intersection point for placing a graphic, and changing the initial value of the intersection point where the graphic is placed to the first assignment; obtaining the graphic prohibited area surrounding the graphic, and changing the initial value of the intersection points located within the graphic prohibited area to the second assignment; selecting any intersection point outside the graphic prohibited area, and the selected intersection point outside the graphic prohibited area is used as the intersection point for placing a graphic in the subsequent graphic arrangement assignment operation algorithm until all the initial values are changed to the first assignment and the second assignment; obtaining the optimal arrangement of the graphic in the two-dimensional grid according to the arrangement of the first assignment and the second assignment in the two-dimensional grid.

[0007] Optionally, the steps of establishing a two-dimensional network include: providing a design mask layout, the design mask layout including a plurality of first metal line patterns extending along a first direction and a plurality of second metal line patterns extending along a second direction, the first direction being perpendicular to the second direction, and the first metal line patterns and the second metal line patterns being orthogonal to each other in pairs; according to the design mask layout, drawing a two-dimensional grid having first grid lines and second grid lines, the first grid lines corresponding one-to-one to the center lines of the first metal line patterns in the first direction, and the second grid lines corresponding one-to-one to the center lines of the second metal line patterns in the second direction.

[0008] Optionally, the algorithm for performing a first assignment process on the intersections includes: selecting intersections where a pattern can be placed and assigning the intersections where a pattern can be placed with a first initial value; selecting intersections where a pattern cannot be placed and assigning the intersections where a pattern cannot be placed with a second initial value, the first initial value and the second initial value constituting the initial values; in the step of changing the initial value of the intersections within the pattern prohibited area to a second assignment, the second assignment is the same as the second initial value.

[0009] Optionally, in the algorithm for performing the first pattern arrangement assignment operation, the step of selecting any intersection for placing a pattern includes: selecting the intersections at the corners of the two-dimensional grid for placing a pattern.

[0010] Optionally, the algorithm for obtaining the pattern prohibited area surrounding the pattern includes: obtaining a first prohibited value between the pattern and each intersection in the first direction; obtaining a second prohibited value between the pattern and each intersection in the second direction; obtaining a third prohibited value between the pattern and each intersection in its diagonal direction.

[0011] Optionally, during the process of selecting any intersection for placing a pattern, the pattern has a first ideal spacing value in the first direction, a second ideal spacing value in the second direction, and a third ideal spacing value in the diagonal direction of the pattern; the algorithm for changing the initial value of the intersections within the pattern prohibited area to a second assignment includes: comparing a plurality of the first prohibited values with the first ideal spacing value, and when the first prohibited value is less than the first ideal spacing value, changing the initial value of the intersection corresponding to the first prohibited value to the second assignment; comparing a plurality of the second prohibited values with the second ideal spacing value, and when the second prohibited value is less than the second ideal spacing value, changing the initial value of the intersection corresponding to the second prohibited value to the second assignment; comparing a plurality of the third prohibited values with the third ideal spacing value, and when the third prohibited value is less than the third ideal spacing value, changing the initial value of the intersection corresponding to the third prohibited value to the second assignment.

[0012] Optionally, obtain the first no-placement value X = S between the figure and each intersection point in the first direction x - 2B x + n*a; where S x represents the distance between the second grid line where the figure is located and other second grid lines, B x represents the etching deviation value of the figure in the first direction, a represents the figure size floating value, n represents a natural number; obtain the second no-placement value Y = Sy - 2By + n*a between the figure and each intersection point in the second direction; where Sy represents the distance between the first grid line where the figure is located and other first grid lines, By represents the etching deviation value of the figure in the second direction, a represents the figure size floating value, n represents a natural number; obtain the third no-placement value between the figure and each intersection point in its diagonal direction where X represents the first no-placement value and Y represents the second no-placement value.

[0013] Optionally, the algorithm for selecting any intersection point outside the no-placement area of the figure includes: selecting the intersection point closest to the intersection point where the figure is placed outside the no-placement area of the figure, and using this intersection point as the intersection point for placing the figure in the subsequent figure arrangement assignment algorithm.

[0014] Optionally, the figure includes an interconnected via pattern.

[0015] Correspondingly, an embodiment of the present invention further provides a figure arrangement optimization algorithm system, including: a building module for building a two-dimensional grid, the two-dimensional grid including a plurality of first grid lines extending in the first direction and a plurality of second grid lines extending in the second direction, the first direction being perpendicular to the second direction, and the first grid lines and the second grid lines intersecting pairwise to form intersection points; a first assignment module for performing a first assignment process on the intersection points and using the assignment of the intersection points as the initial value; a figure arrangement assignment operation algorithm module for repeating the figure arrangement assignment operation algorithm multiple times, the figure arrangement assignment operation algorithm including: selecting any intersection point for placing the figure and changing the initial value of the intersection point where the figure is placed to the first assignment; obtaining the figure no-placement area surrounding the figure and changing the initial value of the intersection points located within the figure no-placement area to the second assignment; selecting any intersection point outside the figure no-placement area, and the selected intersection point outside the figure no-placement area is used as the intersection point for placing the figure in the subsequent figure arrangement assignment operation algorithm until all the initial values are changed to the first assignment and the second assignment; an obtaining module for obtaining the optimal arrangement of the figure in the two-dimensional grid according to the arrangement of the first assignment and the second assignment in the two-dimensional grid.

[0016] Optionally, the establishing module includes: a providing unit configured to design a mask layout, the mask layout including a plurality of first metal lines extending along a first direction and a plurality of second metal lines extending along a second direction, the first direction being perpendicular to the second direction, and the first metal lines and the second metal lines being orthogonal to each other in pairs; a drawing unit configured to draw a two-dimensional grid having first grid lines and second grid lines according to the designed mask layout, the first grid lines corresponding one-to-one to the center lines of the first metal lines in the first direction, and the second grid lines corresponding one-to-one to the center lines of the second metal lines in the second direction.

[0017] Optionally, the first assignment module includes: a first assignment unit configured to select intersection points where a graphic can be placed and assign a first initial value to the intersection points where the graphic can be placed; a second assignment unit configured to select intersection points where a graphic cannot be placed and assign a second initial value to the intersection points where the graphic cannot be placed, the first initial value and the second initial value constituting an initial value; the second assignment in the graphic arrangement assignment operation algorithm module being the same as the second initial value.

[0018] Optionally, the graphic arrangement assignment operation algorithm module includes: a corner selection unit configured to select intersection points at corners in the two-dimensional grid for placing a graphic.

[0019] Optionally, the graphic arrangement assignment operation algorithm module includes: a first obtaining unit configured to obtain a first non-placement value between the graphic and each intersection point in the first direction; a second obtaining unit configured to obtain a second non-placement value between the graphic and each intersection point in the second direction; a third obtaining unit configured to obtain a third non-placement value between the graphic and each intersection point in its diagonal direction.

[0020] Optionally, the graphic arrangement assignment operation algorithm module includes: a first comparison unit configured to compare a plurality of the first non-placement values with the first ideal spacing value, and when the first non-placement value is less than the first ideal spacing value, change the initial value of the intersection point corresponding to the first non-placement value to a second assignment; a second comparison unit configured to compare a plurality of the second non-placement values with the second ideal spacing value, and when the second non-placement value is less than the second ideal spacing value, change the initial value of the intersection point corresponding to the second non-placement value to a second assignment; a third comparison unit configured to compare a plurality of the third non-placement values with the third ideal spacing value, and when the third non-placement value is less than the third ideal spacing value, change the initial value of the intersection point corresponding to the third non-placement value to a second assignment.

[0021] Correspondingly, an embodiment of the present invention further provides a device, including at least one memory and at least one processor. The memory stores one or more computer instructions. Among them, the one or more computer instructions are executed by the processor to implement the graphic layout optimization algorithm provided by the embodiment of the present invention.

[0022] Correspondingly, an embodiment of the present invention further provides a storage medium. The storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the optical proximity correction method provided by the embodiment of the present invention.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0024] The embodiment of the present invention provides a graphic layout optimization algorithm, which repeatedly performs a graphic layout assignment operation algorithm. The graphic layout assignment operation algorithm includes: selecting any intersection point to place a graphic, and changing the initial value of the intersection point where the graphic is placed to the first assignment; obtaining the graphic prohibited placement area surrounding the graphic, and changing the initial value of the intersection points located in the graphic prohibited placement area to the second assignment; selecting any intersection point outside the graphic prohibited placement area, and the selected any intersection point outside the graphic prohibited placement area is used as the intersection point for placing a graphic in the subsequent graphic layout assignment operation algorithm until all the initial values are changed to the first assignment and the second assignment; according to the arrangement of the first assignment and the second assignment in the two-dimensional grid, obtaining the optimal layout of the graphic in the two-dimensional grid. That is to say, a plurality of graphics and the graphic prohibited placement areas surrounding the graphics are set in the limited area surrounded by the two-dimensional grid, so that only the graphics and the graphic prohibited placement areas surrounding the graphics exist in the limited area surrounded by the two-dimensional grid, maximizing the utilization rate of the intersection points for placing graphics in the two-dimensional grid, and obtaining the optimal layout of the graphic in the two-dimensional grid according to the arrangement of the first assignment and the second assignment in the two-dimensional grid, thereby improving the efficiency of the semiconductor manufacturing process and increasing the accuracy and reliability for the performance improvement of the subsequent formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Shows a flowchart of an embodiment of the optical proximity correction method of the present invention;

[0026] Figures 2 to 6 Is a schematic diagram corresponding to each step in an embodiment of the graphic layout optimization algorithm of the present invention;

[0027] Figure 7 Is a functional block diagram of an embodiment of the graphic layout optimization algorithm system of the present invention;

[0028] Figure 8 Is an optional hardware structure diagram of the terminal device provided by the embodiment of the present invention. Detailed implementation manners

[0029] Currently, to reduce the contact resistance between metal lines, increasing the total cross-sectional area of the via holes is a way to reduce the contact area. However, due to process capabilities, the area and placement of the via holes need to be considered simultaneously. Since the process is complex and the total cross-sectional area of the via hole layer needs to be increased as much as possible, currently, multiple departments such as OPC, Litho, ETCH, and design need to modify the layout in multiple rounds until the process capabilities are met, and finally determine the size and placement of the via holes to obtain the final design. During this process, due to repeated adjustments to the design, a large amount of manpower and material resources are consumed, greatly affecting work efficiency.

[0030] To solve the technical problem, an embodiment of the present invention provides a graphic arrangement optimization algorithm. Refer to Figure 1 , which shows a flowchart of an embodiment of the optical proximity correction method of the present invention.

[0031] In this embodiment, the graphic arrangement optimization algorithm includes the following basic steps:

[0032] Step S1: Establish a two-dimensional grid, which includes a plurality of first grid lines extending in a first direction and a plurality of second grid lines extending in a second direction. The first direction is perpendicular to the second direction, and the first grid lines and the second grid lines intersect pairwise to form intersection points;

[0033] Step S2: Perform a first assignment process on the intersection points, and use the assignment of the intersection points as the initial value;

[0034] Step S3: Repeat the graphic arrangement assignment operation algorithm multiple times. The graphic arrangement assignment operation algorithm includes: selecting any intersection point for placing a graphic, and changing the initial value of the intersection point where the graphic is placed to the first assignment; obtaining the graphic prohibited area surrounding the graphic, and changing the initial value of the intersection points within the graphic prohibited area to the second assignment; selecting any intersection point outside the graphic prohibited area, and the selected intersection point outside the graphic prohibited area is used as the intersection point for placing a graphic in the subsequent graphic arrangement assignment operation algorithm until all the initial values are changed to the first assignment and the second assignment;

[0035] Step S4: Obtain the optimal arrangement of the graphic in the two-dimensional grid according to the arrangement of the first assignment and the second assignment in the two-dimensional grid.

[0036] An embodiment of the present invention provides a graphics arrangement optimization algorithm, which repeatedly performs multiple graphics arrangement assignment operation algorithms, and the graphics arrangement assignment operation algorithm includes: selecting any intersection point for placing a graphic, and changing the initial value of the intersection point for placing the graphic to a first assignment; obtaining a graphic forbidden area surrounding the graphic, and changing the initial value of the intersection point located in the graphic forbidden area to a second assignment; selecting any intersection point outside the graphic forbidden area, and any intersection point selected outside the graphic forbidden area is used as an intersection point for placing the graphic in the next graphics arrangement assignment operation algorithm, until all the initial values ​​are changed to the first assignment and the second assignment. ; According to the arrangement of the first assignment and the second assignment in the two-dimensional grid, the optimal arrangement of the graphics in the two-dimensional grid is obtained, that is, a plurality of graphics and a graphic-prohibited area surrounding the graphics are set in a limited area surrounded by the two-dimensional grid, so that there are only graphics and graphic-prohibited areas surrounding the graphics in the limited area surrounded by the two-dimensional grid, so that the utilization rate of the intersections used to place graphics in the two-dimensional grid is maximized, and according to the arrangement of the first assignment and the second assignment in the two-dimensional grid, the optimal arrangement of the graphics in the two-dimensional grid is obtained, thereby improving the efficiency of the semiconductor design process and increasing the accuracy and reliability for the performance improvement of the subsequently formed semiconductor structure.

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figures 2 to 6 It is a schematic diagram corresponding to each step in an embodiment of a graphics arrangement optimization algorithm of the present invention.

[0039] refer to Figures 2 to 3 , execute step S1: establish a two-dimensional grid, the two-dimensional grid includes a plurality of lines along a first direction (such as Figure 3 A first grid line 111 extending in the direction A and a plurality of grid lines extending in the second direction (as shown in FIG. Figure 3 The first direction and the second direction are perpendicular to each other, and the first grid lines 111 and the second grid lines 110 intersect each other to form intersections.

[0040] Specifically, the two-dimensional grid provides a grid diagram for subsequent multiple graphics arrangement assignment operation algorithms. At the same time, the two-dimensional grid has a simple layout and can more intuitively derive the optimal arrangement of graphics in the two-dimensional grid.

[0041] In this embodiment, the step of establishing a two-dimensional grid includes: providing a design mask layout 100, wherein the design mask layout 100 includes a plurality of lines along a first direction (eg Figure 2 A first metal line pattern 102 extending in the direction A and a plurality of metal lines extending in the second direction (as shown in FIG. Figure 2A second metal line pattern 101 extending in the B direction (as shown in the figure), the first direction and the second direction are perpendicular to each other, and the first metal line pattern 102 and the second metal line pattern 101 are orthogonal to each other in pairs; according to the designed mask layout 100, a two-dimensional grid with a first grid line 111 and a second grid line 110 is drawn, and the first grid line 111 corresponds one-to-one with the center line of the first metal line pattern 102 in the first direction, and the second grid line 110 corresponds one-to-one with the center line of the second metal line pattern 101 in the second direction.

[0042] Specifically, the designed mask layout 100 provides a process basis for the formation process of the semiconductor structure, and at the same time, also provides a template for drawing the two-dimensional grid.

[0043] Specifically, and the first metal line pattern 102 and the second metal line pattern 101 are orthogonal to each other in pairs. According to the first metal line pattern 102, a first grid line 111 extending in the first direction is drawn, and according to the second metal line pattern 101, a second grid line 110 extending in the second direction is drawn. Since the first metal line pattern 102 and the second metal line pattern 101 are orthogonal to each other in pairs, the first grid line 111 and the second grid line 110 cross each other in pairs to form intersection points.

[0044] It should be noted that both the first metal line pattern 102 and the second metal line pattern 101 in the designed mask layout 100 have line widths. By making the first grid line 111 correspond one-to-one with the center line of the first metal line pattern 102 in the first direction, and the second grid line 110 correspond one-to-one with the center line of the second metal line pattern 101 in the second direction, the center points of the orthogonal position regions of the first metal line pattern 102 and the second metal line pattern 101 are made to coincide with the intersection points, so that the two-dimensional grid can accurately generate the optimal arrangement of the pattern in the two-dimensional grid.

[0045] Continue to refer to Figure 3 , perform step S2: perform a first assignment process on the intersection points, and use the assignment of the intersection points as the initial value.

[0046] It should be noted that by performing a first assignment process on the intersection points and using the assignment of the intersection points as the initial value, in the subsequent process of performing multiple graphic arrangement assignment operation algorithms, it is possible to more intuitively obtain which intersection points in the two-dimensional grid can place the pattern and which intersection points are the prohibited areas for the pattern (i.e., the areas where the pattern cannot be placed).

[0047] In this embodiment, the algorithm for performing the first assignment process on the intersection points includes: selecting the intersection points where the graphics can be placed, and assigning the intersection points where the graphics can be placed with a first initial value; selecting the intersection points where the graphics cannot be placed, and assigning the intersection points where the graphics cannot be placed with a second initial value, and the first initial value and the second initial value constitute the initial value.

[0048] Specifically, in the process of providing the design mask layout 100, according to the process requirements of the semiconductor structure, some of the first metal line graphics 102 have cuts (i.e., Metal Cut) in the first direction, and some of the second metal line graphics 101 have cuts (i.e., Metal Cut) in the second direction, so that the first metal line graphics 102 and the second metal line graphics 101 with cuts (i.e., Metal Cut) are not orthogonal to each other. Correspondingly, in the process of establishing the two-dimensional grid, the intersection points corresponding to the cuts are all intersection points where the graphics cannot be placed, and the intersection points where the graphics cannot be placed are assigned with a second initial value, and the second initial value can be set to any value or any letter.

[0049] As an example, the second initial value is set to the number "1".

[0050] It should be noted that the intersection points where the graphics can be placed are selected, and the intersection points where the graphics can be placed are assigned with a first initial value, and the first initial value can be set to any value or any letter.

[0051] As an example, the first initial value is set to the number "0".

[0052] It should also be noted that the two-dimensional grid in this embodiment has intersection points corresponding to the cuts. In other embodiments, in the process of providing the design mask layout 100, the first metal line graphics 102 do not have cuts (i.e., Metal Cut) in the first direction, and some of the second metal line graphics 101 do not have cuts (i.e., Metal Cut) in the second direction. Correspondingly, all the intersection points in the two-dimensional grid are intersection points where the graphics can be placed, and all the intersection points in the two-dimensional grid are the first initial value.

[0053] Reference Figures 4 to 5, perform step S3: Repeatedly perform the graphic arrangement assignment operation algorithm multiple times. The graphic arrangement assignment operation algorithm includes: Selecting any intersection point to place the graphic 160, and changing the initial value of the intersection point where the graphic 160 is placed to the first assignment; Obtaining the graphic prohibited placement area surrounding the graphic 160, and changing the initial values of the intersection points within the graphic prohibited placement area to the second assignment; Selecting any intersection point outside the graphic prohibited placement area, and the selected intersection point outside the graphic prohibited placement area is used as the intersection point for placing the graphic 160 in the subsequent graphic arrangement assignment operation algorithm until all the initial values are changed to the first assignment and the second assignment.

[0054] Specifically, selecting any intersection point to place the graphic 160 and changing the initial value of the intersection point where the graphic 160 is placed to the first assignment can distinguish the initial value in the two-dimensional grid from the first assignment, so that the specific intersection points where the graphic 160 is placed and the intersection points where the graphic 160 is not placed can be visually seen.

[0055] As an example, the graphic 160 includes an interconnected via graphic.

[0056] It should be noted that in the process of providing the design mask layout 100, the first metal line graphic 102 is used to form the first metal line, and the second metal line graphic 101 is used to form the second metal line. In the formation process of the semiconductor structure, the first metal line and the second metal line are stacked in upper and lower layers respectively, and the first metal line and the second metal line are electrically connected through interconnected vias. Since the first grid line 111 corresponds to the first metal line and the second grid line 110 corresponds to the second metal line, the intersection point of the first grid line 111 and the second grid line 110 is the electrical connection point between the first metal line and the second metal line. That is to say, the interconnected via graphic needs to be set at the intersection point.

[0057] As an example, the first assignment is "P".

[0058] Specifically, in the formation process of the semiconductor structure, due to the limitation of lithography performance, there is a minimum design rule value between adjacent interconnected via graphics. That is to say, the graphic 160 set at the intersection point has a graphic prohibited placement area, and other interconnected via graphics cannot be placed at the intersection points within the graphic prohibited placement area, reducing the probability of short circuit between adjacent interconnected via graphics.

[0059] In this embodiment, the algorithm for obtaining the graphic prohibited placement area surrounding the graphic 160 includes: Obtaining the first prohibited placement value between the graphic 160 and each intersection point in the first direction; Obtaining the second prohibited placement value between the graphic 160 and each intersection point in the second direction; Obtaining the third prohibited placement value between the graphic 160 and each intersection point in its diagonal direction.

[0060] By obtaining the first prohibited placement value, the second prohibited placement value, and the third prohibited placement value, it is possible to obtain the prohibited placement area of the figure around the figure 160, which is conducive to changing the initial value of the intersection point located within the prohibited placement area of the figure to the second assignment value. At the same time, it also clearly indicates the intersection points in the two-dimensional grid where the figure 160 can still be placed. Furthermore, it can maximize the utilization rate of the intersection points for placing the figure in the two-dimensional grid, and based on the arrangement of the first assignment value and the second assignment value in the two-dimensional grid, obtain the optimal arrangement of the figure in the two-dimensional grid, thereby improving the efficiency of the semiconductor design process and increasing the accuracy and reliability for the performance improvement of the subsequent formed semiconductor structure.

[0061] As an example, to obtain the first prohibited placement value X = S between the figure 160 and each intersection point in the first direction x -2B x +n*a; where S x represents the distance between the second grid line 110 where the figure is located and other second grid lines 110, B x represents the etching deviation value of the figure in the first direction, a represents the figure size floating value, and n represents a natural number.

[0062] As an example, to obtain the second prohibited placement value Y = Sy - 2By + n*a between the figure 160 and each intersection point in the second direction; where Sy represents the distance between the first grid line 111 where the figure is located and other first grid lines 111, By represents the etching deviation value of the figure in the second direction, a represents the figure size floating value, and n represents a natural number.

[0063] As an example, to obtain the third prohibited placement value between the figure 160 and each intersection point in its diagonal direction where X represents the first prohibited placement value and Y represents the second prohibited placement value.

[0064] In this embodiment, in the algorithm for performing the first figure arrangement assignment operation, the step of selecting any intersection point for placing the figure 160 includes: selecting the intersection point at the corner of the two-dimensional grid for placing the figure 160.

[0065] Specifically, by selecting the intersection point at the corner of the two-dimensional grid for placing the figure 160, it is possible to arrange the figure 160 sequentially from the corner of the two-dimensional grid to the central position and the end position, thereby maximizing the utilization rate of the intersection points where the figure 160 can be placed in the two-dimensional grid. Correspondingly, it is also possible to obtain the optimal arrangement of the via holes for interconnecting the first metal line and the second metal line, maximize the total area of the via holes between the first metal line and the second metal line, and thus reduce the contact resistance value between the first metal line and the second metal line.

[0066] In other embodiments, in the algorithm for performing the first graphic arrangement assignment operation, an intersection point at the middle position of the two-dimensional grid can also be selected for placing the graphic.

[0067] It should be noted that during the process of changing the initial value of the intersection point located within the graphic prohibited area to the second assignment, the second assignment is the same as the second initial value.

[0068] Specifically, the second assignment is the same as the second initial value, both representing that the intersection point here cannot place a graphic.

[0069] As an example, the second assignment is "1".

[0070] It should be noted that the graphic 160 has a minimum design rule value (i.e., the first ideal spacing value) in the first direction, a minimum design rule value (i.e., the second ideal spacing value) in the second direction, and a minimum design rule value (i.e., the third ideal spacing value) in the diagonal direction of the graphic 160.

[0071] In this embodiment, during the process of selecting any intersection point for placing the graphic 160, the graphic 160 has a first ideal spacing value in the first direction, a second ideal spacing value in the second direction, and a third ideal spacing value in the diagonal direction of the graphic.

[0072] As an example, the algorithm for changing the initial value of the intersection point located within the graphic prohibited area to the second assignment includes: comparing multiple first prohibited values with the first ideal spacing value, and when the first prohibited value is less than the first ideal spacing value, changing the initial value of the intersection point corresponding to the first prohibited value to the second assignment; comparing multiple second prohibited values with the second ideal spacing value, and when the second prohibited value is less than the second ideal spacing value, changing the initial value of the intersection point corresponding to the second prohibited value to the second assignment; comparing multiple third prohibited values with the third ideal spacing value, and when the third prohibited value is less than the third ideal spacing value, changing the initial value of the intersection point corresponding to the third prohibited value to the second assignment.

[0073] In this embodiment, the algorithm for selecting any intersection point outside the graphic prohibited area includes: selecting the intersection point closest to the intersection point for placing the graphic 160 outside the graphic prohibited area, and using this intersection point as the intersection point for placing the graphic 160 in the subsequent graphic arrangement assignment algorithm.

[0074] Specifically, by selecting the intersection point closest to the intersection point where the pattern is placed from the periphery of the pattern prohibited area for placing the pattern 160, the utilization rate of the intersection points where patterns can be placed in the two-dimensional grid can be maximized. Correspondingly, the optimal arrangement of the mutual connection holes between the first metal line and the second metal line can be obtained, maximizing the total area of the mutual connection holes between the first metal line and the second metal line, and thus reducing the contact resistance value between the first metal line and the second metal line.

[0075] Reference Figure 6 , perform step S4: According to the arrangement of the first assignment and the second assignment in the two-dimensional grid, obtain the optimal arrangement of the pattern 160 in the two-dimensional grid.

[0076] Specifically, according to the arrangement of the first assignment and the second assignment in the two-dimensional grid, obtain the optimal arrangement of the pattern in the two-dimensional grid. Correspondingly, the optimal arrangement of the mutual connection holes between the first metal line and the second metal line can be obtained, maximizing the total area of the mutual connection holes between the first metal line and the second metal line, and thus reducing the contact resistance value between the first metal line and the second metal line, thereby improving the efficiency of the semiconductor design process and increasing the accuracy and reliability for the performance improvement of the subsequent formed semiconductor structure.

[0077] Specifically, the algorithm for obtaining the optimal arrangement of the pattern in the two-dimensional grid includes: the intersection points assigned with "P" in the two-dimensional grid are used to place the pattern, and the intersection points assigned with "1" in the two-dimensional grid are prohibited from placing the pattern.

[0078] Correspondingly, the present invention also provides a pattern arrangement optimization algorithm system. Figure 7 It is a functional block diagram of an embodiment of the pattern arrangement optimization algorithm system of the present invention.

[0079] In this embodiment, the graphic layout optimization algorithm system 300 includes: a building module 301 for building a two-dimensional grid, which includes a plurality of first grid lines extending along a first direction and a plurality of second grid lines extending along a second direction. The first direction is perpendicular to the second direction, and the first grid lines and the second grid lines intersect pairwise to form intersection points; a first assignment module 302 for performing a first assignment process on the intersection points and using the assignment of the intersection points as the initial value; a graphic layout assignment operation algorithm module 303 for repeatedly performing a graphic layout assignment operation algorithm multiple times. The graphic layout assignment operation algorithm includes: selecting any intersection point to place a graphic, and changing the initial value of the intersection point where the graphic is placed to the first assignment; obtaining the graphic prohibited placement area surrounding the graphic, and changing the initial value of the intersection points within the graphic prohibited placement area to the second assignment; selecting any intersection point outside the graphic prohibited placement area, and the selected intersection point outside the graphic prohibited placement area is used as the intersection point for placing a graphic in a subsequent graphic layout assignment operation algorithm until all the initial values are changed to the first assignment and the second assignment; an obtaining module 304 for obtaining the optimal layout of the graphic in the two-dimensional grid according to the layout of the first assignment and the second assignment in the two-dimensional grid.

[0080] Specifically, the two-dimensional grid provided by the building module 301 provides a grid map for performing the graphic layout assignment operation algorithm multiple times. At the same time, the two-dimensional grid layout is simple, and the optimal layout of the graphic in the two-dimensional grid can be obtained more intuitively.

[0081] The building module 301 includes: a providing unit for designing a mask layout, which includes a plurality of first metal line patterns extending along a first direction and a plurality of second metal line patterns extending along a second direction. The first direction is perpendicular to the second direction, and the first metal line patterns and the second metal line patterns are orthogonal to each other pairwise.

[0082] Specifically, designing the mask layout provides a process basis for the formation process of the semiconductor structure. At the same time, it also provides a template for drawing the two-dimensional grid.

[0083] Specifically, and the first metal line patterns and the second metal line patterns are orthogonal to each other pairwise. The first grid lines extending along the first direction are drawn according to the first metal line patterns, and the second grid lines extending along the second direction are drawn according to the second metal line patterns. Since the first metal line patterns and the second metal line patterns are orthogonal to each other pairwise, the first grid lines and the second grid lines intersect pairwise to form intersection points.

[0084] The establishment module 301 includes: a drawing unit, configured to draw a two-dimensional grid having a first grid line and a second grid line according to the designed mask layout, where the first grid line corresponds one-to-one to the center line of the first metal line pattern in a first direction, and the second grid line corresponds one-to-one to the center line of the second metal line pattern in a second direction.

[0085] It should be noted that both the first metal line pattern and the second metal line pattern in the designed mask layout have line widths. By making the first grid line correspond one-to-one to the center line of the first metal line pattern in the first direction, and the second grid line correspond one-to-one to the center line of the second metal line pattern in the second direction, the center points of the orthogonal position regions of the first metal line pattern and the second metal line pattern coincide with the intersection points, so that the two-dimensional grid can accurately generate the optimal arrangement of the patterns in the two-dimensional grid.

[0086] The first assignment module 302 is configured to perform a first assignment process on the intersection points and use the assignment of the intersection points as the initial value.

[0087] It should be noted that by performing a first assignment process on the intersection points and using the assignment of the intersection points as the initial value, in the subsequent process of performing multiple graphic arrangement assignment operation algorithms, it is possible to more intuitively obtain which intersection points in the two-dimensional grid can place patterns and which intersection points are prohibited areas for patterns (i.e., areas where patterns cannot be placed).

[0088] The first assignment module 302 includes: a first assignment unit, configured to select intersection points where patterns can be placed and assign the intersection points where patterns can be placed with a first initial value; a second assignment unit, configured to select intersection points where patterns cannot be placed and assign the intersection points where patterns cannot be placed with a second initial value, and the first initial value and the second initial value constitute the initial value.

[0089] Specifically, in the process of providing the designed mask layout, according to the process requirements of the semiconductor structure, some first metal line patterns have cuts (i.e., Metal Cut) in the first direction, and some second metal line patterns have cuts (i.e., Metal Cut) in the second direction, so that the first metal line patterns and the second metal line patterns with cuts (i.e., Metal Cut) do not achieve orthogonality. Correspondingly, in the process of establishing the two-dimensional grid, the intersection points corresponding to the cuts are all intersection points where patterns cannot be placed, and the intersection points where patterns cannot be placed are assigned with a second initial value, and the second initial value can be set to any value or any letter.

[0090] As an example, the second initial value is set to the number "1".

[0091] It should be noted that the intersection points where the graphics can be placed are selected, and the intersection points where the graphics can be placed are assigned a first initial value, and the first initial value can be set to any value or any letter.

[0092] As an example, the first initial value is set to the number "0".

[0093] It should also be noted that the two-dimensional grid in this embodiment has intersection points corresponding to the partition positions. In other embodiments, during the process of providing the design mask layout, the first metal line graphics do not have partition positions (i.e., Metal Cut) in the first direction, and some second metal line graphics do not have partition positions (i.e., Metal Cut) in the second direction. Correspondingly, all the intersection points in the two-dimensional grid are the intersection points where the graphics can be placed, and all the intersection points in the two-dimensional grid are the first initial values.

[0094] The graphic arrangement assignment operation algorithm module 303 is used to repeat the graphic arrangement assignment operation algorithm multiple times. The graphic arrangement assignment operation algorithm includes: selecting any intersection point for placing a graphic, and changing the initial value of the intersection point where the graphic is placed to a first assignment; obtaining the graphic prohibited placement area surrounding the graphic, and changing the initial value of the intersection points located within the graphic prohibited placement area to a second assignment; selecting any intersection point outside the graphic prohibited placement area, and the selected intersection point outside the graphic prohibited placement area is used as the intersection point for placing a graphic in the subsequent graphic arrangement assignment operation algorithm until all the initial values are changed to the first assignment and the second assignment.

[0095] Specifically, selecting any intersection point for placing a graphic and changing the initial value of the intersection point where the graphic is placed to a first assignment can distinguish the initial value in the two-dimensional grid from the first assignment, so that the specific intersection points where the graphics are placed and the intersection points where no graphics are placed can be intuitively seen.

[0096] As an example, the graphic includes an interconnection via graphic.

[0097] It should be noted that during the process of providing the design mask layout, the first metal line graphics are used to form the first metal line, and the second metal line graphics are used to form the second metal line. In the formation process of the semiconductor structure, the first metal line and the second metal line are stacked in an upper and lower layer, and the first metal line and the second metal line are electrically connected through interconnection vias. Since the first grid line corresponds to the first metal line and the second grid line corresponds to the second metal line, the intersection point of the first grid line and the second grid line is the electrical connection point between the first metal line and the second metal line. That is to say, the interconnection via graphic needs to be set at the intersection point.

[0098] As an example, the first assignment is "P".

[0099] Specifically, in the process of forming a semiconductor structure, due to the limitations of lithography performance, there is a minimum design rule value between adjacent interconnection via patterns. That is to say, the pattern set at the intersection has a pattern prohibited area, and no other interconnection via patterns can be placed at the intersections within the pattern prohibited area, reducing the probability of short - circuit between adjacent interconnection via patterns.

[0100] As an example, the graphic arrangement assignment operation algorithm module 303 includes: a first acquisition unit for acquiring a first prohibited value between the graphic and each intersection in the first direction; a second acquisition unit for acquiring a second prohibited value between the graphic and each intersection in the second direction; and a third acquisition unit for acquiring a third prohibited value between the graphic and each intersection in its diagonal direction.

[0101] By acquiring the first prohibited value, the second prohibited value, and the third prohibited value, the pattern prohibited area surrounding the graphic can be obtained, which is conducive to changing the initial value of the intersections within the pattern prohibited area to the second assignment. At the same time, it also clearly indicates the intersections in the two - dimensional grid where patterns can still be placed, and then the utilization rate of the intersections for placing patterns in the two - dimensional grid can be maximized. According to the arrangement of the first assignment and the second assignment in the two - dimensional grid, the optimal arrangement of the graphic in the two - dimensional grid can be obtained, thereby improving the efficiency of the semiconductor design process and increasing the accuracy and reliability for the performance improvement of the subsequent formed semiconductor structure.

[0102] As an example, the first prohibited value X between the graphic and each intersection in the first direction is X = S x - 2B x + n * a; where S x represents the distance between the second grid line where the graphic is located and other second grid lines, B x represents the etching deviation value of the graphic in the first direction, a represents the graphic size floating value, and n represents a natural number.

[0103] As an example, the second prohibited value Y between the graphic and each intersection in the second direction is Y = Sy - 2By + n * a; where Sy represents the distance between the first grid line where the graphic is located and other first grid lines, By represents the etching deviation value of the graphic in the second direction, a represents the graphic size floating value, and n represents a natural number.

[0104] As an example, the third prohibited value between the graphic and each intersection in its diagonal direction is where X represents the first prohibited value and Y represents the second prohibited value.

[0105] In this embodiment, the graphic arrangement assignment operation algorithm module 303 includes: a corner selection unit for selecting the intersection points at the corners in the two-dimensional grid for placing graphics.

[0106] Specifically, by selecting the intersection points at the corners in the two-dimensional grid for placing graphics, it is possible to arrange the graphics sequentially from the corners of the two-dimensional grid to the central position and the end position, thereby maximizing the utilization rate of the intersection points where graphics can be placed in the two-dimensional grid. Correspondingly, the optimal arrangement of the mutual connection holes between the first metal line and the second metal line can be obtained, maximizing the total area of the mutual connection holes between the first metal line and the second metal line, and thus reducing the contact resistance value between the first metal line and the second metal line.

[0107] In other embodiments, in the algorithm for performing the first graphic arrangement assignment operation, the intersection points at the middle position of the two-dimensional grid can also be selected for placing graphics.

[0108] In this embodiment, the second assignment in the graphic arrangement assignment operation algorithm module 303 is the same as the second initial value.

[0109] Specifically, the second assignment is the same as the second initial value, both representing that the intersection points here cannot be used to place graphics.

[0110] As an example, the second assignment is "1".

[0111] It should be noted that the graphic has a minimum design rule value (i.e., the first ideal spacing value) in the first direction, a minimum design rule value (i.e., the second ideal spacing value) in the second direction, and a minimum design rule value (i.e., the third ideal spacing value) in the diagonal direction of the graphic.

[0112] In this embodiment, during the process of selecting any intersection point for placing graphics, the graphic has a first ideal spacing value in the first direction, a second ideal spacing value in the second direction, and a third ideal spacing value in the diagonal direction of the graphic.

[0113] The graphic arrangement assignment operation algorithm module 303 includes: a first comparison unit, configured to compare multiple first prohibited values with the first ideal spacing value. When a first prohibited value is less than the first ideal spacing value, the initial value of the intersection point corresponding to the first prohibited value is changed to a second assignment; a second comparison unit, configured to compare multiple second prohibited values with the second ideal spacing value. When a second prohibited value is less than the second ideal spacing value, the initial value of the intersection point corresponding to the second prohibited value is changed to a second assignment; a third comparison unit, configured to compare multiple third prohibited values with the third ideal spacing value. When a third prohibited value is less than the third ideal spacing value, the initial value of the intersection point corresponding to the third prohibited value is changed to a second assignment.

[0114] In this embodiment, the algorithm for selecting any intersection point outside the graphic prohibited area includes: selecting the intersection point closest to the intersection point where the graphic is placed outside the graphic prohibited area, and using this intersection point as the intersection point for placing the graphic in the subsequent graphic arrangement assignment algorithm.

[0115] Specifically, by selecting the intersection point closest to the intersection point where the graphic is placed outside the graphic prohibited area for placing the graphic, the utilization rate of the intersection points where the graphic can be placed in the two-dimensional grid can be maximized. Correspondingly, the optimal arrangement of the via holes between the first metal line and the second metal line can be obtained, maximizing the total area of the via holes between the first metal line and the second metal line, and thus reducing the contact resistance value between the first metal line and the second metal line.

[0116] The obtaining module 304 is configured to obtain the optimal arrangement of the graphic in the two-dimensional grid according to the arrangement of the first assignment and the second assignment in the two-dimensional grid.

[0117] Specifically, according to the arrangement of the first assignment and the second assignment in the two-dimensional grid, the optimal arrangement of the graphic in the two-dimensional grid is obtained. Correspondingly, the optimal arrangement of the via holes between the first metal line and the second metal line can be obtained, maximizing the total area of the via holes between the first metal line and the second metal line, and thus reducing the contact resistance value between the first metal line and the second metal line, thereby improving the efficiency of the semiconductor design process and increasing the accuracy and reliability for the performance improvement of the subsequent formed semiconductor structure.

[0118] Specifically, the algorithm for obtaining the optimal arrangement of the graphic in the two-dimensional grid includes: the intersection points assigned with "P" in the two-dimensional grid are used for placing the graphic, and the intersection points assigned with "1" in the two-dimensional grid are prohibited from placing the graphic.

[0119] An embodiment of the present invention further provides a device, which can implement the graphic layout optimization algorithm provided by the embodiment of the present invention by loading the above optical proximity correction method in the form of a program. An optional hardware structure of the terminal device provided by the embodiment of the present invention may be as Figure 8 shown, including: at least one processor 01, at least one communication interface 02, at least one memory 03, and at least one communication bus 04.

[0120] In this embodiment, the number of the processor 01, the communication interface 02, the memory 03, and the communication bus 04 is at least one, and the processor 01, the communication interface 02, and the memory 03 complete mutual communication through the communication bus 04. The communication interface 02 may be an interface of a communication module for network communication, such as an interface of a GSM module. The processor 01 may be a central processing unit CPU, or a specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention. The memory 03 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory, NVM), such as at least one disk memory. Among them, the memory 03 stores one or more computer instructions, and the one or more computer instructions are executed by the processor 01 to implement the graphic layout optimization algorithm provided by the embodiment of the present invention.

[0121] It should be noted that the above-mentioned implementation terminal device may further include other devices (not shown) that may not be necessary for the public content disclosed in the embodiments of the present invention; since these other devices may not be necessary for understanding the public content disclosed in the embodiments of the present invention, the embodiments of the present invention do not introduce them one by one.

[0122] An embodiment of the present invention further provides a storage medium, which stores one or more computer instructions, and the one or more computer instructions are used to implement the graphic layout optimization algorithm provided by the embodiment of the present invention.

[0123] Embodiments of the present invention can be implemented by various means such as, for example, hardware, firmware, software, or combinations thereof. In a hardware configuration, the method according to an exemplary embodiment of the present invention can be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, and the like. In a firmware or software configuration, embodiments of the present invention can be implemented in the form of modules, procedures, functions, and the like. The software code can be stored in a memory unit and executed by a processor. The memory unit is located inside or outside the processor and can send data to and receive data from the processor via various known means.

[0124] Although the present invention has been disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A graphic layout optimization algorithm, characterized in that, it includes: establishing a two-dimensional grid, the two-dimensional grid includes a plurality of first grid lines extending in a first direction and a plurality of second grid lines extending in a second direction, the first direction is perpendicular to the second direction, and the first grid lines and the second grid lines intersect pairwise to form intersection points; performing a first assignment process on the intersection points, and taking the assignment of the intersection points as the initial value; repeating a graphic layout assignment operation algorithm multiple times, the graphic layout assignment operation algorithm includes: selecting any intersection point to place a graphic, and changing the initial value of the intersection point where the graphic is placed to a first assignment; obtaining a graphic prohibited placement area surrounding the graphic, and changing the initial value of the intersection points located within the graphic prohibited placement area to a second assignment; selecting any intersection point outside the graphic prohibited placement area, and the selected intersection point outside the graphic prohibited placement area is used as the intersection point for placing a graphic in the subsequent graphic layout assignment operation algorithm until all the initial values are changed to the first assignment and the second assignment; obtaining the optimal layout of the graphic in the two-dimensional grid according to the layout of the first assignment and the second assignment in the two-dimensional grid.

2. The graphic layout optimization algorithm according to claim 1, characterized in that, the step of establishing a two-dimensional network includes: providing a design mask layout, the design mask layout includes a plurality of first metal line patterns extending in a first direction and a plurality of second metal line patterns extending in a second direction, the first direction is perpendicular to the second direction, and the first metal line patterns and the second metal line patterns are orthogonal to each other pairwise; according to the design mask layout, drawing a two-dimensional grid with first grid lines and second grid lines, the first grid lines correspond one-to-one with the center lines of the first metal line patterns in the first direction, and the second grid lines correspond one-to-one with the center lines of the second metal line patterns in the second direction.

3. The graphic layout optimization algorithm according to claim 1, characterized in that, the algorithm for performing the first assignment process on the intersection points includes: selecting the intersection points where a graphic can be placed, and assigning the intersection points where a graphic can be placed to a first initial value; selecting the intersection points where a graphic cannot be placed, and assigning the intersection points where a graphic cannot be placed to a second initial value, the first initial value and the second initial value form the initial value; in the process of changing the initial value of the intersection points located within the graphic prohibited placement area to the second assignment, the second assignment is the same as the second initial value.

4. The graphic layout optimization algorithm according to claim 1, characterized in that, in the algorithm for performing the first graphic layout assignment operation, the step of selecting any intersection point to place a graphic includes: selecting the intersection points at the corners of the two-dimensional grid to place a graphic.

5. The graphic layout optimization algorithm according to claim 1, characterized in that, The algorithm for obtaining the graphic prohibited placement area surrounding the graphic includes: obtaining the first prohibited placement value between the graphic and each intersection point in the first direction; obtaining the second prohibited placement value between the graphic and each intersection point in the second direction; obtaining the third prohibited placement value between the graphic and each intersection point in its diagonal direction.

6. The graphic arrangement optimization algorithm according to claim 5, wherein, in the process of selecting any intersection point for placing the graphic, the graphic has a first ideal spacing value in the first direction, a second ideal spacing value in the second direction, and a third ideal spacing value in the diagonal direction of the graphic; The algorithm for changing the initial value of the intersection point located in the graphic prohibited placement area to the second assignment includes: comparing a plurality of the first prohibited placement values with the first ideal spacing value, and when the first prohibited placement value is less than the first ideal spacing value, changing the initial value of the intersection point corresponding to the first prohibited placement value to the second assignment; comparing a plurality of the second prohibited placement values with the second ideal spacing value, and when the second prohibited placement value is less than the second ideal spacing value, changing the initial value of the intersection point corresponding to the second prohibited placement value to the second assignment; comparing a plurality of the third prohibited placement values with the third ideal spacing value, and when the third prohibited placement value is less than the third ideal spacing value, changing the initial value of the intersection point corresponding to the third prohibited placement value to the second assignment.

7. The graphic arrangement optimization algorithm according to claim 5, wherein, Obtain the first prohibited placement value X = S between the figure and each intersection point in the first direction x -2B x +n*a; where S x represents the distance between the second grid line where the figure is located and other second grid lines, B x represents the etching deviation value of the figure in the first direction, a represents the figure size floating value, and n represents a natural number; the second prohibited placement value Y obtained between the graphic and each intersection point in the second direction is Y = Sy - 2By + n*a; where Sy represents the distance between the first grid line where the graphic is located and other first grid lines, By represents the etching deviation value of the graphic in the second direction, a represents the graphic size floating value, and n represents a natural number; Obtain the third prohibited value between the obtained figure and each intersection point in the diagonal direction Wherein, X represents the first prohibited value and Y represents the second prohibited value.

8. The graphic arrangement optimization algorithm according to claim 1, wherein, the algorithm for selecting any intersection point outside the graphic prohibited placement area includes: selecting the intersection point closest to the intersection point for placing the graphic outside the graphic prohibited placement area, and using this intersection point as the intersection point for placing the graphic in the subsequent graphic arrangement assignment algorithm.

9. The graphic arrangement optimization algorithm according to claim 1, wherein, the graphic includes an interconnected via pattern.

10. A graphic arrangement optimization algorithm system, wherein, it includes: a building module for building a two-dimensional grid, the two-dimensional grid includes a plurality of first grid lines extending in the first direction and a plurality of second grid lines extending in the second direction, the first direction and the second direction are perpendicular to each other, and the first grid lines and the second grid lines intersect pairwise to form intersection points; a first assignment module for performing a first assignment process on the intersection points and using the assignment of the intersection points as the initial value; The graphic layout assignment operation algorithm module is used to repeat the graphic layout assignment operation algorithm multiple times. The graphic layout assignment operation algorithm includes: selecting any intersection point to place a graphic, and changing the initial value of the intersection point where the graphic is placed to the first assignment; obtaining the graphic placement prohibited area surrounding the graphic, and changing the initial values of the intersection points within the graphic placement prohibited area to the second assignment; selecting any intersection point outside the graphic placement prohibited area, and the selected intersection point outside the graphic placement prohibited area is used as the intersection point for placing a graphic in the subsequent graphic layout assignment operation algorithm until all the initial values are changed to the first assignment and the second assignment; The obtaining module is used to obtain the optimal layout of the graphic in the two-dimensional grid according to the layout of the first assignment and the second assignment in the two-dimensional grid.

11. The graphic layout optimization algorithm system according to claim 10, characterized in that, The establishing module includes: a providing unit for designing a mask layout, the designed mask layout includes a plurality of first metal line graphics extending along a first direction and a plurality of second metal line graphics extending along a second direction, the first direction is perpendicular to the second direction, and the first metal line graphics and the second metal line graphics are orthogonal to each other in pairs; a drawing unit for drawing a two-dimensional grid having first grid lines and second grid lines according to the designed mask layout, the first grid lines corresponding one-to-one to the center lines of the first metal line graphics in the first direction, and the second grid lines corresponding one-to-one to the center lines of the second metal line graphics in the second direction.

12. The graphic layout optimization algorithm system according to claim 10, characterized in that, The first assignment module includes: a first assignment unit for selecting the intersection points where the graphics can be placed and assigning the intersection points where the graphics can be placed to the first initial value; a second assignment unit for selecting the intersection points where the graphics cannot be placed and assigning the intersection points where the graphics cannot be placed to the second initial value, and the first initial value and the second initial value form the initial value; The second assignment in the graphic layout assignment operation algorithm module is the same as the second initial value.

13. The graphic layout optimization algorithm system according to claim 10, characterized in that, The graphic layout assignment operation algorithm module includes: a corner selection unit for selecting the intersection points at the corners in the two-dimensional grid for placing graphics.

14. The graphic layout optimization algorithm system according to claim 10, characterized in that, The graphic layout assignment operation algorithm module includes: a first obtaining unit for obtaining the first prohibited value between the graphic and each intersection point in the first direction; a second obtaining unit for obtaining the second prohibited value between the graphic and each intersection point in the second direction; a third obtaining unit for obtaining the third prohibited value between the graphic and each intersection point in its diagonal direction.

15. The graphic layout optimization algorithm system according to claim 14, characterized in that, The graphic arrangement assignment operation algorithm module includes: a first comparison unit, configured to compare a plurality of the first prohibited placement values with the first ideal spacing value, and when the first prohibited placement value is less than the first ideal spacing value, change the initial value of the intersection point corresponding to the first prohibited placement value to a second assignment; a second comparison unit, configured to compare a plurality of the second prohibited placement values with the second ideal spacing value, and when the second prohibited placement value is less than the second ideal spacing value, change the initial value of the intersection point corresponding to the second prohibited placement value to a second assignment; a third comparison unit, configured to compare a plurality of the third prohibited placement values with the third ideal spacing value, and when the third prohibited placement value is less than the third ideal spacing value, change the initial value of the intersection point corresponding to the third prohibited placement value to a second assignment.

16. A device, characterized in that, it includes at least one memory and at least one processor, the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the graphic arrangement optimization algorithm according to any one of claims 1 to 9.

17. A storage medium, characterized in that, the storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the graphic arrangement optimization algorithm according to any one of claims 1 to 9.

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