Dual-mode multiplier theoretical transformation system and method based on FPGA platform

Abstract

The invention discloses a dual-mode multiplier theory transformation system and method based on an FPGA platform, and relates to the field of post-quantum cryptography, the system comprises a control module, 8 butterfly-shaped execution units and 24 storage units, each butterfly-shaped execution unit is equipped and connected with 3 storage units and is connected with the control unit, and each butterfly-shaped execution unit is connected with the control unit. Two modular multiplication modules for a common modulus and a special modulus are selectable. The upper computer generates related data and sends the related data to 24 storage units of the FPGA, different modular multiplication modules are selected according to different requirements, and each butterfly execution module reads the data and executes data conversion calculation. The method has the advantages of flexibility, high efficiency and reusability, the NTT execution efficiency can be improved, then the quantum cryptography execution efficiency is improved, the method can be used in various encryption schemes needing to execute NTT, and can also be used in cryptography products such as identity authentication and key management, and threats brought by quantum computing are effectively resisted.

Description

Technical Field

[0001] The present invention relates to the field of post - quantum cryptography, and more specifically to a dual - mode multiplier number - theoretic transform system and method based on an FPGA platform. Background Art

[0002] With the continuous evolution of quantum computing technology, traditional public - key encryption technologies, such as RSA and elliptic - curve cryptography, are facing the risk of being cracked by quantum computers, and their security can no longer be guaranteed. Therefore, there is an urgent need to develop a new encryption system that can resist quantum - computing attacks. Post - Quantum Cryptography (PQC), also known as Quantum - resistant Cryptography (QRC), its core computing process involves polynomial multiplication, and among them, the polynomial multiplication based on Number Theoretic Transforms (NTT for short) is the most widely used. NTT is the abbreviation of "Number Theoretic Transforms", which is translated into Chinese as "number - theoretic transform". This is a mathematical transform technology based on number - theoretic principles, mainly used for efficient convolution operations on integer sequences in the modular domain. Similar to the classical Fast Fourier Transform (FFT), NTT also uses the concept of roots of unity, but its uniqueness lies in using the powers of the n - th primitive root of the modulus p as the roots of unity and performing the transform within the finite field (modulo p). This feature enables NTT to avoid the accumulation of floating - point operation errors when dealing with problems such as large - integer multiplication and polynomial multiplication, ensuring the accuracy of the operation results. Summary of the Invention

[0003] The present invention provides a dual - mode multiplier number - theoretic transform system and method based on an FPGA platform, which can improve the execution efficiency of number - theoretic transforms and thus improve the execution efficiency of post - quantum cryptography.

[0004] To achieve the above object, the present invention provides the following technical solutions:

[0005] In a first aspect, the present invention provides a dual - mode multiplier number - theoretic transform system based on an FPGA platform, including: a host computer, a control unit disposed on the FPGA platform, and a plurality of butterfly execution units. Each of the butterfly execution units is communicatively connected to a number of storage units, and each of the butterfly execution units is respectively communicatively connected to the host computer and the control unit; the butterfly execution unit includes a modular adder, a modular subtractor, and a modular multiplier connected to each other, and the modular multiplier includes a general modular multiplier and a special modular multiplier, wherein the general modular multiplier and the special modular multiplier are selected according to the properties of the modular multiplication operation in the process of performing number - theoretic transforms.

[0006] The dual-mode multiplicative number theory transform system based on the FPGA platform as described above. Further, each of the butterfly execution units is communicatively connected to three storage units, where two storage units are used to read and write data during the execution of the number theory transform process, and one storage unit is used to store the rotation factors during the execution of the number theory transform process.

[0007] The dual-mode multiplicative number theory transform system based on the FPGA platform as described above. Further, the execution cycle of the modular multiplication operation during the execution of the number theory transform process by the ordinary modular multiplier is determined by the bit width of the data. The execution cycle of the modular multiplication operation during the execution of the number theory transform process by the special modular multiplier is 1. The execution cycles of the modular addition operation during the execution of the number theory transform process by the modular adder are all 1. The execution cycle of the modular subtraction operation during the execution of the number theory transform process by the modular subtractor is 1.

[0008] The dual-mode multiplicative number theory transform system based on the FPGA platform as described above. Further, the host computer and the butterfly execution unit are communicatively connected by reading the signal DATA through the address line; the control unit and the butterfly execution unit are communicatively connected by the start signal start, the stop signal stop, the write control signal w_r, the read control signal r_r, the modular multiplier selection signal sle, the address parameter signal add_res, and the rotation factor reading signal tw_w; the outputs of the butterfly execution unit are respectively connected to the register EVEN and the register ODD through two address lines.

[0009] In a second aspect, the present invention provides a dual-mode multiplicative number theory transform method, which is applicable to the dual-mode multiplicative number theory transform system based on the FPGA platform as described above, and includes the steps of:

[0010] Perform initialization operations on each unit of the FPGA platform; meanwhile, use the host computer to generate data according to a preset encryption scheme, and transmit the generated data to the storage unit according to a preset storage scheme;

[0011] The butterfly execution unit waits to read the relevant control signals of the control unit;

[0012] The control unit controls the butterfly execution unit to perform number theory transform through signals, where the start signal start is used to control the butterfly execution unit to start the execution of the number theory transform process, the read control signal r_r is used to control the butterfly execution unit to read the data for the execution of the number theory transform process from the storage unit, the rotation factor reading signal tw_w is used to control the butterfly execution unit to read the pre-arranged rotation factors from the storage unit, the modular multiplier selection signal sle is used to select the modular multiplier during the execution of the number theory transform process, and the write control signal w_r is used to control the butterfly execution unit to write the data generated during the execution of the number theory transform process into the storage unit;

[0013] Stop the number-theoretic transform when the preset number of executions is reached; otherwise, continue to execute the previous step. After stopping the number-theoretic transform, the control unit controls the butterfly execution unit to stop executing the number-theoretic transform process through the stop signal stop, and connects the result data to the EVEN register and the ODD register through two address lines respectively.

[0014] In the dual-mode multiplier number-theoretic transform method as described above, further, when the butterfly execution unit reads the data for the number-theoretic transform process through the read control signal r_r, and when the butterfly execution unit writes the data generated during the number-theoretic transform process to the storage unit through the write control signal w_r, the address for data reading and writing is controlled by the address parameter signal add_res, and the address for data reading and writing is generated by the address generation program contained in the control unit.

[0015] In the dual-mode multiplier number-theoretic transform method as described above, further, initialize each unit of the FPGA platform, where each unit includes: a count counter, a control unit, a plurality of butterfly execution units, and several storage units.

[0016] In the dual-mode multiplier number-theoretic transform method as described above, further, the data generated during the number-theoretic transform process includes: the data generated by the host computer according to the preset encryption scheme, the intermediate data generated during the number-theoretic transform process, and the result data generated during the number-theoretic transform process.

[0017] In the dual-mode multiplier number-theoretic transform method as described above, further, reaching the preset number of executions is achieved through the count counter.

[0018] In the dual-mode multiplier number-theoretic transform method as described above, further, when selecting the modular multiplier through the modular multiplier selection signal sle during the number-theoretic transform process, if the modulus is a Mersenne prime, use a special modular multiplier; otherwise, use a common modular multiplier.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention is applicable to any post-quantum encryption scheme that requires the execution of NTT. Its flexibility is reflected in its ability to update the data of storage units in real time to adapt to different scenarios, while its high efficiency stems from its optional modular multipliers, which can achieve different execution performances. The two modular multipliers complement each other and can be configured according to different data bit-width requirements to achieve multiplexing, thereby expanding the application scenarios. In addition, the dual-mode multiplier number theory transformation system of the present invention has 8 parallel computing butterfly execution units, which can significantly reduce the overall execution time. Each execution unit can be configured with storage units with different functions according to requirements to achieve controllability of storage resources. This design not only improves the efficiency of NTT execution but also correspondingly improves the efficiency of post-quantum cryptography execution, is applicable to various encryption schemes that require the execution of NTT, as well as cryptographic products such as identity authentication and key management, and effectively resists the potential threats of quantum computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0021] Figure 1 It is a schematic diagram of the overall framework of the dual-mode multiplier number theory transformation system based on the FPGA platform provided by the present invention;

[0022] Figure 2 It is a schematic diagram of the structure of the butterfly execution unit of the dual-mode multiplier number theory transformation system based on the FPGA platform provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0024] Embodiment:

[0025] It should be noted that the terms "include" and "have" in the embodiments of the present invention and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those clearly listed steps or units, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products, or devices.

[0026] In the description of the present invention, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In addition, unless otherwise clearly specified and defined, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] See Figures 1 to 2 , a dual-mode multiplicative number theory transform system based on an FPGA platform provided by an embodiment of the present invention includes: a host computer, a control unit provided on the FPGA platform, and a plurality of butterfly execution units. Each of the butterfly execution units is communicatively connected to a plurality of storage units, and each of the butterfly execution units is communicatively connected to the host computer and the control unit respectively; the butterfly execution unit includes a modular adder, a modular subtractor, and a modular multiplier connected to each other. The modular multiplier includes a general modular multiplier and a special modular multiplier. Among them, the general modular multiplier and the special modular multiplier are selected according to the properties of the modular multiplication operation in the execution of the number theory transform process.

[0028] Thus, different execution performances are achieved by selecting different modular multiplication modules, and flexible configurable reuse is achieved by updating the data in the storage units.

[0029] In some embodiments, each of the butterfly execution units is communicatively connected to three storage units. Among them, two storage units are used to read and write data in the execution of the number theory transform process, and one storage unit is used to store the rotation factors in the execution of the number theory transform process.

[0030] In some embodiments, the execution cycle of the modular multiplication operation in the execution of the number theory transform process by the general modular multiplier is determined according to the bit width of the data. The execution cycle of the modular multiplication operation in the execution of the number theory transform process by the special modular multiplier is 1. The execution cycle of the modular addition in the execution of the number theory transform process by the modular adder is 1 respectively. The execution cycle of the modular subtraction in the execution of the number theory transform process by the modular subtractor is 1.

[0031] In some embodiments, the host computer and the butterfly execution unit are communicatively connected by reading the signal DATA through the address line; the control unit and the butterfly execution unit are communicatively connected by the start signal start and the stop signal stop, the write control signal w_r and the read control signal r_r, the modular multiplier selection signal sle, the address parameter signal add_res, and the rotation factor reading signal tw_w; the outputs of the butterfly execution unit are respectively connected to the register EVEN and the register ODD through two address lines.

[0032] In another embodiment, the embodiment of the present invention further provides a dual-mode multiplicative number theory transform method, which is applicable to a dual-mode multiplicative number theory transform system based on an FPGA platform, and includes the steps of:

[0033] Step 1: Perform initialization operations on each unit of the FPGA platform; meanwhile, use the host computer to generate data according to a preset encryption scheme, and transmit the generated data to the storage unit according to a preset storage scheme.

[0034] In actual operation, perform initialization operations on each unit of the FPGA platform, where each unit includes: a number counter, a control unit, multiple butterfly execution units, and several storage units.

[0035] In the specific execution process, transmitting the generated data to the storage unit according to a preset storage scheme means that: two storage units are used to read and write data during the execution of the number theory transform process, and one storage unit is used to store the rotation factors during the execution of the number theory transform process. The coefficients DATA enter the storage unit in batches, while the rotation factor tw_w is first generated and then sorted in the host computer, thus avoiding the time and hardware resources consumed by performing generation and sorting in the FPGA. Exemplarily, for an 8-point NTT(x 0 ~x 7 ), a total of 3 stages are executed. The first stage requires rotation factors The second stage requires and The third stage requires The first stage is to perform butterfly operations on (x 0 , x 4 ), (x 1 , x 5 ), (x 2 , x 6 ), (x 3 , x 7 ) to obtain the result (y 0 ~y 7 ). The second stage is to perform butterfly operations on (y 0 , y 2 ), (y 1 , y 3 ), (y 4 , y 6 ), (y 5 , y 7 ) to obtain the result (z 0 ~z 7 ). The third stage is to perform butterfly operations on (z 0 , z 1 ), (z 2 , z 3 ), (z4 , z 5 ), (z 6 , z 7 ). According to the description of this example, put x 0 , x 1 , x 2 , x 3 into one of the storage units, and put the other four into another storage unit. The host computer generates and put them into the third storage unit in sequence.

[0036] Generating data according to a preset encryption scheme means that the host computer is responsible for generating data that meets the requirements of a specific encryption scheme. According to different encryption schemes, different encryption schemes have different data requirements, usually involving setting a modulus q and a data volume N, and then generating N data points by random sampling or other specified sampling methods within the interval (0, q - 1). The present invention adopts a random sampling technique (the user can customize other sampling methods), and sets the modulus q and the data volume N, where q must be a prime number and N should be a power of 2. For example, set q = 520193 and N = 1024, and then generate 1024 data points within the interval (0, 520192), and transmit these data points to the storage unit of the FPGA according to the established requirements.

[0037] And NTT is a derivative of the fast Fourier transform FFT. The execution process of FFT is not different from that of NTT except for the data form. Therefore, the overall number of calculation executions can be determined by the data volume N of NTT and the number of butterfly units. Take the logarithm of N to get the number of stages of NTT, and then each stage needs to perform N / 2 butterfly calculations. The number of butterfly execution units is 8, so the overall number can be determined. According to the above description, let N = 16, log 2 16 = 4, and the number of stages is obtained as 4. Each stage performs 16 / 2 = 8 butterfly operations, for a total of 32 butterfly operations. Since there are 8 butterfly execution units that can perform parallel calculations, the NTT execution in the FPGA requires a total of 32 / 8 = 4 times.

[0038] Step 2: The butterfly execution unit waits to read the relevant control signals of the control unit.

[0039] Step 3: The control unit controls the butterfly execution unit to perform number-theoretic transformation through signals. Specifically, the start signal start is used to control the butterfly execution unit to start the number-theoretic transformation process. The read control signal r_r is used to control the butterfly execution unit to read the data for the number-theoretic transformation process from the storage unit. The twiddle factor read signal tw_w is used to control the butterfly execution unit to read the pre-arranged twiddle factors from the storage unit. During the number-theoretic transformation process, the modular multiplier selection signal sle is used to select the modular multiplier, and the write control signal w_r is used to control the butterfly execution unit to write the data generated during the number-theoretic transformation process into the storage unit.

[0040] In actual operation, the data generated during the number-theoretic transformation process includes: the data generated by the host computer according to the preset encryption scheme, the intermediate data generated during the number-theoretic transformation process, and the result data generated during the number-theoretic transformation process.

[0041] In the specific execution process, when the read control signal r_r is used to control the butterfly execution unit to read the data for the number-theoretic transformation process from the storage unit, and when the write control signal w_r is used to control the butterfly execution unit to write the data generated during the number-theoretic transformation process into the storage unit, the address parameter signal add_res is used to control the address of data reading and writing, and the address of data reading and writing is generated by the address generation program contained in the control unit.

[0042] In actual operation, when the modular multiplier selection signal sle is used to select the modular multiplier during the number-theoretic transformation process, if the modulus is a Mersenne prime, a special modular multiplier is used; otherwise, a general modular multiplier is used. Exemplarily, for general modular multiplication, the number of loops needs to be determined according to the modulus bit width K and the data volume N of the NTT conversion to obtain the parameter W = log 2 2N, and the number of loops required for word-level Montgomery modular multiplication can be determined using K and W. Using word-level Montgomery modular multiplication is superior to using the classical Montgomery modular multiplication design. The classical Montgomery modular multiplication directly processes the data, resulting in the use of more hardware resources such as multipliers with longer bit widths. In contrast, word-level Montgomery modular multiplication uses the "loop" step to "split" the data for processing, avoiding this problem. For a special modular multiplier for a generalized Mersenne prime modulus of the form q = 2 i ±2 j ±1, there is a dedicated modular reduction operation process, which only requires fewer multiplier resources and simple shift operations. The two modular multiplication methods are different from the design of using only one modular multiplication algorithm, providing options that can be selected according to different performance and scenario requirements. Users can switch between different modular multipliers by modifying the sle signal, improving flexibility.

[0043] Step 4: Stop performing the number-theoretic transform when the preset number of executions is reached; otherwise, continue with the previous step. After stopping the number-theoretic transform, the control unit controls the butterfly execution unit to stop the number-theoretic transform process through the stop signal stop, and connects the result data to the register EVEN and the register ODD through two address lines respectively.

[0044] In actual operation, reaching the predetermined number of executions is achieved through a number counter.

[0045] In the specific execution process, the final data will be output to the registers EVEN and ODD. The result of the modular multiplication operation will be output to the register ODD, while other result data will be output to the register EVEN. By setting the caching time of EVEN, it is possible to wait for ODD to receive the result of the modular multiplication operation in the butterfly execution unit, and then both output all results synchronously.

[0046] As an example, a dual-mode multiplier theory transformation method may further include the following processes: ①: First, initialize each unit of the FPGA. The host computer generates data that meets the requirements of the encryption scheme. Since different encryption schemes have different requirements for data, usually after determining the modulus value q and the data volume N, N data are generated within the range of (0, q-1) by means of random sampling and other methods. The present invention adopts random sampling (of course, other sampling methods can also be set), determines the q value and the data volume N, and requires q to be a prime number and N to be a power of 2. For example, set q = 520193 and N = 1024, generate 1024 data within the range of (0, 520192), and transmit them to the storage unit of the FPGA according to the requirements; ②: Each butterfly execution unit is configured to connect three storage units, two of which are used to store coefficients and data, and the other is used to store the rotation factor tw_w, waiting to read the relevant control signals; ③: The control unit is responsible for the overall process control, starts to execute the NTT using the start signal, and uses r_r and w_r to control the reading and writing of data, uses sle to select the modular multiplier, and uses add_res to control the address of data reading and writing; ④: The control unit starts to execute the NTT. First, set the start signal high and the r_r signal high. The butterfly execution unit starts to read data from the storage unit. The data address read is generated by the address generation program contained in the control unit, and the rotation factor is preferably generated and sorted in the host computer and read in sequence; ⑤: After the coefficient and the rotation factor are read, perform butterfly calculation according to the GS butterfly. The coefficient is first subjected to modular addition and modular subtraction, each consuming one cycle; ⑥: The modular multiplication is implemented by a modular multiplier. The modular multiplier selects different modular multipliers according to the high and low levels of the sle signal caused by different moduli, that is, a general modular multiplier and a special modular multiplier; if the modulus is a Mersenne prime number, a special modular multiplier is used, which only requires simple shift and addition and subtraction calculations, otherwise word-level Montgomery modular multiplication is used, and Montgomery modular multiplication is performed LOOP times; in actual operation, the general modular multiplication needs to determine the number of cycles according to the modular digit width K and the data volume N of the NTT conversion, obtain the parameter W = log 2 2N, and the number of cycles that the word-level Montgomery modular multiplication needs to execute can be determined using K and W And the special modular multiplication is for the general Mersenne prime modulus of the form q = 2 i ±2 j ±1; ⑦: The calculation result is written back to the corresponding position of the storage unit by setting w_r high and then according to the parameters generated by the address generation program; ⑧: Stop when the preset number of executions is reached, otherwise continue to execute steps ③-⑧; ⑨: When the preset number of executions is reached, set the control signal stop high and the start low, read the result data, and reset the execution times counter count.

[0047] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0048] The above embodiments are only for illustrating the technical concept and characteristics of the present invention, and the purpose is to enable those of ordinary skill in the art to understand the content of the present invention and implement it accordingly, and it cannot be used to limit the protection scope of the present invention. All equivalent changes or modifications made according to the essence of the content of the present invention should be covered within the protection scope of the present invention.

Claims

1. A dual-mode multiplier theory transformation system based on FPGA platform, characterized in that: include: A host computer, a control unit arranged on an FPGA platform and a plurality of butterfly execution units, each of the butterfly execution units is communicatively connected to a plurality of storage units, and each of the butterfly execution units is communicatively connected to the host computer and the control unit respectively; the butterfly execution unit comprises a modular adder, a modular subtractor and a modular multiplier which are interconnected, the modular multiplier comprises an ordinary modular multiplier and a special modular multiplier, wherein the ordinary modular multiplier and the special modular multiplier are selected according to the properties of the modular multiplication operation in the number theory transformation process.

2. The dual-mode multiplier theory transformation system based on FPGA platform according to claim 1 is characterized in that: Each of the butterfly execution units is communicatively connected to three storage units, wherein two storage units are used to read and write data for executing a number theory transformation process, and one storage unit is used to store rotation factors for executing a number theory transformation process.

3. The dual-mode multiplier theory transformation system based on FPGA platform according to claim 1 is characterized in that: The execution period of the modular multiplication operation of the number theory transformation process performed by the ordinary modular multiplier is determined according to the bit width of the data, the execution period of the modular multiplication operation of the number theory transformation process performed by the special modular multiplier is 1, the execution period of the modular addition operation of the number theory transformation process performed by the modular adder is 1, and the execution period of the modular subtractor modular subtraction operation of the number theory transformation process is 1.

4. The dual-mode multiplier theory transformation system based on FPGA platform according to claim 1 is characterized in that: The host computer and the butterfly execution unit are connected in communication through the address line reading signal DATA; the control unit and the butterfly execution unit are connected in communication through the start signal start and the stop signal stop, the write control signal w_r and the read control signal r_r, the modular multiplier selection signal sle, the address parameter signal add_res, and the rotation factor reading signal tw_w; the output of the butterfly execution unit is connected to the register EVEN and the register ODD respectively through two address lines.

5. A dual-mode multiplier theory transformation method, applicable to the dual-mode multiplier theory transformation system based on FPGA platform as claimed in claim 1, characterized in that: Includes steps: Perform initialization operations on each unit of the FPGA platform; at the same time, use the host computer to generate data according to the preset encryption scheme, and transmit the generated data to the storage unit according to the preset storage scheme; The butterfly execution unit waits for the relevant control signal of the control unit to be read; The control unit controls the butterfly execution unit to perform number theory transformation through signals, wherein the start signal start is used to control the butterfly execution unit to start the number theory transformation process, the read control signal r_r is used to control the butterfly execution unit to read data for performing the number theory transformation process from the storage unit, the rotation factor read signal tw_w is used to control the butterfly execution unit to read pre-arranged rotation factors from the storage unit, the modular multiplier selection signal sle is used to select the modular multiplier during the number theory transformation process, and the write control signal w_r is used to control the butterfly execution unit to write the data generated during the number theory transformation process into the storage unit; When the preset number of executions is reached, the number-theoretic transformation is stopped, otherwise the previous step is continued. After the number-theoretic transformation is stopped, the control unit controls the butterfly execution unit to stop the number-theoretic transformation process through the stop signal stop, and connects the result data to the register EVEN and the register ODD through two address lines respectively.

6. The dual-module multiplier theory transformation method according to claim 5, characterized in that: When the butterfly execution unit is controlled by the read control signal r_r to read the data for executing the number theory transformation process from the storage unit, and when the butterfly execution unit is controlled by the write control signal w_r to write the data generated in the number theory transformation process into the storage unit, the address parameter signal add_res is used to control the address of the data reading and writing, and the address of the data reading and writing is generated by the address generation program contained in the control unit.

7. The dual-module multiplier theory transformation method according to claim 5, characterized in that: The initialization operation is performed on each unit of the FPGA platform, wherein each unit includes: a times counter, a control unit, a plurality of butterfly execution units and a plurality of storage units.

8. The dual-module multiplier theory transformation method according to claim 5, characterized in that: The data generated in the number theory transformation process includes: data generated by the host computer according to a preset encryption scheme, intermediate data generated in the number theory transformation process, and result data generated in the number theory transformation process.

9. The dual-module multiplier theory transformation method according to claim 5, characterized in that: The reaching of the preset execution times is achieved by a times counter.

10. The dual-module multiplier theory transformation method according to claim 5, characterized in that: When the modular multiplier is selected by the modular multiplier selection signal sle during the number theory transformation process, if the modulus is a Mersenne prime, a special modular multiplier is used, otherwise, an ordinary modular multiplier is used.

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