Routing method and device of quantum circuit

Abstract

The invention provides a routing method of a quantum circuit, which can be applied to the technical field of quantum computing. The method comprises the steps of determining at least one target double-bit gate based on a plurality of quantum gates of a to-be-executed quantum circuit and an initial mapping result of the to-be-executed quantum circuit; determining a plurality of alternative swap gates based on the connection attribute of the quantum bits of the at least one target double-bit gate; obtaining the quantum gate density of the to-be-executed quantum circuit based on the target double-bit gate number in the to-be-executed quantum circuit and the quantum bit number of the to-be-executed quantum circuit; for each target double-bit gate, determining a target swap gate in the plurality of alternative swap gates based on the quantum gate density of the quantum circuit to be executed; and based on the target swap gate corresponding to each target double-bit gate, determining a routing result of each target double-bit gate in the quantum line to be executed.

Description

Technical Field

[0001] The present disclosure relates to the field of quantum computing technology, and more particularly, to a routing method and apparatus for quantum circuits. Background Art

[0002] In a quantum computer, the execution of a quantum algorithm generally requires multiple steps such as program generation, hardware-related program compilation, and actual hardware execution. Among them, due to the direct connectivity limitation of physical qubits in a superconducting quantum computer, two-qubit quantum operations can only be performed between specific pairs of physical qubits, and the compiler often needs to insert additional operations to ensure that the program can be executed. In order to improve the execution efficiency and accuracy of quantum programs, local optimization needs to be performed according to the hardware characteristics and chip structure, especially to solve the mapping and routing problems of quantum circuits.

[0003] However, when traditional quantum circuit mapping and routing tools minimize the circuit depth for large-scale quantum circuits, they do not consider the difference in the execution time of quantum gates between different qubits, so that when considering the routing problem, the circuit depth and execution time are regarded as approximately equivalent, resulting in limitations in the quantum circuit routing problem. Summary of the Invention

[0004] In view of this, the present disclosure provides a routing method and apparatus for quantum circuits.

[0005] One aspect of the present disclosure provides a routing method for a quantum circuit, including: determining at least one target two-bit gate based on multiple quantum gates of a to-be-executed quantum circuit and an initial mapping result of the to-be-executed quantum circuit; determining a plurality of candidate swap gates based on the connection attributes of the qubits of the at least one target two-bit gate; obtaining the quantum gate density of the to-be-executed quantum circuit based on the number of target two-bit gates in the to-be-executed quantum circuit and the number of qubits of the to-be-executed quantum circuit; for each target two-bit gate, determining a target swap gate from the plurality of candidate swap gates based on the quantum gate density of the to-be-executed quantum circuit and the state information of the quantum chip; and determining the routing result of each target two-bit gate in the to-be-executed quantum circuit based on the target swap gate corresponding to each target two-bit gate.

[0006] According to an embodiment of the present disclosure, determining a target swap gate among the multiple alternative swap gates based on the quantum gate density of the to-be-executed quantum circuit and the state information of the quantum chip includes: obtaining a density comparison result based on the quantum gate density of the to-be-executed quantum circuit and a density threshold; and when the density comparison result indicates that the quantum gate density of the to-be-executed quantum circuit is greater than the density threshold, determining the target swap gate among the multiple alternative swap gates based on the state information of the quantum chip and the score of each of the multiple alternative swap gates.

[0007] According to an embodiment of the present disclosure, determining the target swap gate among the multiple alternative swap gates based on the state information of the quantum chip and the score of each of the multiple alternative swap gates includes: calculating the score of each of the multiple alternative swap gates in the current iteration based on the average remaining path length of each of the at least one target two-qubit gate, the execution time of each of the multiple alternative swap gates in the current iteration, and the occupation time of the multiple qubits; determining the alternative swap gate with the lowest score in the current iteration among the multiple alternative swap gates based on the score of each of the multiple alternative swap gates in the current iteration to obtain the optimal swap gate in the current iteration; and when the iteration termination condition is satisfied, determining the optimal swap gate in the current iteration as the target swap gate.

[0008] According to an embodiment of the present disclosure, the method further includes: when the iteration termination condition is not satisfied, determining the overall score of the to-be-executed quantum circuit in the current iteration; updating the overall score of the to-be-executed quantum circuit in the current iteration based on the score of the optimal swap gate to obtain the overall score of the to-be-executed quantum circuit in the next iteration; and deleting the optimal swap gate and the alternative swap gates conflicting with the optimal swap gate from the multiple alternative swap gates to update and obtain the multiple alternative swap gates in the next iteration.

[0009] According to an embodiment of the present disclosure, the method further includes: when the density comparison result indicates that the quantum gate density of the to-be-executed quantum circuit is less than the density threshold, calculating the score of each of the multiple alternative swap gates based on the average remaining path length between each of the at least one target two-qubit gate, the execution time of each of the multiple alternative swap gates, and the occupation time of the multiple qubits; and determining the alternative swap gate with the lowest score among the multiple alternative swap gates as the target swap gate based on the score of each of the multiple alternative swap gates.

[0010] According to an embodiment of the present disclosure, the above method further includes: based on the topological structure of the above quantum chip, obtaining the path lengths between the above multiple quantum gates; based on the path lengths between the above multiple quantum gates, determining the average remaining path length of the above at least one target two-qubit gate.

[0011] According to an embodiment of the present disclosure, the above method further includes: using the above target swap gate to execute the above target two-qubit gate until all of the above at least one target two-qubit gate are executed completely, to obtain the execution result of the above quantum circuit to be executed.

[0012] According to an embodiment of the present disclosure, the execution result of the above quantum circuit to be executed further includes the execution result of the target single-qubit gate. Before the above using the above target swap gate to execute the above target two-qubit gate until all of the above at least one target two-qubit gate are executed completely, to obtain the execution result of the above quantum circuit to be executed, the above method further includes: screening out target single-qubit gates from the above multiple quantum gates that have no influence on the execution process of the above target swap gate during the execution process; executing the above target single-qubit gates to obtain the execution result of the above target single-qubit gates.

[0013] According to an embodiment of the present disclosure, using the above target swap gate to execute the above target two-qubit gate until all of the above at least one target two-qubit gate are executed completely, to obtain the execution result of the above quantum circuit to be executed, includes: for each target two-qubit gate, executing the target swap gate corresponding to each target two-qubit gate to obtain the execution time of the above target swap gate and the occupation time of the qubits of the above target swap gate; based on the execution time of the above target swap gate, the occupation time of the qubits of the above target swap gate, and the execution time of the remaining quantum gates, updating to obtain the current occupation time of the above multiple qubits; based on the current occupation time of the above multiple qubits, determining the target swap gate corresponding to other target two-qubit gates; executing the above target swap gate corresponding to other target two-qubit gates until all of the above at least one target two-qubit gate are executed completely, to obtain the execution result of the above quantum circuit to be executed.

[0014] Another aspect of the present disclosure provides a routing device for a quantum circuit, including: a first determination module configured to determine at least one target two-qubit gate based on a plurality of quantum gates of a to-be-executed quantum circuit and an initial mapping result of the to-be-executed quantum circuit; a second determination module configured to determine a plurality of alternative swap gates based on connection attributes of qubits of the at least one target two-qubit gate; a third determination module configured to obtain a quantum gate density of the to-be-executed quantum circuit based on the number of target two-qubit gates in the to-be-executed quantum circuit and the number of qubits of the to-be-executed quantum circuit; a fourth determination module configured to, for each target two-qubit gate, determine a target swap gate from the plurality of alternative swap gates based on the quantum gate density of the to-be-executed quantum circuit and state information of the quantum chip; and a fifth determination module configured to determine a routing result of each target two-qubit gate in the to-be-executed quantum circuit based on the target swap gate corresponding to each target two-qubit gate.

[0015] Another aspect of the present disclosure provides an electronic device, including: one or more processors; a memory configured to store one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the above method.

[0016] Another aspect of the present disclosure provides a computer-readable storage medium having stored thereon a computer program or instruction, and when the computer program or instruction is executed by a processor, the steps of the above method are implemented.

[0017] Another aspect of the present disclosure provides a computer program product including a computer program or instruction, and when the computer program or instruction is executed by a processor, the steps of the above method are implemented.

[0018] According to an embodiment of the present disclosure, based on the quantum gate density and the state information of the quantum chip, an insertion strategy of quantum swap gates is adaptively determined to minimize the number of operations of the swap gates required for executing target two-qubit gates, so that a quantum program can be executed faster. In addition, the embodiment of the present disclosure combines the connection attributes between qubits and the execution order of quantum gates, further shortens the execution time of the quantum program, and has a fast solution ability, so that the solution process can be completed in a short time, thereby enabling routing of large-scale (with a large number of qubits) quantum circuits. Description of the Drawings

[0019] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:

[0020] Figure 1 Schematically shows a flowchart of a routing method for a quantum circuit according to an embodiment of the present disclosure.

[0021] Figure 2 Schematically shows a topological schematic diagram of a quantum chip according to a specific embodiment of the present disclosure.

[0022] Figure 3 Schematically shows a schematic diagram of a quantum circuit to be executed according to a specific embodiment of the present disclosure.

[0023] Figure 4 Schematically shows a schematic diagram of a directed acyclic graph according to a specific embodiment of the present disclosure.

[0024] Figure 5 Schematically shows a flowchart of a method for determining a target swap gate according to a specific embodiment of the present disclosure.

[0025] Figure 6 Schematically shows a schematic diagram of the current busy state of a qubit according to a specific embodiment of the present disclosure.

[0026] Figure 7 Schematically shows a schematic diagram of the busy state of a qubit after update according to a specific embodiment of the present disclosure.

[0027] Figure 8 Schematically shows a schematic diagram of the execution result of a quantum circuit to be executed according to a specific embodiment of the present disclosure.

[0028] Figure 9 Schematically shows a schematic diagram of the execution result of a quantum circuit to be executed according to a specific embodiment of the present disclosure.

[0029] Figure 10 Schematically shows a block diagram of a routing device for a quantum circuit according to an embodiment of the present disclosure.

[0030] Figure 11 Schematically shows a block diagram of an electronic device suitable for implementing a routing method for a quantum circuit according to an embodiment of the present disclosure. Detailed implementation manners

[0031] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the following detailed description, for the sake of explanation, many specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. However, it is obvious that one or more embodiments can be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0032] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. The terms "comprising", "including" and the like as used herein indicate the presence of the described features, steps, operations and / or components, but do not preclude the presence or addition of one or more other features, steps, operations or components.

[0033] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those of ordinary skill in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0034] A quantum computer is a type of physical device that performs high-speed mathematical and logical operations, stores, and processes quantum information in accordance with the laws of quantum mechanics. In a quantum computer, the execution of a quantum algorithm generally requires multiple steps such as program generation, hardware-related program compilation, and actual hardware execution. Among them, quantum program generation starts from a quantum algorithm and converts the calculation process in the algorithm into a quantum program circuit. The implementation of any quantum algorithm requires first designing the corresponding quantum functions and quantum circuits, and using appropriate quantum gates and quantum functions to solve the target problem.

[0035] Hardware-related program compilation maps the quantum program circuit generated in the previous step to the target hardware for execution. The primary goal of program compilation is to solve the problem that may occur during the execution of the program circuit and cannot be directly executed on the target hardware. Due to the direct connectivity limitations of physical qubits in a superconducting quantum computer, two-qubit quantum operations can only be performed between specific pairs of physical qubits, and the compiler often needs to insert additional operations to ensure that the program can be executed.

[0036] Therefore, in order to improve the execution efficiency and accuracy of quantum programs, local optimization needs to be carried out according to the hardware characteristics and chip structure, especially to solve the mapping and routing problems of quantum circuits. During the compilation process, in order to enable the quantum program circuit to be executed quickly and obtain the desired result as much as possible, it is necessary to first consider how the qubits in the logic circuit are mapped one by one to the physical bits on the target hardware, then solve the possible limitations in the execution of quantum gates in the circuit, and further perform local optimization according to the characteristics of the device. Considering the chip structure to rearrange quantum gates and deploy mapped qubits are all necessary steps to execute quantum programs to obtain reasonable results.

[0037] However, when traditional quantum circuit mapping and routing tools minimize the circuit depth for large-scale quantum circuits, they do not consider the differences in the execution times of quantum gates between different qubits, making the circuit depth and execution time regarded as approximately equivalent when considering the routing problem, thus having limitations in the quantum circuit routing problem.

[0038] In view of this, embodiments of the present disclosure adaptively determine an insertion strategy for quantum swap gates based on the quantum gate density and the state information of a quantum chip, so as to minimize the number of swap operations required to execute target two-qubit gates, enabling the quantum program to be executed faster. In addition, embodiments of the present disclosure combine the connection attributes between qubits and the execution order of quantum gates, further shortening the execution time of the quantum program and having a fast solving ability, enabling the solving process to be completed in a short time, thereby enabling routing of large-scale (with a large number of qubits) quantum circuits.

[0039] Specifically, embodiments of the present disclosure provide a routing method and apparatus for a quantum circuit. The method includes determining at least one target two-qubit gate based on a plurality of quantum gates of a quantum circuit to be executed and an initial mapping result of the quantum circuit to be executed; determining a plurality of candidate swap gates based on the connection attributes of the qubits of the at least one target two-qubit gate; obtaining the quantum gate density of the quantum circuit to be executed based on the number of target two-qubit gates in the quantum circuit to be executed and the number of qubits of the quantum circuit to be executed; for each target two-qubit gate, determining a target swap gate from the plurality of candidate swap gates based on the quantum gate density of the quantum circuit to be executed and the state information of the quantum chip; and determining the routing result of each target two-qubit gate in the quantum circuit to be executed based on the target swap gate corresponding to each target two-qubit gate.

[0040] It should be noted that the routing method and apparatus for a quantum circuit determined by embodiments of the present disclosure can be used in the field of quantum information technology, such as the field of quantum circuit mapping technology and the field of quantum computing technology. The routing method and apparatus for a quantum circuit determined by embodiments of the present disclosure can also be used in any field other than the field of quantum information technology, and the application field of the routing method and apparatus for a quantum circuit determined by embodiments of the present disclosure is not limited.

[0041] For ease of understanding, the terms that appear in the specification will be uniformly explained below.

[0042] Quantum circuit: A graphical representation method of a quantum algorithm, consisting of qubits (quantum bits) and quantum gates.

[0043] Qubit: The basic unit of quantum computing. A qubit can be in a superposition state of 0 and 1. In a quantum circuit diagram, each qubit is represented by a horizontal line from left to right, representing the time direction.

[0044] Quantum gate: A symbol for operating on qubits, divided into single-qubit gates and two-qubit gates. A single-qubit gate operates on a single qubit only, while a two-qubit gate operates on two qubits simultaneously. Quantum gates are executed in chronological order, and only after all the previous gates on the current qubit have been executed can the next gate be executed.

[0045] Superconducting quantum chip: A superconducting quantum chip is a technical route to realize a quantum computer, and its topological structure is usually represented by an undirected graph.

[0046] Physical quantum bit: Generally, the quantum bit structure in a quantum chip is called a physical quantum bit, which is the basic unit for actually performing quantum computing. Due to the limitation of hardware connectivity, two-bit gates cannot be performed between any two physical quantum bits.

[0047] Logical quantum bit: Generally, the object bit operated in a quantum circuit is called a logical quantum bit.

[0048] Quantum bit mapping: One-to-one mapping of the logical quantum bits in a quantum circuit to the physical bits on a quantum chip.

[0049] Quantum bit routing: When two logical quantum bits in a quantum circuit need to perform a two-bit gate and there is no connection between the corresponding physical quantum bits, additional operations need to be inserted to move the physical quantum bits to a connected position.

[0050] Quantum gate execution time: Represents the time required to execute a quantum gate. For two-bit gates and one-bit gates, the execution time may be different. The execution time of the same quantum gate on different quantum bits may also be different.

[0051] Quantum circuit execution time: The time required to execute the entire quantum circuit on the target superconducting quantum hardware.

[0052] Numbering of quantum bits: The numbering of quantum bits can be represented by a digital subscript in a quantum algorithm or quantum program. For example, a group of physical quantum bits q 0 、q 1 、q 2 can represent the 0th, 1st, and 2nd quantum bits respectively.

[0053] Figure 1 The flowchart of the routing method of the quantum circuit according to an embodiment of the present disclosure is schematically shown.

[0054] As Figure 1 shown, the method includes operations S110~S150.

[0055] In operation S110, based on multiple quantum gates of the quantum circuit to be executed and the initial mapping result of the quantum circuit to be executed, at least one target two-bit gate is determined.

[0056] In operation S120, based on the connection attributes of the quantum bits of at least one target two-bit gate, multiple alternative swap gates are determined.

[0057] In operation S130, based on the number of target two-qubit gates in the quantum circuit to be executed and the number of qubits in the quantum circuit to be executed, the quantum gate density of the quantum circuit to be executed is obtained.

[0058] In operation S140, for each target two-qubit gate, based on the quantum gate density of the quantum circuit to be executed and the state information of the quantum chip, a target swap gate is determined among multiple candidate swap gates.

[0059] In operation S150, based on the target swap gate corresponding to each target two-qubit gate, the routing result of each target two-qubit gate in the quantum circuit to be executed is determined.

[0060] According to an embodiment of the present disclosure, the initial mapping result represents the physical initial positions obtained by mapping multiple logical qubits to the quantum chip structure in a preset order. This physical initial position determines the specific execution order and manner of multiple quantum gates in the quantum circuit to be executed.

[0061] According to an embodiment of the present disclosure, based on multiple quantum gates in the quantum circuit to be executed and the initial mapping result, one or more quantum gates that cannot be directly executed among the multiple quantum gates are identified and determined as target two-qubit gates. These target two-qubit gates cannot be directly executed due to limited connectivity between physical qubits.

[0062] Figure 2 Schematically shows a topological schematic diagram of a quantum chip according to a specific embodiment of the present disclosure.

[0063] Figure 3 Schematically shows a schematic diagram of a quantum circuit to be executed according to a specific embodiment of the present disclosure.

[0064] As Figure 2 shown, a set of logical qubits is Q 1 , Q 2 , Q 3 , Q 4 , where there is a connection relationship between Q 1 and Q 2 , there is a connection relationship between Q 2 and Q 3 , there is a connection relationship between Q 3 and Q 4 , there is a connection relationship between Q 4 and Q 1 . Mapping them to the quantum chip structure, the resulting quantum circuit to be executed is as Figure 3 shown, and the initial mapping result is , , , . As Figure 3 shown, q1 and q 2 There is a two-bit gate between them. Since Figure 2 Q in 1 and Q 2 There is a connection relationship between them, it means that this two-bit gate can be directly executed. As Figure 3 shown, there is also a two-bit gate between q 1 and q 3 However, based on Figure 2 it is known that there is no connection relationship between Q 1 and Q 3 it means that this two-bit gate cannot be directly executed. Therefore, the two-bit gate between q 1 and q 3 can be used as the target two-bit gate.

[0065] According to an embodiment of the present disclosure, according to the connection attributes of the qubits involved in each target two-bit gate, a plurality of possible quantum swap gates are determined as alternative swap gates, and these alternative swap gates can be used to change the positions of the qubits so that the target two-bit gate can be physically executed. Among them, the quantum swap (SWAP) gate can be used to exchange the information on two qubits.

[0066] According to an embodiment of the present disclosure, according to the number of target two-bit gates in the quantum circuit to be executed and the number of qubits in the quantum circuit to be executed, the quantum gate density of the current quantum circuit is calculated. This density index can be used to reflect the density of quantum gates in the quantum circuit and the difficulty of inserting quantum swap gates.

[0067] According to an embodiment of the present disclosure, for each target two-bit gate, based on the quantum gate density and the state information of the quantum chip, different selection strategies are determined to select one or more optimal target swap gates from the alternative swap gates to obtain a set of target swap gates corresponding to each target two-bit gate. Among them, the selection strategy may include minimizing the number of SWAP operations required to execute the target two-bit gate. Among them, the state information of the quantum chip may include, for example, the connection relationship between qubits, the occupation time of qubits, the execution time of different quantum swap gates, etc.

[0068] According to an embodiment of the present disclosure, based on the set of target swap gates, the actual execution path of each target two-bit gate in the quantum circuit to be executed is determined, for example, including determining the sequence of SWAP operations to be executed before and after executing each target two-bit gate to ensure that the target two-bit gate can be executed on the correct qubit pair.

[0069] Based on this, embodiments of the present disclosure adaptively determine the insertion strategy of quantum swap gates based on the quantum gate density and the state information of the quantum chip to minimize the number of operations of the swap gates required to execute the target two-qubit gate, so that the quantum program can be executed faster. In addition, embodiments of the present disclosure combine the connection attributes between qubits and the execution order of quantum gates to further shorten the execution time of the quantum program and have fast solving capabilities, enabling the solving process to be completed in a short time, thereby enabling routing of large-scale (with a large number of qubits) quantum circuits.

[0070] According to an embodiment of the present disclosure, before determining at least one target two-qubit gate, the quantum circuit to be executed can be preprocessed. Specifically, multiple quantum gates of the quantum circuit to be executed can be mapped to an initial directed acyclic graph. This initial directed acyclic graph can be a structured representation for showing the basic connection relationships between multiple quantum gates. For example, each quantum gate and each qubit can be used as nodes of the directed acyclic graph. The operation order of the quantum gates on the qubits and the dependency relationships between the qubits can be used as the edges of the directed acyclic graph.

[0071] According to a specific embodiment of the present disclosure, in the case where all existing executable quantum gates are regarded as executed, the directed acyclic graph can also be divided into a precursor layer and a successor layer. Among them, the precursor layer can be used to represent the first layer of the directed acyclic graph, and this layer can be used to indicate, for example, the first target two-qubit gate that cannot be directly executed in the quantum circuit. The precursor layer set can include multiple target two-qubit gates that cannot be directly executed in the directed acyclic graph. The successor layer can be used to represent the k layers after the precursor layer, and the successor layer can be used to indicate the quantum gates waiting to be executed after the target two-qubit gate that cannot be directly executed.

[0072] According to a specific embodiment of the present disclosure, when determining multiple candidate swap gates, swap gates that can perform swap gate operations between the physical qubits corresponding to the target two-qubit gates involved in the precursor layer can also be used as candidate swap gates.

[0073] Figure 4 Schematically shows a schematic diagram of a directed acyclic graph according to a specific embodiment of the present disclosure.

[0074] As Figure 4 shown, the initial directed acyclic graph can be mapped based on the quantum circuit to be executed as shown in Figure 3 shown. This initial directed acyclic graph includes vertices 1 to 4, where vertex 1 can represent Figure 3 the first single-qubit gate shown in Figure 3 shown, vertex 2 can represent Figure 3 the second single-qubit gate shown in Figure 3The 4th two-bit gate shown.

[0075] Among them, the 1st single-bit gate and the 2nd single-bit gate can be directly executed and have no influence on the execution process of the 4th two-bit gate. Therefore, after execution, vertices 1 and 2 can be deleted from the initial directed acyclic graph.

[0076] Among them, based on Figure 2 the connection relationship shown, the 3rd two-bit gate can also be directly executed. Therefore, after execution, vertex 3 can be deleted from the initial directed acyclic graph.

[0077] In this specific embodiment, the directed acyclic graph of the updated quantum circuit to be executed only includes vertex 4. Therefore, in this directed acyclic graph, the predecessor layer includes the 4th two-bit gate indicated by vertex 4, and the successor layer is empty.

[0078] In this specific embodiment, since the qubits involved in the predecessor layer are only Q 1 and Q 3 , the set of alternative swap gates includes {SWAP(1, 2), SWAP(1, 4), SWAP(3, 2), SWAP(3, 4)}.

[0079] According to an embodiment of the present disclosure, determining a target swap gate among multiple alternative swap gates based on the quantum gate density of the quantum circuit to be executed includes: obtaining a density comparison result based on the quantum gate density of the quantum circuit to be executed and a density threshold; and when the density comparison result indicates that the quantum gate density of the quantum circuit to be executed is greater than the density threshold, determining the target swap gate among the multiple alternative swap gates based on the density comparison result and the score of each of the multiple alternative swap gates.

[0080] According to an embodiment of the present disclosure, the density threshold of the quantum circuit to be executed can be preset according to the characteristics of the quantum chip and the complexity of the quantum circuit.

[0081] According to an embodiment of the present disclosure, the quantum gate density of the current quantum circuit to be executed can be obtained by performing a division calculation on the number of target two-bit gates in the quantum circuit to be executed and the number of qubits in the quantum circuit to be executed.

[0082] According to an embodiment of the present disclosure, comparing the quantum gate density of the current quantum circuit to be executed with the preset density threshold can obtain a density comparison result.

[0083] In a specific embodiment of the present disclosure, if the density comparison result indicates that the quantum gate density of the quantum circuit to be executed is greater than the density threshold, it means that the current quantum circuit is relatively complex. Based on the scores of multiple alternative swap gates, a combination selection strategy can be used to select one or more optimal target swap gates to reduce the execution time and error rate. If the density comparison result indicates that the quantum gate density of the quantum circuit to be executed is less than or equal to the density threshold, a single selection strategy can be used to select an optimal target swap gate based on the scores of multiple alternative swap gates.

[0084] According to an embodiment of the present disclosure, determining a target swap gate among multiple alternative swap gates based on the density comparison result and the scores of multiple alternative swap gates respectively includes: calculating the scores of multiple alternative swap gates in the current iteration round based on the average remaining path length of each target two-qubit gate, the execution time of multiple alternative swap gates in the current iteration round, and the occupation time of multiple qubits.

[0085] According to an embodiment of the present disclosure, the scores of multiple alternative swap gates respectively can be obtained based on a heuristic algorithm.

[0086] Specifically, for each alternative swap gate, a score is calculated based on the average remaining path length of the target two-qubit gate it affects, the execution time of this swap gate, and the time during which the qubit is occupied when this swap gate is executed, so as to evaluate each alternative swap gate.

[0087] According to an embodiment of the present disclosure, the average remaining path length of each target two-qubit gate can be determined based on the path lengths between multiple quantum gates. Specifically, based on the topological structure of the quantum chip, the path lengths between multiple quantum gates can be obtained, and based on the path lengths between multiple quantum gates respectively, the average remaining path length of at least one target two-qubit gate can be determined.

[0088] Specifically, the shortest path lengths between any two qubits on the quantum chip can be calculated respectively with and without considering weights. For example, when considering weights, the shortest path lengths between any two qubits can be calculated based on the time for executing two-qubit gates between different qubits on the quantum chip. When not considering weights, the shortest path lengths between any two qubits can be calculated based on algorithms such as breadth-first search (BFS), depth-first search (DFS), or Floyd algorithm, and a shortest path length matrix is initialized to store the shortest path lengths between any two qubits.

[0089] In this specific embodiment, the average remaining path length of each target two-qubit gate can be determined based on the number of quantum gates in the precursor layer, the number of quantum gates in the successor layer, and the shortest path length matrix. The expression for the average remaining path length of each target two-qubit gate is as follows:

[0090] (1);

[0091] In the formula, represents any target two-qubit gate, and this target two-qubit gate needs to be executed between q i and q j . represents the average remaining path length of any target two-qubit gate, represents the number of elements in the set, is the weight parameter. D represents the shortest path length matrix of the quantum chip.

[0092] According to the embodiments of the present disclosure, in the process of evaluating each alternative swap gate, not only the average remaining path length of each target two-qubit gate needs to be considered, but also the state information of the quantum chip and the characteristics of the quantum circuit need to be considered. Among them, the quantum circuit characteristics include the quantum gate density, and the state information of the quantum chip includes the execution time of multiple alternative quantum swap gates and the occupied time of qubits in the quantum chip.

[0093] According to the embodiments of the present disclosure, as the routing process progresses, after each quantum gate is executed, the occupied time of the corresponding physical qubit will be updated. Based on the occupied time of qubits in the quantum chip, when selecting a quantum swap gate, qubits that are idle or have a short occupied time can be given priority, so as to complete the corresponding SWAP operation more quickly. Specifically, the expression for updating the occupied time of physical qubits in the quantum chip is as follows:

[0094] (2);

[0095] In the formula, represents the occupied time of the physical qubit; represents the time required to execute a quantum gate.

[0096] According to the embodiments of the present disclosure, in an actual quantum chip, the time for executing a two-qubit gate (such as a quantum swap gate) between different qubits may be different, and the quantum swap gate is a relatively time-consuming two-qubit gate. Therefore, when selecting a quantum swap gate, the execution time of the alternative quantum swap gate needs to be considered. Under the same other conditions, an alternative quantum swap gate with a shorter execution time can be selected as the target swap gate. Specifically, the expression for the execution time of the alternative swap gate is as follows:

[0097] (3);

[0098] Wherein, cost(s) represents the execution time of the alternative quantum swap gate.

[0099] According to an embodiment of the present disclosure, the state information of the above quantum chip can be used as a coefficient to adjust the average remaining path length of each target two-qubit gate shown in formula (1), so as to accurately evaluate the score of each alternative swap gate by optimizing the heuristic function. Specifically, the expression of the heuristic function optimized based on the state information of the quantum chip is as follows:

[0100] (4);

[0101] Wherein, score(s) represents the score of any alternative swap gate, and G represents the quantum chip; and represent two weight parameters used to adjust the influence degree of different factors in the heuristic function.

[0102] According to an embodiment of the present disclosure, the score of each alternative swap gate can be calculated based on formula (4), so as to be used for scoring evaluation of each alternative swap gate.

[0103] According to an embodiment of the present disclosure, based on the density comparison result and the score of each of the multiple alternative swap gates, determining a target swap gate among the multiple alternative swap gates further includes: determining the alternative swap gate with the lowest score in the current iteration round from the multiple alternative swap gates based on the score of each of the multiple alternative swap gates in the current iteration round to obtain the optimal swap gate in the current iteration round; and when the iteration termination condition is satisfied, determining the optimal swap gate in the current iteration round as the target swap gate.

[0104] According to an embodiment of the present disclosure, the routing method further includes: when the iteration termination condition is not satisfied, determining the overall score of the quantum circuit to be executed in the current iteration round; updating the overall score of the quantum circuit to be executed in the current iteration round based on the score of the optimal swap gate to obtain the overall score of the quantum circuit to be executed in the next iteration round; and deleting the optimal swap gate from the multiple alternative swap gates to update and obtain the multiple alternative swap gates in the next iteration round.

[0105] In a specific embodiment of the present disclosure, if the density comparison result indicates that the quantum gate density of the quantum circuit to be executed is greater than the density threshold, it means that the current quantum circuit is relatively complex. Based on the score of each of the multiple alternative swap gates, a combination selection strategy can be used to select one or more optimal target swap gates to reorder the qubits so as to execute these target two-qubit gates more effectively. Among them, the combination selection strategy can be used to represent finding the optimal set of quantum swap gates in an iterative manner to maximize the execution efficiency of the entire quantum circuit.

[0106] Specifically, an initial score can be set as the overall score of the quantum circuit to be executed, and this overall score can be set to be large enough so that a quantum swap gate that can cause the overall score to decrease can be found during subsequent iterative processes. In addition, an optimal swap gate set is initialized to store the optimal swap gates found in each iteration.

[0107] In this specific embodiment, for each of the multiple alternative swap gates, it can be assumed that the swap gates in the optimal swap gate set have all been executed. On this premise, calculate the score of each alternative swap gate and the impact of the score of each alternative swap gate on the overall score, such as how much the overall score will decrease after executing this alternative swap gate.

[0108] In this specific embodiment, select the alternative swap gate with the lowest score or the alternative swap gate that causes the largest decrease in the overall score in the current iteration round from the multiple alternative swap gates as the optimal swap gate in the previous iteration round, and add it to the optimal swap gate set.

[0109] In this specific embodiment, when the lowest score among the multiple alternative swap gates in the current iteration round is greater than or equal to the overall score of the quantum circuit to be executed in the current iteration round, or when there is no alternative swap gate that can cause the overall score to further decrease, the iteration termination condition is satisfied and the iteration terminates. At this time, the optimal swap gate set includes the optimal combination of swap gates found under the combination selection strategy.

[0110] In this specific embodiment, when the lowest score among the multiple alternative swap gates in the current iteration round is less than the overall score of the quantum circuit to be executed in the current iteration round, or when there is an alternative swap gate whose score can cause the overall score to further decrease, enter the next iteration round. Each time (assuming that the optimal swap gate set has all been executed), select the optimal swap gate that causes the largest decrease in the overall score from it, add it to the optimal swap gate set, and update this overall score based on the score of the optimal swap gate to obtain the overall score of the next iteration round. In addition, delete the swap gates that have been determined to be optimal swap gates and the alternative swap gates that conflict with the optimal swap gates from the alternative swap gate set to update and obtain the alternative swap gate set of the next iteration round until the iteration termination condition is satisfied.

[0111] According to an embodiment of the present disclosure, the routing method further includes: when the density comparison result indicates that the quantum gate density of the quantum circuit to be executed is less than the density threshold, calculating the score of each of the plurality of alternative swap gates based on the average remaining path length between at least one target two-qubit gate, the execution time of each of the plurality of alternative swap gates, and the occupation time of the plurality of qubits; and determining the alternative swap gate with the lowest score among the plurality of alternative swap gates as the target swap gate based on the scores of the plurality of alternative swap gates.

[0112] In a specific embodiment of the present disclosure, if the density comparison result indicates that the quantum gate density of the quantum circuit to be executed is less than or equal to the density threshold, it means that the current quantum circuit is relatively simple. A single selection strategy can be used to select an optimal target swap gate to rearrange the qubits based on the scores of the plurality of alternative swap gates. Specifically, the alternative swap gate with the lowest score can be selected as the optimal swap gate, which can be considered as the swap gate that can most improve the execution efficiency of the quantum circuit under the current conditions.

[0113] Figure 5 The flowchart of the method for determining the target swap gate according to a specific embodiment of the present disclosure is schematically shown.

[0114] In operation S501, the quantum gate density of the quantum circuit to be executed is calculated.

[0115] In operation S502, it is determined whether the quantum gate density of the quantum circuit to be executed is greater than the density threshold. If so, operation S503 is executed to select the optimal swap gate using a combined selection strategy based on the scores of the plurality of alternative swap gates.

[0116] In operation S504, it is determined whether the current iteration process satisfies the iteration termination condition. If so, operation S505 is executed to determine the target swap gate set. If not, operation S506 is executed to update the overall score and the alternative swap gate set for the next iteration round, and operation S503 is re-executed.

[0117] In operation S502, it is determined whether the quantum gate density of the quantum circuit to be executed is greater than the density threshold. If not, operation S507 is executed to select the alternative swap gate with the lowest score as the target swap gate using a single selection strategy.

[0118] Based on this, embodiments of the present disclosure compare the quantum gate density of a quantum circuit with a preset density threshold. When the quantum gate density is high, a more complex combination selection strategy is adopted. By continuously updating the set of candidate swap gates and the overall score, the optimal solution is gradually approximated. When the quantum gate density is low, a simpler single selection strategy is adopted, thus realizing the intelligent switching of the optimization strategy. In addition, during the process of determining the target swap gate, multiple factors such as the average remaining path length of the target two-qubit gate, the execution time of the candidate swap gate, and the occupation time of the qubit are comprehensively considered to minimize the number of qubit movements and the occupation time, thereby reducing the consumption of quantum resources.

[0119] According to an embodiment of the present disclosure, the routing method further includes: using the target swap gate to execute the target two-qubit gate until at least one target two-qubit gate is completely executed, and obtaining the execution result of the quantum circuit to be executed.

[0120] According to an embodiment of the present disclosure, using the target swap gate to execute the target two-qubit gate until at least one target two-qubit gate is completely executed, and obtaining the execution result of the quantum circuit to be executed, includes: for each target two-qubit gate, executing the target swap gate corresponding to each target two-qubit gate to obtain the execution time of the target swap gate and the occupation time of the qubit of the target swap gate; based on the execution time of the target swap gate and the occupation time of the qubit of the target swap gate, updating to obtain the current occupation time of multiple qubits; based on the current occupation time of multiple qubits, determining the target swap gate corresponding to other target two-qubit gates; executing the target swap gate corresponding to other target two-qubit gates until at least one target two-qubit gate is completely executed, and obtaining the execution result of the quantum circuit to be executed.

[0121] According to an embodiment of the present disclosure, after determining the optimal set of target swap gates, these target swap gates can be executed one by one in the order of each target two-qubit gate in the directed acyclic graph. The execution of each target swap gate will change the position of the qubit, so that subsequent two-qubit gates can be executed on the correct qubit pair.

[0122] According to an embodiment of the present disclosure, before executing the target swap gate, if there are some single-qubit gates and their execution does not affect the execution of subsequent target swap gates, for example, these single-qubit gates act on qubits that are irrelevant to the target swap gate, then these single-qubit gates can be executed first to obtain the execution result of the target single-qubit gate, so as to save time and improve the execution efficiency of the quantum circuit.

[0123] According to an embodiment of the present disclosure, after executing the current target two-bit gate in the predecessor layer, the information of the predecessor layer and the successor layer can be updated according to the state information and position of the current qubit. In the predecessor layer, the quantum gates that have been executed can be removed, and the next target two-bit gate will be added to the predecessor layer. At the same time, the states of the gates in the successor layer that need to wait for the execution results of the predecessor layer gates will also be updated.

[0124] According to an embodiment of the present disclosure, after executing the current target two-bit gate in the predecessor layer, it is also necessary to update the occupied time of the physical qubits in the quantum circuit, and then update the scores of each alternative swap gate in the next iteration round.

[0125] Specifically, based on the execution time of each target swap gate, the occupied time of the qubits, and the execution time of the remaining quantum gates, the current occupied states of all qubits in the entire quantum circuit are updated, including updating the idle time and occupied time of each qubit after executing the target swap gate. The remaining quantum gates can be used to represent the remaining quantum gates other than the target swap gate, for example, they can include target single-bit quantum gates, directly executable single-bit quantum gates, and / or two-bit quantum gates. After updating the current occupied time of the qubits, according to the target two-bit gates to be executed subsequently, it can be determined which qubit pairs need to perform the SWAP operation, and the corresponding target swap gates can be found for these qubit pairs. Continue to execute the subsequent target swap gates to ensure that each target two-bit gate can be executed on the correct qubit pairs until all the target two-bit gates in the predecessor layer are executed, and then the routing results of each target two-bit gate in the quantum circuit to be executed can be obtained, and an executable circuit of the quantum circuit to be executed can be generated.

[0126] The following refers to Figures 6 - 8 , and further illustrates the routing method of the quantum circuit in combination with specific embodiments.

[0127] Figure 6 Schematically shows a diagram of the current busy state of qubits according to a specific embodiment of the present disclosure.

[0128] Figure 7 Schematically shows a diagram of the updated busy state of qubits according to a specific embodiment of the present disclosure.

[0129] Figure 8 Schematically shows a diagram of the execution result of the quantum circuit to be executed according to a specific embodiment of the present disclosure.

[0130] Based on Figure 2 the schematic diagram of the topological structure of the quantum chip shown, generally the execution time of a two-bit gate is twice that of a single-bit gate. Therefore, it can be assumed that the execution time of each two-bit gate is 2, and the execution time of each single-bit gate is 1.

[0131] Based on Figure 3 the schematic diagram of the quantum circuit to be executed as shown, on this chip, a quantum circuit containing 3 qubits (q 0 , q 1 , q 2 ) can be executed. For the 3rd quantum gate, that is, the CNOT gate between q 1 and q 2 , since there is a connection between Q 1 and Q 2 , the 3rd quantum gate can be directly executed. Since there are still two H gates to be executed on q 2 , therefore, finally, the 1st quantum gate (H gate), the 2nd quantum gate (H gate), and the 3rd quantum gate (the CNOT gate between q 1 and q 2 ) will be executed in sequence. After the execution is completed, the current busy status of the qubits included in the quantum chip is as Figure 6 shown. Among them, the occupied time interval of Q 1 is [2, 4], and the occupied time interval of Q 2 is [0, 4].

[0132] After the first H gate, the second H gate, and the CNOT gate are executed, the precursor layer and the successor layer can be generated respectively. Among them, the precursor layer includes the 4th quantum gate (the CNOT gate between q 1 and q 3 ), and the successor layer is currently empty because there is no gate that can be executed after it.

[0133] Since the qubits involved in the precursor layer are only Q 1 and Q 3 , therefore, the set of alternative swap gates is {SWAP(1, 2), SWAP(1, 4), SWAP(3, 2), SWAP(3, 4)}.

[0134] Set the density threshold to 0.25. Since the number of elements in the precursor layer is 1 and the number of qubits in the quantum circuit is 3, the quantum gate density of this quantum circuit is 0.33. This quantum gate density is greater than 0.25, and the combined selection strategy can be used to determine the target swap gate.

[0135] In addition, since the execution time of two-qubit gates is 2 for all, therefore, the cost of the execution time of the alternative swap gates, cost, can all be set to log2. In addition, set , , to be 0.1, 1, 0.03 respectively. Based on formula (4), the scores of each alternative swap gate can be calculated as follows:[[]]

[0136] (5);

[0137] In the current iteration round, the candidate SWAP gate with the lowest score is SWAP(3,4). Therefore, SWAP(3,4) is selected as the optimal SWAP gate and added to the set of optimal SWAP gates. At this time, since both SWAP(1,4) and SWAP(3,2) conflict with SWAP(3,4), the remaining candidate SWAP gates in the set are SWAP(1,2). In the next iteration round, continue to select a suitable SWAP gate from the set of candidate SWAP gates. Based on the recalculated score of SWAP(1,2), it can be seen that the recalculated score of SWAP(1,2) does not cause the score = 2.018 to continue to decrease. Therefore, the iteration termination condition is satisfied and the iteration process is terminated. Finally, the set of optimal SWAP gates is {SWAP(3,4)}.

[0138] After executing the set of optimal SWAP gates, the original fourth quantum gate (the CNOT gate between q 1 and q 3 ) can be executed. After executing this CNOT gate, the current busy state of the qubits included on the quantum chip is updated, and the updated busy state is as shown in Figure 8 , where the originally idle Q 3 and Q 4 are currently also in a busy state.

[0139] After executing the fourth quantum gate (the CNOT gate between q 1 and q 3 ), the predecessor layer is empty. Therefore, the execution result of the final quantum circuit to be executed can be generated, as shown in Figure 8 , including the first quantum gate (H gate), the second quantum gate (H gate), the third quantum gate (the CNOT gate between q 1 and q 2 ), the SWAP gate, and the fourth quantum gate (the CNOT gate between q 1 and q 4 ).

[0140] Figure 9 Schematically shows a schematic diagram of the execution result of the quantum circuit to be executed according to a specific embodiment of the present disclosure.

[0141] In a specific embodiment, a quantum chip with a relatively large number of quantum circuit qubits (at least 28 and at most 130) can be selected for testing, as shown in Figure 9As shown, by using existing quantum circuit routing methods such as the IBM torino method and the quantum circuit routing method proposed in the present disclosure to test 30 different quantum circuits and quantum chips of the same scale, the execution time and circuit depth are used as the basic evaluation indicators. As Figure 9 shown, the results obtained by testing 30 quantum circuits using the quantum circuit routing method proposed in the present disclosure show that, compared with the existing method, the execution time is reduced by an average of 31% and the quantum circuit depth is reduced by 34%.

[0142] It should be noted that unless it is clearly stated that there is a sequential execution order between different operations in the flowcharts shown in the embodiments of the present disclosure, or there is a sequential execution order between different operations in the technical implementation, the execution order between multiple operations can be unordered, and multiple operations can also be executed simultaneously.

[0143] Figure 10 The block diagram of a quantum circuit routing device according to an embodiment of the present disclosure is schematically shown.

[0144] As Figure 10 shown, the quantum circuit routing device 1000 includes a first determination module 1010, a second determination module 1020, a third determination module 1030, a fourth determination module 1040, and a fifth determination module 1050.

[0145] The first determination module 1010 is configured to determine at least one target two-bit gate based on multiple quantum gates of the quantum circuit to be executed and the initial mapping result of the quantum circuit to be executed.

[0146] The second determination module 1020 is configured to determine a plurality of alternative swap gates based on the connection attributes of the qubits of at least one target two-bit gate.

[0147] The third determination module 1030 is configured to obtain the quantum gate density of the quantum circuit to be executed based on the number of target two-bit gates in the quantum circuit to be executed and the number of qubits of the quantum circuit to be executed.

[0148] The fourth determination module 1040 is configured to, for each target two-bit gate, determine a target swap gate from among the plurality of alternative swap gates based on the quantum gate density of the quantum circuit to be executed and the state information of the quantum chip.

[0149] The fifth determination module 1050 is configured to determine the routing result of each target two-bit gate in the quantum circuit to be executed based on the target swap gate corresponding to each target two-bit gate.

[0150] Any of a plurality of modules, sub-modules, units, and sub-units according to embodiments of the present disclosure, or at least part of the functions of any of them, may be implemented in one module. Any one or more of the modules, sub-modules, units, and sub-units according to embodiments of the present disclosure may be split into multiple modules for implementation. Any one or more of the modules, sub-modules, units, and sub-units according to embodiments of the present disclosure may be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application specific integrated circuit (ASIC), or may be implemented by any other reasonable way of integrating or packaging circuits, or implemented in any one of the three implementation manners of software, hardware, and firmware, or in a suitable combination of any several of them. Alternatively, one or more of the modules, sub-modules, units, and sub-units according to embodiments of the present disclosure may be at least partially implemented as a computer program module, and when the computer program module is run, the corresponding functions may be executed.

[0151] For example, any of the first determination module 1010, the second determination module 1020, the third determination module 1030, the fourth determination module 1040, and the fifth determination module 1050 may be combined and implemented in one module / unit / sub-unit, or any one of the module / unit / sub-unit may be split into multiple modules / units / sub-units. Alternatively, at least part of the functions of one or more of these modules / units / sub-units may be combined with at least part of the functions of other modules / units / sub-units and implemented in one module / unit / sub-unit. According to embodiments of the present disclosure, at least one of the first determination module 1010, the second determination module 1020, the third determination module 1030, the fourth determination module 1040, and the fifth determination module 1050 may be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application specific integrated circuit (ASIC), or may be implemented by any other reasonable way of integrating or packaging circuits, or implemented in any one of the three implementation manners of software, hardware, and firmware, or in a suitable combination of any several of them. Alternatively, at least one of the first determination module 1010, the second determination module 1020, the third determination module 1030, the fourth determination module 1040, and the fifth determination module 1050 may be at least partially implemented as a computer program module, and when the computer program module is run, the corresponding functions may be executed.

[0152] It should be noted that the routing device part of the quantum circuit in the embodiments of the present disclosure corresponds to the routing method part of the quantum circuit in the embodiments of the present disclosure. For the description of the routing device part of the quantum circuit, please specifically refer to the routing method part of the quantum circuit, which will not be elaborated here.

[0153] Figure 11 A block diagram of an electronic device suitable for implementing the routing method of a quantum circuit according to an embodiment of the present disclosure is schematically shown. Figure 11 The electronic device shown is only an example and should not impose any limitations on the functions and usage scope of the embodiments of the present disclosure.

[0154] As Figure 11 shown, the computer electronic device according to an embodiment of the present disclosure includes a processor 1101, which can perform various appropriate actions and processes according to a program stored in a read-only memory ROM 1102 or a program loaded from a storage section 1108 into a random access memory RAM 1103. The processor 1101 may include, for example, a general microprocessor (such as a CPU), an instruction set processor, and / or a related chipset, and / or a dedicated microprocessor (such as an application specific integrated circuit (ASIC)), and so on. The processor 1101 may also include on-board memory for caching purposes. The processor 1101 may include a single processing unit or multiple processing units for performing different actions of the method flow according to the embodiments of the present disclosure.

[0155] In the RAM 1103, various programs and data required for the operation of the electronic device are stored. The processor 1101, ROM 1102, and RAM 1103 are connected to each other through a bus 1104. The processor 1101 performs various operations of the method flow according to the embodiments of the present disclosure by executing the programs in the ROM 1102 and / or RAM 1103. It should be noted that the program may also be stored in one or more memories other than the ROM 1102 and RAM 1103. The processor 1101 may also perform various operations of the method flow according to the embodiments of the present disclosure by executing the programs stored in the one or more memories.

[0156] According to an embodiment of the present disclosure, the electronic device may further include an input / output (I / O) interface 1105, and the input / output (I / O) interface 1105 is also connected to the bus 1104. The electronic device may further include one or more of the following components connected to the input / output (I / O) interface 1105: an input portion 1106 including a keyboard, a mouse, etc.; an output portion 1107 including, for example, a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage portion 1108 including a hard disk, etc.; and a communication portion 1109 including a network interface card such as a LAN card, a modem, etc. The communication portion 1109 performs communication processing via a network such as the Internet. A driver 1110 is also connected to the input / output (I / O) interface 1105 as needed. A removable medium 1111, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the driver 1110 as needed, so that a computer program read from it can be installed into the storage portion 1108 as needed.

[0157] According to an embodiment of the present disclosure, the method flow according to the embodiment of the present disclosure can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable storage medium, and the computer program includes program codes for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication portion 1109, and / or installed from the removable medium 1111. When the computer program is executed by the processor 1101, the above functions defined in the system of the embodiment of the present disclosure are executed. According to an embodiment of the present disclosure, the above-described system, device, apparatus, module, unit, etc. can be implemented by computer program modules.

[0158] The present disclosure also provides a computer-readable storage medium, which may be included in the device / device / system described in the above embodiment; or may exist separately without being assembled into the device / device / system. The above computer-readable storage medium carries one or more programs, and when the above one or more programs are executed, the method according to the embodiment of the present disclosure is implemented.

[0159] According to an embodiment of the present disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium. For example, it may include but is not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In the present disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program, and the program can be used by or in combination with an instruction execution system, apparatus, or device.

[0160] For example, according to an embodiment of the present disclosure, the computer-readable storage medium may include one or more memories other than the above-described ROM 1102 and / or RAM 1103 and / or ROM 1102 and RAM 1103.

[0161] An embodiment of the present disclosure also includes a computer program product, which includes a computer program. The computer program contains program code for executing the method provided by the embodiment of the present disclosure. When the computer program product runs on an electronic device, the program code is used to cause the electronic device to implement the parallel mapping method of the quantum circuit provided by the embodiment of the present disclosure.

[0162] When the computer program is executed by the processor 1101, the above functions defined in the system / apparatus of the embodiment of the present disclosure are executed. According to an embodiment of the present disclosure, the above-described systems, apparatuses, modules, units, etc. may be implemented by computer program modules.

[0163] In one embodiment, the computer program may rely on tangible storage media such as optical storage devices and magnetic storage devices. In another embodiment, the computer program may also be transmitted and distributed in the form of a signal on a network medium, and downloaded and installed through the communication part 1109, and / or installed from the removable medium 1111. The program code contained in the computer program can be transmitted by any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0164] According to embodiments of the present disclosure, program code for executing the computer programs provided by the embodiments of the present disclosure can be written in any combination of one or more programming languages. Specifically, these computing programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. The programming languages include, but are not limited to, programming languages such as Java, C++, Python, the "C" language, or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device can be connected to the user's computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (e.g., by connecting through the Internet using an Internet service provider).

[0165] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, it should also be noted that each block in the block diagram or flowchart, and the combination of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions. Those skilled in the art can understand that the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.

[0166] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments are described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A routing method for a quantum circuit, wherein: The method comprises: Determining at least one target two-bit gate based on a plurality of quantum gates of a quantum circuit to be executed and an initial mapping result of the quantum circuit to be executed, wherein the at least one target two-bit gate is a quantum gate that cannot be directly executed, and the initial mapping result represents an initial position obtained by sequentially mapping the plurality of quantum bits to a quantum chip structure in a preset order; determining a plurality of candidate exchange gates based on the connectivity properties of the qubits of the at least one target two-bit gate; Based on the target number of two-bit gates in the quantum circuit to be executed and the number of quantum bits of the quantum circuit to be executed, obtaining the quantum gate density of the quantum circuit to be executed; For each target two-bit gate, based on the quantum gate density of the quantum circuit to be executed and the state information of the quantum chip, determine the target exchange gate from the multiple candidate exchange gates; Based on the target exchange gate corresponding to each target two-bit gate, a routing result of each target two-bit gate in the to-be-executed quantum circuit is determined.

2. The routing method according to claim 1, wherein: The step of determining a target switching gate from the plurality of candidate switching gates based on the quantum gate density of the quantum circuit to be executed and the state information of the quantum chip comprises: Obtaining a density comparison result based on the quantum gate density and density threshold of the quantum circuit to be executed; When the density comparison result indicates that the quantum gate density of the to-be-executed quantum circuit is greater than the density threshold, the target exchange gate is determined from the multiple candidate exchange gates based on the state information of the quantum chip and the scores of the multiple candidate exchange gates.

3. The routing method according to claim 2, wherein: The state information of the quantum chip includes the execution time of each of the plurality of candidate exchange gates and the occupation time of the plurality of quantum bits. Based on the state information of the quantum chip and the scores of each of the plurality of candidate exchange gates, determining the target exchange gate from the plurality of candidate exchange gates includes: Based on the average remaining path length of each of the at least one target two-bit gates, the execution time of each of the multiple candidate exchange gates in the current iteration round, and the occupation time of the multiple quantum bits, the scores of each of the multiple candidate exchange gates in the current iteration round are calculated; Based on the scores of the multiple candidate exchange gates in the current iteration round, determine the candidate exchange gate with the lowest score in the current iteration round from the multiple candidate exchange gates to obtain the optimal exchange gate in the current iteration round; When the iteration termination condition is met, the optimal exchange gate of the current iteration round is determined as the target exchange gate, wherein the iteration termination condition represents that the lowest score of the multiple candidate exchange gates in the current iteration round is greater than or equal to the overall score of the quantum circuit to be executed in the current iteration round.

4. The routing method according to claim 3, wherein: The method further comprises: When the iteration termination condition is not met, determining the overall score of the quantum circuit to be executed in the current iteration round; Based on the score of the optimal exchange gate, the overall score of the quantum circuit to be executed in the current iteration round is updated to obtain the overall score of the quantum circuit to be executed in the next iteration round; The optimal exchange gate and the candidate exchange gates that conflict with the optimal exchange gate are deleted from the multiple candidate exchange gates to update multiple candidate exchange gates for the next iteration round.

5. The routing method according to claim 2, wherein: The method further comprises: When the density comparison result indicates that the quantum gate density of the quantum circuit to be executed is less than the density threshold, Based on the average remaining path length between each of the at least one target two-bit gates, the execution time of each of the multiple candidate exchange gates, and the occupation time of the multiple quantum bits, the scores of each of the multiple candidate exchange gates are calculated; Based on the scores of the multiple candidate exchange gates, the candidate exchange gate with the lowest score among the multiple candidate exchange gates is determined as the target exchange gate.

6. The routing method according to claim 2, wherein: The method further comprises: Based on the topological structure of the quantum chip, obtaining the path lengths between the plurality of quantum gates; An average remaining path length of the at least one target two-bit gate is determined based on the path lengths between the plurality of quantum gates.

7. The routing method according to claim 1, wherein: The method further comprises: The target two-bit gate is executed by using the target exchange gate until all of the at least one target two-bit gate is executed, thereby obtaining an execution result of the quantum circuit to be executed.

8. The routing method according to claim 7, wherein: The execution result of the quantum circuit to be executed also includes the execution result of the target single-bit gate. Before executing the target two-bit gate by using the target exchange gate until at least one target two-bit gate is fully executed and the execution result of the quantum circuit to be executed is obtained, the method further includes: Screening out a target single-bit gate from the plurality of quantum gates that has no influence on the execution process of the target exchange gate during execution; The target single-bit gate is executed to obtain an execution result of the target single-bit gate.

9. The routing method according to claim 8, wherein: Executing the target two-bit gate using the target exchange gate until all of the at least one target two-bit gate is executed, and obtaining the execution result of the quantum circuit to be executed, including: For each target two-bit gate, execute the target exchange gate corresponding to each target two-bit gate to obtain the execution time of the target exchange gate and the occupation time of the quantum bit of the target exchange gate; Based on the execution time of the target exchange gate, the occupation time of the quantum bits of the target exchange gate, and the execution time of the remaining quantum gates, the current occupation time of the plurality of quantum bits is updated; Determining target exchange gates corresponding to other target two-bit gates based on current occupation times of the plurality of quantum bits; The target exchange gates corresponding to the other target two-bit gates are executed until the at least one target two-bit gate is completely executed, and an execution result of the quantum circuit to be executed is obtained.

10. A routing device for a quantum circuit, wherein: The device comprises: A first determination module is used to determine at least one target two-bit gate based on a plurality of quantum gates of a quantum circuit to be executed and an initial mapping result of the quantum circuit to be executed, wherein the at least one target two-bit gate is a quantum gate that cannot be directly executed, and the initial mapping result represents an initial position obtained by sequentially mapping the plurality of quantum bits to a quantum chip structure in a preset order; A second determination module, configured to determine a plurality of candidate exchange gates based on the connection properties of the quantum bits of the at least one target two-bit gate; A third determination module is used to obtain the quantum gate density of the quantum circuit to be executed based on the target number of two-bit gates in the quantum circuit to be executed and the number of quantum bits of the quantum circuit to be executed; A fourth determination module is used to determine, for each target two-bit gate, a target exchange gate from the multiple candidate exchange gates based on the quantum gate density of the quantum circuit to be executed and the state information of the quantum chip; The fifth determination module is used to determine the routing result of each target two-bit gate in the to-be-executed quantum circuit based on the target exchange gate corresponding to each target two-bit gate.

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