On-chip termination signal generation circuit and memory system

Abstract

The on-chip termination signal generation circuit and the storage system provided by the present disclosure are applied to a storage system, the storage system comprising a memory having an on-chip termination control circuit, and the on-chip termination signal generation circuit comprises a generation circuit, a delay circuit and an output circuit. The generation circuit is configured to receive an initial signal, output a first signal and an indication signal in response to a clock signal; the indication signal is used to indicate a first burst length; the active level period of the first signal is a first time length; the delay circuit is configured to perform delay processing on the first signal and output a second signal; and the output circuit is configured to receive the indication signal and the second signal and output an on-chip termination signal; the width of the active level of the on-chip termination signal is generated according to the indication signal. The on-chip termination signal used to control the state of the termination circuit is generated by the on-chip termination signal generation circuit, so as to ensure the accuracy of data writing.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more particularly to an on-chip termination signal generation circuit and storage system. Background Technology

[0002] Currently, on-die termination (ODT) control circuits are typically set in memory. The on-die termination control circuit adjusts the mode of the termination resistance (RTT) based on the on-die termination signal generated by the on-die termination signal generation circuit, thereby reducing signal reflection.

[0003] Therefore, how to design an ODT generation circuit to control the RTT state is the problem addressed by this disclosure. Summary of the Invention

[0004] The on-chip termination signal generation circuit and storage system disclosed herein are used to provide an on-chip termination signal generation circuit to achieve effective control of RTT.

[0005] In a first aspect, this disclosure provides an on-chip termination signal generation circuit applied to a storage system, the storage system including a memory with on-chip termination control circuitry, the on-chip termination signal generation circuit comprising: a generation circuit, a delay circuit, and an output circuit; wherein...

[0006] The generation circuit is configured to receive an initial signal, respond to a clock signal, and output a first signal and an indication signal; wherein, the initial signal is used to indicate the state of the termination resistor at the data terminal; the indication signal is used to indicate a first burst length; the first burst length is the current burst length of the memory; and the effective level period of the first signal is a first duration.

[0007] The delay circuit is used to receive the first signal, perform delay processing on the first signal, and output the second signal;

[0008] The output circuit is used to receive the indication signal and the second signal, and output an on-chip termination signal. The on-chip termination control circuit receives the on-chip termination signal to adjust the state of the termination resistor at the data terminal. The effective level width of the on-chip termination signal is selected and generated according to the indication signal.

[0009] In some embodiments, the first duration is a fixed value of the data write duration corresponding to the second burst length; the second burst length is the minimum value among the burst lengths supported by the memory;

[0010] Alternatively, the first duration may be a fixed value that is less than the data write duration corresponding to the second burst length.

[0011] In some embodiments, the generation circuit includes: a first generation module, a first acquisition module, and a first encoding module; the encoding module and the first acquisition module are connected.

[0012] The first generation module is configured to generate a first signal in response to the received initial signal and clock signal;

[0013] The first acquisition module is configured to, in response to the received initial signal, determine the first burst length in the first register and output the first burst length;

[0014] The first encoding module is used to receive the first burst length and output an indication signal according to the first burst length and a first correspondence relationship; the first correspondence relationship represents the correspondence between the burst length and the indication signal.

[0015] In some embodiments, if the first burst length is greater than the third burst length, then the first duration is the data writing duration corresponding to the third burst length; the third burst length is a value selected from the burst lengths supported by the memory, excluding the maximum value.

[0016] In some embodiments, the generation circuit includes: a second acquisition module, a comparison module, a second generation module, and a second encoding module;

[0017] The second acquisition module is configured to, in response to the received initial signal, determine the first burst length in the first register and output the first burst length;

[0018] The comparison module is used to receive the first burst length and output a comparison result based on the first burst length and the third burst length; the comparison result is used to characterize the size relationship between the first burst length and the third burst length.

[0019] The second generation module is configured to output a first signal if it is determined that the comparison result indicates that the first burst length is greater than the third burst length;

[0020] The second encoding module is used to receive the first burst length and output an indication signal according to the first burst length and the second correspondence; the second correspondence represents the correspondence between the burst length and the indication signal.

[0021] In some embodiments, the generation circuit further includes:

[0022] The third generation module is connected to the comparison module. The third generation module is used to generate a third signal with a width of a second value for the effective level if the comparison result indicates that the first burst length is less than or equal to the third burst length, and to determine that the third signal is a first signal and output the first signal to the delay circuit; the second value is the data writing duration corresponding to the first burst length.

[0023] In some embodiments, the output circuit includes a data selector and a plurality of first processing modules; wherein,

[0024] The first processing module is used to receive the second signal and increase the width of the effective level of the second signal to obtain a first candidate signal; wherein, the width of the effective level of the first candidate signal output by different first processing modules is different;

[0025] The data selector is used to receive the indication signal and the first candidate signal output by the generation circuit, and to determine and output the on-chip termination signal from a plurality of first candidate signals according to the indication signal.

[0026] In some embodiments, the output circuit includes: a plurality of second processing modules and a switching module corresponding to the second processing modules;

[0027] The second processing module is used to receive the second signal and increase the width of the effective level of the second signal to obtain a second candidate signal; wherein the width of the effective level of the second candidate signal output by different second processing modules is different;

[0028] The switch module is configured to receive the indication signal, and in response to the indication signal, control the switch module to be turned on, determine the second candidate signal generated by the second processing module connected to the switch module as the on-chip termination signal, and output the on-chip termination signal.

[0029] In some embodiments, the delay between the effective edge of the second signal and the effective edge of the first signal is the difference between the third value and the first loss time.

[0030] The third value is the sum of the memory write delay and the state switching time of the termination resistor; the first loss time is the transmission time from the output of the on-chip termination signal to the receiving end of the on-chip termination signal.

[0031] In some embodiments, the delay circuit includes a sampling module and a third processing module; the sampling module and the third processing module are connected.

[0032] The sampling module is configured to receive the first signal and, in response to the clock signal, sample the first signal; if the level value of the sampled signal is determined to be valid, a shift signal is output; the width of the valid level period of the shift signal is the same as the width of the valid level period of the first signal.

[0033] The third processing module is used to perform delay processing on the received shift signal according to a preset delay duration and output a second signal, wherein the preset delay duration is the difference between the third value and the second loss time; the second loss time is the difference between the time when the sampling module samples the effective value of the first signal and the time when the sampling module receives the first signal at the effective value.

[0034] In a second aspect, this disclosure provides a storage system comprising a memory having an on-chip termination control circuit and an on-chip termination signal generation circuit as described in any one of the first aspects.

[0035] The on-chip termination signal generation circuit and storage system disclosed herein are applied to a storage system, the storage system including a memory with an on-chip termination control circuit. The on-chip termination signal generation circuit includes: a generation circuit, a delay circuit, and an output circuit. The generation circuit receives an initial signal and, in response to a clock signal, outputs a first signal and an indication signal. The initial signal indicates the state of adjusting the termination resistor at the data terminal. The indication signal indicates a first burst length, which is the current burst length of the memory. The effective level period of the first signal is a first duration. The delay circuit receives the first signal, delays it, and outputs a second signal. The output circuit receives the indication signal and the second signal, and outputs an on-chip termination signal. The on-chip termination control circuit receives the on-chip termination signal to adjust the state of the termination resistor at the data terminal. The effective level width of the on-chip termination signal is selected and generated based on the indication signal. Furthermore, the on-chip termination signal generated by the above-described on-chip termination signal generation circuit is used to control the RTT state, ensuring the accuracy of data writing. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1This disclosure provides a signal timing diagram;

[0038] Figure 2 This is a structural diagram of an on-chip termination signal generation circuit provided in this disclosure;

[0039] Figure 3 This is yet another signal timing diagram provided in this disclosure;

[0040] Figure 4 This is a schematic diagram of an on-chip termination signal generation circuit provided in an embodiment of the present disclosure;

[0041] Figure 5 This is a schematic diagram of the structure of a second on-chip termination signal generation circuit provided in an embodiment of this disclosure;

[0042] Figure 6 This is a schematic diagram of the structure of a third on-chip termination signal generation circuit provided in an embodiment of this disclosure;

[0043] Figure 7 This is a schematic diagram of the structure of the fourth on-chip termination signal generation circuit provided in the embodiments of this disclosure;

[0044] Figure 8 This is a schematic diagram of the structure of the fifth on-chip termination signal generation circuit provided in the embodiments of this disclosure;

[0045] Figure 9 This is a schematic diagram of the sixth on-chip termination signal generation circuit provided in the embodiments of this disclosure;

[0046] Figure 10 This is yet another signal schematic diagram provided for an embodiment of the present disclosure.

[0047] Explanation of reference numerals in the attached figures:

[0048] 101: Generation circuit; 102: Delay circuit; 103: Output circuit;

[0049] 1011: First generation module; 1012: First acquisition module; 1013: First encoding module;

[0050] 1014: Second acquisition module; 1015: Comparison module; 1016: Second generation module; 1017: Second encoding module; 1018: Third generation module;

[0051] 1021: Sampling module; 1022: Third processing module;

[0052] 1031: First processing module; 1032: Data selector;

[0053] 1033: Second processing module; 1034: Switch module. Detailed Implementation

[0054] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure.

[0055] Currently, in order to ensure the accuracy of signal transmission and avoid memory malfunctions caused by signal reflection, a termination resistor is usually set at the data (dq) end of the memory.

[0056] Figure 1 This is a signal timing diagram provided in this disclosure. For example... Figure 1 As shown, Figure 1 Specifically, this is a timing diagram of the memory receiving a write signal. In related technologies, when the memory receives a write command, the state of the termination resistor at the data terminal needs to be adjusted from RTT-PARK to RTT-WR before the data to be written is received at the data terminal. The time from receiving the write command to the termination resistor adjusting to RTT-WR is represented by tODTLon_WR, where tODTLon_WR = CWL + ODTLon_WR_offset. In the above formula, CWL (CAS Write Latency) is the time from the activation of the write command to the first data write. ODTLon_WR_offset can be understood as the enable offset, an adjustment value issued by the controller to indicate the switching time from RTT-PARK to RTT-WR. Furthermore, a certain switching time is required during the RTT state switch, which is generally represented by tADC.

[0057] After data writing is complete, the RTT needs to be switched from the RTT-WR state to the RTT-PARK state. To ensure the timing requirements of the RTT state switching, the ODT signal generation circuit needs to generate the ODT_CMD signal (referred to as the on-chip termination signal in this disclosure) and send the generated on-chip termination signal to the ODT control circuit so that the ODT control circuit can switch the RTT resistance value before and after data writing. Furthermore, the duration corresponding to the effective level of ODT-CMD needs to be offset by a certain amount based on the data writing duration. This offset can be represented by the following formula: ODT_offset

[0058] ODT_offset=ODTLoff_WR_offset-ODTLon_WR_offset

[0059] ODTLoff_WR_offset can be understood as the offset between the time when data reception ends and the time when the RTT-WR state is switched back to RTT-PARK, which is the shutdown offset mentioned in this disclosure.

[0060] It should be noted that the number of data bits transmitted in a single pulse varies depending on the BL mode. In different BL modes, the duration of the effective level of the aforementioned ODT_CMD signal must be greater than or equal to the data transmission duration corresponding to the BL mode. Furthermore, the aforementioned enable and disable offsets are set by the memory's controller, and their values ​​must meet the range specified in the protocol. Table 1 below shows the value ranges set for DDR5 memory.

[0061]

[0062] Table 1. Specified Offset Value Range

[0063] In Table 1 above, P indicates a valid value, and X indicates an invalid value. For example, the controller can set the values ​​for the on offset and the off offset to -4 and 4 respectively, but it is not allowed to set them to 2 and -2.

[0064] Figure 2 This is a structural diagram of an on-chip termination signal generation circuit provided in this disclosure. Figure 3 This is yet another signal timing diagram provided in this disclosure, specifically, using... Figure 3 The signal timing changes in the middle to Figure 2 The working principle of the on-chip termination signal generation circuit provided in this paper is explained. Figure 2 and Figure 3 Signals with the same name are considered the same signal. For example... Figure 2As shown, the on-chip termination signal generation circuit in the related technology includes three circuit modules connected in sequence (i.e., the first circuit module, the second circuit module, and the third circuit module in the figure). When the memory receives a write instruction, it triggers the generation of a signal to indicate the adjustment of the RTT state, represented by CMD_IN in the figure; and CKT in the figure is used to represent the external clock signal received by the memory, and CLK is used to represent the internal clock signal of the memory. After the first circuit module receives CMD_IN, the first circuit module generates a Burst_out signal based on the internal clock signal and transmits the Burst_out signal to the second circuit module connected to the first circuit module. The effective level period of the Burst_out signal includes the data write duration corresponding to the current burst length of the memory. For example, when the burst length is 8 and one clock cycle is 2tck, the effective level period of the Burst_out signal generated by the first circuit module is 4tck; when the burst length is 16 and one clock cycle is 2tck, the effective level period of the Burst_out signal generated by the first circuit module is 8tck.

[0065] After receiving the Burst_out signal, the second circuit module delays the signal based on its internal clock signal, the current data write duration, and the enable offset. It then transmits the resulting ODT_shift signal to the third circuit module connected to the second circuit module. This delay processing by the second circuit module adjusts the start time of the effective level of the final generated ODT_out signal, i.e., the switching time from RTT-PARK to RTT-WR.

[0066] After receiving the ODT_shift signal, the third circuit module further adjusts the duration of the effective level period of the ODT_shift signal. Specifically, it adds ODT_offset to the effective level period corresponding to the Burst_out signal to obtain the final ODT_out signal. In essence, the third circuit module is mainly used to adjust the end time of the effective level period of the final generated ODT signal, which in turn adjusts the switching time from RTT-WR to RTT-PARK.

[0067] However, the values ​​of the enable offset and disable offset in ODT_offset in the above circuit need to be selected with reference to the valid value range in Table 1.

[0068] This disclosure provides an on-chip termination signal generation circuit and a memory system. When the on-chip termination signal generation circuit generates the final on-chip termination signal, the generation circuit 101 generates a first signal with an effective level period of a first duration. Furthermore, in order to ensure that the effective level period of the final generated on-chip termination signal is greater than or equal to the aforementioned data writing duration, the output circuit 103 also generates an on-chip termination signal corresponding to the first burst length based on the indication signal generated by the generation circuit 101, thereby realizing the control of the RTT state.

[0069] The technical solutions of this disclosure and how they solve the aforementioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0070] Figure 4 This is a schematic diagram of an on-chip termination signal generation circuit provided in an embodiment of the present disclosure. The on-chip termination signal generation circuit in this embodiment is used in a storage system, wherein the storage system includes a memory with on-chip termination control circuitry. Figure 4 As shown, the on-chip termination signal generation circuit in this embodiment includes: a generation circuit 101, a delay circuit 102, and an output circuit 103. The generation circuit 101 receives an initial signal CMD and, triggered by a clock signal, outputs a first signal (represented by Burst_out in the figure) and an indication signal. The initial signal indicates the state of adjusting the termination resistor at the data terminal. The effective level period of the first signal is a first duration. The first burst length is the current burst length of the memory, and the indication signal indicates the first burst length. The delay circuit 102 receives the first signal, delays the first signal Burst_out, and outputs a second signal (represented by latency_out in the figure). The output circuit 103 receives the indication signal and the second signal latency_out, outputs the on-chip termination signal (CMD_out), and sends the on-chip termination signal to the on-chip termination control circuit, so that the on-chip termination control circuit adjusts the state of the termination resistor at the data terminal based on the on-chip termination signal.

[0071] For example, in this embodiment, the on-chip termination circuit includes a generation circuit 101, a delay circuit 102, and an output circuit 103. The generation circuit 101, delay circuit 102, and output circuit 103 operate under the same clock signal. It should be noted that the clock signal CLK here is the internal clock signal of the memory.

[0072] When the storage system determines that it has received a write command signal requiring data to be written to the memory, the storage system internally generates an initial signal CMD and transmits it to the generation circuit 101 to inform the generation circuit 101 that the state of the termination resistor at the memory data terminal needs to be adjusted. Triggered by the initial signal CMD and the clock signal CLK, the generation circuit 101 generates a first signal with an effective level period of a first duration. It should be noted that this first duration is a fixed value; that is, the value of the first duration is independent of the current burst length of the memory.

[0073] In addition, in this embodiment, the generation circuit 101 also generates an indication signal and sends the indication signal to the output circuit 103 connected to the generation circuit 101, so that the output circuit 103 can determine the width of the effective level of the final on-chip termination signal CMD_out according to the burst length indicated by the indication signal.

[0074] After the delay circuit 102 receives the first signal Burst_out, it delays the first signal Burst_out to determine the RTT state switching time based on the effective edge of the second signal latency_out obtained after the delay. For example, when the delay circuit 102 delays the first signal Burst_out, the delay duration can be determined based on the write latency (WL) and ODTLon_WR_offset, thus ensuring that the on-chip termination signal generated before the data terminal of the memory receives the data to be written has controlled the RTT state switching of the data terminal. The specific working principle here can be found in the principle description in related technologies, and will not be repeated here. After the delay circuit 102 generates the second signal, it transmits the generated second signal to the output circuit 103.

[0075] When the output circuit 103 receives the second signal latency_out, it will adjust the width of the effective level of the second signal latency_out in conjunction with the first burst length indicated by the indicator signal, so as to obtain an on-chip termination signal that conforms to the current first burst length.

[0076] In this embodiment, the on-chip termination circuit first generates a first signal with an effective level period of a first duration, then delays the first signal, and adjusts the width of the effective level of the second signal obtained after the delay based on an indication signal, so that the RTT state can be switched accurately and effectively based on the generated on-chip termination signal.

[0077] In one possible implementation, when the first duration is less than the data write duration of the first burst length, to ensure that the effective level width of the final output on-chip termination signal meets the requirements of the current data write duration of the first burst length, the output circuit 103 needs to widen the received second signal latency_out. Furthermore, in this embodiment, the effective level width of the second signal latency_out is less than the data write duration of the first burst length, and the widening amount by which the output circuit 103 widens the effective level of the second signal latency_out can be the sum of a first value and ODT_offset. The first value is the difference between the effective level width of the second signal latency_out and the data write duration corresponding to the first burst length. Compared to... Figure 2 In this embodiment, the effective level width is ultimately generated as WL + ODT_offset. The generation circuit 101 reduces the duration of the effective level period of the generated signal. Consequently, the width of the on-chip termination signal output by the output circuit 103 relative to the second signal latency_out changes from ODT_offset in related technologies to the sum of ODT_offset and the first value in this disclosure. Since the first value is greater than 0, ODT_offset can be less than 0. Figure 2 The circuit shown only supports the pulse widening processing method in Table 1 where ODT_offset is greater than or equal to 0. The method in this embodiment increases the value range of ODT_offset, that is, the value range of ODT_offset can also include [-4tck, 0], thereby increasing the value range of ODTLoff_WR_offset and ODTLon_WR_offset, so that the ODT signal generation circuit can be adapted to various different values ​​of start offset and end offset.

[0078] In some embodiments, the first duration is a fixed value of the data write duration corresponding to the second burst length; the second burst length is the minimum value among the burst lengths supported by the memory; or, the first duration is a fixed value that is less than the data write duration corresponding to the second burst length.

[0079] For example, in this embodiment, based on the above embodiment, when the first duration is a fixed value less than the data write duration corresponding to the minimum burst length (i.e., the second burst length) supported by the memory, the effective level period of the first signal Burst_out output by the generation circuit 101 is less than the data write duration corresponding to the first burst length it currently corresponds to.

[0080] Furthermore, in this embodiment, the effective level period of the first signal output by the generation circuit 101 is a fixed value, meaning that the effective level period of the first signal Burst_out output in any burst length mode is the same, and this fixed value is less than the data write duration corresponding to the second burst length. For example, assuming that the burst lengths supported by the memory include 8 and 16, and the data write duration corresponding to a burst length of 8 is 4 tck and the data write duration corresponding to a burst length of 16 is 8 tck, then the aforementioned first duration can be 2 tck, meaning that regardless of whether the memory operates in a burst length mode of 8 or 16, the effective level period of the first signal Burst_out output by the corresponding generation circuit 101 is always 2 tck.

[0081] It is understood that in this embodiment, the effective level period of the first signal ultimately output by the generation circuit 101 is the same in multiple burst length modes. This not only increases the value of ODT_offset corresponding to the memory in multiple burst length modes, but also, since the generation circuit 101 only needs to output one first signal, it is further more efficient than... Figure 2 The method of adjusting the effective level period of the output Burst_out signal according to the current burst length of the memory in the first circuit module can also reduce the circuit complexity of the generation circuit 101.

[0082] Alternatively, the first duration can also be the data write duration corresponding to the second burst length. For example, assuming the memory supports burst lengths of 8 and 16, and the data write duration corresponding to a burst length of 8 is 4tck, and the data write duration corresponding to a burst length of 16 is 8tck, and taking the first duration of 4tck as an example, when the memory operates in a burst length of 16 mode, since the effective level period of the Burst_out signal is 4tck, the effective level width of the final on-chip termination signal can be characterized as 4tck + 4tck + ODT_offset. Here, one of the two 4tck values ​​represents the original effective level period of the Burst_out signal, and the other represents the difference between the effective level period of the Burst_out signal and 8tck. Furthermore, the output circuit 103 can adjust the width of the effective level of the received Burst_out signal based on 4tck + ODT_offset to enrich the value of ODT_offset.

[0083] In some embodiments, the effective level period of the first signal Burst_out generated by the generation circuit 101 is a fixed value that is less than or equal to the data write duration corresponding to the second burst length; the second burst length is the minimum value among the burst lengths supported by the memory. Figure 5This is a schematic diagram of the structure of the second on-chip termination signal generation circuit provided in the embodiments of this disclosure. Figure 4 Based on the circuit structure shown, the generation circuit 101 provided in this embodiment includes a first generation module 1011, a first acquisition module 1012, and a first encoding module 1013. The first generation module 1011 is used to generate a first signal in response to a received initial signal and a clock signal; the first acquisition module 1012 is used to determine a first burst length in a first register and output the first burst length in response to the received initial signal; the first encoding module 1013 is used to receive the first burst length and output an indication signal according to the first burst length and a first correspondence relationship; the first correspondence relationship represents the correspondence between the burst length and the indication signal.

[0084] In specific operation, the first generation module 1011 is used to receive the clock signal CLK and the initial signal CMD, generate a first signal Burst_out with a fixed effective level period, and transmit the first signal Burst_out to the delay circuit 102 connected to the first generation module 1011.

[0085] Furthermore, the first acquisition module 1012 is used to obtain the first burst length corresponding to the current memory by accessing the register upon triggering the initial signal CMD. In practical applications, the controller can send a CA signal to the memory to control the memory to enter OTF mode. After the first acquisition module 1012 obtains the aforementioned CA signal, it can determine the first burst length corresponding to the memory based on the parameter values ​​stored in the register.

[0086] The first acquisition module 1012 then sends the acquired first burst length to the first encoding module 1013, so that the first encoding module 1013 can determine the indication signal corresponding to the first burst length based on the received first burst length and a preset first correspondence. Specifically, in this embodiment, the indication signal can be used to indicate the width of the effective level of the finally generated on-chip termination signal. The first correspondence is the correspondence between the burst length supported by the memory and the indication signal.

[0087] It is understood that in this embodiment, the generation circuit 101 may include a first generation module 1011 for generating a fixed effective level period, and a first encoding module 1013 for generating a corresponding indication signal based on the acquired first burst length. Specifically, the indication signal may also indicate the width of the effective level of the on-chip termination signal, so that the output circuit 103 can generate an on-chip termination signal based on the indication signal.

[0088] In some embodiments, Figure 4Based on the illustrated embodiment, in this embodiment, if the first burst length is greater than the third burst length, then the first duration is the data writing duration corresponding to the third burst length; the third burst length is a value selected from the burst lengths supported by the memory, excluding the maximum value.

[0089] For example, in this embodiment, the third burst length is any burst length other than the maximum value among the burst lengths supported by the pre-specified memory. The generation circuit 101, when determining that the current first burst length of the memory is greater than the third burst length, generates a first signal Burst_out with a fixed effective level period based on the received initial signal CMD. Here, the fixed value is the data write duration corresponding to the third burst length. That is, as long as the first burst length corresponding to the memory is greater than the third burst length, the effective level period of the first signal Burst_out generated by the generation circuit 101 is always the aforementioned fixed value. Furthermore, since the first burst length is greater than the third burst length, the data write duration corresponding to the first burst length is greater than the data write duration corresponding to the third burst length. Compared to the method in related technologies that directly uses the data write duration corresponding to the first burst length as the effective level period of the generated signal, in this embodiment, when the first burst length is greater than the third burst length, the effective level period of the first signal generated by the generation circuit 101 is less than the data write duration corresponding to the first burst length. Figure 1 The effective level period of the first signal generated by the first circuit module in this embodiment is reduced compared to that generated by the generation circuit 101 provided in this embodiment. Therefore, the subsequent output circuit 103 can perform pulse widening processing on the received second signal latency_out based on the first value and the preset offset ODT_offset.

[0090] It is understood that the on-chip termination signal generation circuit provided in this embodiment can ensure that when the memory is working in a mode with a length greater than the third burst, the range of the preset offset ODT_offset is widened, thereby increasing the function of the ODT signal generation circuit and enabling the ODT signal generation circuit to be applied to more ranges of ODT_offset.

[0091] Based on the above embodiments, Figure 6 This is a schematic diagram of the structure of a third on-chip termination signal generation circuit provided in an embodiment of this disclosure. Figure 4Based on the circuit structure shown, the generation circuit 101 provided in this embodiment includes: a second acquisition module 1014, a comparison module 1015, a second generation module 1016, and a second encoding module 1017; the second acquisition module 1014 is used to determine a first burst length in a first register and output the first burst length in response to the received initial signal; the comparison module 1015 is used to receive the first burst length and output a comparison result based on the first burst length and a third burst length; the comparison result is used to characterize the size relationship between the first burst length and the third burst length; the second generation module 1016 is used to output a first signal if it is determined that the comparison result indicates that the first burst length is greater than the third burst length; the second encoding module 1017 is used to receive the first burst length and output an indication signal based on the first burst length and a second correspondence; the second correspondence characterizes the correspondence between the burst length and the indication signal.

[0092] Exemplarily, in this embodiment, the technical principle of the second acquisition module 1014 in the generation circuit 101 is similar to that of the first acquisition module 1012 in the above embodiment, and will not be repeated here. After the second acquisition module 1014 determines the first burst length, it sends the first burst length to the comparison module 1015. When the comparison module 1015 receives the first burst length, it compares the acquired first burst length with the third burst length and outputs the comparison result to the second generation module 1016. After obtaining the comparison result indicating that the first burst length is greater than the third burst length, the second generation module 1016 directly generates a first signal with a first duration equal to the data writing duration corresponding to the third burst length. When the second generation module 1016 receives the comparison result indicating that the first burst length is less than or equal to the third burst length, the second generation module 1016 does not work.

[0093] In this embodiment, the second encoding module 1017 is connected to the second acquisition module 1014. The working principle of the second encoding module 1017 is similar to that of the first encoding module 1013 in the above embodiment. It can determine the indication signal corresponding to the first burst length according to the preset second correspondence. The indication signal can be used to characterize the value of the first value.

[0094] In addition, Figure 6 The generation circuit 101 shown also includes a third generation module 1018, which is connected to the comparison module 1015. The third generation module 1018 is used to generate a third signal with a width of a second value if the comparison result indicates that the first burst length is less than or equal to the third burst length, and to determine that the third signal is the first signal and output the first signal to the delay circuit 102; the second value is the data writing duration corresponding to the first burst length.

[0095] Specifically, the third generation module 1018 can receive the comparison result output by the comparison module 1015. Only when the comparison result indicates that the first burst length is less than or equal to the third burst length will the third generation module 1018 generate a third signal with an effective level width equal to the data write duration corresponding to the first burst length, based on the current first burst length of the memory. This third signal is then transmitted as the first signal Burst_out, the final output of the generation circuit 101, to the delay circuit connected to the generation circuit 101. Furthermore, the third generation module 1018 does not operate when it determines that the first burst length is greater than the third burst length.

[0096] For example, assuming the memory supports burst lengths of 8 and 16, and the data write time is 4 tck for a burst length of 8 and 8 tck for a burst length of 16, then the third burst length can be 8. That is, when the memory operates in burst length 16 mode, a first signal with a first duration of 4 tck can be output according to the second generation module 1016 in generation circuit 101. When the memory operates in burst length 8 mode, a first signal with a first duration of 4 tck can be output according to the third generation module 1018 in generation circuit 101.

[0097] Alternatively, in scenarios where the burst length supported by the memory includes 8 and 16, and the data write time corresponding to a burst length of 8 is 4tck and the data write time corresponding to a burst length of 16 is 8tck, a module for generating a first time of a fixed value (4tck) can be set in the corresponding generation circuit 101 to output the first signal.

[0098] It is understood that the on-chip termination signal generation circuit provided in this embodiment can ensure that the memory operates in a mode with a burst length greater than the third burst length by increasing the value range of the preset offset ODT_offset. This is equivalent to increasing the value range of ODTLoff_WR_offset and ODTLon_WR_offset, allowing the ODT signal generation circuit to be applied to a wider range of ODT_offset values. Furthermore, it can also ensure that the functionality of the ODT signal generation circuit in related technologies is retained even when the memory operates in a mode with a burst length less than or equal to the third burst length.

[0099] It should be noted that in some embodiments, the generation circuit 101 can also be controlled according to the following logic: for example, when the first burst length is within a first value range, a first signal with a first duration equal to the first value can be output, wherein the first value is greater than the data writing duration corresponding to the largest burst length within the first value range; when the first burst length is within a second value range, a second signal with a first duration equal to the second value can be output, wherein the second value is greater than the data writing duration corresponding to the largest burst length within the second value range.

[0100] In some embodiments, Figure 4 Based on the embodiments shown, Figure 7 This is a schematic diagram of the structure of a fourth on-chip termination signal generation circuit provided in an embodiment of this disclosure. Figure 7 As shown, the output circuit 103 of the on-chip termination signal generation circuit provided in this embodiment includes multiple first processing modules 1031 and data selectors 1032. The first processing module 1031 is used to receive a second signal and increase the width of the effective level of the second signal to obtain a first candidate signal. The width of the effective level of the first candidate signal output by different first processing modules 1031 is different. The data selector 1032 is used to receive the indication signal output by the generation circuit 101 and the first candidate signal, and determine and output the on-chip termination signal from multiple first candidate signals according to the indication signal.

[0101] For example, in the on-chip termination signal generation circuit provided in this embodiment, the output circuit 103 may be composed of a data selector 1032 and multiple first processing modules 1031. Each first processing module 1031 in the output circuit 103 receives the second signal latency_out output by the delay circuit 102, and generates a first candidate signal corresponding to each first processing module 1031 based on the received second signal latency_out. It should be noted that in this embodiment, the effective level width of the first candidate signal output by different first processing modules 1031 under the same second signal is different.

[0102] The data selector 1032 is also used to receive an indication signal output by the generation circuit 101, so that the data selector 1032 can determine the final on-chip termination signal CMD_out from a plurality of first candidate signals based on the received indication signal.

[0103] It is understood that in this embodiment, by setting multiple first processing modules 1031 and a data selector 1032 in the output circuit 103, an on-chip termination signal that conforms to the current burst length can be selected from the first candidate signals obtained by the multiple first processing modules 1031.

[0104] In some embodiments, Figure 4 Based on the embodiments shown, Figure 8 This is a schematic diagram of the fifth on-chip termination signal generation circuit provided in this embodiment of the present disclosure. The output circuit 103 includes: a plurality of second processing modules 1033 and a switch module 1034 corresponding to the second processing modules 1033; the second processing modules 1033 are used to receive a second signal and increase the width of the effective level of the second signal to obtain a second candidate signal; wherein, the width of the effective level of the second candidate signal output by different second processing modules 1033 is different; the switch module 1034 is used to receive an indication signal and control the switch module 1034 to be turned on in response to the indication signal, and determine that the second candidate signal generated by the second processing module 1033 connected to the switch module 1034 is an on-chip termination signal.

[0105] For example, in this embodiment, when setting the output circuit 103 in the on-chip termination signal generation circuit, multiple second processing modules 1033 and corresponding switch modules 1034 can be connected. The second processing modules 1033 are similar to the first processing module 1031 in the above embodiment. The second processing module 1033 is connected to the delay circuit 102 and is used to increase the width of the effective level of the second signal latency_out output by the delay circuit 102, thereby outputting a second candidate signal. Furthermore, it should be noted that the width increase corresponding to each second processing module 1033 is different when adjusting the width of the effective level. In addition, the switch modules 1034 are connected to the generation circuit 101 and the corresponding second processing modules 1033. The switching on and off of the switch modules 1034 is controlled by the indication signal output by the generation circuit 101. Under the control of the indication signal, one of the multiple switching modules 1034 in the output circuit 103 will be turned on, and then the second candidate module output by the second processing module 1033 connected to it will be used as the final on-chip termination signal output by the output circuit 103.

[0106] It is understood that in this embodiment, by setting multiple switch modules 1034 and combining them with the indication signal generated by the generation circuit 101, the switching modules 1034 are controlled to select the on-chip termination signal whose effective level width matches the current burst length, so as to ensure the timing accuracy of the final output on-chip termination signal, improve the accuracy of the state switching of the termination resistor at the data end of the memory, and ensure that the memory can accurately receive the externally input data to be written.

[0107] In some embodiments, the delay between the effective edge of the second signal and the effective edge of the first signal is the difference between a third value and a first loss time; wherein the third value is the sum of the memory write delay and the state switching time of the termination resistor; and the first loss time is the transmission time from the output of the on-chip termination signal to the receiving end of the on-chip termination signal.

[0108] For example, when the delay circuit 102 performs delay processing on the received first signal, considering the time loss during signal processing and transmission within the storage system, and since the delay duration of the delay circuit 102 affects the time it takes for the termination resistor to adjust from RTT-PARK to RTT-WR, the impact of loss is also considered when the delay circuit 102 performs delay processing. Specifically, in this embodiment, the time difference between the effective edge of the second signal latency_out and the effective edge of the first signal Burst_out finally output by the delay circuit 102 is the difference obtained by subtracting the first loss time from the aforementioned third value. The first loss time can be understood as the transmission time from the output end of the on-chip termination signal to the receiving end of the on-chip termination signal. Furthermore, the third value can be understood as the sum of the write delay (WL) and the on-off offset (ODTLon_offset) corresponding to the adjustment of the termination resistor from RTT-PARK to RTT-WR.

[0109] It is understood that, by considering the transmission loss on the data transmission path in this embodiment, and then subtracting the delay caused by the transmission loss during the delay processing of the delay circuit 102, the problem of inaccurate timing of the signal at the on-chip termination signal receiver caused by the transmission path loss can be further avoided.

[0110] In some embodiments, based on the above embodiments, Figure 9 This is a schematic diagram of the sixth on-chip termination signal generation circuit provided in the embodiments of this disclosure, as shown below. Figure 9 As shown, in Figure 4Based on the circuit structure shown, the delay circuit 102 in this embodiment includes a sampling module 1021 and a third processing module 1022; the sampling module 1021 and the third processing module 1022 are connected; the sampling module 1021 is used to receive a first signal Burst_out and, in response to a clock signal, sample the first signal Burst_out; if the level value of the sampled signal is determined to be valid, a shift signal Shift_align is output; the width of the valid level period of the shift signal Shift_align is the same as the width of the valid level period of the first signal; the third processing module 1022 is used to perform delay processing on the received shift signal Shift_align according to a preset delay duration, and output a second signal, wherein the preset delay duration is the difference between a third value and a second loss time; the second loss time is the difference between the time when the sampling module 1021 samples the valid value of the first signal and the time when the sampling module 1021 receives the first signal at the valid value.

[0111] For example, in this embodiment, the sampling module 1021 in the delay circuit 102 is used to receive the first signal Burst_out sent by the generation circuit 101, and sample the level value of the first signal Burst_out at the effective edge of the clock signal CLK. When the level value of the first signal Burst_out is determined to be an effective level value, a shift signal is generated, and the width of the effective level period of the shift signal is the same as the width of the effective level period of the first signal. Then, the sampling module 1021 transmits the obtained shift signal to the third processing module 1022 so that the third processing module 1022 performs delay processing on the received shift signal. Furthermore, in this embodiment, the delay duration of the shift signal by the third processing module 1022 is a preset delay duration, and the preset delay duration is the difference between the third value and the second loss time. The second loss time can be understood as the time difference between the time when the sampling module 1021 receives the first signal with a level at an effective value and the time difference between the time when the sampling module 1021 actually samples and determines that the first signal is at an effective level.

[0112] Understandably, since the delay unit cannot identify the first signal with a valid value in time, when the delay unit performs delay processing, it will also combine the second loss time in the above sampling and identification process to determine the final preset delay duration, so as to effectively control the time when the termination resistor is adjusted from RTT-PARK to RTT-WR, thereby ensuring that the state of the termination resistor can be switched before the data is written, and the data can be accurately written to the memory.

[0113] Figure 10This is another signal diagram provided in an embodiment of the present disclosure. In this embodiment, the current burst length of the memory is 16, and the data write duration corresponding to the burst length of 16 is 8tck for illustration. The length of one clock cycle of the internal clock signal CLK is 2tck.

[0114] Specifically, when generation circuit 101 receives the initial signal CMD at a low level, it generates a first signal Burst_out with an effective level duration of 4 tck. When delay circuit 102 receives the first signal Burst_out, it first generates a shift signal Shift_align with an effective level width of 4 tck at the effective edge of the internal clock signal CLK, and then delays the shift signal Shift_align to obtain the second signal latency_out. The delay time between the second signal latency_out and the shift signal Shift_align can be characterized by the following formula:

[0115] T=WL-(1+N)*2tck+ODTLon_WR_offset

[0116] Where T represents the delay time, i.e., the preset delay duration in the above embodiment. WL is the write delay. N can be used to characterize the number of clock cycles required for the on-chip termination signal to be transmitted from the output circuit 103 to the on-chip termination signal receiver. ODTLon_WR_offset is the enable offset. And 1 in the above formula can be understood as the delay consumed by the sampling module 1021 in sampling the effective level value of the first signal Burst_out, i.e., the number of clock cycles corresponding to the time difference between the first effective edge of the first signal and the first effective edge of the shift signal.

[0117] The on-chip termination signal in the figure is obtained by the output circuit 103 based on the received second signal latency_out. As can be seen from the figure, the width of the effective level of the on-chip termination signal and the second signal latency_out differs by ODT_offset+4tck. Here, 4tck can be understood as the difference between the data write duration of 8tck corresponding to a burst length of 16 and the width of the effective level period of the first signal of 4tck (i.e., the first value in this disclosure).

[0118] The actual signal ODT_DQ pin in the figure is the signal actually received by the receiver of the on-chip termination signal CMD_out. As can be seen from the figure, there is an N*2tck delay between the first valid edge of the on-chip termination signal CMD_out and the first valid edge of the actual signal ODT_DQ pin. Furthermore, the difference between the time of the first valid edge of the actual signal ODT_DQ pin (i.e., the time for the termination resistor to adjust from RTT-PARK to RTT-WR) and the initial signal CMD generation time is WL+ODTLon_WR_offset. The difference between the effective level end time of the on-chip termination signal CMD_out (i.e., the time for the termination resistor to adjust from RTT-WR to RTT-PARK) and the initial signal CMD generation time is WL+BL / 2+ODTLoff_WR_offset, ensuring the accuracy of the timing of the termination resistor state switching. Moreover, based on the embodiments of this disclosure, when setting ODT_offset, a value between [-4tck, 0] can also be supported. Compared to related technologies where ODT_offset can only be selected with values ​​greater than or equal to 0, this technology further expands the value range to [-4tck, 0], which is equivalent to expanding the value range of ODTLon_WR_offset and ODTLoff_WR_offset. Specifically, the value ranges for each can be found in Table 2.

[0119] As shown in Table 2, in this embodiment of the present disclosure, compared with the offset values ​​supported in BL16 mode provided in Table 1, the value range of “X” in Table 1 in BL16 mode can also be effectively supported in this embodiment of the present disclosure, which is beneficial to broaden the scope of offset usage.

[0120]

[0121] Table 2. Range of offset values ​​supported by embodiments of this disclosure

[0122] This disclosure also provides a storage system, which includes a memory with on-chip termination control circuitry and an on-chip termination signal generation circuitry as described in any of the above embodiments.

[0123] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0124] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

[0125] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. An on-die termination signal generation circuit applied to a memory system including a memory having an on-die termination control circuit, characterized by, The on-chip termination signal generation circuit comprises a generation circuit, a delay circuit and an output circuit, wherein The generation circuit is configured to receive an initial signal, output a first signal and an indication signal in response to a clock signal; the initial signal is used to indicate the state of the termination resistance of the data terminal; the indication signal is used to indicate a first burst length; the first burst length is the current burst length of the memory; the active level period of the first signal is a first time length; The delay circuit is configured to receive the first signal and perform delay processing on the first signal to output a second signal; The output circuit is configured to receive the indication signal and the second signal and output an on-chip termination signal; the on-chip termination control circuit receives the on-chip termination signal to adjust the state of the termination resistance of the data terminal; the width of the active level of the on-chip termination signal is selected according to the indication signal.

2. The on-chip termination signal generation circuit of claim 1, wherein, The first time length is a fixed value of the data write time length corresponding to a second burst length; the second burst length is the minimum value in the burst lengths supported by the memory. Alternatively, the first time length is a fixed value smaller than the data write time length corresponding to the second burst length.

3. The on-chip termination signal generation circuit of claim 2, wherein, The generation circuit comprises a first generation module, a first acquisition module and a first encoding module; the encoding module is connected with the first acquisition module; The first generation module is configured to generate a first signal in response to the received initial signal and clock signal; The first acquisition module is configured to determine the first burst length in a first register in response to the received initial signal and output the first burst length; The first encoding module is configured to receive the first burst length and output an indication signal according to the first burst length and a first corresponding relationship; the first corresponding relationship represents the corresponding relationship between the burst length and the indication signal.

4. The on-chip termination signal generation circuit of claim 1, wherein, If the first burst length is greater than a third burst length, the first time length is the data write time length corresponding to the third burst length; the third burst length is one value selected from the remaining values in the burst lengths supported by the memory except for the maximum value.

5. The on-chip termination signal generation circuit of claim 4, wherein, The generation circuit comprises a second acquisition module, a comparison module, a second generation module and a second encoding module; The second acquisition module is configured to determine the first burst length in a first register in response to the received initial signal and output the first burst length; The comparison module is configured to receive the first burst length and output a comparison result according to the first burst length and the third burst length; the comparison result is used to represent the size relationship between the first burst length and the third burst length; The second generation module is configured to output a first signal if it is determined that the comparison result represents that the first burst length is greater than the third burst length; The second encoding module is configured to receive the first burst length and output an indication signal according to the first burst length and a second corresponding relationship; the second corresponding relationship represents the corresponding relationship between the burst length and the indication signal.

6. The on-chip termination signal generation circuit of claim 5, wherein, The generation circuit further comprises A third generating module, connected with the comparing module, is configured to generate a third signal with a second value of the width of the active level if it is determined that the comparison result indicates that the first burst length is less than or equal to the third burst length, and determine the third signal as the first signal and output the first signal to the delay circuit; the second value is a data write duration corresponding to the first burst length.

7. The on-chip termination signal generation circuit of claim 1, wherein, The output circuit includes a data selector and a plurality of first processing modules; wherein, The first processing module is configured to receive the second signal, and increase the width of the active level of the second signal to obtain a first candidate signal; wherein the widths of the active levels of the first candidate signals output by different first processing modules are different; The data selector is configured to receive an indication signal output by the generating circuit and the first candidate signal, and determine and output the on-chip termination signal from the plurality of first candidate signals according to the indication signal.

8. The on-chip termination signal generation circuit of claim 1, wherein, The output circuit includes a plurality of second processing modules and switch modules corresponding to the second processing modules; The second processing module is configured to receive the second signal, and increase the width of the active level of the second signal to obtain a second candidate signal; wherein the widths of the active levels of the second candidate signals output by different second processing modules are different; The switch module is configured to receive the indication signal, and control the switch module to be turned on in response to the indication signal, determine the second candidate signal generated by the second processing module connected with the switch module as the on-chip termination signal, and output the on-chip termination signal.

9. The on-die termination signal generation circuit of any of claims 1-8, wherein, The delay duration between the active edge of the second signal and the active edge of the first signal is a difference between a third value and a first loss time; The third value is a sum of a write delay of the memory and a state switching duration of the termination resistor; and the first loss time is a transmission time from an output end of the on-chip termination signal to a receiving end of the on-chip termination signal.

10. The on-chip termination signal generation circuit of claim 9, wherein, The delay circuit includes a sampling module and a third processing module; the sampling module is connected with the third processing module; The sampling module is configured to receive the first signal, and sample the first signal in response to the clock signal; If it is determined that the level value of the sampled sampling signal is a valid value, a shift signal is output; the width of the active level period of the shift signal is the same as the width of the active level period of the first signal; The third processing module is configured to perform delay processing on the received shift signal according to a preset delay duration to output a second signal; wherein the preset delay duration is a difference between the third value and a second loss time; and the second loss time is a difference between a time when the sampling module samples the valid value of the first signal and a time when the sampling module receives the first signal with the valid value.

11. A storage system, characterized by The storage system includes a memory with an on-chip termination control circuit and an on-chip termination signal generation circuit according to any one of claims 1-10.

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