Memory and memory system

Abstract

The embodiment of the invention discloses a memory and a memory system, and the memory comprises a plurality of memory bank groups, and each memory bank group comprises at least one memory bank; the peripheral circuit comprises a plurality of first global read data registers, a plurality of first data connection paths, a plurality of first signal connection paths, a first read data register and a plurality of second data connection paths. The lengths of the first data connection paths between the memory banks and the corresponding first global read data registers are equal; a first signal connection path between each memory bank and the corresponding first global read data register and a second data connection path between the corresponding first global read data register and the first read data register are negatively correlated in length.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and relate to, but are not limited to, a memory and a memory system. Background Art

[0002] With the continuous development of current science and technology, semiconductor devices are widely used in various electronic devices and electronic products. For example, Dynamic Random Access Memory (DRAM), as a volatile memory, is a commonly used semiconductor storage device in computers. How to improve the performance of dynamic random access memory has become an urgent problem to be solved. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a memory and a memory system.

[0004] In a first aspect, embodiments of the present disclosure provide a memory, including: a plurality of bank groups, each of the bank groups including at least one bank; a peripheral circuit, including: a plurality of first global read data registers, a plurality of first data connection paths, and a plurality of first signal connection paths, each bank in the same bank group being connected to a corresponding one of the first global read data registers through one of the first data connection paths and one of the first signal connection paths; a first read data register, and a plurality of second data connection paths, each of the first global read data registers being connected to the first read data register through one of the second data connection paths;

[0005] Wherein, the lengths of the first data connection paths between each of the banks and the corresponding first global read data registers are equal; the first signal connection paths between each of the banks and the corresponding first global read data registers, and the second data connection paths between the corresponding first global read data registers and the first read data register are negatively correlated in length.

[0006] In a second aspect, embodiments of the present disclosure further provide a memory system, including: a memory controller and the memory as described in any one of the above embodiments. The memory controller is configured to control the memory.

[0007] In the embodiments of the present disclosure, when the lengths of the first data connection paths between each bank and the corresponding first global read data register are equal, the longer the second data connection path corresponding to the bank, the shorter the corresponding first signal connection path. That is, the first signal connection paths between each bank and the corresponding first global read data register are negatively correlated in length with the corresponding second data connection paths.

[0008] In the embodiments of the present disclosure, by reasonably adjusting the lengths of the first signal connection paths corresponding to different memory bank groups, the length of the first signal connection path in the memory bank group closer to the first read data register is extended, so that the read data in each memory bank can reach the first read data register after the same delay, and the data window sizes of the read data in each memory bank are the same when sampled by the read data sampling signal, thereby improving the data offset phenomenon caused by the different lengths of the second data connection paths corresponding to different memory bank groups. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In the drawings, unless otherwise specified, the same reference numerals throughout the several views denote the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings merely depict some embodiments disclosed in accordance with the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0010] Figure 1 FIG. [0000025] is a schematic structural diagram of a memory in some embodiments;

[0011] Figure 2 FIG. [0000028] is a schematic diagram of different data window sizes when data from different memory banks are sampled into the first read data register in some embodiments;

[0012] Figure 3 FIG. [0000031] is a schematic structural diagram of a memory provided by an embodiment of the present disclosure; Figure 1 ;

[0013] Figure 4 FIG. [0000035] is a schematic diagram of the same data window size when data from different memory banks are sampled into the first read data register provided by an embodiment of the present disclosure;

[0014] Figure 5 FIG. [0000038] is a schematic structural diagram of a memory provided by an embodiment of the present disclosure; Figure 2 ;

[0015] Figure 6 AND Figure 7 FIG. [0000043] is a schematic diagram of the positional relationship between multiple memory banks and a peripheral circuit provided by an embodiment of the present disclosure;

[0016] Figure 8 FIG. [0000046] is a schematic structural diagram of a memory provided by an embodiment of the present disclosure; Figure 3 ;

[0017] Figure 9 FIG. [0000050] is a schematic structural diagram of a memory provided by an embodiment of the present disclosure; Figure 4 ;

[0018] Figure 10 FIG. [0000054] is a schematic structural diagram of a memory provided by an embodiment of the present disclosure; Figure 5 ;

[0019] Figure 11 Structural schematic of a memory provided by an embodiment of the present disclosure Figure 6 ;

[0020] Figure 12 Schematic diagram of an exemplary electronic device including a memory system provided by an embodiment of the present disclosure;

[0021] Figure 13 and Figure 14 Schematic diagram of a memory system provided by an embodiment of the present disclosure;

[0022] Figure 15 Schematic diagram of a peripheral circuit and a memory cell array provided by an embodiment of the present disclosure. Detailed implementation manners

[0023] To facilitate the understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be completely conveyed to those skilled in the art.

[0024] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some well-known technical features are not described; that is, all features of the actual embodiments may not be described here, and the well-known functions and structures are not described in detail.

[0025] Generally, terms can be understood at least in part from their use in the context. For example, at least in part depending on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or property in a singular sense, or can be used to describe a combination of features, structures, or properties in a plural sense. Similarly, terms such as "a" or "the" can also be understood to convey a singular usage or a plural usage, which at least in part depends on the context. Additionally, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, and can alternatively allow for the existence of additional factors that are not necessarily explicitly described, which also at least in part depends on the context.

[0026] Unless otherwise defined, the terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0027] To thoroughly understand the present disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may have other embodiments.

[0028] In some embodiments, referring to Figure 1 , the memory 100 may include 4 bank groups (BG) arranged along the X direction, and each bank group includes 2 banks 110. Among them, Bank0 and Bank1 form BG0, Bank2 and Bank3 form BG1, Bank4 and Bank5 form BG2, and Bank6 and Bank7 form BG3. The peripheral circuit 120 is located on one side of the plurality of banks along the Y direction. The peripheral circuit includes: a plurality of first global read data registers 130, each first global read data register 130 corresponding to one bank group and used to receive the read data in one bank group; a plurality of first data connection paths 210 and a plurality of first signal connection paths 310. Each bank in the same bank group is connected to a corresponding first global read data register 130 through a first data connection path 210 and a first signal connection path 310; a first read data register 140 and a plurality of second data connection paths 220. Each first global read data register 130 is connected to the first read data register 140 through a second data connection path 220. Figure 1 Only the first signal connection path 310, the first data connection path 210, and the corresponding second data connection path 220 between Bank1 and Bank7 and the corresponding first global read data register 130 are schematically shown in

[0029] The specific process of reading data from the memory bank in the memory to the first read data register can be as follows: The memory receives a read command from the outside (for example, the host). The command decoder in the peripheral circuit of the memory receives the read command and decodes it to obtain the decoded read signal. The decoded read signal can be represented by 1-bit data and can be in the form of a pulse. For example, a high pulse represents a decoded read signal. If two read commands are received, two decoded read signals, that is, two high pulse signals, will be generated. The read control logic receives at least one decoded read signal. The read control logic can combine at least one decoded read signal and determine the mode of at least one decoded read signal (for example, X8 or X16), thereby outputting the first read information. The Local Bank Control receives the first read information. The Local Bank Control further decodes the address information in the read command and outputs the bank sampling signal dl_oen. That is, compared with the decoded read signal, the bank sampling signal dl_oen also includes the address of the memory bank to be read.

[0030] The read data in the memory bank to be read can be transmitted to the Sense Amplifier through the first Data Line. The bank sampling signal dl_oen acts on the Sense Amplifier corresponding to the memory bank to be read. When the bank sampling signal dl_oen is valid, the Sense Amplifier outputs the read data in the corresponding memory bank to the first global read data register through the first data connection path. Each first global read data register is correspondingly connected to a memory bank group through multiple first signal connection paths and multiple first data connection paths. The Sense Amplifier also outputs the control signal in the corresponding memory bank to the first global read data register through the first signal connection path. For multiple memory banks in the same memory bank group, only the control signal corresponding to one memory bank is valid at the same time. The read data of multiple memory banks in the same memory bank group will first be stored in the first global read data register. The first global read data register receives the control signal, and when the control signal is valid, the read data of the corresponding memory bank in the first global read data register is transmitted to the first read data register through the corresponding second data connection path.

[0031] Refer to Figure 2 , and consider the case of alternately reading memory banks at different distances from the first data read register below. Specifically, first read the data in Bank7, then read the data in Bank1, then continue to read the data in Bank7, and then continue to read the data in Bank1.

[0032] Combined withFigure 1 and Figure 2 The lengths of the second data connection paths between the first global read data registers corresponding to different memory bank groups and the first read data registers are different. Moreover, the length of the second data connection path corresponding to Bank1 is much greater than that of the second data connection path corresponding to Bank7. Meanwhile, during the process of the read data being transferred from the first global read data register to the first read data register, there is no sampling signal following the read data continuously. Instead, the read data sampling signal generated by the read control logic samples the data in the first read data register, and the delays of the read data sampling signal for different memory banks are the same. This will result in a larger data window for Bank7 and a smaller data window for Bank1, that is, data offsets will occur in the read data of different memory banks.

[0033] To solve the above problems, an embodiment of the present disclosure provides a memory. Referring to Figure 3 , it includes: multiple memory bank groups, each memory bank group including at least one memory bank 110; a peripheral circuit 120, including: multiple first global read data registers 130, multiple first data connection paths 210, and multiple first signal connection paths 310. Each memory bank 110 in the same memory bank group is connected to a corresponding first global read data register 130 through a first data connection path 210 and a first signal connection path 310; a first read data register 160, multiple second data connection paths 220. Each first global read data register 130 is connected to the first read data register 160 through a second data connection path 220; wherein, the lengths of the first data connection paths 210 between each memory bank 110 and the corresponding first global read data register 130 are equal; the first signal connection paths 310 between each memory bank 110 and the corresponding first global read data register 130 and the second data connection paths 220 between the corresponding first global read data registers 130 and the first read data register 160 are negatively correlated in length.

[0034] The embodiments provided by the present disclosure are applicable to and not limited to dynamic random access memories (DRAMs), static random access memories (SRAMs). Among them, DRAMs include but are not limited to double data rate synchronous dynamic random access memories (DDR SDRAMs), low power double data rate synchronous dynamic random access memories (LPDDRs). Double data rate synchronous dynamic random access memories also include DDR4, DDR5, and DDR6, etc. Low power double data rate synchronous dynamic random access memories also include LPDDR4, LPDDR5, and LPDDR6, etc.

[0035] Referring to Figure 3 , the memory may include four bank groups BG0 to BG3 arranged in a first direction, and each bank group includes four banks 110. It can be understood that the number of the above bank groups and the number of banks 110 included in the bank groups are only examples, and the present disclosure is not limited thereto.

[0036] The first direction here may be the X direction in the drawings of the present disclosure, and the second direction may be the Y direction in the drawings of the present disclosure.

[0037] In the embodiments of the present disclosure, the banks in multiple bank groups are divided according to the distance between the bank group and the first read data register 160. Here, the banks 110 in BG0 are used as far banks, and the banks 110 in BG1, BG2, and BG3 are divided into near banks.

[0038] Since the length of the first data connection path 210 between each bank 110 and the corresponding first global read data register 130 is equal in the embodiments of the present disclosure, the read data of the far bank and the read data of the near bank can reach their respective corresponding first global read data registers 130 after the same delay. However, since the length of the second data connection path 220 corresponding to the far bank is greater than the length of the second data connection path 220 corresponding to the near bank, in the embodiments of the present disclosure, by extending the length of the first signal connection path 310 corresponding to the near bank, the read data corresponding to the far bank will be output from the corresponding first global read data register 130 later than the read data corresponding to the near bank. Finally, the data in the far bank and the near bank can both take the same time to reach the first read data register 160. Therefore, in the embodiments of the present disclosure, by extending the first signal connection path 310 corresponding to the near bank, the time for the control signal corresponding to the near bank to reach the first global read data register 130 corresponding to the near bank is extended, ensuring that the time taken for the read data output by different banks 110 to reach the first read data register 160 is consistent.

[0039] It can be understood that when the length of the first data connection path 210 between each bank 110 and the corresponding first global read data register 130 is equal, the longer the second data connection path 220 corresponding to the bank 110, the shorter the corresponding first signal connection path 310. That is, the first signal connection path 310 and the corresponding second data connection path 220 between each bank 110 and the corresponding first global read data register 130 are negatively correlated in length.

[0040] Such as Figure 4As shown, in the embodiments of the present disclosure, since Bank7 is the near Bank compared to Bank0, the length of the first signal connection path 310 corresponding to Bank0 is set as the reference length. At this time, the length of the first signal connection path 310 corresponding to Bank7 is delayed. Therefore, the control signal corresponding to Bank7 is shifted to the right as a whole compared to before the first signal connection path 310 is extended. As a result, the data window of Bank7 becomes smaller compared to before the first signal connection path 310 corresponding to it is not extended, and the data window of Bank0 becomes larger compared to before the first signal connection path 310 corresponding to Bank7 is not extended. Finally, the sizes of the data windows of each Bank are kept consistent.

[0041] In the embodiments of the present disclosure, by extending the length of the first signal connection path 310 in the memory bank group closer to the first read data register 160, the read data in each memory bank 110 can reach the first read data register 160 after the same delay, so that the sizes of the data windows of the read data in each memory bank 110 when being sampled by the read data sampling signal are consistent, thereby avoiding the phenomenon of data offset.

[0042] In some embodiments, referring to Figure 5 , the peripheral circuit 120 further includes a plurality of signal synthesis circuits 410; each signal synthesis circuit 410 is configured to receive the control signals corresponding to a plurality of memory banks 110 in the same memory bank group and synthesize the control signals corresponding to the plurality of memory banks 110 in the same memory bank group into a total control signal; the first global read data register 130 is configured to receive the total control signal and output the data read from the corresponding memory bank 110 when the total control signal is in the enabled state.

[0043] In the embodiments of the present disclosure, in order to save the wiring between the memory bank 110 and the first global read data register 130, the peripheral circuit 120 may further include a signal synthesis circuit 410 and a read data synthesis circuit 420. Among them, the signal synthesis circuit 410 is used to synthesize the control signals corresponding to the memory banks 110 to be read in the plurality of memory banks 110 and output a total control signal. In some embodiments, the signal synthesis circuit 410 may include a multiplexer. For example, a four-to-one selector, or two two-to-one selectors. Specifically, it can be selected according to the actual situation. The read data synthesis circuit 420 is used to synthesize the read data corresponding to the memory banks 110 to be read in the plurality of memory banks 110 and output a total read data.

[0044] The first global read data register 130 receives the read data read from the memory bank group and the control signal corresponding to the memory bank group. The control signal is used to sample the read data. When the control signal is valid, the read data is transmitted to the first read data register 160 via the corresponding second data connection path 220.

[0045] In some embodiments, referring to Figure 5 , the first signal connection path 310 includes a first signal line 311 and a second signal line 312; one end of the first signal line 311 is connected to the memory bank 110, the other end of the first signal line 311 is connected to the input end of the signal synthesis circuit 410, the output end of the signal synthesis circuit 410 is connected to one end of the second signal line 312, and the other end of the second signal line 312 is connected to the first global read data register 130; multiple memory banks 110 in the same memory group share one second signal line 312.

[0046] In the embodiments of the present disclosure, the first signal connection path 310 may include a first signal line 311 between the memory bank 110 and the signal synthesis circuit 410 and a second signal line 312 between the signal synthesis circuit and the first global read data register.

[0047] In the embodiments of the present disclosure, by extending the length of the second signal line 312 in the first signal connection path 310 corresponding to the near bank, the time for the control signal corresponding to the near bank to reach the first global read data register 130 corresponding to the near bank is extended.

[0048] In the embodiments of the present disclosure, the second signal line 312 in the first signal connection path 310 between each memory bank 110 and the corresponding first global read data register 130 and the second data connection path 220 between the corresponding first global read data register 130 and the first read data register 160 are negatively correlated in length. The first signal lines 311 in the first signal connection path 310 between each memory bank 110 and the corresponding first global read data register 130 are equal.

[0049] In some embodiments, multiple memory bank groups are arranged along a first direction, and multiple memory banks 110 are distributed on at least one of the two opposite sides of the peripheral circuit 120 along a second direction; the first direction intersects the second direction; multiple first global read data registers 130 are arranged along the first direction.

[0050] Referring to Figure 6 , multiple memory banks 110 are arranged along the first direction and are located on one side of the peripheral circuit 120 along the second direction.

[0051] Referring to Figure 7, a plurality of memory banks 110 are distributed on both sides of the peripheral circuit 120 along the second direction, and the plurality of memory banks 110 on each side are arranged along the first direction.

[0052] In some embodiments, the first read data register 160 is located on one side of the plurality of first global read data registers 130 along the first direction. The lengths of the second data connection paths 220 between different first global read data registers 130 and the first read data register 160 are different; the lengths of the first signal connection paths 310 between different first global read data registers 130 and the corresponding memory bank groups are different.

[0053] In some embodiments, the closer the first global read register 130 is to the first read data register 160, the shorter the length of the corresponding second data connection path 220, and the longer the length of the corresponding first signal connection path 310.

[0054] Refer to Figure 5, the first read data register 160 is located on one side of the multiple first global read data registers 130 along the first direction. The lengths of the second data connection paths 220 between the first global read data register corresponding to each bank group and the first read data register 160 are different, and the length of the second data connection path 220 corresponding to BG0 is greater than the length of the second data connection path 220 corresponding to BG1, which is greater than the length of the second data connection path 220 corresponding to BG2, which is greater than the length of the second data connection path 220 corresponding to BG3. And the length of the second data connection path 220 corresponding to BG0 minus the length of the second data connection path 220 corresponding to BG1 is equal to the length of the second data connection path 220 corresponding to BG1 minus the length of the second data connection path 220 corresponding to BG2, which is equal to the length of the second data connection path 220 corresponding to BG2 minus the length of the second data connection path 220 corresponding to BG3, that is, they are in an arithmetic progression. In the embodiments of the present disclosure, the lengths of the first signal connection paths corresponding to each BG are also set to be different. Specifically, the length of the first signal connection path 310 corresponding to BG3 is greater than the length of the first signal connection path 310 corresponding to BG2, which is greater than the length of the first signal connection path 310 corresponding to BG1, which is greater than the length of the first signal connection path 310 corresponding to BG0. And the length of the first signal connection path 310 corresponding to BG3 minus the length of the first signal connection path 310 corresponding to BG2 is equal to the length of the first signal connection path 310 corresponding to BG2 minus the length of the first signal connection path 310 corresponding to BG1, which is equal to the length of the first signal connection path 310 corresponding to BG1 minus the length of the first signal connection path 310 corresponding to BG0, that is, they are in an arithmetic progression. This makes the sum of the lengths of the second data connection path 220 and the first signal connection path 310 corresponding to each bank group consistent.

[0055] In some embodiments, the first read data register 160 is located between the multiple first global read data registers 130; the lengths of the second data connection paths 220 between at least some of the first global read data registers 130 in the multiple first global read data registers 130 and the first read data register 160 are different; the lengths of the first signal connection paths 310 between at least some of the first global read data registers 130 in the multiple first global read data registers 130 and the corresponding bank groups are different.

[0056] Refer to Figure 8, the first read data register 160 is located between the first global read data register 130 corresponding to BG3 and the first global read data register 130 corresponding to BG2. It can be understood that the first read data register 160 can also be located between the first global read data registers 130 corresponding to other adjacent BGs, and the present disclosure does not limit the specific position of the first read data register 160. At this time, the lengths of the second data connection paths 220 corresponding to BG3 and BG2 are the same and less than the length of the second data connection path 220 corresponding to BG1 and the length of the second data connection path 220 corresponding to BG0. Therefore, the length of the first signal connection path 310 corresponding to BG3 is equal to the length of the first signal connection path 310 corresponding to BG2 and greater than the length of the first signal connection path 310 corresponding to BG1 and the length of the first signal connection path 310 corresponding to BG0. Thus, the sum of the lengths of the second data connection path 220 and the first signal connection path 310 corresponding to each memory bank group can be kept consistent.

[0057] In the embodiment of the present disclosure, the specific length of the first signal connection path 310 in the corresponding memory bank group can be set accordingly according to the specific positional relationship between the first read data register 160 and the multiple first global read data registers 130.

[0058] In some embodiments, referring to Figure 9 , the peripheral circuit 120 further includes: a plurality of second signal connection paths 320, a second read data register 150, and a plurality of third data connection paths 230; wherein, the first global read data register 130 is configured to: when the data in the memory bank 110 needs to be output from the first read data register 160, receive the control signal transmitted by the first signal connection path 310; when the data in the memory bank 110 needs to be output from the second read data register 150, receive the control signal transmitted by the second signal connection path 320; each memory bank 110 in the same memory bank group is connected to a corresponding first global read data register 130 through a second signal connection path 320;

[0059] Each first global read data register 130 is connected to the second read data register 150 through a third data connection path 330; the second signal connection path 320 between each memory bank 110 and the corresponding first global read data register 130 and the third data connection path 230 between the corresponding first global read register 130 and the second read data register 150 are negatively correlated in length.

[0060] In the embodiments of the present disclosure, Bank0 to Bank3 can form BG0, Bank4 to Bank7 can form BG1, Bank8 to Bank11 can form BG2, and Bank12 to Bank15 can form BG3.

[0061] In the embodiments of the present disclosure, referring to Figure 9 , the first read data register 160 is located between BG3 and BG2, and the second read data register 150 is located between BG0 and BG1. Therefore, for BG0, it is the far bank of the first read data register 160 and the near bank of the second read data register 150. For BG1, it is the far bank of the first read data register 160 and the near bank of the second read data register 150. For BG2, it is the near bank of the first read data register 160 and the far bank of the second read data register 150. For BG3, it is the near bank of the first read data register 160 and the far bank of the second read data register 150. That is, for the same memory bank group, due to the different positions of the first read data register 160 and the second read data register 150, the memory bank group has different near and far relationships with the first read data register 160 and the second read data register 150 at different positions.

[0062] Therefore, the embodiments of the present disclosure also provide multiple second signal connection paths 320 and multiple third data connection paths 230. When the read data in the memory bank 110 needs to be transmitted to the second read data register 150, the read data in the memory bank 110 can be transmitted to the first global read data register 130 through the first data connection path 210, and the control signal corresponding to the memory bank 110 can be transmitted to the first global read data register 130 through the second signal connection path 320. When the control signal corresponding to the memory bank 110 is valid, the read data corresponding to the memory bank 110 in the first global read data register 130 is transmitted to the second read data register 150 through the corresponding third data connection path 230.

[0063] It can be understood that when the lengths of the first data connection paths 210 between each memory bank group and the corresponding first global read data register 130 are equal, the longer the third data connection path 230 corresponding to the memory bank group, the shorter the corresponding second signal connection path 320. That is, the second signal connection path 320 between each memory bank 110 and the corresponding first global read data register 130 and the third data connection path 230 between the corresponding first global read data register 130 and the second read data register 150 are negatively correlated in length.

[0064] In the embodiments of the present disclosure, by extending the length of the second signal connection path 320 corresponding to the bank group that is relatively close to the second read data register 150, the read data in each bank 110 can reach the second read data register 150 after the same delay, so that the data window sizes of the read data in each bank 110 are the same when sampled by the read data sampling signal, thereby avoiding the phenomenon of data offset.

[0065] For Figure 9 the embodiment shown, the lengths of the second signal connection paths 320 corresponding to BG0 and BG1 are the same and greater than the lengths of the second signal connection paths 320 corresponding to BG2 and the lengths of the second signal connection paths 320 corresponding to BG3.

[0066] In some embodiments, the data in the bank 110 can be selectively transmitted to the first read data register 160, or can be selectively transmitted to the second read data register 150, or can also be selectively transmitted to both the first read data register 160 and the second read data register 150. The selection can be made according to the actual data transmission requirements.

[0067] In some embodiments, referring to Figure 9 , the memory includes a first sub-storage area and a second sub-storage area. The first sub-storage area and the second sub-storage area are arranged along a first direction and both include multiple bank groups; the first read data register 160 is located on the symmetry line extending along the first direction of the first sub-storage area, and the second read data register 150 is located on the symmetry line extending along the first direction of the second sub-storage area.

[0068] Here, the first sub-storage area may include BG3 and BG2, and the second sub-storage area may include BG1 and BG0.

[0069] In some embodiments, referring to Figure 9 , among the multiple first global read data registers 130 corresponding to the banks 110 in the first sub-storage area, the lengths of the first signal connection paths 310 between different first global read data registers 130 and the corresponding bank groups are equal, and the lengths of the second data connection paths 220 between different first global read data registers 130 and the first read data register 160 are equal; among the multiple first global read data registers 130 corresponding to the banks 110 in the second sub-storage area, the lengths of the second signal connection paths 320 between different first global read data registers 130 and the corresponding bank groups are equal, and the lengths of the third data connection paths 230 between different first global read data registers 130 and the second read data register 150 are equal.

[0070] In some embodiments, referring to Figure 10, the first read data register 160 and the second read data register 150 are respectively located on both sides of a plurality of first global read data registers 130 along the first direction; the lengths of the third data connection paths 230 between different first global read data registers 130 and the second read data register 150 are different; the lengths of the second signal connection paths 320 between different first global read data registers 130 and the corresponding memory bank groups are different.

[0071] In the embodiments of the present disclosure, Bank0 to Bank3 can form BG0, Bank4 to Bank7 can form BG1, Bank8 to Bank11 can form BG2, and Bank12 to Bank15 can form BG3.

[0072] In the embodiments of the present disclosure, with reference to Figure 10 , the first read data register 160 can be symmetrically arranged with the second read data register 150 along the perpendicular bisector of the connection line between BG1 and BG2. And the first read data register 160 is located on the first side of a plurality of first global read data registers 130 along the first direction, and the second read data register 150 is located on the second side of a plurality of first global read data registers 130 along the first direction. The first side and the second side are two opposite sides along the X direction.

[0073] In the embodiments of the present disclosure, for BG0, it is the farthest bank of the first read data register 160 and the nearest bank of the second read data register 150. For BG1, it is the second farthest bank of the first read data register 160 and the second nearest bank of the second read data register 150. For BG2, it is the second nearest bank of the first read data register 160 and the second farthest bank of the second read data register 150. For BG3, it is the nearest bank of the first read data register 160 and the farthest bank of the second read data register 150. That is, for the same memory bank group, due to the different positions of the first read data register 160 and the second read data register 150, the memory bank group has different distance relationships with the first read data register 160 and the second read data register 150 at different positions.

[0074] For Figure 10In the illustrated embodiment, the length of the third data connection path 230 corresponding to BG0 is less than the length of the third data connection path 230 corresponding to BG1, which is less than the length of the third data connection path 230 corresponding to BG2, which is less than the length of the third data connection path 230 corresponding to BG3. The length of the second signal connection path 320 corresponding to BG0 is greater than the length of the second signal connection path 320 corresponding to BG1, greater than the length of the second signal connection path 320 corresponding to BG2, and greater than the length of the second signal connection path 320 corresponding to BG3. As a result, the read data in each memory bank 110 can reach the second read data register 150 after the same delay, so that the data window sizes of the read data in each memory bank 110 are the same when sampled by the read data sampling signal.

[0075] In the embodiments of the present disclosure, the memory bank 110 can be regarded as a whole, or the memory bank 110 can be divided into a first sub-memory bank (BankA) and a second sub-memory bank (BankB). The control signals corresponding to the memory bank 110 can be divided into a first sub-control signal and a second sub-control signal. The first sub-control signal and the second sub-control signal are independent of each other and do not interfere with each other, so that the data read from the first sub-memory bank and the second sub-memory bank can be separately controlled. When the first sub-control signal is valid, the read data in the first sub-memory bank (BankA) can be sampled into the global circuit. When the second sub-control signal is valid, the read data in the second sub-memory bank (BankA) can also be sampled into the global circuit.

[0076] In some embodiments, when the memory is in the X16 mode, the data read from the multiple first sub-memory banks (BankA) in each memory bank group are output to the second read data register 150, and the data read from the multiple second sub-memory banks (BankB) in each memory bank group are output to the first read data register 160. Or, when the memory is in the X16 mode, the data read from the multiple first sub-memory banks (BankA) in each memory bank group are output to the first read data register 160, and the data read from the multiple second sub-memory banks in each memory bank group are output to the second read data register 150.

[0077] In some embodiments, when each memory bank 110 is a whole and the memory is in the X8u mode, the data read from the multiple memory banks 110 are output to the second read data register 150 and the first read data register 160. When the memory is in the X8l mode, the data read from the multiple memory banks 110 are output to the first read data register 160.

[0078] Refer to Figure 10, in the embodiments of the present disclosure, the memory is in the X16 mode. The data read from multiple first sub-banks (BankA) in each bank group can be output to the first read data register 160, and the data read from multiple second sub-banks (BankB) in each bank group can be output to the second read data register 150. When the read data in the first sub-bank (BankA) needs to be transmitted to the first read data register 160, the read data in the first sub-bank (BankA) can be transmitted to the first global read data register 130 through the first data connection path 210, and the first sub-control signal corresponding to the first sub-bank (BankA) can be transmitted to the first global read data register 130 through the first signal connection path 310. When the first sub-control signal corresponding to the first sub-bank (BankA) is valid, the read data of the first sub-bank (BankA) stored in the first global read data register 130 is stored in the first read data register 160 through the corresponding second data connection path 220.

[0079] For Figure 10 the embodiments shown, the length of the second data connection path 220 corresponding to the first sub-bank (BankA) in BG3 is less than the length of the second data connection path 220 corresponding to the first sub-bank (BankA) in BG2, which is less than the length of the second data connection path 220 corresponding to the first sub-bank (BankA) in BG1, which is less than the length of the second data connection path 220 corresponding to the first sub-bank (BankA) in BG0. The length of the first signal connection path 310 corresponding to the first sub-bank (BankA) in BG3 is greater than the length of the first signal connection path 310 corresponding to the first sub-bank (BankA) in BG2, and greater than the length of the first signal connection path 310 corresponding to the first sub-bank (BankA) in BG1, and greater than the length of the first signal connection path 310 corresponding to the first sub-bank (BankA) in BG0. Thus, the read data in each first sub-bank (BankA) can reach the first read data register 160 after the same delay, so that the data window sizes of the read data in each first sub-bank (BankA) when sampled by the read data sampling signal are the same.

[0080] Referring to Figure 11, the memory bank 110 includes a first sub - memory bank (BankA) and a second sub - memory bank (BankB); the peripheral circuit 120 further includes: a plurality of second global read data registers 140, a plurality of fourth data connection paths 240, and a plurality of third signal connection paths 330. The first sub - memory bank in the same memory bank group is correspondingly connected to the same first global read data register 130 through a first data connection path 210 and a first signal connection path 310. The second sub - memory bank in the same memory bank group is correspondingly connected to the same second global read data register 140 through a fourth data connection path 240 and a third signal connection path 330; a plurality of fifth data connection paths 250, and each second global read data register 140 is connected to the first read data register 160 through a fifth data connection path 250; the lengths of the first data connection paths 210 between each first sub - memory bank and the corresponding first global read data register 130 are equal, and the lengths of the fourth data connection paths 240 between each second sub - memory bank and the corresponding second global read data register 140 are equal.

[0081] In the embodiment of the present disclosure, multiple first sub - memory banks (BankA) in the same memory bank group are correspondingly connected to the first global read data register 130, and multiple second sub - memory banks (BankB) in the same memory bank group are correspondingly connected to the second global read data register 140.

[0082] When the memory is in the X16 mode, the data read from multiple first sub - memory banks (BankA) in each memory bank group is first transmitted to the first global read data register 130, and then output to the first read data register 160. The data read from multiple second sub - memory banks (BankB) in each memory bank group is first transmitted to the second global read data register 140, and then output to the second read data register 150.

[0083] When the memory is in the X8u mode, the data read from multiple first sub - memory banks (BankA) in each memory bank group is first transmitted to the first global read data register 130, and then output to the first read data register 160. The data read from multiple second sub - memory banks (BankB) in each memory bank group is first transmitted to the second global read data register 140, and then output to the second read data register 150.

[0084] When the memory is in the X8l mode, the data read from the multiple first sub-banks (BankA) in each bank group is first transferred to the first global read data register 130 and then output to the second read data register 150. The data read from the multiple second sub-banks (BankB) in each bank group is first transferred to the second global read data register 140 and then output to the first read data register 160.

[0085] Specifically, the second sub-bank (BankB) can transfer the read data to the second global read data register 140 through the corresponding fourth data connection path 240. And transfer the corresponding control signal to the second global read data register 140 through the third signal connection path 330, and then output the read data to the first read data register 160.

[0086] In this case, the length of the fifth data connection path 250 corresponding to BG0 is greater than the length of the fifth data connection path 250 corresponding to BG1 is greater than the length of the fifth data connection path 250 corresponding to BG2 is greater than the length of the fifth data connection path 250 corresponding to BG0. Correspondingly, the length of the third signal connection path 330 corresponding to BG0 is less than the length of the third signal connection path 330 corresponding to BG1 is less than the length of the third signal connection path 330 corresponding to BG2 is less than the length of the third signal connection path 330 corresponding to BG3.

[0087] The second sub-bank (BankB) can also transfer the read data to the second global read data register 140 through the corresponding fourth data connection path 240. And transfer the corresponding control signal to the second global read data register 140 through the fourth signal connection path 340, and then output the read data to the second read data register 150 through the sixth data connection path.

[0088] In this case, the length of the sixth data connection path corresponding to BG0 is less than the length of the sixth data connection path corresponding to BG1 is less than the length of the sixth data connection path corresponding to BG2 is less than the length of the sixth data connection path corresponding to BG0. Correspondingly, the length of the fourth signal connection path 340 corresponding to BG0 is greater than the length of the fourth signal connection path 340 corresponding to BG1 is greater than the length of the fourth signal connection path 340 corresponding to BG2 is greater than the length of the fourth signal connection path 340 corresponding to BG3.

[0089] In some embodiments, refer to Figure 10 and Figure 11, the peripheral circuit 120 further includes a plurality of selection circuits 510; a first input end of the selection circuit 510 is connected to the first signal connection path 310, a second input end of the selection circuit 510 is connected to the second signal connection path 320, and an output end of the selection circuit 510 is connected to the first global read data register 130; the selection circuit 510 is configured to: in response to the data in the memory bank 110 needing to be output from the first read data register 160, select and output the control signal transmitted by the first signal connection path 310; in response to the data in the memory bank 110 needing to be output from the second read data register 150, select and output the control signal transmitted by the second signal connection path 320.

[0090] Each memory bank group may correspond to one selection circuit 510. The selection circuit 510 includes a first input end, a second input end, a selection signal end and an output end.

[0091] Specifically, when the selection signal received by the selection signal end is the first value, it indicates that the read data in the corresponding memory bank group needs to be output from the first read data register 160, and the selection circuit 510 selects to receive the control signal received by the first input end. The first input end of the selection circuit 510 is connected to the first signal connection path 310. When the selection signal received by the selection signal end is the second value, it indicates that the read data in the corresponding memory bank group needs to be output from the second read data register 150, and the selection circuit 510 selects to receive the control signal received by the second input end. The second input end of the selection circuit 510 is connected to the second signal connection path 320.

[0092] In the embodiments of the present disclosure, according to the different read data registers for selecting and outputting the read data in the memory bank 110, the selection circuit 510 is used to select and receive the signals output by the first signal connection path 310 or the second signal connection path 320, so that the read data in each memory bank 110 can reach the target read data register after the same delay, and the data window sizes of the read data in each memory bank 110 when being sampled by the read data sampling signal are the same, thereby avoiding the phenomenon of data offset.

[0093] In some embodiments, each memory bank 110 in the same memory bank group includes a first sub-memory bank and a second sub-memory bank, and a plurality of first sub-memory banks and a plurality of second sub-memory banks in the same memory bank group share one first global read data register 130.

[0094] In some embodiments, each memory bank 110 in the same memory bank group includes a first sub-memory bank and a second sub-memory bank, and a plurality of first sub-memory banks in the same memory bank group share one first global read data register 130, and a plurality of second sub-memory banks in the same memory bank group share one second global read data register.

[0095] Reference Figures 9 to 11 According to the embodiments of the present disclosure, there are also provided a plurality of repeaters 600. The repeaters 600 are configured to control the transmission direction of the read data. For example, the data is transmitted in the positive direction or the negative direction along the first direction. The repeaters 600 can be coupled to both the second data connection path 220 and the third data connection path 230. The repeaters 600 can also be coupled to the fifth data connection path 250 and the sixth data connection path. The position and number of the repeaters 600 can be set according to actual requirements, and the present disclosure does not limit this.

[0096] The embodiments of the present disclosure also provide a memory system, including: a memory controller and a memory as described in any of the above embodiments; the memory controller is configured to control the memory.

[0097] The following is in conjunction with Figures 12 to 15 to further describe the memory and the memory system.

[0098] Figure 12 FIG. shows a schematic block diagram of the composition of an exemplary electronic device according to an embodiment of the present disclosure. The electronic device 1 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory. As Figure 12 shown, the electronic device 1 can include a host and a memory system 30. The memory system 30 includes a memory controller 10 and one or more memories 20. The host can be a processor of the electronic device (e.g., a Central Processing Unit (CPU) or a Graphic Processing Unit (GPU)). The host is configured to send data to the memory 20 or receive data from the memory 20. The memory controller 10 is coupled to the memory 20 and the host and is configured to control the memory 20. The memory controller 10 can manage the data stored in the memory 20 and communicate with the host.

[0099] The memory controller 10 can be configured to control the operations of the memory 20, such as read, erase, write, and refresh operations. In some embodiments, the memory controller 10 is further configured to process an Error Correction Code (ECC) for the data read from the memory 20 or written to the memory 20. The memory controller 10 can also perform any other suitable functions, such as formatting the memory 20.

[0100] In some specific embodiments, the memory controller 10 and one or more memories 20 can be integrated into various types of electronic devices. For example, the memory controller 10 can be integrated into the north bridge of a computer motherboard or directly integrated into the computer CPU, and multiple memories 20 can be integrated into a memory module. That is to say, the memory system 30 can be implemented and encapsulated into different types of terminal electronic products.

[0101] The memory controller 10 can send data to / receive data from the host, and can send a command CMD and an address ADDR to the memory 20. The memory controller 10 can include a command generator 11, an address generator 12, a device interface 13, and a host interface 14. The host interface 14 can receive a command CMD and an address ADDR from the host. The command generator 11 can generate an access command, etc. by decoding the command CMD received from the host, and can provide the access command to the memory 20 through the device interface 13. The access command can be a signal instructing the memory 20 to write or read data by accessing a row of the memory cell array 22 corresponding to the address ADDR. The address generator 12 in the memory controller 10 can generate a row address and a column address to be accessed in the memory cell array 22 by decoding the address ADDR received from the host interface 14. In addition, the memory 20 can generate an address of a memory bank to be accessed when the memory cell array 22 includes multiple memory banks.

[0102] In addition, the memory controller 10 can control memory operations such as writing and reading by providing various signals to the memory 20 via the device interface 13. For example, the memory controller 10 can provide a write command to the memory 20. The write command is used to instruct the memory 20 to perform a write operation to store data in the memory 20.

[0103] In some embodiments, the memory 20 includes a memory cell array 22 and a peripheral circuit 120. Among them, the memory cell array 22 includes a plurality of banks, each bank includes a plurality of memory blocks (Blocks), each memory block includes a plurality of memory cell rows and a plurality of memory cell columns, each memory cell row is coupled to a corresponding word line, and each memory cell column is coupled to a corresponding bit line. The peripheral circuit 120 can write data into the memory cell array 22 or read data from the memory cell array 22 based on a command CMD and an address ADDR received from the memory controller 10, or can provide a control signal CTRL for refreshing the memory cells included in the memory cell array 220 to the row decoding circuit and the column decoding circuit. In other words, the peripheral circuit 120 can perform all operations to process the data in the memory cell array 22. The peripheral circuit 120 may include: control circuits corresponding to each bank, such as sense amplifier circuits and word-line driver circuits (Word-Line Driver WLD), etc., control circuits corresponding to each bank, such as row decoding circuits, column decoding circuits, etc., and control circuits corresponding to all banks, such as command buffers, command decoders, address buffers, input / output buffers, mode registers, etc.

[0104] The memory 20 may be a random access memory (RAM), such as a dynamic random access memory (Dynamic Random Access Memory, DRAM), a synchronous DRAM (SDRAM), a static RAM (SRAM), a double data rate SDRAM (DDR SDRAM), a DDR2 SDRAM, a DDR3 SDRAM, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), etc. Hereinafter, only DRAM will be taken as an example for illustration.

[0105] Figure 13 It is a schematic diagram of the composition block diagram of an exemplary solid state drive (Solid State Drives, SSD) according to an embodiment of the present disclosure. Here, the SSD can be understood as a kind of the foregoing Figure 12 memory system, and in this example, the DRAM can be used as a buffer memory.

[0106] As Figure 13As shown, the SSD 30a may include an SSD controller 10a, a buffer memory 20a, and a non-volatile memory 40. The SSD controller 10a may provide a physical connection between the host and the SSD 30a. That is, the SSD controller 10a may provide an interface between the host and the SSD 30a in accordance with the bus format of the host. The SSD controller 10a may decode instructions provided from the host. The SSD controller 10a may access the non-volatile memory 40 based on the decoded result. The buffer memory 20a may temporarily store write data provided from the host or data read from the non-volatile memory 40. When the host issues a read request, if the data present in the non-volatile memory 40 is cached, the buffer memory 20a may support a cache function for directly providing the cached data to the host. The data transfer rate through the bus format of the host (e.g., SATA or SAS) is much higher than the data transfer rate of the memory channel of the SSD 30a. That is, when the interface speed of the host is significantly high, the performance degradation due to the speed difference may be minimized by providing a high-capacity buffer memory 20a. In addition, the buffer memory 20a may store an address mapping table of the non-volatile memory 40. The buffer memory 20a may include, but is not limited to, DRAM. The non-volatile memory 40 is provided as a storage medium of the SSD 30a. The non-volatile memory 40 may include, but is not limited to, NAND-type memory.

[0107] Figure 14 Schematic diagram of the composition block diagram of an exemplary memory according to an embodiment of the present disclosure. Here, the memory may be understood as a kind of the memory system described above Figure 12 In this example, DRAM may be used as a storage medium.

[0108] As Figure 14 shown, the memory 30b can be easily attached or installed to the electronic device or detached from the electronic device 1 through the illustrated interface. The memory 30b may include a plurality of volatile memories 20b (e.g., DRAM) and a memory controller 10b. The memory module memory 30b can be used to write data, store data, obtain (or read) data, and / or erase data under the control of the processor of the computer. In some embodiments, the controller memory controller 10b may communicate with the DRAM using at least one communication protocol or technical standard typically associated with, for example, dual in-line memory module (DIMM), registered DIMM (RDIMM), low-loading DIMM (LRDIMM), unregistered DIMM (UDIMM), etc.

[0109] It should be noted that Figure 13 the buffer memory 20a in Figure 14 and the volatile memory 20b in Figure 15An application scenario of the memory 20.

[0110] Figure 15 The right side shows the circuit of the memory cell in DRAM. DRAM includes at least one DRAM chip (Die). Each DRAM chip includes a memory cell array. The memory cell array includes a plurality of memory cells 50 arranged in an array. Each memory cell 50 includes a transistor T (Transistor) and a capacitor C (Capacitor). The main principle of the memory cell is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The memory cells are arranged in an array, which can be regarded as a typical mesh structure. The memory cell array uses rows and columns to specify addresses. By specifying the intersection of a row and a column (by specifying the row address and column address of the DRAM), the memory controller can independently access each memory cell in the DRAM chip and perform operations such as reading, writing, or refreshing the data stored therein.

[0111] Figure 15 The left side shows the memory cell array in DRAM and a part of the peripheral circuit 120. It should be noted that the row decoding circuit responds to the address input to the row decoding circuit, selects the word line to select the row of the memory cell to be accessed. The row decoding circuit decodes the input address and enables (activates) the word line corresponding to the decoded address. The column decoding circuit responds to the address input to the column decoding circuit, selects the bit line to select the column of the memory cell to be accessed. For the specific functions of the first global data register 130, the first signal connection path 310, the first data connection path 210, the second data connection path 220, and the first read data register 160 in the peripheral circuit 120, reference can be made to the above embodiments and will not be elaborated here.

[0112] The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0113] The features disclosed in several device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0114] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the "in one embodiment" or "in an embodiment" that appears throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitude of the serial numbers of the above processes does not mean the sequence of execution. The execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the superiority or inferiority of the embodiments.

[0115] It should be noted that in this text, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0116] As described above, it is only the implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present disclosure, and all of them should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A memory device, characterized in that, it includes: a plurality of memory bank groups, each of the memory bank groups includes at least one memory bank; a peripheral circuit, including: a plurality of first global read data registers, a plurality of first data connection paths, and a plurality of first signal connection paths. Each memory bank in the same memory bank group is connected to a corresponding first global read data register through one of the first data connection paths and one of the first signal connection paths; a first read data register, and a plurality of second data connection paths. Each of the first global read data registers is connected to the first read data register through one of the second data connection paths; wherein, the lengths of the first data connection paths between each memory bank and the corresponding first global read data register are equal; the lengths of the first signal connection paths between each memory bank and the corresponding first global read data register and the lengths of the second data connection paths between the corresponding first global read data registers and the first read data register are negatively correlated.

2. The memory device according to claim 1, characterized in that, the plurality of memory bank groups are arranged in a first direction, and the plurality of memory banks are distributed on at least one of the two opposite sides of the peripheral circuit in a second direction; the first direction intersects the second direction; the plurality of first global read data registers are arranged in the first direction.

3. The memory device according to claim 2, characterized in that, the first read data register is located on one side of the plurality of first global read data registers in the first direction; the lengths of the second data connection paths between different first global read data registers and the first read data register are different; the lengths of the first signal connection paths between different first global read data registers and the corresponding memory bank groups are different.

4. The memory device according to claim 3, characterized in that, the shorter the length of the second data connection path corresponding to the first global read register closer to the first read data register, the longer the length of the first signal connection path corresponding to the first global read register closer to the first read data register.

5. The memory device according to claim 2, characterized in that, the first read data register is located between the plurality of first global read data registers; the lengths of the second data connection paths between at least some of the plurality of first global read data registers and the first read data register are different; the lengths of the first signal connection paths between at least some of the plurality of first global read data registers and the corresponding memory bank groups are different.

6. The memory device according to claim 2, characterized in that, the peripheral circuit further includes: a plurality of second signal connection paths, a second read data register, and a plurality of third data connection paths; wherein, the first global read data register is configured to: When the data in the memory bank needs to be output from the first read data register, receive the control signal transmitted through the first signal connection path; When the data in the memory bank needs to be output from the second read data register, receive the control signal transmitted through the second signal connection path; Each memory bank in the same memory bank group is connected to a corresponding first global read data register through one of the second signal connection paths; Each of the first global read data registers is connected to the second read data register through one of the third data connection paths; the second signal connection path between each memory bank and the corresponding first global read data register and the third data connection path between the corresponding first global read register and the second read data register are negatively correlated in length.

7. The memory according to claim 6, wherein, the first read data register and the second read data register are respectively located on both sides of a plurality of the first global read data registers along the first direction; the lengths of the third data connection paths between different first global read data registers and the second read data register are different; the lengths of the second signal connection paths between different first global read data registers and the corresponding memory bank groups are different.

8. The memory according to claim 6, wherein, the first read data register and the second read data register are respectively located among a plurality of the first global read data registers; the memory includes a first sub-storage area and a second sub-storage area, the first sub-storage area and the second sub-storage area are arranged along the first direction and both include a plurality of memory bank groups; the first read data register is located on the symmetry line extending along the first direction of the first sub-storage area, and the second read data register is symmetrically located on the symmetry line extending along the first direction of the second sub-storage area with respect to the perpendicular bisector of the second sub-storage area.

9. The memory according to claim 8, wherein, among the plurality of first global read data registers corresponding to the memory banks in the first sub-storage area, the lengths of the first signal connection paths between different first global read data registers and the corresponding memory bank groups are equal, and the lengths of the second data connection paths between different first global read data registers and the first read data register are equal; among the plurality of first global read data registers corresponding to the memory banks in the second sub-storage area, the lengths of the second signal connection paths between different first global read data registers and the corresponding memory bank groups are equal, and the lengths of the third data connection paths between different first global read data registers and the second read data register are equal.

10. The memory according to claim 6, wherein, The peripheral circuit further includes a plurality of selection circuits; a first input end of the selection circuit is connected to the first signal connection path, a second input end of the selection circuit is connected to the second signal connection path, and an output end of the selection circuit is connected to the first global read data register; the selection circuit is configured to: In response to the data in the memory bank needing to be output from the first read data register, select and output the control signal transmitted by the first signal connection path; In response to the data in the memory bank needing to be output from the second read data register, select and output the control signal transmitted by the second signal connection path.

11. The memory according to claim 1, wherein, the peripheral circuit further includes a plurality of signal synthesis circuits; each of the signal synthesis circuits is configured to receive control signals corresponding to a plurality of the memory banks in the same memory bank group, and synthesize the control signals corresponding to the plurality of the memory banks in the same memory bank group into a total control signal; the first global read data register is configured to receive the total control signal, and output the data read from the corresponding memory bank when the total control signal is in an enabled state.

12. The memory according to claim 11, wherein, the first signal connection path includes a first signal line and a second signal line; one end of the first signal line is connected to the memory bank, the other end of the first signal line is connected to an input end of the signal synthesis circuit, an output end of the signal synthesis circuit is connected to one end of the second signal line, and the other end of the second signal line is connected to the first global read data register; a plurality of memory banks in the same memory group share one second signal line.

13. The memory according to claim 1, wherein, the memory bank includes a first sub-memory bank and a second sub-memory bank; the peripheral circuit further includes: a plurality of second global read data registers, a plurality of fourth data connection paths, a plurality of third signal connection paths, the first sub-memory bank in the same memory bank group is connected to a corresponding first global read data register through one first data connection path and one first signal connection path, and the second sub-memory bank in the same memory bank group is connected to a corresponding second global read data register through one fourth data connection path and one third signal connection path; Multiple fifth data connection paths, each of the second global read data registers is connected to the first read data register through one of the fifth data connection paths; the lengths of the first data connection paths between each of the first sub-banks and the corresponding first global read data registers are equal, and the lengths of the fourth data connection paths between each of the second sub-banks and the corresponding second global read data registers are equal; the length of the third signal connection path between each of the second sub-banks and the corresponding second global read data register is negatively correlated with the length of the fifth data connection path between the corresponding second global read data register and the first read data register.

14. A memory system, characterized in that it includes: a memory controller and a memory according to any one of claims 1 to 13; the memory controller is configured to control the memory.

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