Memory comprising an ECC engine

Abstract

The invention relates to a memory including an ECC engine. A memory may include: a memory core; a first ECC engine configured to correct an error having a first pattern occurring in read data read from the memory core; and a second ECC engine configured to correct an error having a second pattern occurring in read data read from the memory core. One of the first ECC engine and the second ECC engine may be selectively activated based on an address for accessing the memory core.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0168735, filed on November 29, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure relate to a memory, and more particularly, to error correction in a memory. Background Art

[0004] In the early stages of the semiconductor memory industry, a plurality of originally good die were distributed on a wafer, and each die did not have defective memory cells in the memory that had passed the semiconductor manufacturing process. However, as the capacity of the memory has gradually increased, it has become difficult to produce a memory without defective memory cells. Currently, it is impossible to manufacture such a memory. One way to overcome this situation is to use a method of using redundant memory cells to repair defective memory cells in the memory.

[0005] Another way is to use an error - correcting code (ECC) engine that corrects errors in memory cells. Summary of the Invention

[0006] A memory according to an embodiment of the present disclosure may include: a memory core; a first ECC engine configured to correct an error having a first pattern that occurs in read data read from the memory core; and a second ECC engine configured to correct an error having a second pattern that occurs in read data read from the memory core, wherein one of the first ECC engine and the second ECC engine is selectively activated based on an address for accessing the memory core.

[0007] A memory according to an embodiment of the present disclosure may include: a memory core; an ECC engine configured to correct an error in data read from the memory core; and a data exchange circuit configured to change an arrangement of data transmitted between the ECC engine and the memory core based on an address for accessing the memory core.

[0008] A method of operating a memory according to an embodiment of the present disclosure may include: correcting, by a first ECC engine, an error having a first pattern that occurs in read data read from the memory core based on an address for accessing the memory core; and correcting, by a second ECC engine, an error having a second pattern that occurs in read data read from the memory core based on an address for accessing the memory core. Brief Description of the Drawings

[0009] Figure 1 is a diagram showing a configuration of an ECC engine according to an embodiment of the present disclosure.

[0010] Figure 2 is a diagram showing the configuration of a memory according to an embodiment of the present disclosure.

[0011] Figure 3 is a diagram showing the form in which 8-bit data is stored in Figure 2 the cell region of.

[0012] Figure 4 is a diagram showing the configuration of a memory according to another embodiment of the present disclosure.

[0013] Figure 5 is a diagram showing the form in which 8-bit data is stored in Figure 4 the cell region of.

[0014] Figure 6 is a diagram for describing the operation of a data exchange circuit according to an embodiment of the present disclosure. Detailed Description

[0015] Various embodiments of the present disclosure relate to a technique for reducing the circuit area required for error correction of a memory.

[0016] Embodiments of the present disclosure provide a technique for reducing the circuit area required for error correction of a memory.

[0017] Hereinafter, embodiments according to the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

[0018] Figure 1 is a diagram showing the configuration of an ECC engine 100 according to an embodiment of the present disclosure.

[0019] Referring to Figure 1 , the ECC engine 100 may include an error correction code encoder 110 and an error correction code decoder 120.

[0020] The error correction code encoder 110 may generate an error correction code ECC by using data DATA transmitted from outside the memory (e.g., transmitted from a memory controller) during a write operation. That is, the error correction code encoder 110 may generate an error correction code ECC for correcting errors in the data by encoding the data DATA. The data DATA to be encoded during the process of generating the error correction code ECC is also referred to as a message. During a write operation, since the error correction code ECC is generated but no error correction operation is performed, the data DATA input to the error correction code encoder 110 and the data DATA' output from the error correction code encoder 110 may be the same.

[0021] During a write operation, data DATA' and an error correction code ECC can be stored in a memory core (not shown). During a read operation, data DATA' and the error correction code ECC can be read from the memory core and sent to an error correction code decoder 120.

[0022] During a read operation, the error correction code decoder 120 can correct errors in the data DATA' by using the error correction code ECC. Correcting errors can mean detecting errors in the data DATA' by using the error correction code ECC and correcting the errors when they are detected. The data DATA corrected by the error correction code decoder 120 can be output to the outside of the memory (e.g., sent to a memory controller).

[0023] Figure 2 FIG. is a diagram showing a configuration of a memory 200 according to an embodiment of the present disclosure.

[0024] Referring to Figure 2 , the memory 200 may include a data transmit / receive circuit 210, an ECC block 220, and a memory core 270.

[0025] The data transmit / receive circuit 210 can transmit / receive data DATA. The data transmit / receive circuit 210 can receive the data DATA sent from a memory controller during a write operation and can send the data DATA to the memory controller during a read operation. Figure 2 FIG. shows that the number of bits of the data DATA transmitted / received by the data transmit / receive circuit 210 during one write and read operation is 256 bits (i.e., D0 to D255).

[0026] During a write operation, the ECC block 220 can generate 16-bit error correction codes E0 to E15 by using the data D0 to D255 received via the data transmit / receive circuit 210. Since the error correction codes E0 to E15 are generated during a write operation without performing an error correction operation, the data D0 to D255 input to the ECC block 220 during a write operation and the data D0' to D255' output from the ECC block 220 can be the same.

[0027] During a read operation, the ECC block 220 can correct errors in the data D0' to D255' sent from the memory core 270 by using the error correction codes E0 to E15. Correcting errors can mean detecting errors in the data D0' to D255' by using the error correction codes E0 to E15 and correcting the errors when they are detected.

[0028] The ECC block 220 may include a first ECC engine 221 and a second ECC engine 223. One of the two ECC engines 221 and 223 may be selected and activated by a row address R_ADD for accessing the memory core 270. That is, the operations of generating error correction codes E0 to E15 and correcting errors may be performed by the activated ECC engine among the two ECC engines 221 and 223. Details thereof are described below.

[0029] The memory core 270 may include a plurality of cell regions 275_0 to 275_33. Each cell region may include a plurality of rows, a plurality of columns, and a plurality of memory cells formed at intersections of the rows and columns. Each of the cell regions 275_0 to 275_33 may store 8-bit data for one write operation. For example, data D0' to D7' may be stored in the cell region 275_0, and data D8' to D15' may be stored in the cell region 275_1. Error correction codes E0 to E7 may be stored in the cell region 275_32, and error correction codes E8 to E15 may be stored in the cell region 275_33.

[0030] During a write operation, one of the plurality of rows (i.e., word lines) may be selected in each of the cell regions 275_0 to 275_33 by a row address R_ADD, eight of the plurality of columns (i.e., bit lines) may be selected by a column address C_ADD, and data may be stored in eight memory cells of the selected row and the selected column. Similarly, during a read operation, data may be read from eight memory cells selected by a row address R_ADD and a column address C_ADD in each of the cell regions 275_0 to 275_33.

[0031] Figure 2 FIG. shows that 256-bit data D0 to D255 is input to / output from the memory 200 during one write and read operation, and 16-bit error correction codes E0 to E15 are used. However, this is merely an example, and the number of bits of the data and the number of bits of the error correction code may be different from the Figure 2 example in.

[0032] Figure 3 is a diagram showing a form in which 8-bit data D0' to D7' is stored in the Figure 2 cell region 275_0 of.

[0033] Figure 3 Part (a) of shows a form in which data D0' to D7' is stored in the cell region 275_0 when the row address R_ADD is even.

[0034] Refer to Figure 3In (a), the 8-bit data D0' to D7' are stored in 8 memory cells formed at the intersections between the even word line Even WL (meaning the word line selected by an even row address) and 8 bit lines BLk to BLk+7 (meaning 8 bit lines selected by a column address). Figure 3 The dashed lines in (a) of are lines that group the memory cells where a storage node bridging failure is highly likely to occur. For example, this may mean that bridging is highly likely to occur between the storage nodes of the memory cell storing data D0' and the storage node of the memory cell storing data D1', and bridging is highly likely to occur between the storage nodes of the memory cell storing data D2' and the storage node of the memory cell storing data D3'. That is, errors are highly likely to occur simultaneously in data D0' and data D1', and errors are highly likely to occur simultaneously in data D2' and data D3'.

[0035] Figure 3 Part (b) of shows the form in which the data D0' to D7' are stored in the cell region 275_0 when the row address R_ADD is odd.

[0036] Refer to Figure 3 In (b) of, the 8-bit data D0' to D7' are stored in 8 memory cells formed at the intersections between the odd word line Odd WL (meaning the word line selected by an odd row address) and 8 bit lines BLk to BLk+7 (meaning 8 bit lines selected by a column address). Figure 3 The dashed lines in (b) of are lines that group the memory cells where a storage node bridging failure is highly likely to occur. In Figure 3 In (b) of, different from Figure 3 In (a) of, errors are highly likely to occur simultaneously in data D1' and data D2', and errors are highly likely to occur simultaneously in data D5' and data D6'. This may be because the arrangement forms of the memory cells of the even word line Even WL and the odd word line Odd WL are different from each other.

[0037] That is, the 2-bit data pairs in which errors are highly likely to occur simultaneously are different from the cases of Figure 3 (a) and (b) of.

[0038] Figure 3 shows the form in which the 8-bit data D0' to D7' are stored in the cell region 275_0. The forms in which the 8-bit data D8' to D15' are stored in the cell region 275_1, the 8-bit data D16' to D23' are stored in the cell region 275_2, and the data D24' to D255' and the error correction codes E0 to E15 are stored in the cell regions 275_3 to 275_33 may also be the same.

[0039] Refer again to Figure 2 , each of the first ECC engine 221 and the second ECC engine 223 of the ECC block 220 can correct all single-bit errors that occur in the data D0' to D255'. For example, when an error occurs only in the data D9', the first ECC engine 221 and the second ECC engine 223 can correct the error.

[0040] Each of the first ECC engine 221 and the second ECC engine 223 can correct double-bit errors with limited patterns that occur in the data D0' to D255'. It would be preferable if the ECC engine could correct double-bit errors with all patterns; however, in this case, the number of bits of the error correction code needs to be increased, and the area of the ECC engine needs to be greatly expanded.

[0041] As Figure 3 shown in (a) of

[0042] As Figure 3 shown in (b) of

[0043] When the row address R_ADD is even, that is, when accessing the even word lines EvenWL in the cell regions 275_0 to 275_33, the first ECC engine 221 can be selected and activated in the ECC block 220. That is, during the write operation and the read operation, when the row address R_ADD is even, the first ECC engine 221 can be used. This is because the first ECC engine 221 can correct 2-bit errors that are highly likely to occur in the even word line EvenWL, so it is advantageous to use the first ECC engine 221.

[0044] When the row address R_ADD is odd, that is, when accessing the odd word lines OddWL in the cell regions 275_0 to 275_33, the second ECC engine 223 can be selected and activated in the ECC block 220. That is, during the write operation and the read operation, when the row address R_ADD is odd, the second ECC engine 223 can be used. This is because the second ECC engine 223 can correct 2-bit errors that are highly likely to occur in the odd word line OddWL, so it is advantageous to use the second ECC engine 223.

[0045] Since one of the first ECC engine 221 and the second ECC engine 223 is selected and used according to the likelihood of error occurrence, the error correction efficiency of the memory 200 can be improved.

[0046] Figure 4 FIG. is a diagram showing the configuration of a memory 400 according to another embodiment of the present disclosure.

[0047] Referring to Figure 4 , the memory 400 may include a data transmit / receive circuit 410, an ECC block 420, a data exchange circuit 430, and a memory core 470.

[0048] The data transmit / receive circuit 410 can transmit / receive data DATA. The data transmit / receive circuit 410 can receive the data DATA sent from the memory controller during the write operation, and can send the data DATA to the memory controller during the read operation. Figure 4 It is shown that the number of bits of the data DATA transmitted / received by the data transmit / receive circuit 410 during one write and read operation is 256 bits (i.e., D0 to D255).

[0049] During a write operation, the ECC block 420 can generate 16-bit error correction codes E0 to E15 by using the data D0 to D255 received via the data transmission / reception circuit 410. Since the error correction codes E0 to E15 are generated during the write operation without performing an error correction operation, the data D0 to D255 input to the ECC block 420 during the write operation and the data D0' to D255' output from the ECC block 420 can be the same.

[0050] During a read operation, the ECC block 420 can correct errors in the data D0' to D255' transmitted from the memory core 470 by using the error correction codes E0 to E15 transmitted from the memory core 470. Correcting an error can mean detecting an error in the data D0' to D255' by using the error correction codes E0 to E15 and correcting the error when the error is detected.

[0051] The ECC block 420 can include a first ECC engine 421 and a second ECC engine 423. One of the two ECC engines 421 and 423 can be selected and activated by the row address R_ADD for accessing the memory core 470. That is, the operations of generating the error correction codes E0 to E15 and correcting errors can be performed by the activated ECC engine among the two ECC engines 421 and 423. The details are described below.

[0052] The data exchange circuit 430 can change the arrangement of the data transmitted between the ECC block 420 and the memory core 470 in response to the addresses R_ADD and C_ADD. That is, the data exchange circuit 430 can change the correspondence between the data D0' to D255' and the data D0” to D255”. The data exchange circuit 430 can also change the correspondence between the error correction codes E0 to E15 and the error correction codes E0' to E15'. The details are described below.

[0053] The memory core 470 can include a plurality of cell regions 475_0 to 475_33. Each of the cell regions 475_0 to 475_33 can include a plurality of rows, a plurality of columns, and a plurality of memory cells formed at the intersections of the rows and columns. Each of the cell regions 475_0 to 475_33 can store 8-bit data for one write operation. For example, the data D0” to D7”' can be stored in the cell region 475_0, and the data D8” to D15” can be stored in the cell region 475_1. The error correction codes E0' to E7' can be stored in the cell region 475_32, and the error correction codes E8' to E15' can be stored in the cell region 475_33.

[0054] During a write operation, one of a plurality of rows (i.e., word lines) can be selected in each of cell regions 475_0 to 475_33 by a row address R_ADD, eight of a plurality of columns (i.e., bit lines) can be selected by a column address C_ADD, and data can be stored in eight memory cells of the selected row and the selected columns. Similarly, during a read operation, data can be read from eight memory cells selected by a row address R_ADD and a column address C_ADD in each of cell regions 475_0 to 475_33.

[0055] Figure 5 is a diagram showing a form in which 8-bit data D0” to D7” is stored in Figure 4 cell region 475_0.

[0056] Figure 5 Part (a) of shows a form in which data D0” to D7” is stored in cell region 475_0 when the row address R_ADD is even and the column address C_ADD is even.

[0057] Referring to Figure 5 (a) of, 8-bit data D0” to D7” is stored in eight memory cells formed at intersections between an even word line Even WL (indicating a word line selected by an even row address) and eight bit lines BLn to BLn+7 (meaning eight bit lines selected by an even column address). Figure 5 The dashed line in (a) of is a line that groups memory cells in which a storage node bridging failure is highly likely to occur. For example, this may mean that bridging is highly likely to occur between the storage nodes of the memory cell storing data D0” and the storage node of the memory cell storing data D1”, and bridging is highly likely to occur between the storage nodes of the memory cell storing data D2” and the storage node of the memory cell storing data D3”. That is, errors are highly likely to occur simultaneously in data D0” and data D1”, and errors are highly likely to occur simultaneously in data D2” and D3”.

[0058] Figure 5 Part (b) of shows a form in which data D0” to D7” is stored in cell region 475_0 when the row address R_ADD is even and the column address C_ADD is odd.

[0059] Referring to Figure 5 (b) of, 8-bit data D0” to D7” is stored in eight memory cells formed at intersections between an even word line Even WL and eight bit lines BLm to BLm+7 (meaning eight bit lines selected by an odd column address). In Figure 5In the case of (b), data D0” to D7” are stored in eight storage units in the order of D6”, D7”, D4”, D5”, D2”, D3”, D0” and D1”. Figure 5 The dashed line in (b) is a line that groups storage units where a storage node bridging failure is highly likely to occur. In Figure 5 (b), the data are stored in the storage units in a different order from Figure 5 (a), but the data where errors are highly likely to occur are the same.

[0060] That is to say, in Figure 5 (b), as in Figure 5 (a), errors are highly likely to occur simultaneously in data D2” and data D3”, and errors are highly likely to occur simultaneously in data D0” and data D1”.

[0061] Figure 5 Part (c) shows the form in which data D0” to D7” are stored in cell region 475_0 when the row address R_ADD is odd and the column address C_ADD is even.

[0062] Referring to Figure 5 (c), 8-bit data D0” to D7” are stored in 8 storage units formed at the intersection between an odd word line Odd WL (meaning a word line selected by an odd row address) and 8 bit lines BLn to BLn+7 (meaning 8 bit lines selected by an even column address). Figure 5 The dashed line in (c) is a line that groups storage units where a storage node bridging failure is highly likely to occur. In Figure 5 (c), different from Figure 5 (a) and (b), errors are highly likely to occur simultaneously in data D1” and data D2”, and errors are highly likely to occur simultaneously in data D5” and data D6”. This may be due to the different forms of arrangement of the storage units of the even word line Even WL and the odd word line Odd WL.

[0063] That is to say, the pair of 2-bit data where errors are highly likely to occur simultaneously is different from Figure 5 the case of (c) and Figure 5 the cases of (a) and (b).

[0064] Figure 5 Part (d) shows the form in which data D0” to D7” are stored in cell region 475_0 when the row address R_ADD is odd and the column address C_ADD is odd.

[0065] Referring to Figure 5In (d), the 8-bit data D0” to D7” are stored in 8 memory cells formed at the intersections between the odd word line Odd WL and 8 bit lines BLm to BLm+7 (meaning 8 word lines selected by an odd column address). Figure 5 The dashed lines in (d) of are lines that group the memory cells in which a storage node bridging failure is highly likely to occur. In Figure 5 the case of (d), the data D0” to D7” are stored in the eight memory cells in the order of D6”, D7”, D4”, D5”, D2”, D3”, D0” and D1”. Figure 5 The dashed lines in (d) of are lines that group the memory cells in which a storage node bridging failure is highly likely to occur. In Figure 5 in (d), different from Figure 5 (a) to (c) of, errors are highly likely to occur simultaneously in data D7” and data D4”, highly likely to occur simultaneously in data D5” and data D2”, and highly likely to occur simultaneously in data D3” and data D0”.

[0066] That is to say, in Figure 5 the case of (d), the 2-bit data pairs in which errors are highly likely to occur simultaneously are different from Figure 5 (a) to (c) of.

[0067] Figure 5 shows the form in which the 8-bit data D0” to D7” are stored in the cell area 475_0. The forms in which the 8-bit data D8” to D15” are stored in the cell area 475_1, the 8-bit data D16” to D23” are stored in the cell area 475_2, and the data D24” to D255” and the error correction codes E0' to E15' are stored in the cell areas 475_3 to 475_33 can also be the same.

[0068] Referring again to Figure 4 , each of the first ECC engine 421 and the second ECC engine 423 of the ECC block 420 can correct all 1-bit errors occurring in the data D0' to D255'. For example, when an error occurs only in the data D9', the first ECC engine 421 and the second ECC engine 423 can correct the error.

[0069] Each of the first ECC engine 421 and the second ECC engine 423 can correct 2-bit errors with limited patterns occurring in the data D0' to D255'. If the ECC engine can correct 2-bit errors with all patterns, it would be preferable; however, in this case, the number of bits of the error correction code needs to be increased, and the area of the ECC engine needs to be greatly expanded.

[0070] As shown Figure 5 in (a) and (b) of Figure 5 , the first ECC engine 421 can correct errors in 2-bit data with patterns where errors may occur simultaneously. For example, when an error occurs in 2-bit data D0' and D1', in 2-bit data D2' and D3', in 2-bit data D4' and D5', or in 2-bit data D6' and D7', the first ECC engine 421 can correct the error. Similarly, even when an error occurs in 2-bit data D8' and D9', the first ECC engine 421 can correct the error. That is, the first ECC engine 421 can correct errors that occur in 2-bit data Dx' and Dx + 1' (x is an even number 0 or greater). On the other hand, when an error occurs in 2-bit data D1' and D2', the first ECC engine 421 cannot correct the error.

[0071] As shown Figure 5 in (c) of Figure 5 , the second ECC engine 423 can correct errors in 2-bit data with patterns where errors may occur simultaneously. For example, when an error occurs in 2-bit data D1' and D2', in 2-bit data D3' and D4', in 2-bit data D5' and D6', or in 2-bit data D7' and D0', the second ECC engine 423 can correct the error. Similarly, even when an error occurs in 2-bit data D9' and D10', the second ECC engine 423 can correct the error. On the other hand, the second ECC engine 423 cannot correct errors in 2-bit data that can be corrected by the first ECC engine 421. For example, the second ECC engine 423 cannot correct an error that occurs in 2-bit data D0' and D1'.

[0072] When the row address R_ADD is even, that is, when accessing the even word lines EvenWL in the cell regions 475_0 to 475_33, the first ECC engine 421 can be selected and activated in the ECC block 420. That is, during the write operation and the read operation, when the row address R_ADD is even, the first ECC engine 421 can be used. This is because the first ECC engine 421 can correct highly likely 2-bit errors as shown Figure 5 in (a) and (b) of Figure 5 , so it is advantageous to use the first ECC engine 421.

[0073] When the row address R_ADD is odd, that is, when accessing the odd word lines OddWL in the cell regions 475_0 to 475_33, the second ECC engine 423 can be selected and activated in the ECC block 420. That is, during the write operation and the read operation, when the row address R_ADD is odd, the second ECC engine 423 can be used. The second ECC engine 423 can correct Figure 5 the highly probable 2-bit errors shown in (c) of Figure 5 . However, since the second ECC engine 423 cannot correct the highly probable 2-bit errors shown in

[0074] (d) of Figure 5 , the data exchange circuit 430 may be required.

[0075] Figure 6 FIG. is a diagram for describing the operation of the data exchange circuit 430 according to another embodiment of the present disclosure. Figure 6 Part (a) of Figure 6 shows the operation of the data exchange circuit 430 when the row address R_ADD is odd and the column address C_ADD is odd. Referring to Figure 5 (a) of

[0076] Figure 6 , data D0” corresponds to data D6', data D1” corresponds to data D7', data D2” corresponds to data D4', data D3” corresponds to data D5', data D4” corresponds to data D2', data D5” corresponds to data D3', data D6” corresponds to data D0', and data D7” corresponds to data D1'. As a result, the second ECC engine 423 can correct Figure 6 the highly probable 2-bit errors shown in (c) of Figure 5 , such as the 2-bit error that occurs in D7” and D4”.

[0076] Figure 6 Part (b) of Figure 6 shows the operation of the data exchange circuit 430 when the row address R_ADD is even and when the row address R_ADD is odd and the column address C_ADD is even. Referring to Figure 6In (b) thereof, data D0” to D7” and data D0' to D7' correspond to each other in a one-to-one manner without changing the order.

[0077] Figure 6 Parts (a) and (b) thereof only show the correspondence relationship between data D0” to D7”, but data D8” to D255” and error correction codes E0' to E15' can correspond to each other in the same manner.

[0078] According to the above embodiments of the present disclosure, a plurality of ECC engines capable of correcting errors with different patterns are provided, and one of the plurality of ECC engines can be selected according to an address. According to the probability of error occurrence, the error correction efficiency can be improved by selecting an appropriate ECC engine. In order to increase the number of error patterns that can be processed by an ECC engine, the arrangement of data transmitted between the ECC engine and the memory core can be changed according to an address. This can increase the error occurrence patterns that can be processed by one ECC engine. The above features can be used together or individually.

[0079] Although the embodiments according to the technical idea of the present disclosure have been described above with reference to the drawings, this is only for describing the embodiments according to the concept of the present disclosure, and the present disclosure is not limited to the above embodiments. Without departing from the technical idea of the present disclosure defined in the appended claims, those skilled in the art to which the present disclosure pertains can make various types of substitutions, modifications, and changes to the embodiments, and it should be understood that these substitutions, modifications, and changes belong to the scope of the present disclosure. In addition, these embodiments can be combined to form additional embodiments.

Claims

1. A memory, comprising: Memory core; A first ECC engine that: corrects errors having a first pattern occurring in read data read from the memory core; and a second ECC engine that: corrects errors having a second pattern occurring in read data read from the memory core, One of the first ECC engine and the second ECC engine is selectively activated based on an address used to access the memory core.

2. The memory according to claim 1, wherein: During a write operation of the memory, an ECC engine selected from the first ECC engine and the second ECC engine generates a write error correction code by using write data, and the write data and the write error correction code are written to the memory core; as well as During a read operation of the memory, the selected ECC engine corrects the error in the read data by using the read data and a read error correction code.

3. The memory according to claim 1, wherein: The first ECC engine corrects random 1-bit errors and 2-bit errors arranged in the first pattern in the read data; as well as The second ECC engine corrects random 1-bit errors and 2-bit errors arranged in the second pattern in the read data.

4. The memory according to claim 2, further comprising: A data exchange circuit changes the arrangement of data transmitted between the selected ECC engine and the memory core according to the address.

5. The memory according to claim 4, wherein: The data exchange circuit also changes an arrangement of error correction codes transmitted between the selected ECC engine and the memory core according to the address.

6. The memory according to claim 4, wherein: The address includes a row address and a column address; and One of the first ECC engine and the second ECC engine is selected according to whether the value of the row address is an even number or an odd number.

7. The memory according to claim 6, wherein: When the second ECC engine is selected, the data exchange circuit changes the arrangement of the data according to whether the value of the column address is an even number or an odd number; as well as When the first ECC engine is selected, the data exchange circuit does not change the arrangement of the data.

8. The memory according to claim 1, wherein: An error pattern mainly occurring in data read from the memory core differs depending on the address.

9. A memory comprising: Memory core; An ECC engine that: corrects errors in read data read from the memory core; and A data exchange circuit changes the arrangement of data transferred between the ECC engine and the memory core based on an address used to access the memory core.

10. The memory according to claim 9, wherein: During a write operation of the memory, the ECC engine generates a write error correction code by using write data, and the write data and the write error correction code are written to the memory core; as well as During a read operation of the memory, the ECC engine corrects errors in the read data by using the read data and a read error correction code.

11. The memory according to claim 10, wherein: The data exchange circuit also changes an arrangement of error correction codes transmitted between the ECC engine and the memory core according to the address.

12. The memory according to claim 9, wherein: The address includes a row address and a column address; and The data exchange circuit changes the arrangement according to whether the value of the row address is an even number or an odd number.

13. The memory according to claim 9, wherein: The address includes a row address and a column address; and The data exchange circuit changes the arrangement according to whether the value of the column address is an even number or an odd number.

14. The memory according to claim 9, wherein: An error pattern mainly occurring in data read from the memory core differs depending on the address.

15. A method for operating a memory, the method comprising: correcting, by a first ECC engine, an error having a first pattern occurring in read data read from the memory core based on an address used to access the memory core; as well as An error having a second pattern occurring in the read data read from the memory core is corrected by a second ECC engine based on the address used to access the memory core.

16. The operating method according to claim 15, further comprising: Arrangement of data transferred between the memory core and the first and second ECC engines is changed based on the address used to access the memory core.

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