Media scrubber in memory system

Abstract

The invention relates to a media scrubber in a memory system. The controller may count the number of forwarded codewords in the memory media, for example during a scrubbing cycle. The controller may add the number to a total number of forwarding codewords in the memory media. The controller may avoid forwarding additional codewords based on the number. When a spare bit is allocated to an error bit in a codeword, the controller may write a valid logic state to the spare bit. The individual memory cells may indicate a change in allocation of the spare bits and whether the spare bits contain a valid logic state. The controller may retrieve a codeword from a memory media and invert one or more bits of the codeword prior to writing the codeword to the memory media.

Description

[0001] Relevant information on divisional applications

[0002] This application is a divisional application. Its parent application is a patent application for invention titled "Media Scrubber in Memory System" with an application date of July 23, 2019, an application number of 201980057563.5.

[0003] Cross-reference

[0004] This patent application claims priority to PCT Application No. PCT / US2019 / 043052, titled "Media Scrubber in Memory System", filed by Pawlowski on July 23, 2019, which claims priority to U.S. Patent Application No. 16 / 516,936, titled "Media Scrubber in Memory System", filed by Pawlowski on July 19, 2019, and U.S. Provisional Patent Application No. 62 / 702,765, titled "Media Scrubber in Memory System", filed by Pawlowski on July 24, 2018. Each of the U.S. patent applications is assigned to the assignee of this application, and each of the U.S. patent applications is hereby incorporated by reference in its entirety. Technical Field

[0005] This technical field relates to media scrubbers in memory systems. Background Art

[0006] The following generally relates to operating a memory subsystem or system, and more particularly, to media scrubber operations in a memory system.

[0007] A computing system may include a memory subsystem or system that includes various types of memory devices and controllers coupled to one or more buses to manage information in a plurality of electronic devices such as computers, wireless communication devices, Internet of Things, cameras, digital displays, etc. Memory devices are widely used to store information in such electronic devices. Information is stored by programming different states of the memory device. For example, a binary device has two states, which are typically represented by a logic "1" or a logic "0". In other systems, more than two states may be stored in the memory device. To access the stored information, components of the electronic device may read or sense the stored state in the memory device. To store information, components of the electronic device may write or program a state in the memory device.

[0008] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, NAND flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory can maintain its logical state over an extended period of time even without an external power source. Volatile memory cells (e.g., DRAM cells) may lose their stored state over time when disconnected from an external power source.

[0009] An improved computing system may include enhancing the performance of the memory system, such as reducing power consumption, increasing memory capacity and reliability, improving read / write speed, providing non-volatility by using a permanent memory medium or reducing manufacturing cost at a certain performance point, and other metrics. SUMMARY

[0010] A method is described. The method may include: identifying a value of a first counter associated with a memory medium, the first counter indicating a first number of codewords retained at the memory medium during a first duration, the first number of codewords being configured to be forwarded codewords; setting a value of a second counter associated with the memory medium at least in part based on identifying the value of the first counter, the second counter indicating a second number of codewords retained at the memory medium during a second duration, the second number of codewords being configured to be forwarded codewords; and receiving a first codeword from the memory medium at least in part based on setting the value of the second counter.

[0011] Another method is described. The method can include: receiving a codeword reserved at a portion of a memory medium, the codeword including a plurality of bits including a certain number of spare bits for the codeword; accessing a memory array of a port manager at least in part based on receiving the codeword; performing an error control operation on the codeword at least in part based on accessing the memory array of the port manager to restore a logical state of the plurality of bits; and writing the logical state of the bits in the plurality of bits at spare bits in the certain number of spare bits at least in part based on performing the error control operation.

[0012] Another method is described. The method can include: receiving a codeword from an address of a memory medium, the codeword including a set of bits; inverting a portion of the set of bits at least in part based on receiving the codeword; setting values of bits in the set of bits at least in part based on inverting the portion of the set of bits to indicate a codeword condition including an inverted state of the codeword; and writing the codeword back to the address of the memory medium at least in part based on setting the values of the bits indicating the inverted state. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 An example of a computing system supporting media scrubber operations in a memory system in accordance with aspects disclosed herein is shown.

[0014] Figure 2 An example of a computing system supporting media scrubber operations in a memory system in accordance with aspects disclosed herein is shown.

[0015] Figure 3 An example of a codeword format supporting media scrubber operations in a memory system in accordance with aspects disclosed herein is shown.

[0016] Figure 4 An example of a configuration of a memory die and a configuration of a memory medium supporting media scrubber operations in a memory system in accordance with aspects disclosed herein is shown.

[0017] Figure 5 A block diagram of a device supporting media scrubber operations in a memory system in accordance with aspects disclosed herein is shown.

[0018] Figures 6 to 8 One or more methods supporting media scrubber operations in a memory system in accordance with aspects disclosed herein are shown. DETAILED DESCRIPTION

[0019] The performance of a computing system (e.g., a server that includes a memory system or subsystem) can depend on various factors, such as providing reliable information to the computing system with low latency (e.g., load-to-use latency). In the context of a computing system or subsystem, the data carrying the information can be referred to as a codeword. In some cases, a codeword can include a certain amount of user data and additional bits (e.g., bits that support error control operations), where the additional bits carry various information to provide reliable user data with low latency. A codeword can be associated with an element of the computing system such as a memory medium of a memory system or subsystem and can be transmitted and received during one or more access operations or background operations or both. A background operation in a computing system can refer to a process that runs without external or user intervention (e.g., an access command from a host device).

[0020] In some cases, the memory cells of one or more memory dies in a memory medium can support a limited number of access operations (e.g., read cycles or write cycles or both) before becoming unreliable or problematic. In some cases, the memory cells can experience a change in electrical characteristics (e.g., the threshold voltage of the memory cells) after a certain period of time without access operations. Such changes (e.g., an increase in the threshold voltage of the memory cells) can adversely affect the operating window of the memory cells, such that the error rate of the memory medium such as the raw bit error rate (RBER) can increase. When a memory cell becomes unreliable (e.g., due to the limited number of access operations that the memory cell can support or the inherent change in the electrical characteristics of the memory cell without access operations or both), the information generated by the memory cell can become incorrect, less reliable, or invalid, and such a memory cell (or the information generated by the memory cell) can be referred to as an error bit. When a certain number of memory cells associated with a codeword generate error bits, the codeword (e.g., the user data in the codeword) can become incorrect, less reliable, or invalid beyond the error recovery capabilities of the memory system or subsystem.

[0021] In some cases, one or more spare bits in a codeword can be allocated to replace an error bit in the codeword. In some cases, the overall unstable state of a codeword may require configuring the codeword as a forwarding codeword that points to a different address to retrieve reliable user data. In some cases, performing an access operation (e.g., a read operation, a write operation) can mitigate an undesired change in the electrical characteristics of the memory cells that hold the codeword. Thus, operations that can efficiently perform the various functions described herein (e.g., allocating one or more spare bits to replace an error bit in a codeword, writing one or more spare bits with valid information to replace an error bit that supports low-latency operations, counting and monitoring the number of forwarding codewords retained at a memory medium, periodically performing access operations on a set of codewords retained at a memory medium) can improve the reliability of the system. In some cases, the various functions described herein can be referred to as media scrubber operations and can be performed as part of one or more background operations to improve the overall performance of a computing system.

[0022] A controller (e.g., a port manager associated with a memory medium) can, in some cases, count or monitor the number of forwarding codewords retained in a memory medium as part of a media scrubber operation. The controller can identify the value of a first counter associated with the memory medium. The first counter can indicate the number of codewords that are configured as forwarding codewords during a scrubbing period (e.g., the duration during which a media scrubber operation can be performed on the memory medium). The controller can set (e.g., initially set, update) the value of a second counter associated with the memory medium based on the value of the first counter, where the second counter can indicate the total number of forwarding codewords that can be accumulated in the memory medium during the lifetime of the memory medium. The lifetime of the memory medium can refer to the estimated duration during which the memory medium meets a set of operating criteria.

[0023] The controller can also reset the value of the first counter based on setting the value of the second counter before starting the next scrubbing period to count another number of codewords that are configured as forwarding codewords during the next scrubbing period. In this way, the controller can count the number of codewords that are configured as forwarding codewords during a given scrubbing period and can accumulate the total number of forwarding codewords retained at the memory medium during the lifetime of the memory medium. In some cases, the controller can avoid configuring additional codewords as forwarding codewords based on the number of forwarding codewords during a scrubbing period or during the lifetime of the memory medium.

[0024] The memory array of a memory die can be configured to include a set of minimum substitution regions (MSRs). The MSRs can be configured as reasonable fault accommodation areas for efficiently managing (e.g., replacing, substituting) error bits in the memory array. In some cases, an MSR can include a group of memory cells of data units configured to be associated with error control operations. Further, each bit of a codeword (e.g., each of the 1,408 bits in a codeword) can be associated with a corresponding MSR in the set (e.g., 1,408 MSRs). A group of MSRs across a set of channels of a memory medium (e.g., a group of MSRs operating in parallel) can hold a certain number of codewords. A group of MSRs configured to produce a certain number of codewords can be referred to as an MSR stripe or an MSR region. In some cases, an MSR stripe can be associated with a bit (e.g., a flag) in a separate memory array, where the bit can be configured to indicate a change in the substitution relationship (e.g., one or more indications of spare bit allocation for replacing one or more error bits) for the certain number of codewords held at the MSR stripe.

[0025] The controller can, in some cases as part of a media scrubbing operation (e.g., during a first media scrubbing cycle for an MSR stripe), allocate one or more spare bits in a codeword (e.g., one or more MSRs corresponding to the spare bits) to replace an error bit (e.g., an MSR corresponding to the error bit) in a codeword (e.g., one of the certain number of codewords held at the MSR stripe). The controller can set a bit (e.g., a flag) in a separate memory array to indicate such a change in the substitution relationship associated with the codewords held at the MSR stripe. Setting the bit (e.g., the flag) can also indicate that, although the substitution relationship of the spare bits may have been determined, the spare bits may not contain a valid logical state of the codeword.

[0026] The controller can, in some cases as part of a media scrubbing operation (e.g., during a second media scrubbing cycle for an MSR stripe), access the codeword, replace the error bit with the one or more spare bits according to the substitution relationship stored in a separate memory array, and perform error control operations to restore the logical state of the codeword (e.g., the codeword including the one or more spare bits replacing the error bit). The controller can write the restored logical state (e.g., a valid logical state) at the one or more spare bits and can reset the bit (e.g., the flag) in the separate memory array. In this way, the one or more spare bits can contain a valid logical state of the codeword, and the bit (e.g., the flag) can indicate that the one or more spare bits contain a valid logical state to be implemented (multiplexed into the bit stream of the codeword with a series of data bursts) when the host requests the codeword.

[0027] The controller can retrieve codewords from a memory medium as part of the operation of a media scrubber in some cases and invert at least some (if not all) of the bits of a codeword before writing the codeword back to the memory medium. Writing the codeword back to the memory medium can mitigate undesired changes in the electrical characteristics of the memory cells retaining the codeword - for example, a drift in the threshold voltage of the memory cells that may occur during an extended period without access operations. Inverting the logical state of the memory cells (e.g., writing a logical "1" to a memory cell retaining logical "0" or vice versa) can further mitigate undesired changes in the electrical characteristics of the memory cells.

[0028] The following will further describe the features of the present disclosure introduced herein at a demonstration system level in the context of Figure 1 . Then specific examples of the configuration of the system and the memory medium of the system will be described in the context of Figures 2 to 4 . These and other features of the present disclosure are further shown and described with reference to the device diagrams of Figure 5 and the flowcharts of Figures 6 to 8 , the device diagrams describe the various components related to the controller, and the flowcharts relate to the operations in the media scrubber operation in the memory system.

[0029] Figure 1 An example of a computing system 100 that supports media scrubber operations in a memory system in accordance with aspects disclosed herein is shown. The computing system 100 can include a host device 105 that is coupled to a device 140 via a host interface 115 (which can also be referred to as a host link). Among other examples, the host device 105 can be or include a server, a system-on-chip (SoC), a central processing unit (CPU), or a graphics processing unit (GPU). In some instances, the host device 105 can access (e.g., read from, write to) one or more memory media 130 located in the device 140 via the host interface 115.

[0030] The host interface 115 (e.g., host link) can be compatible with or adopt a protocol (e.g., Gen-Z, Cache Coherent Interconnect for Accelerators (CCIX) protocol) to facilitate access operations between the host device 105 and the one or more memory media 130. The host interface 115 can be configured to transfer data at a first data transfer rate (e.g., 25 gigabytes per second (GBps)) in at least one direction (e.g., send or receive). In some instances, when the transaction size is 64 bytes, a 25 GBps data transfer rate can support approximately 586 million transactions per second. In other instances, when the transaction size is 128 bytes, a 25 GBps data transfer rate can support approximately 312.5 million transactions per second.

[0031] Device 140 may in some cases be referred to as a memory system or subsystem or a memory device. In some cases, device 140 may include a power management component. The power management component may monitor a power level that may indicate a power change or loss related to device 140 or computing system 100. In some cases, the fluctuation of the power level may exceed a normal range to indicate such a power change or loss event. Device 140 may include a controller 120 that may be coupled to one or more memory media 130 via a channel 125. In some cases, channel 125 may be referred to as an aggregate channel 125, which includes a plurality of other channels (e.g., channels with a bandwidth less than that of aggregate channel 125) as described with reference to Figure 2 what is described. Device 140 may include a non-volatile memory 131 coupled to controller 120 via a channel 126. In some instances, controller 120, the one or more memory media 130, or non-volatile memory 131, or any combination thereof, may be integrated with, in contact with, or placed on a board (e.g., a Peripheral Component Interconnect Express (PCIe) board). In some cases, non-volatile memory 131 may be integrated as part of controller 120.

[0032] Controller 120 may include various functional blocks that facilitate the operation of device 140 in conjunction with the one or more memory media 130. In some cases, the power management component may be integrated as part of controller 120. In some cases, controller 120 may include aspects of an interface controller to accommodate different specifications, limitations, or characteristics associated with host interface 115, channel 125, channel 126, or any combination thereof. In some instances, controller 120 may be an application-specific integrated circuit (ASIC), a general-purpose processor, other programmable logic devices, discrete hardware components (e.g., die), or the controller may be a combination of components.

[0033] In some cases, controller 120 may cooperate with a local controller (e.g., local to memory media 130-a) that may perform various operations (such as writing data to memory cells, reading data from memory cells, arranging codewords according to the codeword format described with reference to Figure 3 what is described) to read data from or write data to memory media 130 (e.g., memory media 130-a). In some instances, the local controller may send the requested data to controller 120 via one of the channels in channel 125, which may be an instance of the aggregate channel.

[0034] Each memory medium (e.g., memory medium 130-a) may include multiple memory dies (e.g., forty-four (44) memory dies) to obtain a specified or desired memory capacity of the memory medium. In some instances, the memory die may include a three-dimensional cross-point array of memory cells containing chalcogenides (e.g., a 3D XPoint TM 3DXP memory die of memory cells). In other instances, the memory die may include other types of memory devices (e.g., FeRAM die, MRAM die, PCM die). In some instances, a codeword (e.g., a codeword containing 128 bytes of user data) may be divided across the multiple memory dies within a memory medium (e.g., memory medium 130-a).

[0035] In some cases, each memory die of the multiple memory dies (e.g., each 3DXP memory die) may generate a certain amount of data (e.g., 128-bit data) as a whole in association with an access operation (e.g., a read operation) from the memory die. The certain amount of data (e.g., 128-bit data) may include a series of bursts (e.g., sixteen (16) bursts), each burst including a certain amount of data (e.g., eight (8)-bit data) transmitted from the memory die on a bus (e.g., an 8-bit wide bus). As an example, when the memory medium includes eleven (11) memory dies operating in parallel, and when each of the eleven (11) memory dies generates eight (8)-bit data at a given burst, the memory medium may generate 88-bit data for the given burst. Since the eleven (11) memory dies may generate data over a total of sixteen (16) bursts, each burst including 88-bit data from the eleven (11) memory dies, a data unit associated with the memory medium during an access operation—e.g., a data unit transmitted on a channel (e.g., an aggregation channel)—may include 1,408 bits.

[0036] Thus, in this instance, a codeword associated with the memory medium (e.g., a data unit during a transaction of an access operation) may include 1,408 bits. In some cases, a burst may be referred to as a channel burst or a data burst. In some cases, the channel between the controller 120 and the memory medium (e.g., memory medium 130-a) may include multiple channels, where each channel may be associated with one or more memory dies of the memory medium (e.g., memory medium 130-a) as described with reference to Figure 3 and 4 the memory medium (e.g., memory medium 130-a).

[0037] A memory medium (e.g., memory medium 130-a) may include a set of memory dies each including a memory array. Each memory die in the set (e.g., each memory array) may be configured to include a set of MSRs, as described with reference to Figure 4 The MSRs may be configured as reasonable fail-safe regions for efficiently managing (e.g., replacing, substituting) error bits in the memory array. Additionally, at least some (if not each) of the MSRs in the set may be associated with a counter configured to count the number of error bits in the set of MSRs.

[0038] Channel 125 may be configured to transfer data (e.g., codewords) between controller 120 and the one or more memory media 130. Each channel in channel 125 (e.g., channel 125-a which may be an instance of an aggregated channel) may include a plurality of other channels (e.g., channels with a bandwidth less than that of channel 125-a) for transferring data (e.g., codewords) in parallel. In some cases, a codeword may include user data (e.g., 128 bytes of user data in the codeword) and other data sets (e.g., the remaining data in the codeword for generating reliable data with low latency). Each channel in channel 125 (e.g., channel 125-a which may be an instance of an aggregated channel) may include additional channels to carry information related to various auxiliary functions such as metadata. In some cases, a codeword format (which may also be referred to as a codeword layout) or a forwarded codeword format (e.g., a forwarded codeword layout) may define how each channel in channel 125 (e.g., channel 125-a) may transfer data (e.g., codewords) between controller 120 and the one or more memory media 130.

[0039] Non-volatile memory 131 may include an array of non-volatile memory cells that can maintain their logical states for an extended period of time even without an external power source. For example, among other instances, the non-volatile memory cells may be or may include 3D XPoint TM memory cells, PCM cells, FeRAM cells, or NAND memory cells. Additionally, non-volatile memory 131 may be configured to communicate information with controller 120 via channel 126. For example, non-volatile memory 131 may receive information from controller 120 via channel 126 and save the information when detecting a power change or loss related to computing system 100.

[0040] In some cases, a memory subsystem or system that can include device 140 can include a power management component for managing power change or loss events. The power management component can be operable to detect signs of a power change or loss (e.g., a power level indicating that a power change or loss may occur) and transmit an indication of the sign of the power change or loss to controller 120. Upon receiving the indication, controller 120 can transfer information (e.g., an indication of an error state associated with a codeword, one or more indications of spare bit allocations to error bits) stored in a memory array (e.g., an SRAM memory array) in controller 120 to non-volatile memory 131. Non-volatile memory 131 can store the information such that the information can be stored without power supply to the memory subsystem or system, which can include device 140. When power to computing system 100 is restored or otherwise adjusted, controller 120 can retrieve information from non-volatile memory 131 based on the information stored in non-volatile memory 131 to continue an operation that has been interrupted by a power change or loss event.

[0041] A controller (e.g., controller 120) can, in some cases, count the number of forwarded codewords retained in a memory medium (e.g., memory medium 130-a) as part of an operation of acting as a media scrubber. The forwarded codewords can include a certain number of copies of the forwarding address of the codeword, as described in reference Figure 3 The controller 120 can identify the value of a first counter associated with the memory medium. The first counter can indicate the number of codewords configured to be forwarded during a scrubbing period (e.g., the duration during which a media scrubber operation can be performed for the memory medium). The controller can set (e.g., initially set, update) the value of a second counter associated with the memory medium based on the value of the first counter, where the second counter can indicate the total number of forwarded codewords that can be accumulated in the memory medium during the lifetime of the memory medium. The lifetime of the memory medium can refer to an estimated duration during which the memory medium meets a set of operating criteria - e.g., among other instances, a raw bit error rate (RBER) associated with the memory die included in the memory medium, a preconfigured ratio between the number of forwarded codewords and the total number of codewords retained in the memory medium, or a load-to-use latency.

[0042] The controller 120 may also receive a first codeword from the memory medium based on setting a value of a second counter. In some cases, the controller 120 may initiate a next scrubbing cycle by receiving the first codeword from the memory medium. In some cases, the controller 120 may also reset the value of the first counter based on setting the value of the second counter before initiating the next scrubbing cycle to count another quantity of codewords that are configured to be forwarded during the next scrubbing cycle. The cycle may be a duration of a preconfigured cycle for scrubbing a set of codewords retrieved from the memory medium. For example, the preconfigured cycle for performing one or more media scrubber operations may correspond to several hours. In some cases, the controller 120 may receive the first codeword by retrieving the first codeword as part of a periodic background operation (e.g., a media scrubber operation) independent of access commands from a host.

[0043] In this way, the controller 120 may count the number of codewords that are configured to be forwarded during a given scrubbing cycle and may accumulate the total number of forwarded codewords retained at the memory medium (e.g., memory medium 130-a) during the life cycle of the memory medium. In some cases, the controller may avoid configuring additional codewords as forwarded codewords based on the number of forwarded codewords during a scrubbing cycle or during the life cycle of the memory medium.

[0044] Figure 2 An example of a computing system 200 that supports media scrubber operations in a memory system in accordance with aspects disclosed herein is shown. The computing system 200 may be an example of the computing system 100 described with reference to Figure 1 The computing system 200 may include a main device 205 that is coupled to a memory subsystem or system 220 using at least one host interface (e.g., host interface 215-a). In some cases, the host interface 215 may be referred to as one or more host links. The main device 205 may be an example of the main device 105 described with reference to Figure 1 The host interface 215 may be an example of the host interface 115 described with reference to Figure 1 In some instances, the host interface 215 may be configured to transfer data at a first data transfer rate (e.g., 50 GBps, with 25 GBps in each direction).

[0045] The computing system 200 may include a memory subsystem or system 220. The memory subsystem or system 220 may be an example of the memory subsystem or system described with reference to Figure 1An example of the described device 140. The memory subsystem or system 220 may be referred to as one or more memory devices. The memory subsystem or system 220 may include a controller 230. In some cases, the memory subsystem or system 220 may include a power management component. The power management component may monitor the power level, which may indicate a power change or loss related to the memory subsystem or system 220 or the computing system 200. In some cases, the fluctuation of the power level may exceed the normal range to indicate such power change or loss events. The controller 230 may be an example of the controller 120 referred to in Figure 1 An example of the described controller 120. The controller 230 may include an interface component 210 and a plurality of port managers 260. In some cases, the power management component may be integrated as part of the controller 230.

[0046] The interface component 210 may be configured to facilitate data exchange between the host device 205 and the memory subsystem or system 220 through the host interface 215. The interface component 210 may be configured to exchange data with the plurality of port managers 260 (e.g., using the signal path 250). Each signal path in the signal path 250 may be configured to exchange data at a rate different from the first data transfer rate of the host interface 215 (e.g., 12.8 GBps). In some cases, the interface component 210 may be configured to provide routing network functionality to allow more than one host interface (e.g., host interface 215-a and host interface 215-b) to be associated with the plurality of port managers 260.

[0047] The memory subsystem or system 220 may include non-volatile memory 296. The non-volatile memory 296 may be configured to transfer information to and from the controller 230 through the channel 292. The non-volatile memory 296 may be an example of the non-volatile memory 131 referred to in Figure 1 An example of the described non-volatile memory 131. Additionally, the channel 292 may be an example of the channel 126 referred to in Figure 1 An example of the described channel 126 or include aspects of the channel. Further, the non-volatile memory 296 may be configured to transfer information to and from the port managers 260 in the controller 230. For example, the port manager 260 may transfer various information (e.g., an indication of the error status associated with the codeword, one or more indications of spare bit allocation to error bits) to the non-volatile memory 296 through the channel 292 and save the information in the non-volatile memory 296 when the port manager 260 receives an indication of a power change or loss related to the computing system 200 or the memory subsystem or system 220. In some cases, the non-volatile memory 296 may be integrated as part of the controller 230.

[0048] Each port manager among the plurality of port managers 260 (e.g., port manager 260-b) may be coupled to a memory medium (e.g., memory medium 295-b) via an aggregation channel (e.g., aggregation channel 290-b). In some cases, each port manager among the plurality of port managers may be coupled to a different one or more memory media 295. In some instances, an individual port manager among the plurality of port managers 260 (e.g., port manager 260-a) may operate independently of one another (e.g., port managers 260-b, 260-c, and 260-c) and may support access operations or background operations associated with one or more memory media 295. The one or more memory media 295 may be an instance of the one or more memory media 130 described with reference to Figure 1 the one or more memory media 130. In some cases, each of the one or more memory media 295 may be referred to as a media port.

[0049] Each aggregation channel in the aggregation channels 290 may include one or more channels 291. In some cases, the channel 291 may be referred to as a logical channel 291. In some instances, each channel 291 may be associated with one or more memory dies in a memory medium (e.g., memory medium 295-a) and may have a bandwidth smaller than the bandwidth of the aggregation channel (e.g., aggregation channel 290-b). In some instances, an aggregation channel (e.g., aggregation channel 290-a) may include eleven (11) channels 291 (e.g., channels 291-a to 291-k). As will be appreciated by those of ordinary skill in the art, the plurality of channels 291 (e.g., channels 291-a to channel 291-k) are depicted for port manager 260-a to represent one of the aggregation channels 290 (e.g., aggregation channel 290-a), while the other aggregation channels 290 (e.g., aggregation channels 290-b, 290-c, and 290-d) are depicted for port managers 260-b, 260-c, and 260-d, and the plurality of channels 291 associated with each aggregation channel are not shown, such depiction being for increased visibility and clarity of the features shown.

[0050] A separate memory medium (e.g., memory medium 295-a) among the one or more memory media 295 may include one or more memory devices (e.g., 3DXP memory dies). In some cases, the memory devices in the separate memory medium may be configured to operate in parallel to obtain a desired (or specified) aggregate bandwidth through one of the aggregation channels 290. As an example, a 3DXP memory die may be configured to have an 8-bit wide data bus and may be associated with each channel in channel 291 (e.g., channel 291-a), such that each channel 291 is 8-bit wide. Additionally, the 3DXP memory die may be configured to generate 128 bits of data during a series of sixteen (16) bursts, where each burst may generate 8-bit wide data on channel 291. Thus, the 128 bits of data may be regarded as a single data unit generated by each 3DXP memory die based on an access command (or during a background operation) for reading memory cells within the 3DXP memory die.

[0051] In some cases, a codeword (or forward codeword) may be configured to include a set of bit fields indicating multiple data bursts (e.g., a series of sixteen (16) bursts) across multiple channels (e.g., eleven (11) channels 291-a to 291-k each generating 88 bits of data per data burst). Thus, the codeword may include 1,408 bits of information in some cases. The description herein may be understood from a logical view of the memory medium. A number of physical 3DXP memory dies greater than the number of logical 3DXP memory dies may exist in the memory medium, thereby accounting for the overhead associated with various access operations (e.g., read operations, write operations) or background operations associated with the memory medium. Within the memory medium, as described with reference to Figure 3 the codeword may be divided into parts and written to or read from more than one die (e.g., 128 bytes of user data reserved across ten (10) 3DXP memory dies).

[0052] The various examples described herein use 3DXP memory dies (e.g., including 3D XPoint TM memory cells) in accordance with the methods, devices, and systems disclosed herein that support media scrubber operations in a memory system to demonstrate how the memory medium 295 may be configured and operated in conjunction with the port manager 260. In some cases, the memory medium 295 may include other types of memory devices that employ a memory technology different from 3DXP memory technology, such as FeRAM technology, PCM technology, MRAM technology, etc. Thus, the concepts disclosed herein are not limited to a particular memory technology (e.g., 3D XPoint TM memory technology).

[0053] A memory medium (e.g., memory medium 295-a) may include a set of memory dies each including a memory array. Each memory die in the set (e.g., each memory array) may be configured to include a set of MSRs, as described with reference to Figure 4 described. An MSR may be configured as a reasonable failure accommodation area for efficiently managing (e.g., replacing, substituting) error bits in a memory array. In some cases, each bit of a codeword (e.g., each of the 1,408 bits in a codeword) may be associated with a corresponding MSR in a set (e.g., 1,408 MSRs). A group of MSRs across a set of channels of a memory medium (e.g., channels 291-a to 291-k of memory medium 295-a) may be configured to operate in parallel to preserve or generate a certain number of codewords. In some cases, a group of MSRs configured to generate a certain number of codewords may be referred to as an MSR stripe or an MSR region. Additionally, at least some (if not each) of the MSRs in the set may be associated with a counter configured to count the number of error bits in the MSRs in the set.

[0054] A port manager (e.g., port manager 260-a) may, in some cases, count the number of forwarded codewords retained in a memory medium (e.g., memory medium 295-a) as part of the operation of a media scrubber. A forwarded codeword may include a certain number of copies of the forwarding address of a codeword, as described with reference to Figure 3 described. The port manager 260-a may identify the value of a first counter associated with the memory medium. The first counter may indicate a first number of codewords configured to be forwarded during a first duration. In some cases, the first duration may be based on a preconfigured period for retrieving a set of codewords from the memory medium. The port manager 260-a may set (e.g., initially set, update) the value of a second counter associated with the memory medium based on the value of the first counter, where the second counter may indicate a second number of forwarded codewords that may be accumulated in the memory medium during a second duration. In some cases, the second duration may be based on the life cycle of the memory medium (e.g., an estimated duration for which the memory medium meets a set of operating criteria). The port manager 260-a may also receive a first codeword from the memory medium based on setting the value of the second counter.

[0055] In some cases, the port manager 260-a may determine that the first codeword meets a condition for configuring the first codeword as a forwarded codeword. The condition may be based on, as described with reference to Figure 3The number of error bits in the described first codeword. The port manager 260-a may also configure the first codeword as a forwarding codeword based on determining that the first codeword meets the condition. In some cases, the port manager 260-a may write the first codeword back to the memory medium (e.g., memory medium 295-a) based on configuring the first codeword as a forwarding codeword.

[0056] In some cases, the port manager 260-a may update the value of the first counter based on configuring the first codeword as a forwarding codeword. The port manager 260-a may also determine the updated value of the first counter relative to a first threshold associated with the number of forwarding codewords reserved at the memory medium. In some cases, the first threshold may be related to the number of codeword forwarding events allowed during a first duration. In some cases, the number of codeword forwarding events may be preconfigured based on the ratio between the total number of budgeted forwarding codewords in the memory medium and the total number of codewords reserved in the memory medium. In other cases, the first threshold may be related to one or more defect mechanisms that can make the memory cell clusters unreliable or problematic. As a result of updating the value of the first counter (e.g., configuring the codeword as a forwarding codeword during a scrubbing cycle), the port manager 260-a may determine that the value of the first counter (e.g., the updated number of codeword forwarding events) may be equal to the number of codeword forwarding events allowed during the first duration or within a determined range of the number of codeword forwarding events allowed during the first duration.

[0057] Further, the port manager 260-a may receive a second codeword from the memory medium based on updating the value of the first counter. The port manager 260-a may also determine that the second codeword meets the condition for configuring the second codeword as a forwarding codeword based on receiving the second codeword. In some cases, the port manager 260-a may avoid configuring the second codeword as a forwarding codeword based on the updated value of the first counter relative to the first threshold. For example, the port manager 260-a may initiate an alternative error control scheme (e.g., a channel for replacing the codeword) instead of configuring the second codeword as a forwarding codeword. When the error bits may be due to one or more defect mechanisms associated with the memory die of the memory medium, the channel for replacing the codeword may be a more effective scheme for managing the error bits in the codeword.

[0058] In some cases, the port manager 260-a may determine that the first codeword corresponds to the last codeword reserved at the memory medium (e.g., completing a media scrubber operation for the current scrub cycle). The port manager 260-a may also update the value of a second counter based on updating the value of the first counter and determining that the first codeword corresponds to the last codeword reserved at the memory medium. In some cases, the port manager 260-a may determine an updated value of the second counter relative to a second threshold associated with the number of forwarded codewords reserved at the memory medium. The port manager 260-a may also avoid configuring a codeword as a forwarded codeword based on the updated value of the second counter. In some cases, the second threshold may relate to the number of codeword forwarding events allowed during the life cycle of the memory medium. In some cases, the number of codeword forwarding events allowed during the life cycle of the memory medium may be preconfigured based on the ratio between the total number of forwarded codewords budgeted for the memory medium and the total number of codewords reserved in the memory medium.

[0059] Figure 3 Examples of codeword formats (which may also be referred to as codeword layouts 300-a and 300-b) shown as 300-a and 300-b that support media scrubber operations in a memory system in accordance with aspects disclosed herein are presented. The codeword formats 300-a and 300-b may be examples of codeword formats for an entire codeword. A codeword may include a set of bit fields indicating multiple data bursts across multiple channels (e.g., channels 291-a through 291-k as described with reference to Figure 2 ). Figure 3 Also included are formats 301 through 305 (also referred to as layouts) showing various configurations for an individual channel (e.g., channel 291-a as described with reference to Figure 2 ). Figure 3 Format 306 is also shown, which may correspond to a portion of the codeword (e.g., a subset of bit fields during one or more first data bursts across the multiple channels).

[0060] As examples of codeword formats and structures, the codeword formats 300-a and 300-b may include a number of fields (e.g., bit fields) of data (e.g., 1,408-bit data), which may be stored by a memory medium (e.g., as described with reference to Figure 1 and 2The described memory medium 130-a or memory medium 295-a) is generated in response to an access command or during a background operation, or both. A codeword may contain 128 bytes (e.g., 1,024 bits) of user data. The remaining bit fields within the codeword (e.g., 384 bits of data) may carry various information that may facilitate delivery of accurate user data during an access operation or during a background operation, or both. Further, the remaining bits that carry the various information may be configured to facilitate low latency operations (e.g., standby replacement) associated with the codeword during an access operation.

[0061] Codeword formats 300-a and 300-b may span multiple channels (e.g., channels 310-a through 310-k). One of these channels (e.g., 310-a through 310-k) may be a reference channel. Figure 2 Instances of or including aspects of the described channels 291 (e.g., channels 291-a). In some cases, each channel in the plurality of channels 310 (e.g., channels 310-a) can be associated with one or more 3DXP dies that can include an 8-bit wide data bus. For example, each channel can generate a total of 128 bits of data as a single object of a transaction (e.g., communication, operation) associated with an access command (e.g., a read command) or a background operation or both. Further, the 128 bits of data can be generated as a series of sixteen (16) data bursts, each data burst being configured to generate eight (8) bits of data on an 8-bit wide data bus. Thus, each channel within the codeword format (e.g., each channel in channels 310-a through 310-k) can correspond to 128 bits of data comprising sixteen (16) groups of 8-bit data, such as G7..G0 of channel 310-g, where G7..G0 can represent a series of eight (8) zeros and ones, where G7 can be the most significant bit (e.g., the eighth bit in the series of eight (8) zeros and ones) and G0 can be the least significant bit (e.g., the first bit in the series of eight (8) zeros and ones), where each of the sixteen (16) groups of 8-bit data can be associated with one of the sixteen (16) data bursts.

[0062] In one example, codeword formats 300-a and 300-b can span eleven (11) channels, and each of the eleven (11) channels can generate 8 bits of data at each data burst, and a total of 88 bits of data can be generated across the eleven (11) channels at each data burst (e.g., first data burst 320-1 of 88 bits of data). Thus, codeword formats 300-a and 300-b can contain 1,408 bits of data (e.g., first data burst 320-1 to sixteenth data burst 320-16, where each data burst generates 88 bits of data) as a single object for a transaction to a memory medium (e.g., memory medium 130-a or memory medium 295-a). Codeword formats 300-a and 300-b can support reliable transactions (e.g., convey the exact content of user data) with low latency (e.g., a small number of clock edges for generating user data).

[0063] Each field (e.g., each bit field) or set of fields (e.g., set of bit fields) within a codeword can contain information that facilitates reliable user data transactions with low latency. In some cases, one or more fields (e.g., bit fields) within a codeword format can be configured to indicate codeword conditions (e.g., using one or more CwCon bits). A codeword can be configured to be in one of a plurality of possible states (e.g., four states) indicated using the CwCon bits.

[0064] As an example, one or more CwCon bits can indicate whether a codeword is one of a normal codeword or a forwarding codeword. As one example, normal codewords can include codeword formats 300-a and 300-b. A forwarding codeword can include a codeword layout that can facilitate identifying a valid replacement address (e.g., a forwarding address) for the codeword. In some cases, a forwarding codeword can include at least one copy of a valid address associated with the codeword. Further, one or more CwCon bits can additionally or alternatively indicate whether a codeword is one of a non-inverted codeword or an inverted codeword. In some cases, the logical state (e.g., 1 and 0) of bits within an inverted codeword may need to be inverted (e.g., flipped, reversed) before the information in the inverted codeword can be interpreted (e.g., parsed), whereas a non-inverted codeword may not need to be inverted before interpreting (e.g., parsing) the information in the non-inverted codeword.

[0065] A controller (e.g., the controller 120 or port manager 260-a described with reference to Figure 1 and 2 can, in some cases, as part of the media scrubbing operation, from a memory medium (e.g., with reference to Figure 1 and 2The described memory medium 130-a or memory medium 295-a) retrieves a codeword and inverts at least some (if not all) of the bits of the codeword before writing the codeword back to the memory medium. Writing the codeword back to the memory medium can mitigate undesired changes in the electrical characteristics of the memory cells retaining the codeword - for example, the drift of the threshold voltage of the memory cells that may occur during an extended period without access operations. Inverting the logical state of the memory cells (e.g., writing a logical "1" to a memory cell retaining a logical "0" or vice versa) can further mitigate undesired changes in the electrical characteristics of the memory cells.

[0066] In some cases, the controller can receive a codeword from an address of the memory medium, the codeword comprising a set of bits (e.g., a set of bit fields). The controller can also invert a portion of the bits based on receiving the codeword. In some cases, the controller can set the value of a bit in the set (e.g., the CwCon bit) to indicate a codeword condition comprising the inverted state of the codeword based on inverting the portion of the bits. The controller can also write the codeword back to the address of the memory medium based on setting the value of the bit indicating the inverted state. In some cases, the portion of the bits can comprise each bit in the set. In some cases, the controller can retrieve each of a plurality of codewords retained at the memory medium as part of a periodic background operation (e.g., a media scrubber operation) independent of an access command from a host, where the portion of the bits can be inverted based on retrieving each of the plurality of codewords.

[0067] In some cases, one or more fields within the codeword format can be configured to indicate the number of access operations (e.g., read operations, write operations) associated with the codeword (e.g., the WrCnt bit). In some cases, one or more fields within the codeword format can be configured to indicate that a portion of the codeword may be invalid (e.g., using a poison or indication bit). In some cases, one or more fields within the codeword format can be configured as cyclic redundancy check (CRC) bits that can identify error bits related to error control operations.

[0068] In some cases, one or more fields within the codeword format can be configured as codeword error control code bits (e.g., CwECC bits) that support error control operations. In some cases, one or more fields within the codeword format can be configured as XOR bits. Each XOR bit among the XOR bits can comprise the digital or Boolean logical exclusive OR (XOR) product of corresponding bits of other channels of a respective data burst. Thus, the XOR bits can support repairing the corresponding bits of other channels and can be referred to as repair bits. In some cases, each XOR bit (e.g., the XOR / Sub bit or XORSub bit) can replace a field within the codeword rather than a repair field.

[0069] In some cases, one or more fields within a codeword format may be configured as spare bits (e.g., CRC / Spare bits, XORSub / Spare bits). Among other alternatives, bits configured as spare bits may be configured as CRC bits or XOR bits (or XORSub bits). As an example, Figure 3 the codeword formats 300-a and 300-b depicted respectively in TM may include up to twenty-two (22) spare bits—e.g., twenty (20) CRC / Spare bits and two (2) XORSub / Spare bits. That is, some fields of CRC bits may be configured as spare bits. Similarly, some fields of repair bits (e.g., XORSub bits) may be configured as spare bits. Thus, a certain number of spare bits within a codeword may be configurable because the certain number of spare bits may be exchangeable with a certain number of CRC bits or XORSub bits. In some cases, the number of spare bits in a codeword may be determined based on the maturity of the memory technology (e.g., 3DXPoint TM , FeRAM, MRAM technology) used to construct the memory media (e.g., memory media 130, memory media 295).

[0070] In some cases, spare bits may be configured to operate as spare bits to replace designated invalid bits (e.g., error bits) of a codeword. In some cases, the designated invalid bits may be associated with the MSR of a memory die (e.g., an MSR containing a certain number of memory cells that may have become faulty or unreliable). Spare bits (e.g., the MSR corresponding to the spare bits) may be routed (e.g., multiplexed using a multiplexing component) to replace (e.g., substitute for) the designated invalid bits (e.g., the MSR corresponding to the error bits) to support reliable transactions of user data within the codeword.

[0071] Still referring to Figure 3 , each field (e.g., bit field) within the codeword format may be configured (e.g., arranged) to support low-latency operations during access operations associated with the memory media. Figure 3 Formats 301 to 305 include various configurations showing 8-bit groups for individual channels (e.g., each of channels 310-a to 310-k). For example, each of formats 301 to 305 includes an eight (8)-bit group that a memory device (e.g., a 3DXP die) within a memory media (e.g., memory media 295-a) may generate at a given data burst. Example formats are described below, but the disclosure herein is not limited to these examples.

[0072] Format 301 may include one or more (e.g., three) fields of CwCon bits, one or more (e.g., two) fields of CRC / alternate bits (which may be configured as CRC bits or alternate bits), and one or more (e.g., three) fields of CRC bits. Format 302 may include one or more (e.g., three) fields of CwCon bits, one or more (e.g., two) fields of CRC / alternate bits (which may be configured as CRC bits or alternate bits), one or more (e.g., two) fields of CRC bits, and one or more (e.g., three) fields of WrCnt bits (e.g., counter bits).

[0073] Format 303 may include one or more (e.g., three) fields of CwCon bits, one or more (e.g., two) fields of CRC / alternate bits (which may be configured as CRC bits or alternate bits), and one or more (e.g., three) fields of WrCnt bits (e.g., counter bits). Format 304 may include one or more (e.g., three) fields of CwCon bits, one or more (e.g., two) fields of CRC / alternate bits (which may be configured as CRC bits or alternate bits), one or more fields of WrCnt bits (e.g., counter bits), and one or more (e.g., two) fields of corrupt bits (e.g., bits indicating the invalidity of a portion of a codeword). Format 305 may include one or more (e.g., three) fields of CwCon bits, one or more (e.g., two) fields of XORSub / alternate bits (which may be configured as XORSub bits or alternate bits), and one or more (e.g., three) fields of XORSub bits.

[0074] Codeword formats 300-a and 300-b may also exhibit a 1,024-bit user data field (e.g., channels 310-a to 310-h on the second data burst 320-2 to the 16th data burst 320-16 and channels 310-i and 310-j on the second data burst 320-2 to the fifth data burst 320-5), a CwECC field (e.g., channels 310-i and 310-j on the 6th data burst 320-6 to the 16th data burst 320-16), and an XOR / Sub field (e.g., channel 310-k on the second data burst 320-2 to the 16th data burst 320-16).

[0075] As an example of a codeword format that supports low-latency operations, a subset of bit fields corresponding to a first data burst (e.g., data burst 320-1) can be configured as shown in format 306. In format 306, each 8-bit group of channel 310-a (e.g., A7..A0) and channel 310-b (e.g., B7..B0) can be configured to have format 301. Similarly, the 8-bit group of channel 310-c (e.g., C7..C0) can be configured to have format 302. At least some (if not each) of the 8-bit groups of channels 310-d (e.g., D7..D0) through 310-i (e.g., I7..I0) can be configured to have format 303. The 8-bit group of channel 310-j (e.g., J7..J0) can be configured to have format 304. Additionally, the 8-bit group of channel 310-k (e.g., K7..K0) can be configured to have format 305.

[0076] As a result of configuring a subset of bit fields (e.g., a total of 88 bits including eight (8) bits from each of eleven (11) channels) corresponding to a first data burst (e.g., first data burst 320-1) for codeword formats 300-a and 300-b, the first data burst of 88 bits (e.g., the 88 bits of format 306) can contain information for facilitating low-latency reliable transactions associated with accessing operations related to the codeword (e.g., reading 1,024 bits of user data). In some cases, a port manager (e.g., port manager 260-a) can receive a first portion of a codeword associated with a memory medium (e.g., the bits of format 306 corresponding to the first data burst 320-1). During a subsequent data burst, the port manager can parse (e.g., interpret) the first portion of the codeword (e.g., identify spare bits) concurrently with receiving additional portions of the codeword (e.g., the bits of codeword formats 300-a and 300-b corresponding to the second data burst 320-2, etc.). Thus, the port manager can parallelize various operations associated with the codeword to provide reliable low-latency communication or information exchange with the host.

[0077] When the codeword becomes unreliable or nearly unreliable, the controller (e.g., refer to Figure 1 and 2The described controller 120 or port manager 260 - a) may configure a codeword to be a forwarding codeword. Compared to codeword formats that contain user data (e.g., codeword formats 300 - a and 300 - b), a forwarding codeword format (which may also be referred to as a forwarding codeword layout) may contain a certain number of copies of a forwarding address (e.g., a replacement address) to facilitate access to user data. Additionally, in some cases, the forwarding codeword format may contain a certain number of bit fields (e.g., one or more CwCon bits) that indicate the codeword condition. The forwarding codeword format may also support low - latency operations, which in turn may include determining that a codeword is a forwarding codeword and identifying the forwarding address from the forwarding codeword.

[0078] In some cases, the controller may decide to configure a codeword as a forwarding codeword without waiting for the codeword (e.g., the user data therein) to become irrecoverable beyond the error - recovery capabilities of the memory system or subsystem. Since a codeword may contain information related to error - control operations (e.g., one or more CRC bits, one or more CwECC bits), the controller may, in some cases, determine the number of erroneous bits (e.g., faulty bits) in the codeword based on performing error - control operations on the codeword during an access operation (e.g., a read operation). The controller may determine the number of erroneous bits relative to (e.g., exceeding, equal to, approaching) an error threshold (e.g., an error threshold at which the codeword may become unreliable or invalid). In some cases, the error threshold may be related to the allowable limit of the number of erroneous bits in the codeword (e.g., the number of erroneous bits that the codeword is pre - configured to recover).

[0079] The controller may configure the codeword as a forwarding codeword according to the forwarding codeword format based on determining the number of erroneous bits in the codeword. In some cases, the error threshold may be configurable based on a number of factors (e.g., the memory technology of the memory devices used to fabricate the memory media, the maturity of such memory technology, the memory media usage pattern). The controller may also set one or more CwCon bits to indicate that the codeword is a forwarding codeword.

[0080] Figure 4 An example of a configuration 401 of a memory array and a configuration 402 of a memory media that support media scrubber operations in a memory system in accordance with aspects disclosed herein is shown. The memory array depicted in configuration 401 may be an example of memory dies in the memory media (e.g., memory media 130 or memory media 295) described with reference to Figure 1 and 2 The memory media depicted in configuration 402 may be the memory media described with reference to Figure 1 and 2Examples of the described memory media (e.g., memory media 130 or memory media 295). The memory media depicted in configuration 402 may include a certain number of memory arrays (e.g., forty-four (44) memory arrays) that may each be configured according to configuration 401.

[0081] Configuration 401 may include memory array 410. In some cases, memory array 410 may include a set of memory cells (e.g., 512 gigabits of memory cells, 2 39 memory cells). Memory array 410 may be organized with an array width 415 and an array depth 425. In some cases, array width 415 may be referred to as die width 415, and array depth 425 may be referred to as die depth 425. Further, each of array width 415 and array depth 425 may be divided into a certain number of partitions. In some cases, array width 415 may be divided into 128 segments. Thus, segment 420 depicted in configuration 401 may represent one of the 128 segments in array width 415. Further, each segment (e.g., segment 420) may be divided into 128 blocks such that array depth 425 may be divided into 128 bars. A bar may be referred to as a segment, sub-segment, portion, element, etc. Thus, bar 430 depicted in configuration 401 may represent one of the 128 bars in array depth 425.

[0082] Thus, memory array 410 (e.g., 512 gigabits of memory cells) may be divided into a certain number of segments 435 (e.g., segment 435-a, 435-b, or 435-c) each depicted as a box within memory array 410 as an example. In this example, as a result of dividing array width 415 into 128 segments each further divided into 128 bars (e.g., segments, sub-segments, portions, elements) in array depth 425, memory array 410 may include 16,384 segments. Each segment 435 of memory array 410 may be referred to as an MSR 435. In some cases, an MSR 435 may include a group of memory cells (e.g., 2 25 memory cells) that may be configured as data units associated with error control operations. An MSR may be configured as a reasonable fault accommodation area for efficiently managing (e.g., replacing, substituting) error bits in memory array 410.

[0083] The number of segments in the array width 415 (e.g., 128 segments) can be determined based on the way the memory array (e.g., memory array 410) is constructed in the memory die. For example, the memory array 410 can have a certain number of tiles (e.g., 128 tiles), and the number of segments in the array width 415 can be based on the number of tiles of the memory array 410. Similarly, the number of bars in the array depth 425 (e.g., 128 bars) can be determined based on common characteristics associated with various functional components such as row decoders, column decoders, etc. As a result of partitioning the memory array 410 as depicted in configuration 401, each segment 435 (e.g., an MSR among the 16,384 MSRs in the memory array 410 that contains 512 gigabits and contains 2 25 memory cells) can provide a group of memory cells (e.g., data units) to efficiently manage (e.g., replace, substitute) error bits in the memory array 410 without incurring a huge overhead. In some cases, the size of the memory cell unit (e.g., 2 25 memory cells of an MSR) can be referred to as the data granularity for supporting efficient error control operations associated with the memory media.

[0084] Still referring to configuration 401, the bars 430 across a certain number of segments (e.g., 128 segments) can represent a first number of bits (e.g., 128 bits) that are part of a codeword generated by the memory array 410 (e.g., part of a codeword that contains 1,408 bits). The first number of bits (e.g., 128 bits) of the bars 430 can be further demultiplexed down to a second number of bit sets (e.g., eight (8) bits), where each set of the second number of bits (e.g., eight (8) bits) can be generated at a given data burst (e.g., one of the sixteen (16) data bursts that generate a total of 128 bits). Thus, the bars 430 can generate a part of the codeword, where each segment 435 (e.g., MSR 435) contributes one bit of the first number of bits (e.g., 128 bits) of the codeword. Further, the bars 430 (e.g., 128 bits generated over 16 data bursts) can correspond to a channel (e.g., channel 291-a as referred to Figure 2 in the description). When a certain number of memory arrays 410 (e.g., eleven (11) memory arrays 410) operate in parallel such that each memory array 410 can generate a part of the bits that make up a complete codeword, a complete codeword (e.g., a 1,408-bit codeword) can be generated - for example, each memory array 410 generates 128 bits over sixteen (16) data bursts across eleven (11) channels, thus totaling 1,408 bits in total of the codeword.

[0085] Configuration 402 may include a set of memory arrays 410 (e.g., forty-four (44) memory arrays 410) to implement a desired or specified capacity of a memory medium (e.g., the memory medium 130 or the memory medium 295 described with reference to Figure 1 and 2 ). The set of memory arrays in the memory medium may be arranged to form multiple channels for the memory medium. In some cases, the memory medium may include eleven (11) channels (e.g., channels 440-a to 440-k) as shown in configuration 402. Each channel 440 may be an instance of the channel 291 (e.g., channels 291-a to 291-k) described with reference to Figure 2 or include aspects of the channel. Further, each channel 440 may be configured to include a subset of memory arrays. In some cases, a channel (e.g., channel 440-a) may include four (4) memory arrays 410-a to 410-d. Thus, each of the multiple channels may in some cases include a total number of rods 430 (e.g., 512 rods) corresponding to a multiple of the number of rods in the memory arrays 410 within the channel (e.g., 128 rods) multiplied by the number of memory arrays 410 (e.g., four (4) memory arrays).

[0086] In some cases, an MSR group across multiple channels (e.g., eleven (11) channels, i.e., channels 440-a to 440-k) that generate codewords may be referred to as an MSR stripe (e.g., the MSR stripe 445 depicted in configuration 402). An MSR stripe may also be referred to as an MSR region. For example, the memory medium of configuration 402 includes 512 MSR stripes (e.g., 512 MSR regions). Similarly, an MSR stripe (e.g., MSR stripe 445) may correspond to the collective array depth (e.g., collective die depth) of the memory medium - for example, the MSR stripe 445 depicted in configuration 402 may correspond to the 130th array depth of the memory medium (e.g., the 130th MSR stripe in the total array depth of 512 MSR stripes), where each memory array 410 includes 128 MSR stripes. In some cases, a flag may be associated with an MSR stripe (or MSR region) to indicate a change in the spare bit allocation associated with the codewords reserved at the MSR stripe (e.g., MSR stripe 345 or MSR region 345). The flag may be part of a separate memory array (e.g., an SRAM memory cell) that may in some cases be integrated in a controller (e.g., the controller 120 or the port manager 260-a described with reference to Figure 1 and 2 ).

[0087] At least some (if not every) MSRs (e.g., MSR 435-a, MSR 435-b, MSR 435-c) of a memory array (e.g., memory array 410) may be associated with a counter configured to count the number of error bits therein. For example, a port manager (e.g., port manager 260-a described with reference to Figure 2 ) may read codewords from an MSR stripe (e.g., MSR stripe 445) as part of a background operation (e.g., media scrubber operation) and perform error control operations on the codewords. The port manager may identify a certain number of error bits and correct the certain number of error bits in the codewords using a set of bits in the codewords (e.g., bits supporting an error correction function). Each of the certain number of error bits (e.g., an erroneous or unreliable memory cell) may correspond to a respective MSR of the MSR stripe. The port manager may update a first counter associated with a first MSR of the MSR stripe to count the number of error bits (e.g., error bit count) in the first MSR of the MSR stripe.

[0088] The port manager may sort the values (e.g., error bit counts) stored in the counters of the codewords (e.g., 1,408 counters each corresponding to 1,408 MSRs) to identify a subset of values greater than the remaining values. For example, the port manager may sort the values (e.g., error bit counts) in descending order to identify a subset of values (e.g., 160 of the highest error bit counts among the 1,408 error bit counts associated with the codewords). In this way, the port manager may identify a subset of MSRs each containing a higher number of error bits compared to other MSRs. The port manager may identify the subset of MSRs (e.g., 160 of the 1,408 MSRs) as candidates for replacement (e.g., replacing such MSRs with reliable MSRs such as spare MSRs). In some cases, the port manager may configure the number of values in the subset (e.g., 200 of the highest error bit counts instead of 160 of the highest error bit counts) based on the number of error bits identified in the codewords. In some cases, such a number of values in the subset (e.g., the subset of MSRs identified as candidates for replacement) may be based on various factors (e.g., the memory technology of the memory devices used to manufacture the memory media, the maturity of such memory technology, the memory media usage pattern).

[0089] Further, the port manager may replace one or more MSRs with higher error bit counts with a set of spare MSRs (e.g., a subset of MSRs identified as candidates for replacement) until the set of spare MSRs is exhausted. The port manager may determine to replace an MSR based on the number of error bits (e.g., error bit count) in the MSR relative to a threshold (e.g., a bit-level replacement threshold). In some cases, the port manager may determine to replace an MSR with an error bit count equal to or greater than the threshold. The threshold may be based on the raw bit error rate (RBER) associated with the memory media. In some cases, the threshold may be based on the size of the MSR (e.g., 2 25 bits in the MSR). In some cases, the threshold may be configurable (e.g., programmable) to account for the maturity of the technology of the memory cells used to manufacture the memory media, e.g., process variations that may affect the electrical characteristics of the memory cells of the memory media.

[0090] The port manager may allocate spare MSRs (e.g., spare bits in a codeword) to replace any one of the MSRs (e.g., error bits in a codeword) identified as candidates for replacement. In some cases, the spare bits (e.g., spare MSRs) may be allocated on a first identified, first allocated basis. The port manager may repeat allocating spare bits to error bits in the codeword until all spare bits (e.g., up to twenty-two (22) spare bits as described in the reference Figure 3 are allocated. In some cases, the spare bits (e.g., spare MSRs) may be reallocated to different error bits (e.g., different MSRs containing an equal to or greater than the bit-level threshold number of error bits). In other cases, once a spare bit has been allocated to a corresponding error bit, each spare bit may remain allocated to the corresponding error bit in the codeword.

[0091] The port manager may, in some cases, as part of the operation of the media scrubber (e.g., during a first media scrubbing cycle for an MSR stripe), allocate one or more spare bits (e.g., one or more MSRs corresponding to the spare bits) in a codeword to replace an error bit (e.g., an MSR corresponding to the error bit) in the codeword (e.g., one of the codewords retained at the MSR stripe). The port manager may set bits (e.g., flags) in a separate memory array to indicate such changes in the replacement relationship associated with the codeword retained at the MSR stripe. Setting the bits (e.g., flags) may also indicate that, while the replacement relationship of the spare bits may have been determined, the spare bits may not contain a valid logical state of the codeword.

[0092] The port manager may save the replacement relationships (e.g., alternate bit assignments to corresponding error bits) for the codewords reserved at the memory media (e.g., MSR strips) in a separate memory array. In some cases, the memory array may be integrated as part of the port manager. In some cases, the separate memory array may include static random access memory (SRAM) cells.

[0093] The size of the memory array (e.g., the number of SRAM cells) allocated to save the replacement relationships may be based on the bits indicating changes in the replacement relationships (e.g., flags indicating changes in the alternate assignments), the identification of the channel associated with the codeword (e.g., the identification of the channel to be replaced), the number of alternate bits in the codeword (e.g., up to twenty-two (22) alternate bits), the identification of the MSR in a first number of MSRs (e.g., 1,408 MSRs) associated with the codeword, the number of bits associated with the forwarded codeword in the memory media, the error correction capability for the replacement relationships, the number of memory dies corresponding to the channel associated with the codeword (e.g., four (4) memory dies per channel), or a second number of MSR groups in the memory dies in the number of memory dies (e.g., 128 MSR bars) or any combination thereof.

[0094] The port manager may access the codewords, in some cases as part of the media scrubber operation (e.g., during a second media scrubbing cycle for MSR strips), replace the error bits with the one or more alternate bits according to the replacement relationships saved in the memory array (e.g., SRAM cells), and perform error control operations to restore the logical state of the codeword (e.g., the codeword including the one or more alternate bits replacing the error bits). The port manager may write the restored logical state (e.g., valid logical state) at the one or more alternate bits and may reset the bits (e.g., flags) in the memory array (e.g., SRAM cells). In this way, the one or more alternate bits may contain the valid logical state of the codeword, and the bits (e.g., flags) may indicate that the one or more alternate bits in the codeword contain the valid logical state to be implemented (multiplexed into the bit stream of the codeword with a series of data bursts) when the host requests the codeword.

[0095] In some cases, a port manager may receive a codeword reserved at a portion of a memory medium, the codeword including a plurality of bits that contain a certain number of spare bits for the codeword. The port manager may also access a memory array of the port manager based on receiving the codeword. In some cases, the port manager may perform error control operations on the codeword based on accessing the memory array of the port manager to recover a logical state of the plurality of bits. The port manager may also write a logical state of bits in the plurality of bits at spare bits among the certain number of spare bits based on performing the error control operations. In some cases, receiving the codeword may include retrieving each of a plurality of codewords reserved at the portion of the memory medium as part of a periodic background operation independent of an access command from a host.

[0096] In some cases, the port manager may replace bits in the plurality of bits with spare bits among the certain number of spare bits based on accessing the memory array, wherein performing error control operations on the codeword may be based on replacing bits in the plurality of bits. The port manager may also identify a value of a flag in the memory array based on accessing the memory array, the value of the flag indicating a change in a replacement relationship for a codeword reserved at the portion of the memory medium, wherein performing error control operations on the codeword may be based on identifying the value of the flag. In some cases, the port manager may reset a value of a flag in the memory array based on writing a logical state of bits in the plurality of bits, the value of the flag indicating that spare bits among the certain number of spare bits contain a logical state valid for replacing bits in the plurality of bits.

[0097] In some cases, the port manager may receive an indication of a power level from a power management component coupled to the port manager and transfer information (e.g., an indication of an error state associated with a codeword, one or more indications of spare bit allocations to error bits) stored in the memory array (e.g., SRAM cells) to a non-volatile memory (e.g., a persistent memory) as described in reference Figure 1 and 2 described.

[0098] Figure 5 FIG. 500 is a block diagram showing a controller 515 that supports media scrubber operations in a memory system in accordance with aspects disclosed herein. The controller 515 may be an example of aspects of the controller 120 or the controller 230 described in reference Figures 1 to 2 described. The controller 515 may include a bias component 520, a timing component 525, an access manager 530, a codeword manager 535, and an error control manager 540. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0099] The access manager 530 may receive a first codeword from the memory medium based on setting the value of a second counter. In some cases, the access manager 530 may receive a second codeword from the memory medium based on updating the value of a first counter. In some cases, the access manager 530 may write the first codeword back to the memory medium based on configuring the first codeword as a forwarding codeword. In some cases, receiving the first codeword may further include retrieving the first codeword as part of a periodic background operation independent of an access command from a host.

[0100] In some cases, the access manager 530 may receive a codeword reserved at a portion of the memory medium, the codeword including a plurality of bits containing a certain number of spare bits for the codeword. In some cases, the access manager 530 may write the logical state of a bit in the plurality of bits at a spare bit among the certain number of spare bits based on performing an error control operation. In some cases, receiving the codeword may further include retrieving each of a plurality of codewords reserved at the portion of the memory medium as part of a periodic background operation independent of an access command from a host, wherein access to the memory array may be based on retrieving each of the plurality of codewords.

[0101] In some cases, the access manager 530 may receive a codeword from an address of the memory medium, the codeword including a set of bits. In some cases, the access manager 530 may write the codeword back to the address of the memory medium based on setting the value of a bit indicating an inversion state.

[0102] The codeword manager 535 may identify the value of a first counter associated with the memory medium, the first counter indicating a first quantity of codewords reserved at the memory medium during a first duration, the first quantity of codewords being configured as forwarding codewords. In some cases, the codeword manager 535 may set the value of a second counter associated with the memory medium based on identifying the value of the first counter, the second counter indicating a second quantity of codewords reserved at the memory medium during a second duration, the second quantity of codewords being configured as forwarding codewords. In some cases, the codeword manager 535 may configure the first codeword as a forwarding codeword based on a determination.

[0103] In some cases, the codeword manager 535 may update the value of the first counter based on configuring the first codeword as a forwarding codeword. In some cases, the codeword manager 535 may determine an updated value of the first counter relative to a first threshold associated with the number of forwarding codewords reserved at the memory medium. In some cases, the codeword manager 535 may avoid configuring the second codeword as a forwarding codeword based on the updated value of the first counter relative to the first threshold. In some cases, the codeword manager 535 may determine that the first codeword corresponds to the last codeword reserved at the memory medium. In some cases, the codeword manager 535 may update the value of the second counter based on updating the value of the first counter and determining that the first codeword corresponds to the last codeword reserved at the memory medium.

[0104] In some cases, the codeword manager 535 may determine an updated value of the second counter relative to a second threshold associated with the number of forwarding codewords reserved at the memory medium. In some cases, the codeword manager 535 may avoid configuring a codeword as a forwarding codeword based on the updated value of the second counter. In some cases, the codeword manager 535 may reset the value of the first counter based on setting the value of the second counter, wherein receiving the first codeword may be based on resetting the value of the first counter. In some cases, the first duration may be based on a preconfigured period for retrieving a set of codewords from the memory medium. In some cases, the second duration may be based on the lifetime of the memory medium, and wherein the lifetime of the memory medium may be based on an estimated duration for which the memory medium meets a set of operating criteria. In some cases, the forwarding codeword may include a certain number of copies of the forwarding address of the first codeword.

[0105] In some cases, the codeword manager 535 may invert a portion of a set of bits based on receiving a codeword, wherein the codeword may include the set of bits. In some cases, the codeword manager 535 may set the value of a bit in the set of bits to indicate a codeword condition including the inverted state of the codeword based on inverting a portion of the bits. In some cases, the portion of the bits may include each bit in the set of bits.

[0106] The error control manager 540 may determine that the first codeword meets a condition for configuring the first codeword as a forwarding codeword, the condition being based on the number of error bits in the first codeword. In some cases, the error control manager 540 may determine that the second codeword meets a condition for configuring the second codeword as a forwarding codeword based on receiving the second codeword.

[0107] In some cases, the error control manager 540 may access the memory array of the port manager based on the received codeword. In some cases, the error control manager 540 may perform error control operations on the codeword based on accessing the memory array of the port manager to restore the logical states of multiple bits of the codeword. In some cases, the error control manager 540 may replace a bit in the multiple bits with a spare bit from the certain number of spare bits based on accessing the memory array, where performing the error control operations on the codeword may be based on replacing the bit in the multiple bits. In some cases, the error control manager 540 may identify the value of a flag in the memory array based on accessing the memory array, where the value of the flag indicates a change in the replacement relationship for the codeword reserved at a portion of the memory media, and where performing the error control operations on the codeword may be based on identifying the value of the flag.

[0108] In some cases, the error control manager 540 may reset the value of a flag in the memory array based on writing the logical states of the bits in the multiple bits, where the value of the flag indicates that a spare bit from the certain number of spare bits contains a logical state valid for replacing the bit in the multiple bits. In some cases, the size of the memory array for storing the replacement relationship for the codeword reserved at a portion of the memory media may be based on bits indicating a change in the replacement relationship, an identification of a channel associated with the codeword, the number of spare bits in the codeword, an identification of a minimum replacement region (MSR) among a first number of MSRs associated with the codeword, the number of bits associated with a forwarded codeword in the memory media, the error correction capability of the replacement relationship, the number of memory dies corresponding to the channel associated with the codeword, or a second number of MSR groups in the memory die among the number of memory dies or any combination thereof.

[0109] Figure 6 A flowchart showing a method 600 for supporting media scrubber operations in a memory system in accordance with aspects disclosed herein is shown. The operations of method 600 may be implemented by a controller or components thereof as described with reference to Figures 1 to 2 For example, the operations of method 600 may be performed by the controller 120 or the controller 230 described with reference to Figures 1 to 2 In some instances, the controller 230 may execute a set of code for functional elements of a control device to perform the functions described below. Additionally or alternatively, the controller 230 may perform aspects of the functions described below using dedicated hardware.

[0110] At 605, the controller 230 may identify the value of a first counter associated with the memory medium, the first counter indicating a first number of codewords retained at the memory medium during a first duration, the first number of codewords being configured to be forwarded codewords. The operation of 605 may be performed according to the method described in reference Figures 1 - 5 as described. In certain instances, aspects of the operation of 605 may be performed by a codeword manager as described in reference Figure 5 as described.

[0111] At 610, the controller 230 may set the value of a second counter associated with the memory medium based on identifying the value of the first counter, the second counter indicating a second number of codewords retained at the memory medium during a second duration, the second number of codewords being configured to be forwarded codewords. The operation of 610 may be performed according to the method described in reference Figures 1 - 5 as described. In certain instances, aspects of the operation of 610 may be performed by a codeword manager as described in reference Figure 5 as described.

[0112] At 615, the controller 230 may receive a first codeword from the memory medium based on setting the value of the second counter. The operation of 615 may be performed according to the method described in reference Figures 1 - 5 as described. In certain instances, aspects of the operation of 615 may be performed by an access manager as described in reference Figure 5 as described.

[0113] Apparatus for performing one or more methods such as method 600 is described. The apparatus may include: means for identifying the value of a first counter associated with the memory medium, the first counter indicating a first number of codewords retained at the memory medium during a first duration, the first number of codewords being configured to be forwarded codewords; means for setting the value of a second counter associated with the memory medium based on identifying the value of the first counter, the second counter indicating a second number of codewords retained at the memory medium during a second duration, the second number of codewords being configured to be forwarded codewords; and means for receiving a first codeword from the memory medium based on setting the value of the second counter.

[0114] Describes another apparatus for performing one or more methods such as method 600. The apparatus may include a memory medium and a controller in electronic communication with the memory medium, where the controller may be operable to: identify a value of a first counter associated with the memory medium, the first counter indicating a first number of codewords retained at the memory medium during a first duration, the first number of codewords being configured to be forwarded codewords; set a value of a second counter associated with the memory medium based on identifying the value of the first counter, the second counter indicating a second number of codewords retained at the memory medium during a second duration, the second number of codewords being configured to be forwarded codewords; and receive a first codeword from the memory medium based on setting the value of the second counter.

[0115] Some examples of method 600 and apparatus described herein may further include a process, feature, component, or instruction for determining that the first codeword meets a condition for configuring the first codeword as a forwarded codeword, the condition being based on a number of error bits in the first codeword. Some examples of method 600 and apparatus described herein may further include a process, feature, component, or instruction for configuring the first codeword as a forwarded codeword based on the determination. Some examples of method 600 and apparatus described herein may further include a process, feature, component, or instruction for updating the value of the first counter based on configuring the first codeword as a forwarded codeword. Some examples of method 600 and apparatus described herein may further include a process, feature, component, or instruction for determining an updated value of the first counter relative to a first threshold associated with a number of forwarded codewords retained at the memory medium.

[0116] Some examples of method 600 and apparatus described herein may further include a process, feature, component, or instruction for receiving a second codeword from the memory medium based on updating the value of the first counter. Some examples of method 600 and apparatus described herein may further include a process, feature, component, or instruction for determining that the second codeword meets a condition for configuring the second codeword as a forwarded codeword based on receiving the second codeword. Some examples of method 600 and apparatus described herein may further include a process, feature, component, or instruction for avoiding configuring the second codeword as a forwarded codeword based on the updated value of the first counter relative to the first threshold.

[0117] Some examples of the method 600 and apparatus described herein may further include a process, feature, component, or instruction for determining that a first codeword corresponds to the last codeword reserved at a memory medium. Some examples of the method 600 and apparatus described herein may further include a process, feature, component, or instruction for updating a value of a second counter based on updating a value of a first counter and determining that the first codeword corresponds to the last codeword reserved at the memory medium. Some examples of the method 600 and apparatus described herein may further include a process, feature, component, or instruction for determining an updated value of the second counter relative to a second threshold associated with a number of forwarded codewords reserved at the memory medium. Some examples of the method 600 and apparatus described herein may further include a process, feature, component, or instruction for avoiding configuring a codeword as a forwarded codeword based on the updated value of the second counter.

[0118] Some examples of the method 600 and apparatus described herein may further include a process, feature, component, or instruction for writing the first codeword back to the memory medium based on configuring the first codeword as a forwarded codeword. Some examples of the method 600 and apparatus described herein may further include a process, feature, component, or instruction for resetting a value of the first counter based on setting a value of the second counter, wherein receiving the first codeword may be based on resetting the value of the first counter. In some examples of the method 600 and apparatus described herein, a first duration may be based on a preconfigured period for retrieving a set of codewords from the memory medium. In some examples of the method 600 and apparatus described herein, a second duration may be based on a lifetime of the memory medium, and wherein the lifetime of the memory medium may be based on an estimated duration for which the memory medium meets a set of operating criteria.

[0119] In some examples of the method 600 and apparatus described herein, receiving the first codeword may further include retrieving the first codeword as part of a periodic background operation independent of an access command from a host. In some examples of the method 600 and apparatus described herein, a forwarded codeword may include a number of copies of a forwarding address of the first codeword.

[0120] Figure 7 A flowchart showing a method 700 for supporting media scrubber operations in a memory system in accordance with aspects disclosed herein is shown. Operations of method 700 may be implemented by a controller or components thereof as described with reference to Figures 1 to 2 For example, operations of method 700 may be implemented by a controller or components thereof as described with reference to Figures 1 to 2Performed by the described controller 120 or controller 230. In some instances, controller 230 may execute a set of code for functional elements of the control device to perform the functions described below. Additionally or alternatively, controller 230 may use dedicated hardware to perform aspects of the functions described below.

[0121] At 705, controller 230 may receive a codeword reserved at a portion of the memory medium, the codeword comprising a plurality of bits including a certain number of spare bits for the codeword. The operation of 705 may be performed according to the method described in the reference Figures 1 - 5 described. In certain instances, aspects of the operation of 705 may be performed by an access manager as described in the reference Figure 5 described.

[0122] At 710, controller 230 may access the memory array of the port manager based on the received codeword. The operation of 710 may be performed according to the method described in the reference Figures 1 - 5 described. In certain instances, aspects of the operation of 710 may be performed by an error control manager as described in the reference Figure 5 described.

[0123] At 715, controller 230 may perform error control operations on the codeword based on accessing the memory array of the port manager to restore the logical states of the plurality of bits. The operation of 715 may be performed according to the method described in the reference Figures 1 - 5 described. In certain instances, aspects of the operation of 715 may be performed by an error control manager as described in the reference Figure 5 described.

[0124] At 720, controller 230 may write the logical states of the bits in the plurality of bits at the spare bits among the certain number of spare bits based on performing the error control operations. The operation of 720 may be performed according to the method described in the reference Figures 1 - 5 described. In certain instances, aspects of the operation of 720 may be performed by an access manager as described in the reference Figure 5 described.

[0125] Apparatus for performing one or more methods such as method 700 is described. The apparatus may include: means for receiving a codeword reserved at a portion of the memory medium, the codeword comprising a plurality of bits including a certain number of spare bits for the codeword; means for accessing the memory array of the port manager based on the received codeword; means for performing error control operations on the codeword based on accessing the memory array of the port manager to restore the logical states of the plurality of bits; and means for writing the logical states of the bits in the plurality of bits at the spare bits among the certain number of spare bits based on performing the error control operations.

[0126] Describes another apparatus for performing one or more methods, such as method 700. The apparatus can include a memory medium and a controller in electronic communication with the memory medium, where the controller can be operable to: receive a codeword reserved at a portion of the memory medium, the codeword including a plurality of bits that include a certain number of spare bits for the codeword; access a memory array of a port manager based on receiving the codeword; perform an error control operation on the codeword based on accessing the memory array of the port manager to restore a logical state of the plurality of bits; and write the logical state of the bits in the plurality of bits at spare bits in the certain number of spare bits based on performing the error control operation.

[0127] Some examples of method 700 and apparatus described herein can further include a process, feature, component, or instruction for replacing a bit in the plurality of bits with a spare bit in the certain number of spare bits based on accessing the memory array, where performing the error control operation on the codeword can be based on replacing the bit in the plurality of bits.

[0128] Some examples of method 700 and apparatus described herein can further include a process, feature, component, or instruction for identifying a value of a flag in the memory array based on accessing the memory array, the value of the flag indicating a change in a replacement relationship for a codeword reserved at a portion of the memory medium, where performing the error control operation on the codeword can be based on identifying the value of the flag. Some examples of method 700 and apparatus described herein can further include a process, feature, component, or instruction for resetting the value of a flag in the memory array based on writing the logical state of the bits in the plurality of bits, the value of the flag indicating that a spare bit in the certain number of spare bits includes a logical state valid for replacing the bit in the plurality of bits.

[0129] In some examples of method 700 and apparatus described herein, the size of the memory array for storing a replacement relationship for a codeword reserved at a portion of the memory medium can be based on a bit indicating a change in the replacement relationship, an identification of a channel associated with the codeword, a number of spare bits in the codeword, an identification of a minimum replacement region (MSR) in a first number of MSRs associated with the codeword, a number of bits associated with a forwarded codeword in the memory medium, an error correction capability of the replacement relationship, a number of memory dies corresponding to the channel associated with the codeword, or a second number of MSR groups in the memory die in the number of memory dies or any combination thereof.

[0130] In some examples of the methods 700 and apparatuses described herein, receiving the codewords can further include retrieving each of the plurality of codewords retained at a portion of the memory medium as part of a periodic background operation independent of access commands from a host, wherein accessing the memory array can be based on retrieving each of the plurality of codewords.

[0131] Figure 8 A flowchart illustrating a method 800 that supports media scrubber operations in a memory system in accordance with aspects disclosed herein is shown. The operations of method 800 can be implemented by a controller or components thereof as described with reference to Figures 1 to 2 For example, the operations of method 800 can be performed by controller 120 or controller 230 as described with reference to Figures 1 to 2 In some examples, controller 230 can execute a set of code for functional elements of a controller device to perform the functions described below. Additionally or alternatively, controller 230 can perform aspects of the functions described below using dedicated hardware.

[0132] At 805, controller 230 can receive a codeword from an address of a memory medium, the codeword including a set of bits. The operation of 805 can be performed in accordance with a method as described with reference to Figures 1 - 5 In certain examples, aspects of the operation of 805 can be performed by an access manager as described with reference to Figure 5

[0133] At 810, controller 230 can invert a portion of the bits based on the received codeword. The operation of 810 can be performed in accordance with a method as described with reference to Figures 1 - 5 In certain examples, aspects of the operation of 810 can be performed by a codeword manager as described with reference to Figure 5

[0134] At 815, controller 230 can set the values of the bits in the set to indicate a codeword condition that includes the inverted state of the codeword based on inverting the portion of the bits. The operation of 815 can be performed in accordance with a method as described with reference to Figures 1 - 5 In certain examples, aspects of the operation of 815 can be performed by a codeword manager as described with reference to Figure 5

[0135] At 820, controller 230 can write the codeword back to the address of the memory medium based on setting the values of the bits indicating the inverted state. The operation of 820 can be performed in accordance with a method as described with reference to Figures 1 - 5 In certain examples, aspects of the operation of 820 can be performed by an access manager as described with reference to Figure 5

[0136] ​​​​Apparatuses for performing one or more methods such as method 800 are described. An apparatus may include: means for receiving a codeword from an address of a memory medium, the codeword including a set of bits; means for inverting a portion of the bits based on the received codeword; means for setting values of bits in the set to indicate a codeword condition including an inversion state of the codeword based on inverting the portion of the bits; and means for writing the codeword back to the address of the memory medium based on setting the values of the bits indicating the inversion state.

[0137] Another apparatus for performing one or more methods such as method 800 is described. The apparatus may include a memory medium and a controller in electronic communication with the memory medium, wherein the controller may be operable to: receive a codeword from an address of the memory medium, the codeword including a set of bits; invert a portion of the bits based on the received codeword; set values of bits in the set to indicate a codeword condition including an inversion state of the codeword based on inverting the portion of the bits; and write the codeword back to the address of the memory medium based on setting the values of the bits indicating the inversion state.

[0138] In some instances of method 800 and the apparatuses described herein, the portion of the bits may include each bit in the set. In some instances of method 800 and the apparatuses described herein, receiving the codeword may further include retrieving each of a plurality of codewords retained at the memory medium as part of a periodic background operation independent of access commands from a host, wherein inverting the portion of the bits may be based on successively retrieving each of the plurality of codewords.

[0139] It should be noted that the methods described herein describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Further, instances of two or more of the methods may be combined.

[0140] Any of a variety of different processes and techniques may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may show a signal as a single signal; however, those of ordinary skill in the art will understand that a signal may represent a signal bus, where the bus may have various bit widths.

[0141] The terms "electronically communicate" and "coupled" refer to a relationship between components that supports an electronic flow between the components. This can include a direct connection between the components or can include intermediate components. Components that electronically communicate or are coupled to each other may actively exchange electrons or signals (e.g., in a powered-on circuit) or may not actively exchange electrons or signals (e.g., in a powered-off circuit), but may be configured and operable to exchange electrons or signals when the circuit is powered on. For example, two components physically connected by a switch (e.g., a transistor) electronically communicate or may be coupled, regardless of the state of the switch (i.e., open or closed).

[0142] A chalcogenide material can be a material or alloy that includes at least one of the elements S, Se, and Te. The phase change materials discussed herein can be chalcogenide materials. Chalcogenide materials can include alloys of S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), platinum (Pt). Example chalcogenide materials and alloys can include but are not limited to: Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, or Ge-Te-Sn-Pt. As used herein, a chemical composition symbol with a hyphen indicates the elements included in a particular compound or alloy and is intended to represent all stoichiometries that include the indicated elements. For example, Ge-Te can include Ge x Te y , where x and y can be any positive integers. Other examples of variable resistance materials can include binary metal oxide materials or mixed valence oxides that include two or more metals such as transition metals, alkaline earth metals, and / or rare earth metals. The examples are not limited to a particular variable resistance material or a material associated with a memory element of a memory cell. For example, other examples of variable resistance materials can be used to form memory elements and can include chalcogenide materials, giant magnetoresistive materials, or polymer-based materials, etc.

[0143] Devices discussed herein, including the memory medium 130, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation or by any other doping means during the initial formation or growth of the substrate.

[0144] The description set forth herein describes example configurations in conjunction with the drawings and does not represent all instances that may be implemented within the scope of the claims or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example / instance or illustration", rather than "preferred" or "superior to other instances". For providing an understanding of the described technology, the detailed description includes specific details. However, these technologies may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0145] In the drawings, like components or features may have the same reference numeral. Further, each of the same type of components may be distinguished by adding a dash after the reference numeral and a second label that differentiates between the like components. If only the first reference numeral is used in the specification, the description applies to any of the like components having the same first reference numeral, regardless of the second reference numeral.

[0146] Any of a variety of different processes and techniques may be used to represent the information and signals described herein. For example, the data, instructions, commands, information, signals, bits, symbols, and chips referred to throughout the description of this document may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0147] The various illustrative blocks and modules described in connection with the disclosure herein can be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a digital signal processor (DSP) and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0148] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination of these items. The features implementing the functions can also be physically located in various locations, including being distributed such that portions of the functions are implemented at different physical locations. Also, as used herein (including in the claims), the "or" as used in a list of items (e.g., a list that begins with phrases such as "at least one of..." or "one or more of...") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope disclosed herein. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0149] A computer-readable medium includes both a non-transitory computer storage medium and a communication medium, where the communication medium includes any medium that facilitates transfer of a computer program from one place to another. The non-transitory storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer. By way of example, and not limitation, the non-transitory computer-readable medium can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store the desired program code components in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if software is transferred using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of the medium. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0150] The description herein is provided to enable a person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of the present disclosure. Thus, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus for memory operations, which comprises: a controller associated with a memory medium and configured to perform the following operations: identifying a value of a first counter associated with the memory medium, the first counter indicating a first number of codewords retained at the memory medium during a first duration, the first number of codewords being configured as forwarded codewords; setting a value of a second counter associated with the memory medium based on identifying the value of the first counter, the second counter indicating a second number of codewords retained at the memory medium during a second duration, the second number of codewords being configured as forwarded codewords; and receiving a first codeword from the memory medium based on setting the value of the second counter.

2. The apparatus according to claim 1, wherein the controller is further configured to perform the following operations: determining that the first codeword meets a condition for configuring a codeword as a forwarded codeword, the condition being based on a number of error bits in the codeword; and configuring the first codeword as a first forwarded codeword based on determining that the first codeword meets the condition.

3. The apparatus according to claim 2, wherein the controller is further configured to perform the following operations: updating the value of the first counter based on configuring the first codeword as the forwarded codeword; and determining an updated value of the first counter relative to a first threshold associated with a number of forwarded codewords retained at the memory medium.

4. The apparatus according to claim 3, wherein the controller is further configured to perform the following operations: receiving a second codeword from the memory medium based on updating the value of the first counter; determining that the second codeword meets the condition for configuring a codeword as a forwarded codeword; and avoiding configuring the second codeword as a forwarded codeword based on the updated value of the first counter relative to the first threshold.

5. The apparatus according to claim 3, wherein the controller is further configured to perform the following operations: determining that the first codeword corresponds to a last codeword retained at the memory medium; updating the value of the second counter based on updating the value of the first counter and determining that the first codeword corresponds to the last codeword retained at the memory medium; determining an updated value of the second counter relative to a second threshold associated with the number of forwarded codewords retained at the memory medium; and avoiding configuring additional codewords as forwarded codewords based on the updated value of the second counter.

6. The apparatus according to claim 2, wherein the controller is further configured to perform the following operations: writing the first codeword back to the memory medium based on configuring the first codeword as the forwarded codeword.

7. The apparatus according to claim 1, wherein the controller is further configured to perform the following operations: resetting the value of the first counter based on setting the value of the second counter, wherein receiving the first codeword is based on resetting the value of the first counter.

8. The device according to claim 1, wherein the first duration is based on a preconfigured period for retrieving a set of codewords from the memory medium.

9. The device according to claim 1, wherein the second duration is based on the life cycle of the memory medium, and wherein the life cycle of the memory medium is based on an estimated duration for which the memory medium meets a set of operating criteria.

10. The device according to claim 1, wherein, for receiving the first codeword, the controller is further configured to perform the following operations: Retrieve the first codeword as part of a periodic background operation independent of access commands from a host.

11. A device for memory operations, which comprises: A memory medium; A first counter configured to indicate a first number of codewords retained at the memory medium during a first duration, the first number of codewords being configured as forwarded codewords; A second counter configured to indicate a second number of codewords retained at the memory medium during a second duration, the second number of codewords being configured as forwarded codewords; and A controller configured to perform the following operations: Identify the value of the first counter; Set the value of the second counter based on identifying the value of the first counter; and Receive a first codeword from the memory medium based on setting the value of the second counter.

12. The device according to claim 11, wherein the controller is further configured to perform the following operations: Determine that the first codeword meets a condition for configuring a codeword as a forwarded codeword, the condition being based on the number of error bits in the codeword; and Configure the first codeword as a first forwarded codeword based on determining that the first codeword meets the condition.

13. The device according to claim 12, wherein the controller is further configured to perform the following operations: Update the value of the first counter based on configuring the first codeword as the forwarded codeword; and Determine an updated value of the first counter relative to a first threshold associated with the number of forwarded codewords retained at the memory medium.

14. The device according to claim 13, wherein the controller is further configured to perform the following operations: Receive a second codeword from the memory medium based on updating the value of the first counter; Determine that the second codeword meets the condition for configuring a codeword as a forwarded codeword; and Avoid configuring the second codeword as a forwarded codeword based on the updated value of the first counter relative to the first threshold.

15. A device for memory operations, which comprises: A memory medium, which includes: A first memory array configured to store codewords; and A second memory array; and A controller in electronic communication with the first memory array and the second memory array, the controller operable to perform the following operations: Retrieve the codeword from the first memory array, the codeword including a plurality of bits; Obtain a replacement relationship from the second memory array, the replacement relationship indicating a first one of the plurality of bits to be replaced by a spare bit among the plurality of bits; Replace the first bit in the codeword with the spare bit according to the replacement relationship; After replacing the first bit with the spare bit, perform an error control operation on the codeword to restore the logical states of the plurality of bits; and Write the restored logical state, which corresponds to the logical state of the first bit, to the spare bit.

16. The apparatus according to claim 15, wherein the error control operation is performed on the codeword at least in part based on replacing the first bit in the codeword with the spare bit.

17. The apparatus according to claim 15, wherein the controller is further configured to perform the following operations: Identify a value of a flag in the second memory array, the value of the flag indicating a change in the replacement relationship, wherein the replacement relationship is obtained from the second memory array at least in part based on identifying the value of the flag.

18. The apparatus according to claim 15, wherein the controller is further configured to perform the following operations: Reset a value of a flag in the second memory array at least in part based on writing the restored logical state to the spare bit, the value of the flag indicating that the spare bit includes the restored logical state corresponding to the logical state of the first bit.

19. The apparatus according to claim 15, wherein the replacement relationship comprises: an indication of a change in the replacement relationship, an identification of a channel associated with the codeword, a number of spare bits in the codeword, an identification of an MSR in a first number of minimum replacement regions MSRs associated with the codeword, a number of bits associated with a forwarded codeword in the memory medium, an error correction capability of the replacement relationship, a number of memory dies corresponding to the channel associated with the codeword, or a second number of MSR groups in the number of memory dies or any combination thereof.

20. The apparatus according to claim 15, wherein the codeword is one of a plurality of codewords reserved at the first memory array, and wherein the controller is further configured to perform the following operations: Retrieve each of the plurality of codewords from the first memory array as part of a periodic background operation independent of an access command, wherein the replacement relationship is obtained from the second memory array at least in part based on retrieving each of the plurality of codewords from the first memory array.

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