Memory and testing method

Abstract

The present disclosure provides a memory and a testing method, in one step, different voltages are applied to a first bit line and a second bit line for a non-first-and-last-position memory array piece to realize bit line stress testing of the non-first-and-last-position memory array piece; and in another step, different voltages are applied to an odd-numbered first bit line and an even-numbered first bit line for a first-and-last-position memory array piece to realize bit line stress testing of the first-and-last-position memory array piece.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more particularly to a memory and a testing method. Background Technology

[0002] With the development of semiconductor technology, the integration requirements and performance standards of memory are gradually increasing. Therefore, the internal circuit structure is also being optimized. Providing matching test methods for the optimized internal circuit structure is also a problem that needs to be solved. Summary of the Invention

[0003] This disclosure provides a memory and a testing method.

[0004] The technical solution disclosed herein is implemented as follows:

[0005] In a first aspect, this disclosure provides a memory comprising N memory array chips arranged sequentially along a first direction, where N is a natural number; each memory array chip includes a plurality of first bit lines and a plurality of second bit lines, wherein the first bit lines and second bit lines are alternately arranged along a second direction; for memory array chips not at the beginning or end, the first bit line and the adjacent second bit line are electrically isolated; for memory array chips at the beginning or end, the first bit line is electrically connected to the second bit line adjacent to the first side, and the first bit line is electrically isolated from the second bit line adjacent to the second side; the memory is configured to, in one step, apply non-performing voltages to the first bit line and the second bit line respectively for memory array chips not at the beginning or end. Different voltages are applied to the first bit line of the memory array chips at non-first and last positions to achieve bit line stress testing; and in another step, different voltages are applied to the first bit line of the odd-numbered memory array chips and the first bit line of the even-numbered memory array chips to achieve bit line stress testing of the memory array chips at the first and last positions; wherein, the memory array chips are numbered along a first direction, and for the odd-numbered memory array chips, its first bit line is the second bit line; for the even-numbered memory array chips, its first bit line is the first bit line; for each memory array chip, the first bit line therein is numbered sequentially along a second direction, and the second bit line therein is numbered sequentially along the second direction.

[0006] In some embodiments, a readout amplification module is distributed between every two memory array chips, and the readout amplification module includes a plurality of sensitive amplifiers arranged sequentially along a second direction; the second end of the sensitive amplifier is connected to a first bit line on the third side through a first debias switch, and the first end of the sensitive amplifier is connected to a first bit line on the third side through a first isolation switch; the first end of the sensitive amplifier is also connected to a second bit line on the fourth side through a second debias switch, and the second end of the sensitive amplifier is also connected to a second bit line on the fourth side through a second isolation switch.

[0007] In some embodiments, the readout amplifier modules are numbered along a first direction; for odd-numbered readout amplifier modules, the first or second terminal of the sensitive amplifier is further connected to a first power supply terminal via a precharge switch; for even-numbered readout amplifier modules, the first or second terminal of the sensitive amplifier is further connected to a second power supply terminal via a precharge switch.

[0008] In some embodiments, the memory is specifically configured to, in one step, turn off all sensitive amplifiers, control the first power supply terminal to a first voltage value and the second power supply terminal to a second voltage value, and perform a regular pre-charge operation; and, after a preset time, control the first power supply terminal to the second voltage value and the second power supply terminal to the first voltage value, and perform a regular pre-charge operation; wherein the first voltage value and the second voltage value are different; and in the regular pre-charge operation, all pre-charge switches, isolation switches and de-bias switches are in the ON state.

[0009] In some embodiments, each of the first and last memory array chips includes multiple bi-cells. Each bi-cell includes two memory cells storing the same data. Both memory cells are electrically connected to the same word line, and there is an electrical connection between the corresponding bit lines of the two memory cells. The bi-cells simultaneously read and write data. For each memory array chip at the first and last positions, the bi-cells are numbered along a second direction. The memory is further configured to, in another step, only activate the sensitive amplifiers adjacent to the memory array chips at the first and last positions, write first data to the odd-numbered bi-cells, and write second data to the even-numbered bi-cells; and, after a preset time period, write second data to the odd-numbered bi-cells and write first data to the even-numbered bi-cells; wherein the first data and the second data are different.

[0010] In some embodiments, the readout amplification modules are numbered along a first direction, and the first readout amplification module is an odd number; for each readout amplification module, the sensitive amplifiers therein are numbered along a second direction; for the odd-numbered readout amplification modules, the second terminal of the odd-numbered sensitive amplifier is connected to a third power supply terminal through a precharge switch, and the first terminal of the even-numbered sensitive amplifier is connected to a fourth power supply terminal through a precharge switch; for the even-numbered readout amplification modules, the second terminal of the odd-numbered sensitive amplifier is connected to a fifth power supply terminal through a precharge switch, and the first terminal of the even-numbered sensitive amplifier is connected to a sixth power supply terminal through a precharge switch.

[0011] In some embodiments, the memory is specifically configured to, in one step, turn off all sensitive amplifiers, control the third and fourth power supply terminals to be at a first voltage value, and control the fifth and sixth power supply terminals to be at a second voltage value; and perform a regular pre-charge operation; and, after a preset time, control the third and fourth power supply terminals to be at the second voltage value, and control the fifth and sixth power supply terminals to be at the first voltage value; and perform a regular pre-charge operation.

[0012] In some embodiments, the memory is specifically configured to, in another step, turn off all sensitive amplifiers, control the third and fifth power supply terminals to be at a first voltage value, and the fourth and sixth power supply terminals to be at a second voltage value; and perform a regular pre-charge operation; and, after a preset time, control the third and fifth power supply terminals to be at the second voltage value, and the fourth and sixth power supply terminals to be at the first voltage value; and perform a regular pre-charge operation.

[0013] In some embodiments, the memory is specifically configured to, in one step, turn off all sensitive amplifiers, control the third and fourth power supply terminals to be at a first voltage value, and control the fifth and sixth power supply terminals to be at a second voltage value; and perform a first test pre-charge operation; and, after a preset time, control the third and fourth power supply terminals to be at the second voltage value, and control the fifth and sixth power supply terminals to be at the first voltage value; and perform the first test pre-charge operation; wherein, in the first test pre-charge operation, the isolation switches and debias switches between the readout amplification modules at the beginning and end positions and the memory array chips at the beginning and end positions are all in the off state, and all other pre-charge switches, isolation switches, and debias switches are in the on state.

[0014] In some embodiments, the memory is specifically configured to, in another step, turn off all sensitive amplifiers, control the third and fifth power supply terminals to be at a first voltage value, and the fourth and sixth power supply terminals to be at a second voltage value; and perform a second test pre-charge operation; and, after a preset time, control the third and fifth power supply terminals to be at the second voltage value, and the fourth and sixth power supply terminals to be at the first voltage value; and perform the second test pre-charge operation; wherein, in the second test pre-charge operation, the isolation switches and debias switches between the read amplification modules at the beginning and end positions and the memory array chips at the beginning and end positions are both in the open state, and the isolation switches and debias switches between the read amplification modules at the beginning and end positions and the memory array chips at the non-beginning and end positions are both in the closed state; the pre-charge switches of the read amplification modules at the beginning and end positions are both in the open state, and the pre-charge switches in the remaining read amplification modules are both in the closed state.

[0015] In some embodiments, the first test precharge operation, the second test precharge operation, and the regular precharge operation are all precharge operations. The memory further includes: a control circuit configured to generate a valid initial isolation signal and a valid initial depolarization signal when the memory is instructed to perform a precharge operation; and to generate an invalid initial isolation signal and an invalid initial depolarization signal when the memory is not instructed to perform a precharge operation; a first preprocessing circuit configured to generate a first edge isolation signal and a second edge isolation signal based on the edge test parameter set and the initial isolation signal; and to generate a first edge depolarization signal and a second edge depolarization signal based on the edge test parameter set and the initial depolarization signal; and a second preprocessing circuit configured to generate an internal test parameter set and an initial isolation signal. A first internal isolation signal and a second internal isolation signal are generated; and based on the internal test parameter set and the initial debiasing signal, a first internal debiasing signal and a second internal debiasing signal are generated; wherein, the first isolation switch, the second isolation switch, the first debiasing switch, and the second debiasing switch between the first and last readout amplifier modules and the adjacent memory array chips are controlled by the first edge isolation signal, the second edge isolation signal, the first edge debiasing signal, and the second edge debiasing signal; the first isolation switch, the second isolation switch, the first debiasing switch, and the second debiasing switch between the readout amplifier modules at non-first and last positions and the adjacent memory array chips are correspondingly controlled by the first internal isolation signal, the second internal isolation signal, the first internal debiasing signal, and the second internal debiasing signal.

[0016] In some embodiments, the edge test parameter group includes at least a first test parameter and a second test parameter, and the internal test parameter group includes at least a third test parameter and a fourth test parameter. If the current pre-charge operation is a regular pre-charge operation, then the first test parameter, the second test parameter, the third test parameter, and the fourth test parameter are all in a first state. If the test parameter group indicates that the current pre-charge operation is a first test pre-charge operation, then the second test parameter is in a second state, and the first test parameter, the third test parameter, and the fourth test parameter are all in a first state. If the current pre-charge operation is a second test pre-charge operation, then the first test parameter is in a second state, and the second test parameter, the third test parameter, and the fourth test parameter are all in a first state. If the second test parameter is in a first state, then the levels of the first edge isolation signal and the first edge de-polarization signal are the same as those of the initial isolation signal and the initial de-polarization signal. If the second test parameter is in a second state... If the first test parameter is in the first state, then the second edge isolation signal and the second edge depolarization signal have the same level as the initial isolation signal and the initial depolarization signal. If the first test parameter is in the second state, then the second edge isolation signal and the second edge depolarization signal are both invalid. If the fourth test parameter is in the first state, then the first internal isolation signal and the first internal depolarization signal have the same level as the initial isolation signal and the initial depolarization signal. If the fourth test parameter is in the second state, then the first internal isolation signal and the first internal depolarization signal are both invalid. If the third test parameter is in the first state, then the second internal isolation signal and the second internal depolarization signal have the same level as the initial isolation signal and the initial depolarization signal. If the third test parameter is in the second state, then the second internal isolation signal and the second internal depolarization signal are both invalid.

[0017] In some embodiments, the first state is high level and the second state is low level; the first preprocessing circuit includes: a first AND gate, whose two inputs receive a first test parameter and an initial isolation signal respectively, and whose output outputs a second edge isolation signal; a second AND gate, whose two inputs receive a second test parameter and an initial isolation signal respectively, and whose output outputs a first edge isolation signal; a third AND gate, whose two inputs receive a first test parameter and an initial debiasing signal respectively, and whose output outputs a second edge debiasing signal; a fourth AND gate, whose two inputs receive a second test parameter and an initial debiasing signal respectively, and whose output outputs a second edge debiasing signal; and a fourth AND gate, whose two inputs receive a second test parameter and an initial debiasing signal respectively, and whose output outputs a second edge debiasing signal. The output terminal outputs a first edge depolarization signal; the second preprocessing circuit includes: a fifth AND gate, whose two input terminals receive a third test parameter and an initial isolation signal respectively, and whose output terminal outputs a second internal isolation signal; a sixth AND gate, whose two input terminals receive a fourth test parameter and an initial isolation signal respectively, and whose output terminal outputs a first internal isolation signal; a seventh AND gate, whose two input terminals receive a third test parameter and an initial depolarization signal respectively, and whose output terminal outputs a second internal depolarization signal; and an eighth AND gate, whose two input terminals receive a fourth test parameter and an initial depolarization signal respectively, and whose output terminal outputs a first internal depolarization signal.

[0018] Secondly, this disclosure provides a testing method applied to a memory, the memory including N memory array chips arranged sequentially along a first direction, each memory array chip including a plurality of first bit lines and a plurality of second bit lines, wherein the first bit lines and second bit lines are alternately arranged along a second direction; for memory array chips not at the beginning or end, the first bit line and the adjacent second bit line are electrically isolated; for memory array chips at the beginning or end, the first bit line is electrically connected to the second bit line adjacent to the first side and the first bit line is electrically isolated from the second bit line adjacent to the second side; the method includes: in one step, for memory array chips not at the beginning or end, applying an inverse force to the first bit line and the second bit line respectively. Different voltages are applied to the first and second bit lines of the memory array chips at non-first and last positions to achieve bit line stress testing. In another step, different voltages are applied to the first bit line of the odd-numbered and the first bit line of the even-numbered memory array chips to achieve bit line stress testing. The memory array chips are numbered along a first direction. For the odd-numbered memory array chips, the first bit line is the second bit line. For the even-numbered memory array chips, the first bit line is the first bit line. For each memory array chip, the first bit line is numbered sequentially along a second direction, and the second bit line is numbered sequentially along the second direction.

[0019] In some embodiments, for the first memory array chip, the second bit lines are connected to their respective precharge sources via precharge switches, and the first bit lines are precharged via the precharge source corresponding to the second bit lines electrically connected to them; for the last memory array chip, the first bit lines are connected to their respective precharge sources via precharge switches, and the second bit lines are precharged via the precharge source corresponding to the first bit lines electrically connected to them; for memory array chips that are neither the first nor the last, the first bit lines are connected to their respective precharge sources via precharge switches, and the second bit lines are connected to their respective precharge sources via precharge switches; the second bit lines in odd-numbered memory arrays and the first bit lines in even-numbered memory array chips... All pre-charge power sources are the first power supply terminal. The pre-charge power sources for the first bit line in the odd-numbered memory array and the second bit line in the even-numbered memory array are the second power supply terminals. For memory arrays that are not at the beginning or end, different voltages are applied to the first bit line and the second bit line, including: controlling the first power supply terminal to a first voltage value and the second power supply terminal to a second voltage value; the first voltage value and the second voltage value are different; performing a regular pre-charge operation; wherein, in the regular pre-charge operation, each bit line is connected to its respective pre-charge power source; after a preset time, the regular pre-charge operation is stopped, the first power supply terminal is controlled to the second voltage value and the second power supply terminal is controlled to the first voltage value; the regular pre-charge operation is performed and maintained for the preset time.

[0020] In some embodiments, the first and last memory array chips each include multiple bi-cells. Each bi-cell includes two memory cells storing the same data. Both memory cells are electrically connected to the same word line, and the corresponding bit lines of the two memory cells are electrically connected. The bi-cells simultaneously read and write data. For the first and last memory array chips, different voltages are applied to the first bit line of the odd-numbered chips and the first bit line of the even-numbered chips, respectively. This includes: writing first data to the bi-cells of the odd-numbered chips and writing second data to the bi-cells of the even-numbered chips; the first data and the second data are different; stopping the data writing operation after a preset time, writing the second data to the bi-cells of the odd-numbered chips and writing the first data to the bi-cells of the even-numbered chips, and maintaining this for the preset time.

[0021] In some embodiments, for the first memory array chip, the second bit lines are connected to their respective pre-charge sources via pre-charge switches, and the first bit lines are pre-charged via the pre-charge source corresponding to the second bit lines electrically connected to them; for the last memory array chip, the first bit lines are connected to their respective pre-charge sources via pre-charge switches, and the second bit lines are pre-charged via the pre-charge source corresponding to the first bit lines electrically connected to them; for memory array chips that are neither the first nor the last, the first bit lines are connected to their respective pre-charge sources via pre-charge switches, and the second bit lines are connected to their respective pre-charge sources via pre-charge switches; the pre-charge source for the second bit lines in odd-numbered memory arrays is a third power supply terminal, and the pre-charge source for the second bit lines in even-numbered memory arrays is a third power supply terminal. The pre-charge power source for a single bit is the fourth power supply terminal; the pre-charge power source for the first bit in an odd-numbered memory array is the fifth power supply terminal; and the pre-charge power source for the second bit in an even-numbered memory array is the sixth power supply terminal. For memory arrays that are not at the beginning or end, different voltages are applied to the first and second bit lines, including: controlling the third and fourth power supply terminals to a first voltage value, and the fifth and sixth power supply terminals to a second voltage value; the first and second voltage values ​​are different; performing a regular pre-charge operation; stopping the regular pre-charge operation after a preset time, controlling the third and fourth power supply terminals to the second voltage value, and the fifth and sixth power supply terminals to the first voltage value; performing a regular pre-charge operation and maintaining it for the preset time.

[0022] In some embodiments, for the first and last storage array chips, different voltages are applied to the first line of the odd-numbered chips and the first line of the even-numbered chips, respectively, including: controlling the third and fifth power supply terminals to a first voltage value and the fourth and sixth power supply terminals to a second voltage value; performing a regular pre-charge operation; stopping the regular pre-charge operation after a preset time, controlling the third and fifth power supply terminals to the second voltage value and the fourth and sixth power supply terminals to the first voltage value; performing the regular pre-charge operation and maintaining it for the preset time.

[0023] In some embodiments, the pre-charge source for the second bit line in an odd-numbered memory array is a third power supply terminal, the pre-charge source for the first bit line in an even-numbered memory array is a fourth power supply terminal, the pre-charge source for the first bit line in an odd-numbered memory array is a fifth power supply terminal, and the pre-charge source for the second bit line in an even-numbered memory array is a sixth power supply terminal; for memory arrays at the beginning and end positions, one of the first and second bit lines corresponds to a pre-charge source; for memory arrays not at the beginning or end positions, different voltages are applied to the first and second bit lines, including controlling the third power supply terminal and the fourth power supply terminal. The first power supply terminal is set to the first voltage value, and the fifth and sixth power supply terminals are set to the second voltage value; the first voltage value and the second voltage value are different; a first test pre-charge operation is performed; wherein, in the first test pre-charge operation, all bit lines in the first and last positions of the memory array chip are disconnected from their respective pre-charge power sources, and all bit lines in the memory array chips other than the first and last positions are connected to their respective pre-charge power sources; after a preset time, the pre-charge operation is stopped, the third and fourth power supply terminals are set to the second voltage value, and the fifth and sixth power supply terminals are set to the first voltage value; the first test pre-charge operation is performed and maintained for the preset time.

[0024] In some embodiments, for the first and last memory array chips, different voltages are applied to the first bit line of the odd-numbered chips and the first bit line of the even-numbered chips, respectively, including: controlling the third and fifth power supply terminals to a first voltage value, and the fourth and sixth power supply terminals to a second voltage value; the first voltage value and the second voltage value are different; performing a second test precharge operation; wherein, in the second test precharge operation, all bit lines in the first and last memory array chips are connected to their respective precharge sources, and all bit lines in the memory array chips other than the first and last chips are disconnected from their respective precharge sources; stopping the precharge operation after a preset time, controlling the third and fifth power supply terminals to the second voltage value, and the fourth and sixth power supply terminals to the first voltage value; performing the second test precharge operation and maintaining it for the preset time.

[0025] This disclosure provides a memory and a testing method that reduces the area of ​​the memory array chip located at the edge to half the area of ​​other memory array chips, thereby reducing the chip area and improving integration. It also provides a corresponding testing method for this structure, improving the testing process for this type of memory and ensuring factory performance. Attached Figure Description

[0026] Figure 1 A schematic diagram of a partial structure of a DRAM. Figure 1 ;

[0027] Figure 2 A schematic diagram of a partial structure of a DRAM. Figure 2 ;

[0028] Figure 3A A partial structural diagram of a memory provided in an embodiment of this disclosure. Figure 1 ;

[0029] Figure 3B A partial structural diagram of a memory provided in an embodiment of this disclosure. Figure 2 ;

[0030] Figure 4 A partial structural diagram of a memory provided in this embodiment of the present disclosure is shown in Figure 3.

[0031] Figure 5 Schematic diagram of the structure of the sensitive amplifier provided in the embodiments of this disclosure Figure 1 ;

[0032] Figure 6 A partial structural diagram of a memory provided in an embodiment of this disclosure. Figure 4 ;

[0033] Figure 7 A partial structural diagram of a memory provided in an embodiment of this disclosure. Figure 5 ;

[0034] Figure 8 Schematic diagram of the structure of the sensitive amplifier provided in the embodiments of this disclosure Figure 2 ;

[0035] Figure 9 A schematic diagram of the structure of the first preprocessing circuit and the second preprocessing circuit provided in the embodiments of this disclosure;

[0036] Figure 10 Another schematic diagram of the structure of the first preprocessing circuit provided in the embodiments of this disclosure;

[0037] Figure 11 This is a flowchart illustrating a testing method provided in an embodiment of the present disclosure. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0039] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0040] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0042] Taking Dynamic Random Access Memory (DRAM) as an example, see [link to relevant documentation]. Figure 1 This illustration shows a partial structural diagram of a DRAM provided in an embodiment of the present disclosure. Figure 1 As shown, the core of DRAM consists of a memory array (or section), a read amplifier module, a row decoder and controller (XDEC) circuit, a column decoder and controller (YDEC) circuit, a second-level read amplifier (SSa) circuit, and a write driver circuit. The second-level read amplifier circuit and the write driver circuit are collectively referred to as the SSa & Write Driver circuit.

[0043] A storage array consists of a large number of storage cells, which can be used to read, write, or refresh data in selected storage cells via word lines (WL) and bit lines (BL).

[0044] Generally, 65 memory array slices along the first direction can serve as a repeatable structure in the memory (e.g., a half-bank memory). Figure 1 For further zoom, please see [link / reference]. Figure 2 In each memory array slice (e.g., 11_1, 11_2...11_65), the bit lines are alternately called the first bit line BLa and the second bit line BLb. Figure 2Only the first bit line BLa and the second bit line BLb are shown as examples. Specifically, for memory array slices with odd numbers (e.g., 11_1, 11_3...11_65), the first bit line is the second bit line BLb; for memory array slices with even numbers (e.g., 11_2, 11_4...11_64), the first bit line is the first bit line BLa. In particular, the first bit line BLa and the second bit line BLb are only a position-based division; in fact, the first bit line BLa and the second bit line BLb have exactly the same physical structure.

[0045] A readout amplifier module (e.g., 12_1, 12_2...12_64) is set between every two memory array chips. Each readout amplifier module includes multiple sense amplifiers (Sa). One end of each Sa is connected to a bit line in the memory array chip on one side (e.g., the top), and the other end of Sa is connected to a bit line in the memory array chip on the other side (e.g., the bottom).

[0046] Please refer to Figure 1 and Figure 2 The XDEC provides a word line signal to enable the target word line in the memory array chip, and then the YDEC provides a column selection signal to control the corresponding Sa to work. In this way, the Sa exchanges electrical signals with the target bit line, and finally writes, reads or refreshes data to the target memory cell.

[0047] like Figure 2 As shown, for the memory array chips at the beginning and end positions (Edge), only half of the bit lines can be connected to the adjacent read amplifier module. This means that the other half of the bit lines and their corresponding memory cells are actually unusable. For example, the first bit line BLa in memory array chips 11_1 and 11_65 is not connected to the read amplifier module, resulting in a waste of memory cells and hindering the improvement of chip integration.

[0048] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0049] In one embodiment of this disclosure, see Figure 3A or Figure 3B This illustration shows a partial structural diagram of a memory 10 provided in an embodiment of the present disclosure. For example... Figure 3A or Figure 3B As shown, the memory 10 includes N memory array slices (e.g., 11_1, 11_2...11_N, i.e., the memory array slices are numbered along the first direction) arranged sequentially along a first direction. Here, N can be any natural number. Figure 3A Let's take an odd number as an example. Figure 3B The example is illustrated when N is an even number.

[0050] Please refer to Figure 3A and Figure 3B Each memory array chip includes multiple first bit lines BLa and multiple second bit lines BLb, and the first bit lines BLa and the second bit lines BLb are arranged alternately along a second direction; for memory array chips that are not at the beginning or end (e.g., 11_2……11_N-1), the first bit line BLa and the adjacent second bit line BLb are electrically isolated; for memory array chips at the beginning or end (e.g., 11_1 and 11_N), the first bit line BLa is electrically connected to the second bit line BLb adjacent to the first side (e.g., the right side), and the first bit line BLa is electrically isolated from the second bit line BLb adjacent to the second side (e.g., the left side).

[0051] Here, the sensitive amplification circuit 10 in this embodiment is applied to various signal amplification scenarios, such as DRAM, Synchronous Dynamic Random Access Memory (SDRAM), Double Speed ​​DRAM, Low Power DRAM, etc., and those skilled in the art can apply it flexibly.

[0052] It should be noted that for the first and last memory array slices (11_1, 11_N), since the two bit lines are essentially connected to form a single bit line, the length of each bit line can be shortened by nearly half. Specifically, for memory array slices not at the first or last position, the distance between one end of each bit line connected to Sa and the other end of that bit line is denoted as L1. For memory array slices at the first and last position, the distance between one end of the entire bit line (first bit line + second bit line) connected to Sa and the other end of that entire bit line is denoted as L2, where L1 = L2.

[0053] Therefore, the area of ​​the memory array chips at the beginning and end (11_1, 11_N) is reduced by nearly half compared to the area of ​​the memory array chips at the other ends (11_2...11_N-1), thus increasing the integration of the memory 10 and reducing the overall area occupied by the memory cells.

[0054] Specifically, bit line stress testing (BL stress) is an important performance test item for the memory 10. The test method involves applying different voltages to adjacent bit lines and then observing whether the memory cell can function normally. Figure 3A or Figure 3B The memory 10 shown has a different bit line structure for the memory array slices (11_1, 11_N) at the beginning and end positions than that for the memory array slices (11_2...11_N-1) at the end and end positions, which makes it impossible to achieve BL stress using conventional methods.

[0055] Therefore, embodiments of this disclosure also provide for... Figure 3A or Figure 3BThe method for testing the BL stress of the memory 10 shown.

[0056] For ease of explanation, regarding Figure 3A or Figure 3B For the memory array slices with odd numbers (11_1, 11_3, 11_5...), its first bit line is the second bit line BLb; for the memory array slices with even numbers (11_2, 11_6, 11_6...), its first bit line is the first bit line BLa. For each memory array slice, the first bit line BLa is numbered sequentially along the second direction, and the second bit line BLb is numbered sequentially along the second direction.

[0057] For example, if the starting number is odd, please refer to [link / reference]. Figure 4 (This example uses N=65; other values ​​of N should be understood accordingly.) The bit lines in memory array chip 11_1 along the second direction are: BLbo, BLao, BLbe, BLae; the bit lines in memory array chip 11_2 along the second direction are: BLao, BLbo, BLae, BLbe...

[0058] Specifically, memory 10 is configured to, in one step, for memory array slices (11_2...11_64) that are not at the beginning or end, send data to the first line BLa (for... Figure 4 Both BLao and BLae are the first line (BLa) and the second line (BLb) (for Figure 4 Different voltages are applied to the second bit lines BLb (BLbo and BLbe are both second bit lines) to achieve bit line stress testing (BL stress) for memory array chips (11_2...11_64) that are not at the beginning or end of the array; and in another step, different voltages are applied to the first bit line BLao (odd number) and the first bit line BLae (even number) for memory array chips (11_1 and 11_65) that are at the beginning or end of the array to achieve bit line stress testing (BL stress) for memory array chips (11_1 and 11_N) that are at the beginning or end of the array.

[0059] In this way, BL stress is broken down into two steps. One step applies BL stress to memory array slices that are not at the beginning or end, while the other step applies BL stress to memory array slices at the beginning and end. This achieves... Figure 3A or Figure 3B The BL stress of the memory shown ensures the performance of the memory product. The execution order of the two steps is not fixed and can be flexibly determined according to the application scenario.

[0060] Please note, such as Figure 3A or Figure 3BEach memory array slice is shown as having 8 bit lines, but this is only an abbreviated representation; in reality, each memory array slice has a much larger number of bit lines.

[0061] The following illustrations and explanations will all use N=65. Please adapt the interpretation to cases where N is an even number or takes other values.

[0062] Please see Figure 4 There are read amplification modules distributed between every two storage array chips, and the read amplification modules are numbered along the first direction, that is, the read amplification modules are numbered sequentially along the first direction as 12_1, 12_2...12_64.

[0063] The readout amplification module includes multiple sensitive amplifiers Sa arranged sequentially along the second direction. For example... Figure 5 As shown, each sensitive amplifier Sa includes a first transistor 21, a second transistor 22, a third transistor 23, and a fourth transistor 24 that are cross-coupled. The source of the first transistor 21 and the drain of the third transistor 23 are both connected to the second complementary bit line SaBlb. The source of the second transistor 22 and the drain of the fourth transistor 24 are both connected to the first complementary bit line saBLa. The gate of the third transistor 23 is connected to the first bit line BLa, and the gate of the fourth transistor 24 is connected to the second bit line BLb. In addition, NCS refers to the pull-down module and PCS refers to the pull-up module. This part does not affect the understanding of the present disclosure and will not be explained further.

[0064] Please see Figure 5 The first end of the sensitive amplifier Sa is connected to a second bit line BLb on the third side (e.g., above) through the first debiasing switch 31, and the second end of the sensitive amplifier Sa is connected to a second bit line BLb on the third side through the first isolation switch 32.

[0065] The second end of the sensitive amplifier Sa is also connected to a first line BLa on the fourth side (e.g., below) via a second debias switch 33, and the first end of the sensitive amplifier Sa is also connected to a first line BLa on the fourth side via a second isolation switch 34.

[0066] Here, the first debiasing switch 31, the second debiasing switch 33, the first isolation switch 32, and the second isolation switch 34 are all transistors. The gates of the first debiasing switch 31 and the second debiasing switch 33 each receive the debiasing signal OcEn, and the gates of the first isolation switch 32 and the second isolation switch 34 each receive the isolation signal Iso.

[0067] It should be noted that, as Figure 5 As shown, the first or second terminal of the sensitive amplifier Sa is also connected to the pre-charge power source VAD via a pre-charge switch 35. Specifically, in Figure 5In this embodiment, the precharge switch 35 is located on the side of the second bit line BLb, specifically connected to the first terminal of the sensitive amplifier Sa, but this does not constitute a specific limitation. In other embodiments, the precharge switch 35 may also be located on the side of the first bit line BLa, specifically connected to the second terminal of the sensitive amplifier Sa.

[0068] Please refer to Figure 6 In the first specific embodiment, for the odd-numbered readout amplification modules (12_1, 12_3...12_63), the first or second end of the sensitive amplifier Sa is also connected to the first power supply terminal VAD2O via a precharge switch 35; for the even-numbered readout amplification modules (12_2, 12_4...12_64), the first or second end of the sensitive amplifier Sa is also connected to the second power supply terminal VAD2E via a precharge switch 35.

[0069] It should be noted that, in Figure 6 In this process, for each readout amplification module, the second terminal of the odd-numbered sensitive amplifier 40o is connected to the corresponding power supply terminal through the precharge switch 35, and the first terminal of the even-numbered sensitive amplifier 40e is connected to the corresponding power supply terminal through the precharge switch 35. However, this does not constitute a restriction, as long as the precharge source corresponding to the sensitive amplifier Sa in the odd-numbered readout amplification module is the first power supply terminal VAD2O, and the precharge source corresponding to the sensitive amplifier Sa in the even-numbered readout amplification module is the first power supply terminal VAD2E.

[0070] based on Figure 6 The structure of the memory 10 and the process of performing BL stress on the non-edge memory array slices are as follows:

[0071] The memory 10 is specifically configured to, in one step, turn off all sensitive amplifiers Sa, control the first power supply terminal VAD2O to the first voltage value and the second power supply terminal VAD2E to the second voltage value, and perform a regular pre-charge operation; in the regular pre-charge operation, all pre-charge switches 35, isolation switches and de-bias switches are in the on state; and, after a preset time (the specific value can be determined according to the actual application scenario), control the first power supply terminal VAD2O to the second voltage value and the second power supply terminal VAD2E to the first voltage value, and perform a regular pre-charge operation.

[0072] Here, the first voltage value and the second voltage value are different. For example, the first voltage value is high and the second voltage value is low, or the first voltage value is low and the second voltage value is high.

[0073] based on Figure 6 The structure shown below will be explained in detail below, taking the first voltage value as high level and the second voltage value as low level as an example.

[0074] First, control the first power supply terminal VAD2O to a high level (e.g., 1.55V) and the second power supply terminal VAD2E to a low level (e.g., 0V). The result of a normal pre-charge operation at this time is:

[0075] (1) For memory array chip 11_1, all the first bit lines and the second bit lines connected to them are at a high level (precharged by VAD2O);

[0076] (2) For memory array chip 11_65, all first bit lines and their connected second bit lines are at low level (precharged by VAD2E);

[0077] (3) For non-edge and odd-numbered memory array chips (e.g., memory array chips 11_3, 11_5...11_63), the first bit line BLa is low (precharged by VAD2E), and the second bit line BLb is high (precharged by VAD2O).

[0078] (4) For non-edge and even-numbered memory array chips (e.g., memory array chips 11_2, 11_4...11_64), the first bit line BLa is high (precharged by VAD2O), and the second bit line BLb is low (precharged by VAD2E).

[0079] That is, this step can only make adjacent bit lines in memory array slices that are not at the beginning or end of the array have different voltage values.

[0080] Secondly, by controlling the first power supply terminal VAD2O to be low and the second power supply terminal VAD2E to be high, the result of the normal pre-charge operation is as follows:

[0081] (5) For memory array chip 11_1, all the first bit lines and the second bit lines connected to them are low (precharged by VAD2O);

[0082] (6) For memory array chip 11_65, all first bit lines and their connected second bit lines are at high level (precharged by VAD2E);

[0083] (7) For non-edge and odd-numbered memory array chips (e.g., memory array chips 11_3, 11_5...11_63), the first bit line BLa is high (precharged by VAD2E), and the second bit line BLb is low (precharged by VAD2O).

[0084] (8) For non-edge and even-numbered memory array chips (e.g., memory array chips 11_2, 11_4...11_64), the first bit line BLa is low (precharged by VAD2O), and the second bit line BLb is high (precharged by VAD2E).

[0085] Similarly, this step can only make adjacent bit lines in memory array slices that are not at the beginning or end of the array have different voltage values.

[0086] In this way, by following the above steps, the BL Stress of the memory array slices that are not at the beginning or end can be completed.

[0087] It should also be noted that for the first and last memory array slices, since their two bit lines are combined into a single bit line, each operation must target a pair of memory cells, not a single memory cell. Specifically, each of the first and last memory array slices includes multiple twin cells. A twin cell consists of two memory cells storing the same data. Both memory cells are electrically connected to the same word line, and there is an electrical connection between the corresponding bit lines of the two memory cells. The twin cells perform data reading and writing simultaneously. For ease of explanation, the twin cells of each memory array slice at the first and last positions are numbered along the second direction.

[0088] In another step, the memory 10 performs BL stress on the edge memory array slices as follows:

[0089] The memory 10 is further configured to, in another step, only activate the sensitive amplifiers Sa adjacent to the first and last memory array slices, write first data to the odd-numbered double sub-cells and write second data to the even-numbered double sub-cells, such that the voltage of the first bit line of the odd-numbered cell and its connected second bit line is a first voltage value, and the voltage of the first bit line of the even-numbered cell and its connected second bit line is a second voltage value; and, after a preset time period, write the second data to the odd-numbered double sub-cells and write the first data to the even-numbered double sub-cells, such that the voltage of the first bit line of the odd-numbered cell and its connected second bit line is a second voltage value, and the voltage of the first bit line of the even-numbered cell and its connected second bit line is a first voltage value. The first data and the second data are different.

[0090] It should be understood that during a write operation, all isolating switches, precharge switches, and debias switches are turned off, and the data to be written is transmitted to the corresponding bit line via the local data line (LIO).

[0091] Taking the first data as 1 and the second data as 0 as an example, it can be seen that for the memory array slices at the first and last positions, when writing 1 to the odd-numbered double sub-cell and writing 0 to the even-numbered double sub-cell, the first bit line BLao of the odd-numbered slice and its connected second bit line BLbo are at a high level, and the first bit line BLae of the even-numbered slice and its connected second bit line BLbe are at a low level; conversely, when writing 0 to the odd-numbered double sub-cell and writing 1 to the even-numbered double sub-cell, the first bit line BLao of the odd-numbered slice and its connected second bit line BLbo are at a low level, and the first bit line BLae of the even-numbered slice and its connected second bit line BLbe are at a high level; thus completing the BL stress of the memory array slices at the first and last positions.

[0092] In this way, BL stress is applied to the memory array slices at non-first and last positions and the first and last positions respectively through two steps to achieve the corresponding test results.

[0093] In a second specific embodiment, another specific structure of the memory 10 is provided. See also... Figure 7 For the odd-numbered readout amplifier modules (12_1, 12_3...12_63), the second end of the odd-numbered sensitive amplifier 40o is connected to the third power supply terminal VAD2Oa through the precharge switch 35, and the first end of the even-numbered sensitive amplifier 40e is connected to the fourth power supply terminal VAD2Ob through the precharge switch 35.

[0094] For the even-numbered readout amplifier modules (12_2, 12_4...12_64), the second terminal of the odd-numbered sensitive amplifier 40o is connected to the fifth power supply terminal VAD2Ea via a precharge switch 35, and the first terminal of the even-numbered sensitive amplifier 40e is connected to the sixth power supply terminal VAD2Eb via a precharge switch 35.

[0095] based on Figure 7 The structure of the memory 10 and the process of performing BL stress on the non-edge memory array slices are as follows:

[0096] The memory 10 is specifically configured to, in one step, turn off all sensitive amplifiers Sa, control the third power supply terminal VAD2Oa and the fourth power supply terminal VAD2Ob to both be at the first voltage value, and control the fifth power supply terminal VAD2Ea and the sixth power supply terminal VAD2Eb to both be at the second voltage value; and perform a normal pre-charge operation; and, after a preset time, control the third power supply terminal VAD2Oa and the fourth power supply terminal VAD2Ob to both be at the second voltage value, and control the fifth power supply terminal VAD2Ea and the sixth power supply terminal VAD2Eb to both be at the first voltage value; and perform a normal pre-charge operation.

[0097] In simple terms, the pre-charge source for the sensitive amplifier Sa in the memory is divided into 4 groups, thereby enabling more flexible pre-charge operations.

[0098] The above steps will be explained in detail below, taking the first voltage value as high level and the second voltage value as low level as an example.

[0099] First, control the third power supply terminal VAD2Oa to be high (e.g., 1.55V) and the fifth power supply terminal VAD2Ea to be low (e.g., 0V) and the sixth power supply terminal VAD2Eb to be low. At this time,

[0100] (1) For memory array chip 11_1, all the first bit lines and the second bit lines connected to them are high (precharged by VAD2Oa or VAD2Ob);

[0101] (2) For memory array chip 11_65, all first bit lines and their connected second bit lines are low (precharged by VAD2Ea or VAD2Eb);

[0102] (3) For non-edge and odd-numbered memory array chips (e.g., memory array chips 11_3, 11_5...11_63), the first bit line BLa is low (precharged by VAD2Ea or VAD2Eb), and the second bit line BLb is high (precharged by VAD2Oa or VAD2Ob).

[0103] (4) For non-edge and even-numbered memory array chips (e.g., memory array chips 11_2, 11_4...11_64), the first bit line BLa is high (precharged by VAD2Oa or VAD2Ob), and the second bit line BLb is low (precharged by VAD2Ea or VAD2Eb).

[0104] That is, this step can only make adjacent bit lines in memory array slices that are not at the beginning or end of the array have different voltage values.

[0105] Secondly, controlling the third power supply terminal VAD2Oa = the fourth power supply terminal VAD2Ob to be low, and the fifth power supply terminal VAD2Ea = the sixth power supply terminal VAD2Eb to be high, will result in the following during normal pre-charge operation:

[0106] (1) For memory array chip 11_1, all the first bit lines and the second bit lines connected to them are low (precharged by VAD2Oa or VAD2Ob);

[0107] (2) For memory array chip 11_65, all first bit lines and their connected second bit lines are high (precharged by VAD2Ea or VAD2Eb);

[0108] (3) For non-edge and odd-numbered memory array chips (e.g., memory array chips 11_3, 11_5...11_63), the first bit line BLa is high (precharged by VAD2Ea or VAD2Eb), and the second bit line BLb is low (precharged by VAD2Oa or VAD2Ob).

[0109] (4) For non-edge-positioned and even-numbered memory array chips (e.g., memory array chips 11_2, 11_4...11_64), the first bit line BL1 is always low (pre-charged by VAD2Oa or VAD2Ob), and the second bit line BL2 is always high (pre-charged by VAD2Ea or VAD2Eb). Similarly, this step can only make adjacent bit lines in memory array chips that are not at the beginning or end positions have different voltage values.

[0110] In this way, by following the above steps, the BL Stress of the memory array slices that are not at the beginning or end can be completed.

[0111] based on Figure 7 The structure of the memory 10 and the process of performing BL stress on the memory array slices at the beginning and end positions are as follows:

[0112] The memory 10 is specifically configured to, in another step, turn off all sensitive amplifiers Sa, control the third power supply terminal VAD2Oa and the fifth power supply terminal VAD2Ea to both be at the first voltage value, and control the fourth power supply terminal VAD2Ob and the sixth power supply terminal VAD2Eb to be at the second voltage value; and perform a normal pre-charge operation; and, after a preset time, control the third power supply terminal VAD2Oa and the fifth power supply terminal VAD2Ea to both be at the second voltage value, and control the fourth power supply terminal VAD2Ob and the sixth power supply terminal VAD2Eb to be at the first voltage value; and perform a normal pre-charge operation.

[0113] The above steps will be explained in detail below, taking the first voltage value as high level and the second voltage value as low level as an example.

[0114] First, control the third power supply terminal VAD2Oa = the fifth power supply terminal VAD2Ea to be at a high level, and the fourth power supply terminal VAD2Ob = the sixth power supply terminal VAD2Eb to be at a low level. The result of the normal pre-charge operation at this time is:

[0115] (1) For memory array chip 11_1, the first bit line BLao of the odd number and its connected second bit line BLbo are both high level (precharged by VAD2Oa), and the first bit line BLae of the even number and its connected second bit line BLbe are both low level (precharged by VAD2Ob).

[0116] (2) For memory array chip 11_65, the first bit line BLao of the odd number and its connected second bit line BLbo are both high level (precharged by VAD2Ea), and the first bit line BLae of the even number and its connected second bit line BLbe are both low level (precharged by VAD2Eb).

[0117] (3) For non-edge and odd-numbered memory array chips (e.g., memory array chips 11_3, 11_5...11_63), the first bit line BLao of the odd number is high (precharged by VAD2Ea), the second bit line BLbo of the odd number is high (precharged by VAD2Oa), the first bit line BLae of the even number is low (precharged by VAD2Eb), and the second bit line BLbe of the even number is low (precharged by VAD2Ob).

[0118] (4) For non-edge and even-numbered memory array chips (e.g., memory array chips 11_2, 11_4...11_64), the first bit line BLao of the odd number is high (precharged by VAD2Oa), the second bit line BLbo of the odd number is high (precharged by VAD2Ea), the first bit line BLae of the even number is low (precharged by VAD2Ob), and the second bit line BLbe of the even number is low (precharged by VAD2Eb).

[0119] That is, in this step, only adjacent bit lines in the memory array at the beginning and end positions can be made to have different voltage values.

[0120] Secondly, control the third power supply terminal VAD2Oa = the fifth power supply terminal VAD2Ea = low level, and the fourth power supply terminal VAD2Ob = the sixth power supply terminal VAD2Eb = high level. The result of the normal pre-charge operation at this time is:

[0121] (5) For memory array chip 11_1, the first bit line BLao of the odd number and its connected second bit line BLbo are both low level (precharged by VAD2Oa), and the first bit line BLae of the even number and its connected second bit line BLbe are both high level (precharged by VAD2Ob).

[0122] (6) For memory array chip 11_65, the first bit line BLao of the odd number and its connected second bit line BLbo are both low level (precharged by VAD2Ea), and the first bit line BLae of the even number and its connected second bit line BLbe are both high level (precharged by VAD2Eb).

[0123] (7) For non-edge and odd-numbered memory array chips (e.g., memory array chips 11_3, 11_5...11_63), the first bit line BLao of the odd number is low (precharged by VAD2Ea), the second bit line BLbo of the odd number is low (precharged by VAD2Oa), the first bit line BLae of the even number is high (precharged by VAD2Eb), and the second bit line BLbe of the even number is high (precharged by VAD2Ob).

[0124] (8) For non-edge and even-numbered memory array chips (e.g., memory array chips 11_2, 11_4...11_64), the first bit line BLao of the odd number is low (precharged by VAD2Oa), the second bit line BLbo of the odd number is low (precharged by VAD2Ea), the first bit line BLae of the even number is high (precharged by VAD2Ob), and the second bit line BLbe of the even number is high (precharged by VAD2Eb).

[0125] Similarly, in this step, only adjacent bit lines in the memory array at the beginning and end positions can be made to have different voltage values.

[0126] In short, by dividing the pre-charge source of the sensitive amplifier Sa into 4 groups, the BL stress test of all memory array chips can be completed through pre-charge operation alone, making the test procedure simpler.

[0127] However, in the above testing steps, during the BL stress test on memory array chips that are not at the beginning or end, the bit lines in the memory array chips at the beginning and end are also pre-charged; during the BL stress test on memory array chips at the beginning and end, the bit lines in the memory array chips that are not at the beginning or end are also pre-charged, resulting in wasted energy and overcharging. To further address this issue, the embodiments of this disclosure target... Figure 7 The memory 10 structure shown also provides the following test methods:

[0128] based on Figure 7 The structure of the memory 10 and the process of performing BL stress on the non-edge memory array slices are as follows:

[0129] The memory 10 is specifically configured as follows: in one step, all sensitive amplifiers Sa are turned off, the third power supply terminal VAD2Oa and the fourth power supply terminal VAD2Ob are controlled to be at the first voltage value, and the fifth power supply terminal VAD2Ea and the sixth power supply terminal VAD2Eb are at the second voltage value; and a first test pre-charge operation is performed; and after a preset time, the third power supply terminal VAD2Oa and the fourth power supply terminal VAD2Ob are controlled to be at the second voltage value, and the fifth power supply terminal VAD2Ea and the sixth power supply terminal VAD2Eb are at the first voltage value; and the first test pre-charge operation is performed; wherein, in the first test pre-charge operation, the isolation switches and debias switches between the readout amplification modules at the beginning and end positions and the memory array chips at the beginning and end positions are all in the off state, and all other pre-charge switches, isolation switches and debias switches are in the on state.

[0130] The above steps will be explained in detail below, taking the first voltage value as high level and the second voltage value as low level as an example.

[0131] First, control the third power supply terminal VAD2Oa = the fourth power supply terminal VAD2Ob to be at a high level, and the fifth power supply terminal VAD2Ea = the sixth power supply terminal VAD2Eb to be at a low level. Also, the isolation switch and debias switch between the readout amplifier module 12_1 (the sensitive amplifier Sa in it) and the storage array chip 11_1 are both in the off state, and the isolation switch and debias switch between the readout amplifier module 12_64 (the sensitive amplifier Sa in it) and the storage array chip 11_65 are both in the off state. All other precharge switches, isolation switches and debias switches are in the on state.

[0132] The result of the first pre-charge test at this time is:

[0133] (1) For memory array chip 11_1 and memory array chip 11_65, since the bit lines therein are electrically isolated from the sensitive amplifier Sa, the bit lines therein will not be precharged;

[0134] (2) For non-edge and odd-numbered memory array chips (e.g., memory array chips 11_3, 11_5...11_63), the first bit line BLa is low (precharged by VAD2Ea or VAD2Eb), and the second bit line BLb is high (precharged by VAD2Oa or VAD2Ob).

[0135] (3) For non-edge and even-numbered memory array chips (e.g., memory array chips 11_2, 11_4...11_64), the first bit line BLa is high (precharged by VAD2Oa or VAD2Ob), and the second bit line BLb is low (precharged by VAD2Ea or VAD2Eb).

[0136] That is, this step can only make adjacent bit lines in memory array slices that are not at the beginning or end of the array have different voltage values.

[0137] Secondly, the third power supply terminal VAD2Oa = the fourth power supply terminal VAD2Ob = low level, and the fifth power supply terminal VAD2Ea = the sixth power supply terminal VAD2Eb = high level. Similarly, the isolation switch and debiasing switch between the readout amplifier module 12_1 (sensitive amplifier Sa in it) and the storage array chip 11_1 are both in the off state, and the isolation switch and debiasing switch between the readout amplifier module 12_64 (sensitive amplifier Sa in it) and the storage array chip 11_65 are both in the off state. All other precharge switches, isolation switches and debiasing switches are in the on state.

[0138] The result of the first pre-charge test at this time is:

[0139] (4) For memory array chip 11_1 and memory array chip 11_65, since the bit lines are electrically isolated from the sensitive amplifier Sa, the bit lines are not precharged.

[0140] (5) For non-edge and odd-numbered memory array chips (e.g., memory array chips 11_3, 11_5...11_63), the first bit line BLa is high (precharged by VAD2Ea or VAD2Eb), and the second bit line BLb is low (precharged by VAD2Oa or VAD2Ob).

[0141] (6) For non-edge and even-numbered memory array chips (e.g., memory array chips 11_2, 11_4...11_64), the first bit line BLa is low (precharged by VAD2Oa or VAD2Ob), and the second bit line BLb is high (precharged by VAD2Ea or VAD2Eb).

[0142] That is, this step can only make adjacent bit lines in memory array slices that are not at the beginning or end of the array have different voltage values.

[0143] In this way, by following the above steps, the BL Stress of the memory array slices that are not at the beginning or end can be completed.

[0144] In another step, the memory 10 performs BL stress on the edge memory array slices as follows:

[0145] The memory 10 is specifically configured such that, in another step, all sensitive amplifiers Sa are turned off, the third power supply terminal VAD2Oa and the fifth power supply terminal VAD2Ea are both controlled to be at the first voltage value, and the fourth power supply terminal VAD2Ob and the sixth power supply terminal VAD2Eb are at the second voltage value; and a second test pre-charge operation is performed; and, after a preset time, the third power supply terminal VAD2Oa and the fifth power supply terminal VAD2Ea are controlled to be at the second voltage value, and the fourth power supply terminal VAD2Ob and the sixth power supply terminal VAD2Eb are at the first voltage value; and a second test pre-charge operation is performed; wherein, in the second test pre-charge operation, the isolation switches and de-bias switches between the readout amplification modules at the beginning and end positions and the memory array chips at the beginning and end positions are both in the open state, and the isolation switches and de-bias switches between the readout amplification modules at the beginning and end positions and the memory array chips at other positions are both in the closed state; the pre-charge switches 35 of the readout amplification modules at the beginning and end positions are both in the open state, and the pre-charge switches 35 of the remaining readout amplification modules are both in the closed state.

[0146] It should be noted that the precharge switch 35 in the non-first and last readout amplifier modules is closed, meaning that this part of the sensitive amplifier Sa will not be precharged. Therefore, the isolation switch / debias switch between the non-first and last readout amplifier modules and the adjacent memory array chips can be either on or off.

[0147] The following example illustrates the above steps in detail, using a first voltage value of high level (e.g., 1.55V) and a second voltage value of low level (e.g., 0V).

[0148] First, the third power supply terminal VAD2Oa and the fifth power supply terminal VAD2Ea are both set to high level, and the fourth power supply terminal VAD2Ob and the sixth power supply terminal VAD2Eb are set to low level. Simultaneously, the isolation switch and debiasing switch between the read amplifier module 12_1 and the storage array chip 11_1 are both on, and the isolation switch and debiasing switch between the read amplifier module 12_64 and the storage array chip 11_65 are both on. However, the isolation switch and debiasing switch between the read amplifier module 12_1 and the storage array chip 11_2 are both off, and the isolation switch and debiasing switch between the read amplifier module 12_64 and the storage array chip 11_64 are both off. At the same time, the precharge switches 35 corresponding to the read amplifier modules 12_1 and 12_64 are both on, but the precharge switches 35 corresponding to the read amplifier modules 12_2 to 12_63 are all off.

[0149] The result of the second pre-charge test at this time is:

[0150] (1) For memory array chip 11_1, the first bit line BLao of the odd number and its connected second bit line BLbo are both high level (precharged by VAD2Oa), and the first bit line BLae of the even number and its connected second bit line BLbe are both low level (precharged by VAD2Ob).

[0151] (2) For memory array chip 11_65, the first bit line BLao of the odd number and its connected second bit line BLbo are both high level (precharged by VAD2Ea), and the first bit line BLae of the even number and its connected second bit line BLbe are both low level (precharged by VAD2Eb).

[0152] (3) For memory array chips that are not at the beginning or end, firstly, for memory array chips 11_3 to 11_63, their adjacent Sa will not be precharged (precharge switch is off), so the bit lines therein will not be precharged either; secondly, for memory array chip 11_2, although the read amplifier module 12_1 on one side will be precharged, the bit lines therein are electrically isolated from the Sa in the read amplifier module 12_1 (isolation switch and debias switch are off), so they will not be precharged either; for memory array chip 11_64, although the read amplifier module 12_64 on one side will be precharged, the bit lines therein are electrically isolated from the Sa in the read amplifier module 12_64 (isolation switch and debias switch are off), so they will not be precharged either.

[0153] Secondly, the third power supply terminal VAD2Oa and the fifth power supply terminal VAD2Ea are controlled to be at a low level, and the fourth power supply terminal VAD2Ob and the sixth power supply terminal VAD2Eb are controlled to be at a high level. At the same time, the isolation switch and debiasing switch between the read amplifier module 12_1 and the storage array chip 11_1 are both in the open state, and the isolation switch and debiasing switch between the read amplifier module 12_64 and the storage array chip 11_65 are both in the open state. However, the isolation switch and debiasing switch between the read amplifier module 12_1 and the storage array chip 11_2 are both in the closed state, and the isolation switch and debiasing switch between the read amplifier module 12_64 and the storage array chip 11_64 are both in the closed state. At the same time, the precharge switches 35 corresponding to the read amplifier modules 12_1 and 12_64 are both in the open state, but the precharge switches 35 corresponding to the read amplifier modules 12_2 to 12_63 are both in the closed state.

[0154] The result of the second pre-charge test at this time is:

[0155] (1) For memory array chip 11_1, the first bit line BLao of the odd number and its connected second bit line BLbo are both low level (precharged by VAD2Oa), and the first bit line BLae of the even number and its connected second bit line BLbe are both high level (precharged by VAD2Ob).

[0156] (2) For memory array chip 11_65, the first bit line BLao of the odd number and its connected second bit line BLbo are both low level (precharged by VAD2Ea), and the first bit line BLae of the even number and its connected second bit line BLbe are both high level (precharged by VAD2Eb).

[0157] (3) For memory array chips that are not at the beginning or end, firstly, for memory array chips 11_3 to 11_63, their adjacent Sa will not be precharged (precharge switch is off), so the bit lines therein will not be precharged either; secondly, for memory array chip 11_2, although the read amplifier module 12_1 on one side will be precharged, the bit lines therein are electrically isolated from the Sa in the read amplifier module 12_1 (isolation switch and debias switch are off), so they will not be precharged either; for memory array chip 11_64, although the read amplifier module 12_64 on one side will be precharged, the bit lines therein are electrically isolated from the Sa in the read amplifier module 12_64 (isolation switch and debias switch are off), so they will not be precharged either.

[0158] Similarly, in this step, only adjacent bit lines in the memory array at the beginning and end positions can be made to have different voltage values.

[0159] In short, by precharging only the memory array chips at the beginning and end or only the memory array chips in the inner positions, the problem of over-precharging can be avoided. This allows for better completion of the BLstress test for all memory array chips, while saving power and avoiding over-stress.

[0160] To implement the above testing method, please refer to [link / reference]. Figure 8 The gate of the first debiasing switch 31 and the gate of the second debiasing switch 33 receive control signals OcEnb and OcEna, respectively, and the gate of the first isolation switch 32 and the gate of the second isolation switch 34 receive control signals Isob and Isoa, respectively.

[0161] For Figure 7The readout amplification module 12-1 is connected to the memory array chip 11-1 via the first debias switch 31 and the first isolation switch 32, while the readout amplification module 12-64 is connected to the memory array chip 11-65 via the second debias switch 33 and the second isolation switch 34. To facilitate the above testing method, in a specific embodiment, by changing certain definitions (e.g., changing the definitions of the first and second bit lines in the last and second-to-last memory array chip, or changing the definitions of the debias switches and isolation switches in the readout amplification module 12-64), the readout amplification module 12-64 is also connected to the memory array chip 11-65 via the first debias switch 31 and the first isolation switch 32. Therefore, by simply turning off the first debias switches 31 and 32 corresponding to the readout amplification module 12-1 and the readout amplification module 12-64, the memory array chips at the beginning and end positions can be electrically isolated from the adjacent sensitive amplifier Sa.

[0162] At this time, memory 10 also includes:

[0163] The control circuit is configured to generate a valid initial isolation signal IsoPre and a valid initial debiasing signal OcPre when the memory 10 is instructed to perform a precharge operation; and to generate an invalid initial isolation signal IsoPre and an invalid initial debiasing signal OcPre when the memory 10 is not instructed to perform a precharge operation; wherein the first test precharge operation, the second test precharge operation, and the normal precharge operation are all precharge operations.

[0164] The first preprocessing circuit 50 is configured to generate a first edge isolation signal IsobEdge and a second edge isolation signal IsoaEdge based on the edge test parameter set and the initial isolation signal IsoPre; and to generate a first edge depolarization signal OcEnbEdge and a second edge depolarization signal OcEnaEdge based on the edge test parameter set and the initial depolarization signal OcPre.

[0165] The second preprocessing circuit 60 is configured to generate a first internal isolation signal IsobInter and a second internal isolation signal IsoaInter based on the internal test parameter set and the initial isolation signal IsoPre; and to generate a first internal depolarization signal OcEnbInter and a second internal depolarization signal OcEnaInter based on the internal test parameter set and the initial depolarization signal OcPre.

[0166] Wherein, (1) the first edge isolation signal IsobEdge is used to control the first isolation switch 32 between the read amplification module at the beginning and end positions and the memory array chip at the beginning and end positions, that is, IsobEdge can be regarded as the Isob between the read amplification module at the beginning and end positions and the memory array chip at the beginning and end positions; (2) the second edge isolation signal IsoaEdge is used to control the second isolation switch 34 between the read amplification module at the beginning and end positions and the memory array chip at the non-beginning and end positions, that is, as IsoaEdge can be regarded as the Iso between the read amplification module at the beginning and end positions and the memory array chip at the non-beginning and end positions. a);(3) The first edge debiasing signal OcEnbEdge is used to control the first debiasing switch 31 between the read amplification module at the beginning and end positions and the memory array chip at the beginning and end positions. That is, OcEnbEdge can be regarded as the OcEnb between the read amplification module at the beginning and end positions and the memory array chip at the beginning and end positions; (4) The second edge debiasing signal OcEnaEdge is used to control the second debiasing switch 33 between the read amplification module at the beginning and end positions and the memory array chip at the non-beginning and end positions. That is, OcEnaEdge can be regarded as the OcEnb between the read amplification module at the beginning and end positions and the memory array chip at the non-beginning and end positions. cEna; (5) The first internal isolation signal IsobInter is used to control the first isolation switch 32 between the read amplification module at the non-first and last position and the adjacent memory array chip, that is, IsobInter can be regarded as Isob between the read amplification module at the non-first and last position and the adjacent memory array chip; (6) The second internal isolation signal IsoaInter is used to control the second isolation switch 34 between the read amplification module at the non-first and last position and the adjacent memory array chip, that is, IsoaInter can be regarded as Isoa between the read amplification module at the non-first and last position and the adjacent memory array chip; (7) The first internal debiasing signal OcEnbInter is used to control the first debiasing switch 31 between the read amplification module at the non-first and last position and the adjacent memory array chip. That is, OcEnbInter can be regarded as OcEnb between the read amplification module at the non-first and last position and the adjacent memory array chip; (8) The second internal debiasing signal OcEnaInter is used to control the second debiasing switch 33 between the read amplification module at the non-first and last position and the adjacent memory array chip. That is, OcEnaInter can be regarded as OcEna between the read amplification module at the non-first and last position and the adjacent memory array chip.

[0167] In this way, by introducing additional preprocessing circuitry to distinguish between the regular precharge operation, the first test precharge operation, and the second test precharge operation, the bit lines in the memory array chips that are not at the beginning or end are precharged only in the first test precharge operation, and the bit lines in the memory array chips that are at the beginning or end are precharged only in the second test precharge operation. This saves energy and avoids the problems of bit line overcharging and excessive pressure.

[0168] In some embodiments, the edge test parameter set includes at least a first test parameter TmEdge. <0> The second test parameter, TmEdge <1> The internal test parameter set includes at least the third test parameter TmInter. <0> and the fourth test parameter TmInter <1> .

[0169] If the test parameter group indicates that this pre-charge operation is a regular pre-charge operation, then the first test parameter TmEdge <0> The second test parameter, TmEdge <1> The third test parameter TmInter <0> The fourth test parameter, TmInter <1> All are in the first state; if the test parameter group indicates that this pre-charge operation is the first test pre-charge operation, then the second test parameter TmEdge <1> For the second state, the first test parameter is TmEdge. <0> The third test parameter TmInter <0> and the fourth test parameter TmInter <1> All are in the first state; if the test parameter group indicates that this pre-charge operation is the second test pre-charge operation, then the first test parameter TmEdge <0> It is the second state, and the second test parameter TmEdge <1> The third test parameter TmInter <0> The fourth test parameter, TmInter <1> All are in the first state;

[0170] If the second test parameter TmEdge <1> In the first state, the levels of the first edge isolation signal IsobEdge and the first edge depolarization signal OcEnbEdge are the same as those of the initial isolation signal IsoPre and the initial depolarization signal OcPre; if the second test parameter TmEdge <1> In the second state, both the first edge isolation signal IsobEdge and the first edge depolarization signal OcEnbEdge are invalid.

[0171] If the first test parameter TmEdge <0> In the first state, the second edge isolation signal IsoaEdge and the second edge depolarization signal OcEnaEdge correspond one-to-one with the levels of the initial isolation signal IsoPre and the initial depolarization signal OcPre; if the first test parameter TmEdge <0> In the second state, both the second edge isolation signal IsoaEdge and the second edge depolarization signal OcEnaEdge are invalid.

[0172] If the fourth test parameter TmInter <1> In the first state, the levels of the first internal isolation signal IsobInter and the first internal debiasing signal OcEnbInter are the same as those of the initial isolation signal IsoPre and the initial debiasing signal OcPre; if the fourth test parameter TmInter <1> In the second state, both the first internal isolation signal IsobInter and the first internal debiasing signal OcEnbInter are invalid.

[0173] If the third test parameter TmInter <0> In the first state, the second internal isolation signal IsoaInter and the second internal depolarization signal OcEnaInter correspond one-to-one with the levels of the initial isolation signal IsoPre and the initial depolarization signal OcPre; if the third test parameter TmInter <0> In the second state, both the second internal isolation signal IsoaInter and the second internal debiasing signal OcEnaInter are invalid.

[0174] It should be noted that for the isolation signal, depolarization signal, and precharge signal mentioned above, when they are invalid, the corresponding switch is in the off state; when they are valid, the corresponding switch is in the on state.

[0175] In some embodiments, see Figure 9 The first state is high level, and the second state is low level. Valid means the signal is high level, and invalid means the signal is low level. The first preprocessing circuit 50 includes:

[0176] The first AND gate 501 receives the first test parameter TmEdge at its two inputs. <0> The initial isolation signal IsoPre is output, and the second edge isolation signal IsoaEdge is output from its output terminal; the second AND gate 502 receives the second test parameter TmEdge from its two input terminals respectively. <1> The initial isolation signal IsoPre is output, and its output terminal outputs the first edge isolation signal IsobEdge; the third AND gate 503 receives the first test parameter TmEdge at its two input terminals respectively. <0> The initial depolarization signal OcPre is output, and the second edge depolarization signal OcEnaEdge is output from its output terminal; the fourth AND gate 504 receives the second test parameter TmEdge from its two input terminals respectively. <1> And the initial depolarization signal OcPre, its output terminal outputs the first edge depolarization signal OcEnbEdge;

[0177] The second preprocessing circuit 60 includes:

[0178] The fifth AND gate 601 receives the third test parameter TmInter at its two inputs. <0> The initial isolation signal IsoPre is output, and its output terminal outputs the second internal isolation signal IsoaInter; the sixth AND gate 602 receives the fourth test parameter TmInter at its two input terminals respectively. <1> The initial isolation signal IsoPre is output, and its output terminal outputs the first internal isolation signal IsobInter; the seventh AND gate 603 receives the third test parameter TmInter at its two input terminals respectively. <0> The initial debiasing signal OcPre is output, and its output terminal outputs the second internal debiasing signal OcEnaInter; the eighth AND gate 604 receives the fourth test parameter TmInter at its two input terminals respectively. <1> The initial debiasing signal OcPre is used, and its output terminal outputs the first internal debiasing signal OcEnbInter.

[0179] In one specific embodiment, the first disconnect switch 32, the second disconnect switch 34, the first debiasing switch 31, and the second debiasing switch 33 are all N-type field-effect transistors; the following provides a detailed description of the conventional pre-charge operation, the first test pre-charge operation, and the second test pre-charge operation.

[0180] Specifically, (1) during the execution of the normal precharge operation, TmEdge<1:0>=11, TmInter<1:0>=11, therefore, the first edge isolation signal IsobEdge=the second edge isolation signal IsoaEdge=the first edge debiasing signal OcEnbEdge=the second edge debiasing signal OcEnaEdge=the first internal isolation signal IsobInter=the second internal isolation signal IsoaInter=the first internal debiasing signal OcEnbInter=the second internal debiasing signal OcEnaInter=1, so all the first isolation switches 32, the second isolation switches 34, the first debiasing switch 31, and the second debiasing switch 33 are turned on; thus, all bit lines can be precharged.

[0181] (2) During the execution of the first test precharge operation, TmEdge<1:0>=01, TmInter<1:0>=11. Therefore, the first edge isolation signal IsobEdge=the first edge depolarization signal OcEnbEdge=0, the second edge isolation signal IsoaEdge=the second edge depolarization signal OcEnaEdge=the first internal isolation signal IsobInter=the second internal isolation signal IsoaInter=the first internal depolarization signal OcEnbInter=the second internal depolarization signal Signal OcEnaInter = 1, thus the read amplifier module 12_1 is electrically isolated from the memory array chip 11_1, and the read amplifier module 12_64 is electrically isolated from the memory array chip 11_65. However, the read amplifier module 12_1 is electrically connected to the memory array chip 11_2, and the read amplifier module 12_64 is electrically connected to the memory array chip 11_64. The read amplifier modules 12_2 to 12_63 in the middle section are each electrically connected to the memory array chips on both sides. Therefore, only the bit lines in the memory array chip in the middle section are precharged.

[0182] (3) During the execution of the second test precharge operation, TmEdge<1:0>=10, TmInter<1:0>=11. Therefore, the first edge isolation signal IsobEdge=the first edge depolarization signal OcEnbEdge=the first internal isolation signal IsobInter=the second internal isolation signal IsoaInter=the first internal depolarization signal OcEnbInter=the second internal depolarization signal OcEnaInter=1, and the second edge isolation signal IsoaEdge=the second edge depolarization signal =0. Thus, the electrical connection between the amplification module 12_1 and the storage array chip 11_1 is read. The read amplifier module 12_64 is electrically connected to the memory array chip 11_65, but the read amplifier module 12_1 is electrically isolated from the memory array chip 11_2, and the read amplifier module 12_64 is electrically isolated from the memory array chip 11_64. On the other hand, although each of the read amplifier modules 12_2 to 12_63 is electrically connected to its adjacent memory array chips on both sides, the precharge switches in the read amplifier modules 12_1 to 12_64 are not activated. Therefore, the bit lines in the memory array chips adjacent to each of the read amplifier modules 12_1 to 12_64 are not precharged. Thus, only the bit lines in the first and last memory array chips are precharged.

[0183] Of course, in another embodiment, the readout amplification module 12_1 and the storage array chip 11_1 are connected by a first debias switch 31 and a first isolation switch 32, and the readout amplification module 12_65 and the storage array chip 11_64 are connected by a second debias switch 33 and a second isolation switch 34. Based on this, another structure of the first preprocessing circuit 50 is provided.

[0184] like Figure 10 As shown, the first preprocessing circuit 50 includes a first processing sub-circuit 51 and a second processing sub-circuit 52, and the edge test parameter group includes the head end parameter group TmEdge0<1:0> and the tail end parameter group TmEdge1<1:0>.

[0185] The first processing circuit 51 is configured to generate a first front-end isolation signal IsobEdge0 and a second front-end isolation signal IsoaEdge0 based on the front-end parameter group TmEdge0<1:0> and the initial isolation signal IsoPre; and to generate a first front-end debiasing signal OcEnbEdge0 and a second front-end debiasing signal OcEnaEdge0 based on the front-end parameter group and the initial debiasing signal OcPre.

[0186] The second processing circuit 52 is configured to generate a first tail-end isolation signal IsobEdge1 and a second tail-end isolation signal IsoaEdge1 based on the tail-end parameter group TmEdge1<1:0> and the initial isolation signal IsoPre; and to generate a first tail-end debiasing signal OcEnbEdge1 and a second tail-end debiasing signal OcEnaEdge1 based on the head-end parameter group and the initial debiasing signal OcPre.

[0187] Specifically, the first isolation switch 32, the second isolation switch 34, the first debiasing switch 31, and the second debiasing switch 33 between the first readout amplification module and the adjacent memory array chip are controlled by the first head-end isolation signal IsobEdge0, the second head-end isolation signal IsoaEdge0, the first head-end debiasing signal OcEnbEdge0, and the second head-end debiasing signal OcEnaEdge0, respectively; the first isolation switch 32, the second isolation switch 34, the first debiasing switch 31, and the second debiasing switch 33 between the last readout amplification module and the adjacent memory array chip are controlled by the first tail-end isolation signal IsobEdge1, the second tail-end isolation signal IsoaEdge1, the first tail-end debiasing signal OcEnbEdge1, and the second tail-end debiasing signal OcEnaEdge1, respectively.

[0188] Specifically, the first-end test parameter group includes the fifth test parameter TmEdge0. <0> And the sixth test parameter TmEdge0 <1> The tail end test parameter group includes the seventh test parameter TmEdge1 <0> And the eighth test parameter TmEdge1 <1> .

[0189] Correspondingly, such as Figure 10 As shown, the first processing sub-circuit 51 includes:

[0190] The ninth AND gate 511 receives the fifth test parameter TmEdge0 at its two inputs. <0> And the initial isolation signal IsoPre, its output terminal outputs the second initial isolation signal IsoaEdge0;

[0191] The tenth AND gate 512 receives the sixth test parameter TmEdge0 at its two inputs. <1> And the initial isolation signal IsoPre, its output terminal outputs the first initial isolation signal IsobEdge0;

[0192] The eleventh AND gate 513 receives the fifth test parameter TmEdge0 at its two inputs. <0> And the initial debiasing signal OcPre, its output terminal outputs the second initial debiasing signal OcEnaEdge0;

[0193] The twelfth AND gate 514 receives the sixth test parameter TmEdge0 at its two inputs. <1> The initial debiasing signal OcPre is used, and its output terminal outputs the first debiasing signal OcEnbEdge0.

[0194] The second processing sub-circuit 52 includes:

[0195] The thirteenth AND gate 521 receives the seventh test parameter TmEdge1 at its two inputs. <0> And the initial isolation signal IsoPre, its output terminal outputs the second tail isolation signal IsoaEdge1;

[0196] The fourteenth AND gate 522 receives the eighth test parameter TmEdge1 at its two inputs. <1> And the initial isolation signal IsoPre, its output terminal outputs the first tail isolation signal IsobEdge1;

[0197] The fifteenth AND gate 523 receives the seventh test parameter TmEdge1 at its two inputs. <0> And the initial debiasing signal OcPre, its output terminal outputs the second tail debiasing signal OcEnaEdge1;

[0198] The sixteenth AND gate 524 receives the eighth test parameter TmEdge1 at its two inputs. <1> The initial debiasing signal OcPre is used, and its output terminal outputs the first tail debiasing signal OcEnbEdge1.

[0199] Specifically, during the execution of the regular precharge operation, TmEdge0<1:0>=11, TmInter<1:0>=11, TmEdge0<1:0>=11, therefore, all the first isolation switches 32, the second isolation switches 34, the first debiasing switches 31, and the second debiasing switches 33 are turned on; thus, all bit lines can be precharged.

[0200] During the execution of the first test precharge operation, TmEdge0<1:0>=01, TmInter<1:0>=11, and TmEdge1<1:0>=10. Therefore, the read amplifier module 12_1 is electrically isolated from the memory array chip 11_1, and the read amplifier module 12_64 is electrically isolated from the memory array chip 11_65. However, the read amplifier module 12_1 is electrically connected to the memory array chip 11_2, and the read amplifier module 12_64 is electrically connected to the memory array chip 11_64. The read amplifier modules 12_2 to 12_63 are each electrically connected to the memory array chips on both sides. Thus, the bit lines in the memory array chips that are not at the beginning or end can be precharged.

[0201] During the execution of the second test precharge operation, TmEdge0<1:0>=10, TmInter<1:0>=11, and TmEdge1<1:0>=01, thus the read amplifier module 12_1 is electrically connected to the memory array chip 11_1, and the read amplifier module 12_64 is electrically connected to the memory array chip 11_65. However, the read amplifier module 12_1 is electrically isolated from the memory array chip 11_2, and the read amplifier module 12_64 is electrically isolated from the memory array chip 11_64. Each of the read amplifier modules 12_1 to 12_64 is electrically connected to the memory array chips on both sides. However, since the precharge switches in the read amplifier modules 12_2 to 12_63 are not turned on, the bit lines in the memory array chips adjacent to each of the read amplifier modules 12_2 to 12_63 are not precharged. Therefore, the bit lines in the memory array slices that are not at the beginning or end can all be pre-charged.

[0202] In summary, the embodiments of this disclosure provide a memory that reduces the area of ​​the edge memory array chip to half the area of ​​other memory array chips, thereby reducing the chip area and improving integration. Furthermore, corresponding testing methods are provided for this structure, improving the testing process for this memory structure and ensuring factory performance.

[0203] In another embodiment of this disclosure, see Figure 11 This illustrates a flowchart of a testing method provided in an embodiment of this disclosure. Figure 11 As shown, this test method is applied to Figure 3A or Figure 3B The memory 10 shown includes N memory array chips arranged sequentially along a first direction. Each memory array chip includes a plurality of first bit lines and a plurality of second bit lines, and the first bit lines and second bit lines are arranged alternately along a second direction. For memory array chips that are not at the beginning or end, the first bit line and the adjacent second bit line are electrically isolated. For memory array chips at the beginning or end, the first bit line is electrically connected to the second bit line adjacent to the first side and the first bit line is electrically isolated from the second bit line adjacent to the second side.

[0204] For ease of explanation, the memory array slices are numbered along the first direction. For memory array slices with odd numbers, the first bit line is the second bit line; for memory array slices with even numbers, the first bit line is the first bit line. For each memory array slice, the first bit line is numbered sequentially along the second direction, and the second bit line is numbered sequentially along the second direction.

[0205] The method includes:

[0206] S701: For memory array chips that are not at the beginning or end, different voltages are applied to the first bit line and the second bit line to achieve bit line stress testing of memory array chips that are not at the beginning or end.

[0207] S702: For the first and last memory array chips, different voltages are applied to the first bit line of the odd-numbered chips and the first bit line of the even-numbered chips to achieve bit line stress testing of the first and last memory array chips.

[0208] Here, there is no restriction on the order in which steps S701 and S702 are executed.

[0209] In some embodiments, for Figure 6 The memory 10 shown is configured such that: for the first memory array chip, the second bit lines are connected to their respective pre-charge sources via pre-charge switches, and the first bit lines are pre-charged via the pre-charge source corresponding to the second bit lines electrically connected to them; for the last memory array chip, the first bit lines are connected to their respective pre-charge sources via pre-charge switches, and the second bit lines are pre-charged via the pre-charge source corresponding to the first bit lines electrically connected to them; for memory array chips that are not at the beginning or end, the first bit lines are connected to their respective pre-charge sources via pre-charge switches, and the second bit lines are connected to their respective pre-charge sources via pre-charge switches; the pre-charge sources for the second bit lines in odd-numbered memory arrays and the first bit lines in even-numbered memory array chips are both first power supply terminals, and the pre-charge sources for the first bit lines in odd-numbered memory arrays and the second bit lines in even-numbered memory array chips are both second power supply terminals; for memory array chips at the beginning and end, only one of the first bit lines and the second bit lines corresponds to a pre-charge source.

[0210] The aforementioned step S701 includes:

[0211] Control the first power supply terminal to a first voltage value and the second power supply terminal to a second voltage value; the first voltage value and the second voltage value are different; perform a regular pre-charge operation; wherein, in the regular pre-charge operation, each line is connected to its respective pre-charge power source; after a preset time, stop the regular pre-charge operation, control the first power supply terminal to the second voltage value and the second power supply terminal to the first voltage value; perform the regular pre-charge operation and maintain it for the preset time.

[0212] It should be noted that the storage array slices at the beginning and end each include multiple dual sub-cells. Each dual sub-cell includes two storage cells that store the same data. Both storage cells are electrically connected to the same word line, and the corresponding bit lines of the two storage cells are electrically connected. The dual sub-cells perform data reading and writing simultaneously.

[0213] Based on this, the aforementioned step S702 includes:

[0214] For the storage array slices at the beginning and end, write the first data to the odd-numbered double sub-cells and write the second data to the even-numbered double sub-cells; the first data and the second data are different; after a preset time, stop the data writing operation, write the second data to the odd-numbered double sub-cells and write the first data to the even-numbered double sub-cells, and maintain this for the preset time.

[0215] In some embodiments, for Figure 7 The memory 10 shown has the following configurations: For the first memory array chip, the second bit lines are connected to their respective pre-charge sources via pre-charge switches, and the first bit lines are pre-charged via the pre-charge source corresponding to the second bit lines electrically connected to them; For the last memory array chip, the first bit lines are connected to their respective pre-charge sources via pre-charge switches, and the second bit lines are pre-charged via the pre-charge source corresponding to the first bit lines electrically connected to them; For memory array chips that are not at the beginning or end, the first bit lines are connected to their respective pre-charge sources via pre-charge switches, and the second bit lines are connected to their respective pre-charge sources via pre-charge switches; that is, the pre-charge source for the second bit lines in odd-numbered memory arrays is the third power supply terminal, the pre-charge source for the first bit lines in even-numbered memory array chips is the fourth power supply terminal, the pre-charge source for the first bit lines in odd-numbered memory arrays is the fifth power supply terminal, and the pre-charge source for the second bit lines in even-numbered memory array chips is the sixth power supply terminal.

[0216] The aforementioned step 701 includes:

[0217] Control the third and fourth power terminals to the first voltage value, and the fifth and sixth power terminals to the second voltage value; the first voltage value and the second voltage value are different; perform a normal pre-charge operation; after a preset time, stop the normal pre-charge operation, control the third and fourth power terminals to the second voltage value, and the fifth and sixth power terminals to the first voltage value; perform a normal pre-charge operation and maintain the preset time.

[0218] The aforementioned step 702 includes:

[0219] Control the third and fifth power terminals to the first voltage value, and the fourth and sixth power terminals to the second voltage value; perform a normal pre-charge operation; after a preset time, stop the normal pre-charge operation, control the third and fifth power terminals to the second voltage value, and the fourth and sixth power terminals to the first voltage value; perform a normal pre-charge operation and maintain the preset time.

[0220] In other embodiments, the same applies. Figure 7 The memory 10 shown above, the aforementioned step 701 includes:

[0221] The third and fourth power terminals are controlled to a first voltage value, and the fifth and sixth power terminals are controlled to a second voltage value; the first voltage value and the second voltage value are different; a first test pre-charge operation is performed; wherein, in the first test pre-charge operation, all bit lines in the first and last positions of the memory array chip are disconnected from their respective pre-charge power sources, and all bit lines in the memory array chips other than the first and last positions are connected to their respective pre-charge power sources; after a preset time, the pre-charge operation is stopped, the third and fourth power terminals are controlled to the second voltage value, and the fifth and sixth power terminals are controlled to the first voltage value; the first test pre-charge operation is performed and maintained for the preset time.

[0222] In some embodiments, step 702 described above includes:

[0223] The third and fifth power terminals are controlled to a first voltage value, and the fourth and sixth power terminals are controlled to a second voltage value; the first voltage value and the second voltage value are different; a second test pre-charge operation is performed; wherein, in the second test pre-charge operation, all bit lines in the first and last positions of the memory array chip are connected to their respective pre-charge power sources, and all bit lines in the memory array chips other than the first and last positions are disconnected from their respective pre-charge power sources; after a preset time, the pre-charge operation is stopped, the third and fifth power terminals are controlled to the second voltage value, and the fourth and sixth power terminals are controlled to the first voltage value; the second test pre-charge operation is performed and maintained for the preset time.

[0224] In summary, the embodiments of this disclosure provide a testing method that reduces the area of ​​the memory array chip located at the edge to half the area of ​​other memory array chips, thereby reducing the chip area and improving integration. Furthermore, it provides a corresponding testing method for this structure, improving the testing process for this type of memory and ensuring factory performance.

[0225] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0226] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0227] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory, comprising: The memory comprises N memory array slices arranged in sequence along a first direction, N being a natural number; each of the memory array slices comprises a plurality of first bit lines and a plurality of second bit lines, and the first bit lines and the second bit lines are alternately arranged along a second direction; for the memory array slices other than the first and last ones, the first bit lines and the adjacent second bit lines are electrically isolated; for the first and last memory array slices, the first bit lines are electrically connected with the second bit lines adjacent to the first side, and the first bit lines are electrically isolated from the second bit lines adjacent to the second side; The memory is configured to, in one step, apply different voltages to the first bit lines and the second bit lines respectively for the memory array slices other than the first and last ones, so as to realize bit line stress testing of the memory array slices other than the first and last ones; and in another step, apply different voltages to the odd-numbered first bit lines and the even-numbered first bit lines respectively for the first and last memory array slices, so as to realize bit line stress testing of the first and last memory array slices; Wherein, the memory array slices are numbered along the first direction, for the odd-numbered memory array slices, the first bit line is the second bit line; for the even-numbered memory array slices, the first bit line is the first bit line; for each of the memory array slices, the first bit lines therein are sequentially numbered along the second direction, and the second bit lines therein are sequentially numbered along the second direction.

2. The memory of claim 1, wherein, A readout amplification module is distributed between every 2 memory array slices, and the readout amplification module comprises a plurality of sensitive amplifiers arranged in sequence along the second direction; The first end of the sensitive amplifier is connected with one of the second bit lines on the third side through a first un-bias switch, and the second end of the sensitive amplifier is connected with one of the second bit lines on the third side through a first isolation switch; The second end of the sensitive amplifier is also connected with one of the first bit lines on the fourth side through a second un-bias switch, and the first end of the sensitive amplifier is also connected with one of the first bit lines on the fourth side through a second isolation switch.

3. The memory of claim 2, wherein, The readout amplification modules are numbered along the first direction; For the odd-numbered readout amplification modules, the first end or the second end of the sensitive amplifier therein is also connected to a first power supply end through a pre-charge switch; For the even-numbered readout amplification modules, the first end or the second end of the sensitive amplifier therein is also connected to a second power supply end through the pre-charge switch.

4. The memory according to claim 3, wherein The memory is specifically configured to, in one step, turn off all the sensitive amplifiers, control the first power supply end to be a first voltage value and the second power supply end to be a second voltage value, and perform a regular pre-charge operation; and After a preset time length, control the first power supply end to be the second voltage value and the second power supply end to be the first voltage value, and perform the regular pre-charge operation; Wherein, the first voltage value and the second voltage value are different; in the regular pre-charge operation, all the pre-charge switches, isolation switches and un-bias switches are in the on state.

5. The memory of claim 4, wherein, The storage array pieces at the head and tail positions each include a plurality of doublet cells, the doublet cells include 2 storage cells storing the same data, the 2 storage cells are electrically connected to the same word line, and there is an electrical connection between the corresponding bit lines of the 2 storage cells, the doublet cells simultaneously perform data reading and writing; for each of the storage array pieces at the head and tail positions, the doublet cells are numbered along a second direction; The memory is further configured to, in another step, only turn on the sensitive amplifiers adjacent to the storage array pieces at the head and tail positions, write first data to the doublet cells numbered with odd numbers, and write second data to the doublet cells numbered with even numbers; and, After a preset time length, the second data is written to the doublet cells numbered with odd numbers, and the first data is written to the doublet cells numbered with even numbers. The first data and the second data are different.

6. The memory of claim 2, wherein, The readout amplification modules are numbered along a first direction, and a first readout amplification module is numbered with odd numbers; for each readout amplification module, the sensitive amplifiers therein are numbered along a second direction; For the readout amplification modules numbered with odd numbers, the second ends of the sensitive amplifiers numbered with odd numbers are connected to a third power supply end through a pre-charge switch, and the first ends of the sensitive amplifiers numbered with even numbers are connected to a fourth power supply end through a pre-charge switch; For the readout amplification modules numbered with even numbers, the second ends of the sensitive amplifiers numbered with odd numbers are connected to a fifth power supply end through a pre-charge switch, and the first ends of the sensitive amplifiers numbered with even numbers are connected to a sixth power supply end.

7. The memory of claim 6, wherein, The memory is specifically configured to, in a step, turn off all sensitive amplifiers, control the third power supply end and the fourth power supply end to be a first voltage value, and the fifth power supply end and the sixth power supply end to be a second voltage value; and perform a regular pre-charge operation; and, After a preset time length, control the third power supply end and the fourth power supply end to be a second voltage value, and the fifth power supply end and the sixth power supply end to be a first voltage value; and perform the regular pre-charge operation.

8. The memory of claim 7, wherein, The memory is specifically configured to, in another step, turn off all sensitive amplifiers, control the third power supply end and the fifth power supply end to be a first voltage value, and the fourth power supply end and the sixth power supply end to be a second voltage value; and perform the regular pre-charge operation; and, After the preset time length, control the third power supply end and the fifth power supply end to be a second voltage value, and the fourth power supply end and the sixth power supply end to be a first voltage value; and perform the regular pre-charge operation.

9. The memory of claim 6, wherein, The memory is specifically configured to, in a step, turn off all sensitive amplifiers, control the third power supply end and the fourth power supply end to be a first voltage value, and the fifth power supply end and the sixth power supply end to be a second voltage value; and perform a first test pre-charge operation; and, After a preset time length, control the third power supply end and the fourth power supply end to be a second voltage value, and the fifth power supply end and the sixth power supply end to be a first voltage value; and perform the first test pre-charge operation. ​ ​ ​ ​ ​ ​ after a preset time length, the third power supply end and the fourth power supply end are controlled to be the second voltage value, and the fifth power supply end and the sixth power supply end are controlled to be the first voltage value; and the first test pre-charge operation is performed; In the first test pre-charge operation, the isolation switches and the offset cancellation switches between the readout amplifier modules at the head and tail positions and the storage array slices at the head and tail positions are in the off state, and all the pre-charge switches, isolation switches and offset cancellation switches are in the on state.

10. The memory of claim 9, wherein, In another step, all the sense amplifiers are turned off, the third power supply end and the fifth power supply end are controlled to be the first voltage value, and the fourth power supply end and the sixth power supply end are controlled to be the second voltage value; and the second test pre-charge operation is performed; after the preset time length, the third power supply end and the fifth power supply end are controlled to be the second voltage value, and the fourth power supply end and the sixth power supply end are controlled to be the first voltage value; and the second test pre-charge operation is performed; In the second test pre-charge operation, the isolation switches and the offset cancellation switches between the readout amplifier modules at the head and tail positions and the storage array slices at the head and tail positions are in the on state, the isolation switches and the offset cancellation switches between the readout amplifier modules at the head and tail positions and the storage array slices at the non-head and non-tail positions are in the off state, the pre-charge switches of the readout amplifier modules at the head and tail positions are in the on state, and the pre-charge switches of the readout amplifier modules at the non-head and non-tail positions are in the off state. The first test pre-charge operation, the second test pre-charge operation and the normal pre-charge operation all belong to pre-charge operations, and the memory further comprises:

11. The memory of claim 10, wherein, a control circuit configured to generate a valid initial isolation signal and a valid initial offset cancellation signal when the memory is instructed to perform the pre-charge operation, and generate an invalid initial isolation signal and an invalid initial offset cancellation signal when the memory is not instructed to perform the pre-charge operation; a first pre-processing circuit configured to generate a first edge isolation signal and a second edge isolation signal based on an edge test parameter group and the initial isolation signal, and generate a first edge offset cancellation signal and a second edge offset cancellation signal based on the edge test parameter group and the initial offset cancellation signal; a second pre-processing circuit configured to generate a first internal isolation signal and a second internal isolation signal based on an internal test parameter group and the initial isolation signal, and generate a first internal offset cancellation signal and a second internal offset cancellation signal based on the internal test parameter group and the initial offset cancellation signal; ​ The first isolation switch, the second isolation switch, the first un-bias switch and the second un-bias switch between the read-out amplification module at the head or tail position and the adjacent storage array slice are controlled by the first edge isolation signal, the second edge isolation signal, the first edge un-bias signal and the second edge un-bias signal respectively; the first isolation switch, the second isolation switch, the first un-bias switch and the second un-bias switch between the read-out amplification module at the non-head or non-tail position and the adjacent storage array slice are controlled by the first internal isolation signal, the second internal isolation signal, the first internal un-bias signal and the second internal un-bias signal respectively.

12. The memory of claim 11, wherein, The edge test parameter group at least includes a first test parameter and a second test parameter, and the internal test parameter group at least includes a third test parameter and a fourth test parameter; If the current pre-charging operation is a normal pre-charging operation, the first test parameter, the second test parameter, the third test parameter and the fourth test parameter are all in a first state; if the test parameter group indicates that the current pre-charging operation is a first test pre-charging operation, the second test parameter is in a second state, and the first test parameter, the third test parameter and the fourth test parameter are all in the first state; if the current pre-charging operation is a second test pre-charging operation, the first test parameter is in the second state, and the second test parameter, the third test parameter and the fourth test parameter are all in the first state; If the second test parameter is in the first state, the first edge isolation signal and the first edge un-bias signal are respectively in the same level as the initial isolation signal and the initial un-bias signal; if the second test parameter is in the second state, the first edge isolation signal and the first edge un-bias signal are both invalid; If the first test parameter is in the first state, the second edge isolation signal and the second edge un-bias signal are respectively in the same level as the initial isolation signal and the initial un-bias signal; if the first test parameter is in the second state, the second edge isolation signal and the second edge un-bias signal are both invalid; If the fourth test parameter is in the first state, the first internal isolation signal and the first internal un-bias signal are respectively in the same level as the initial isolation signal and the initial un-bias signal; if the fourth test parameter is in the second state, the first internal isolation signal and the first internal un-bias signal are both invalid; If the third test parameter is in the first state, the second internal isolation signal and the second internal un-bias signal are respectively in the same level as the initial isolation signal and the initial un-bias signal; if the third test parameter is in the second state, the second internal isolation signal and the second internal un-bias signal are both invalid.

13. The memory of claim 12, wherein, The first state is a high level, and the second state is a low level; The first pre-processing circuit comprises: a first AND gate, whose two input ends receive the first test parameter and the initial isolation signal respectively, and whose output end outputs the second edge isolation signal; a second AND gate, two input ends of which receive the second test parameter and the initial isolation signal respectively, and an output end of which outputs the first edge isolation signal; a third AND gate, two input ends of which receive the first test parameter and the initial cancellation signal respectively, and an output end of which outputs the second edge cancellation signal; a fourth AND gate, two input ends of which receive the second test parameter and the initial cancellation signal respectively, and an output end of which outputs the first edge cancellation signal; the second preprocessing circuit comprises: a fifth AND gate, two input ends of which receive the third test parameter and the initial isolation signal respectively, and an output end of which outputs the second internal isolation signal; a sixth AND gate, two input ends of which receive the fourth test parameter and the initial isolation signal respectively, and an output end of which outputs the first internal isolation signal; a seventh AND gate, two input ends of which receive the third test parameter and the initial cancellation signal respectively, and an output end of which outputs the second internal cancellation signal; an eighth AND gate, two input ends of which receive the fourth test parameter and the initial cancellation signal respectively, and an output end of which outputs the first internal cancellation signal.

14. A test method characterized by, The application is applied to a memory, which comprises N memory array pieces arranged in sequence along a first direction, the memory array pieces comprise a plurality of first bit lines and a plurality of second bit lines, and the first bit lines and the second bit lines are arranged alternately along a second direction; for the memory array pieces at non-first and non-last positions, the first bit lines and the adjacent second bit lines are electrically isolated; for the memory array pieces at first and last positions, the first bit lines are electrically connected with the second bit lines adjacent to the first side and are electrically isolated with the second bit lines adjacent to the second side; The method comprises: In one step, for the memory array pieces at non-first and non-last positions, different voltages are respectively applied to the first bit lines and the second bit lines in the memory array pieces to realize bit line stress test of the memory array pieces at non-first and non-last positions; In another step, for the memory array pieces at first and last positions, different voltages are respectively applied to the first bit lines with odd numbers and the first bit lines with even numbers in the memory array pieces to realize bit line stress test of the memory array pieces at first and last positions; Wherein, the memory array pieces are numbered along the first direction, for the memory array pieces with odd numbers, the first bit line is the second bit line; for the memory array pieces with even numbers, the first bit line is the first bit line; for each memory array piece, the first bit lines in the memory array piece are numbered in sequence along the second direction, and the second bit lines in the memory array piece are numbered in sequence along the second direction.

15. The method of claim 14, wherein, For the first storage array slice, the second bit line is connected to the corresponding pre-charge power supply through a pre-charge switch, and the first bit line is pre-charged by the pre-charge power supply corresponding to the second bit line; for the last storage array slice, the first bit line is connected to the corresponding pre-charge power supply through a pre-charge switch, and the second bit line is pre-charged by the pre-charge power supply corresponding to the first bit line; for the storage array slice other than the first and last positions, the first bit line is connected to the corresponding pre-charge power supply through a pre-charge switch, and the second bit line is connected to the corresponding pre-charge power supply through a pre-charge switch; the pre-charge power supply of the first bit line in the odd-numbered storage array slice and the pre-charge power supply of the second bit line in the even-numbered storage array slice are both first power supply ends, and the pre-charge power supply of the second bit line in the odd-numbered storage array slice and the pre-charge power supply of the first bit line in the even-numbered storage array slice are both second power supply ends; The different voltages applied to the first bit line and the second bit line in the storage array slice other than the first and last positions include: The first power supply end is controlled to be a first voltage value and the second power supply end is controlled to be a second voltage value; the first voltage value and the second voltage value are different; A normal pre-charge operation is performed; in the normal pre-charge operation, each bit line and the corresponding pre-charge power supply are in an on state; After a preset time period, the normal pre-charge operation is stopped, the first power supply end is controlled to be a second voltage value and the second power supply end is controlled to be a first voltage value; The normal pre-charge operation is performed and the preset time period is maintained.

16. The method of claim 15, wherein, The first and last storage array slices each include a plurality of twin cells, the twin cell includes two storage units storing the same data, the two storage units are electrically connected to the same word line, and the bit lines corresponding to the two storage units are electrically connected, and the twin cell simultaneously performs data reading and writing; The different voltages applied to the odd-numbered first bit line and the even-numbered first bit line in the first and last storage array slices include: For the first and last storage array slices, the odd-numbered twin cells are written with first data and the even-numbered twin cells are written with second data; the first data and the second data are different; After a preset time period, the data writing operation is stopped, the second data is written to the odd-numbered twin cells and the first data is written to the even-numbered twin cells, and the preset time period is maintained.

17. The method of claim 14, wherein, For the first storage array slice, the second bit line is connected to the corresponding pre-charge source through a pre-charge switch, and the first bit line is pre-charged by the pre-charge source corresponding to the second bit line; for the last storage array slice, the first bit line is connected to the corresponding pre-charge source through a pre-charge switch, and the second bit line is pre-charged by the pre-charge source corresponding to the first bit line; for the storage array slice in a non-first or non-last position, the first bit line is connected to the corresponding pre-charge source through a pre-charge switch, and the second bit line is connected to the corresponding pre-charge source through a pre-charge switch; the pre-charge source of the second bit line in the odd-numbered storage array is a third power terminal, the pre-charge source of the first bit line in the even-numbered storage array slice is a fourth power terminal, the pre-charge source of the first bit line in the odd-numbered storage array is a fifth power terminal, and the pre-charge source of the second bit line in the even-numbered storage array slice is a sixth power terminal; For the storage array slice in a non-first or non-last position, different voltages are applied to the first bit line and the second bit line, respectively, including: The third power terminal and the fourth power terminal are controlled to be a first voltage value, and the fifth power terminal and the sixth power terminal are controlled to be a second voltage value; the first voltage value and the second voltage value are different; A normal pre-charge operation is performed; After a preset time period, the normal pre-charge operation is stopped, the third power terminal and the fourth power terminal are controlled to be a second voltage value, and the fifth power terminal and the sixth power terminal are controlled to be a first voltage value; A normal pre-charge operation is performed, and the preset time period is maintained.

18. The method of claim 17, wherein, For the first storage array slice, the second bit line is connected to the corresponding pre-charge source through a pre-charge switch, and the first bit line is pre-charged by the pre-charge source corresponding to the second bit line; for the last storage array slice, the first bit line is connected to the corresponding pre-charge source through a pre-charge switch, and the second bit line is pre-charged by the pre-charge source corresponding to the first bit line; for the storage array slice in a non-first or non-last position, the first bit line is connected to the corresponding pre-charge source through a pre-charge switch, and the second bit line is connected to the corresponding pre-charge source through a pre-charge switch; the pre-charge source of the second bit line in the odd-numbered storage array is a third power terminal, the pre-charge source of the first bit line in the even-numbered storage array slice is a fourth power terminal, the pre-charge source of the first bit line in the odd-numbered storage array is a fifth power terminal, and the pre-charge source of the second bit line in the even-numbered storage array slice is a sixth power terminal; For the storage array slice in a non-first or non-last position, different voltages are applied to the first bit line and the second bit line, respectively, including: The third power terminal and the fourth power terminal are controlled to be a first voltage value, and the fifth power terminal and the sixth power terminal are controlled to be a second voltage value; the first voltage value and the second voltage value are different; A normal pre-charge operation is performed; After a preset time period, the normal pre-charge operation is stopped, the third power terminal and the fourth power terminal are controlled to be a second voltage value, and the fifth power terminal and the sixth power terminal are controlled to be a first voltage value; 19. The method of claim 14, wherein, A normal pre-charge operation is performed, and the preset time period is maintained. For the first storage array slice, the second bit line is connected to the corresponding pre-charge source through a pre-charge switch, and the first bit line is pre-charged by the pre-charge source corresponding to the second bit line; for the last storage array slice, the first bit line is connected to the corresponding pre-charge source through a pre-charge switch, and the second bit line is pre-charged by the pre-charge source corresponding to the first bit line; for the storage array slice in a non-first or non-last position, the first bit line is connected to the corresponding pre-charge source through a pre-charge switch, and the second bit line is connected to the corresponding pre-charge source through a pre-charge switch; the pre-charge source of the second bit line in the odd-numbered storage array is a third power terminal, the pre-charge source of the first bit line in the even-numbered storage array slice is a fourth power terminal, the pre-charge source of the first bit line in the odd-numbered storage array is a fifth power terminal, and the pre-charge source of the second bit line in the even-numbered storage array slice is a sixth power terminal; For the storage array slice in a non-first or non-last position, different voltages are applied to the first bit line and the second bit line, respectively, including: The third power terminal and the fourth power terminal are controlled to be a first voltage value, and the fifth power terminal and the sixth power terminal are controlled to be a second voltage value; the first voltage value and the second voltage value are different; performing a first test pre-charge operation; wherein in the first test pre-charge operation, all bit lines in the memory array slice at the head and tail positions are in an off state with respective pre-charge sources, and all bit lines in the memory array slice at non-head and non-tail positions are in an on state with respective pre-charge sources; stopping the pre-charge operation after a preset time period, and controlling the third and fourth power supply ends to be a second voltage value, and the fifth and sixth power supply ends to be a first voltage value; performing the first test pre-charge operation and maintaining the preset time period.

20. The method of claim 19, wherein, for the memory array slice at the head and tail positions, respectively applying different voltages to the first bit lines with odd numbers and the first bit lines with even numbers therein, including: controlling the third and fifth power supply ends to be a first voltage value, and the fourth and sixth power supply ends to be a second voltage value; the first voltage value and the second voltage value are different; performing a second test pre-charge operation; wherein in the second test pre-charge operation, all bit lines in the memory array slice at the head and tail positions are in an on state with respective pre-charge sources, and all bit lines in the memory array slice at non-head and non-tail positions are in an off state with respective pre-charge sources; stopping the pre-charge operation after a preset time period, and controlling the third and fifth power supply ends to be a second voltage value, and the fourth and sixth power supply ends to be a first voltage value; performing the second test pre-charge operation and maintaining the preset time period.

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