Power-on detection method and memory storage device

Abstract

The invention provides a power-on detection method and a memory storage device, which can improve the data stability and correctness of a rewritable nonvolatile memory module and reduce the possibility of data loss. The power-on detection method comprises the steps of obtaining filling origin and destination information corresponding to a first entity unit when power-on is performed again after power-off; judging whether the first entity unit meets a first condition or a second condition based on the filling origin-destination information; if the first condition or the second condition is met, executing a reading operation on a first word line of the first entity unit, and judging whether the reading operation meets a third condition or not; and if a third condition is met, taking the data stored in the first word line as filling data, writing the filling data into the first entity unit, and updating the filling origin-destination information, performing an error check operation on the first entity unit; and if the error checking operation fails, executing an updating operation on the first entity unit.

Description

Technical Field

[0001] The present invention relates to a memory management technology, and more particularly to a power-on detection method and a memory storage device. Background Art

[0002] In recent years, the growth of smart phones, tablet computers, and personal computers has been very rapid, resulting in a sharp increase in consumers' demand for storage media. Since rewritable non-volatile memory modules (e.g., flash memory) have the characteristics of data non-volatility, low power consumption, small size, and no mechanical structure, they are very suitable for being built into various portable multimedia devices exemplified above.

[0003] With the development of the memory technology field, the number of bits that can be stored in each memory cell has been increasing day by day. Currently, most host systems use the triple-level cell (TLC) mode to write data into rewritable non-volatile memory modules. However, during the operation of the memory storage device, power failure may occur at any time, making the data stored in the physical cells that are not fully written in an unstable state, thus resulting in the problem of data loss. Summary of the Invention

[0004] Exemplary embodiments of the present invention provide a power-on detection method and a memory storage device, which can improve the data stability and correctness of rewritable non-volatile memory modules and reduce the possibility of data loss.

[0005] Exemplary embodiments of the present invention provide a power-on detection method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical cells. The power-on detection method includes: when power is restored after power failure, obtaining the filling start and end information corresponding to a first physical cell; based on the filling start and end information, determining whether the first physical cell meets a first condition or a second condition; if the first condition or the second condition is met, performing a read operation on a first word line of the first physical cell and determining whether the read operation meets a third condition; if the third condition is met, using the data stored in the first word line as filling data, writing the filling data into the first physical cell, and updating the filling start and end information; performing an error check operation on the first physical cell; and if the error check operation fails, performing an update operation on the first physical cell.

[0006] In an exemplary embodiment of the present invention, the power-on detection method further includes: if the filling start and end information does not exist, performing the read operation on the first word line.

[0007] In an exemplary embodiment of the present invention, the power-on detection method further includes: if the third condition is not met, performing the update operation on the first physical unit.

[0008] In an exemplary embodiment of the present invention, the power-on detection method further includes: if the error checking operation is successful, performing subsequent access operations on the first physical unit.

[0009] In an exemplary embodiment of the present invention, the fill start and end information is used to indicate the start physical programming unit and the end physical programming unit in the first physical unit for storing the fill data.

[0010] In an exemplary embodiment of the present invention, the start physical programming unit is the Xth physical programming unit in the first physical unit, the end physical programming unit is the Yth physical programming unit in the first physical unit, and the first unwritten physical programming unit in the first physical unit is the Nth physical programming unit in the first physical unit, where X, Y, and N are all positive integers.

[0011] In an exemplary embodiment of the present invention, the step of determining whether the first physical unit meets the first condition or the second condition includes: if X is less than Y and Y is not equal to N - 1, determining that the first condition is met; and if X is greater than Y, determining that the second condition is met.

[0012] In an exemplary embodiment of the present invention, the error checking operation includes a first error checking operation and a second error checking operation. The first error checking operation is performed on the first physical programming unit to the (N - 1)th physical programming unit of the first physical unit. The second error checking operation is performed on the first physical programming unit to the (X - 1)th physical programming unit of the first physical unit.

[0013] In an exemplary embodiment of the present invention, if the first condition is met, the error checking operation is the first error checking operation, and if the second condition is met, the error checking operation is the second error checking operation.

[0014] In an exemplary embodiment of the present invention, the power-on detection method further includes: if the first condition and the second condition are not met, performing the second error checking operation on the first physical unit.

[0015] In an exemplary embodiment of the present invention, the step of determining whether the read operation meets the third condition includes: if no uncorrectable error correction code is generated, determining that the third condition is met.

[0016] In an exemplary embodiment of the present invention, the first word line is the word line written before the first unwritten physical programming unit of the first physical unit.

[0017] In an exemplary embodiment of the present invention, the first physical unit is an open physical unit.

[0018] An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The connection interface unit is coupled to a host system. The rewritable non-volatile memory module includes a plurality of physical units. When power is restored after power-off, the memory control circuit unit is configured to obtain fill start and end information corresponding to a first physical unit. The memory control circuit unit is further configured to determine whether the first physical unit meets a first condition or a second condition based on the fill start and end information. If the first condition or the second condition is met, the memory control circuit unit is further configured to perform a read operation on a first word line of the first physical unit and determine whether the read operation meets a third condition. If the third condition is met, the memory control circuit unit is further configured to use the data stored in the first word line as fill data, write the fill data into the first physical unit, and update the fill start and end information. The memory control circuit unit is further configured to perform an error check operation on the first physical unit. If the error check operation fails, the memory control circuit unit is further configured to perform an update operation on the first physical unit.

[0019] In an exemplary embodiment of the present invention, if the fill start and end information does not exist, the memory control circuit unit is further configured to perform the read operation on the first word line.

[0020] In an exemplary embodiment of the present invention, if the third condition is not met, the memory control circuit unit is further configured to perform the update operation on the first physical unit.

[0021] In an exemplary embodiment of the present invention, if the error check operation is successful, the memory control circuit unit is further configured to perform subsequent access operations on the first physical unit.

[0022] In an exemplary embodiment of the present invention, if X is less than Y and Y is not equal to N - 1, the memory control circuit unit is further configured to determine that the first physical unit meets the first condition. If X is greater than Y, the memory control circuit unit is further configured to determine that the first physical unit meets the second condition.

[0023] In an exemplary embodiment of the present invention, if the first condition and the second condition are not met, the memory control circuit unit is further configured to perform the second error checking operation on the first physical unit.

[0024] In an exemplary embodiment of the present invention, if an uncorrectable error correction code is not generated, the memory control circuit unit is further configured to determine that the read operation meets the third condition.

[0025] Based on the above, the present invention provides a power-on detection method and a memory storage device, which can improve the data stability and correctness of a rewritable non-volatile memory module and reduce the possibility of data loss by writing padding data into open physical units.

[0026] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device shown according to an exemplary embodiment of the present invention;

[0028] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device shown according to an exemplary embodiment of the present invention;

[0029] Figure 3 is a schematic diagram of a host system and a memory storage device shown according to an exemplary embodiment of the present invention;

[0030] Figure 4 is a schematic diagram of a memory storage device shown according to an exemplary embodiment of the present invention;

[0031] Figure 5 is a schematic diagram of a memory control circuit unit shown according to an exemplary embodiment of the present invention;

[0032] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module shown according to an exemplary embodiment of the present invention;

[0033] Figure 7 is a flowchart of a power-on detection method shown according to an exemplary embodiment of the present invention;

[0034] Figure 8 is a schematic diagram of an open physical unit that meets the first condition shown according to an exemplary embodiment of the present invention;

[0035] Figure 9Schematic diagram of an open entity unit that meets the second condition as shown in an exemplary embodiment of the present invention;

[0036] Figure 10 Schematic diagram of an open entity unit that does not meet the first condition and the second condition as shown in an exemplary embodiment of the present invention;

[0037] Figure 11 Flowchart of a power-on detection method as shown in an exemplary embodiment of the present invention. Detailed implementation manners

[0038] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0039] Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). The memory storage device can be used with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0040] Figure 1 Schematic diagram of a host system, a memory storage device, and an input / output (I / O) device as shown in an exemplary embodiment of the present invention. Figure 2 Schematic diagram of a host system, a memory storage device, and an I / O device as shown in an exemplary embodiment of the present invention.

[0041] Please refer to Figure 1 and Figure 2 , the host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be coupled to a system bus 110.

[0042] In an exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 through a data transmission interface 114. For example, the host system 11 may store data in the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be coupled to the I / O device 12 through a system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0043] In an exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 may be disposed on a main board 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the main board 20 may be coupled to the memory storage device 10 in a wired or wireless manner.

[0044] In an exemplary embodiment, the memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fidelity (WiFi) memory storage device, a Bluetooth memory storage device, or a low energy Bluetooth memory storage device (e.g., iBeacon), etc., which are memory storage devices based on various wireless communication technologies. In addition, the main board 20 may also be coupled to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the main board 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0045] In an exemplary embodiment, the host system 11 is a computer system. In an exemplary embodiment, the host system 11 may be any system that can substantially cooperate with the memory storage device to store data. In an exemplary embodiment, the memory storage device 10 and the host system 11 may respectively include Figure 3 the memory storage device 30 and the host system 31.

[0046] Figure 3 is a schematic diagram of a host system and a memory storage device shown in an exemplary embodiment of the present invention.

[0047] Please refer to Figure 3, the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342 that directly couple a memory module to a substrate of the host system.

[0048] Figure 4 is a schematic diagram of a memory storage device shown according to an exemplary embodiment of the present invention.

[0049] Please refer to Figure 4 , the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0050] The connection interface unit 41 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an exemplary embodiment, the connection interface unit 41 can also be compliant with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be encapsulated in a single chip with the memory control circuit unit 42, or the connection interface unit 41 is disposed outside a chip that includes the memory control circuit unit 42.

[0051] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware form and perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0052] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one storage cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one storage cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one storage cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module capable of storing 4 bits in one storage cell), other flash memory modules, or other memory modules with the same characteristics.

[0053] Each storage cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each storage cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the storage cell. This operation of changing the threshold voltage of the storage cell is also referred to as "writing data to the storage cell" or "programming the storage cell". As the threshold voltage changes, each storage cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a storage cell belongs to, and thus one or more bits stored in this storage cell can be obtained.

[0054] In an exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 may form a plurality of physical programming units, and these physical programming units may form a plurality of physical units. Specifically, the memory cells on the same word line may form one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be at least classified into lower physical programming units and upper physical programming units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally, in a MLC NAND flash memory, the write speed of the lower physical programming unit is greater than that of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit.

[0055] In an exemplary embodiment, the physical programming unit is the smallest unit for programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area contains a plurality of physical sectors for storing user data, and the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In this exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or a greater or smaller number of physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical unit is the smallest unit for erasing. That is, each physical unit contains the smallest number of memory cells that are erased together. For example, the physical unit is a physical block.

[0056] Figure 5 It is a schematic diagram of a memory control circuit unit shown in an exemplary embodiment of the present invention.

[0057] Please refer to Figure 5 , the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0058] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions are executed to perform operations such as data writing, reading, and erasing. When explaining the operation of the memory management circuit 51 below, it is equivalent to explaining the operation of the memory control circuit unit 42.

[0059] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in the form of firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into this read-only memory. When the memory storage device 10 operates, these control instructions are executed by the microprocessor unit to perform operations such as data writing, reading, and erasing.

[0060] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of the rewritable non-volatile memory module 43 in the form of code (for example, the system area in the memory module dedicated to storing system data). In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. After that, the microprocessor unit runs these control instructions to perform operations such as data writing, reading, and erasing.

[0061] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are coupled to the microcontroller. The storage unit management circuit is used to manage the storage units or groups of storage units of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process the data to be written into the rewritable non-volatile memory module 43 and the data read from the rewritable non-volatile memory module 43. The write instruction sequence, the read instruction sequence, and the erase instruction sequence can each include one or more codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 can also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct the execution of corresponding operations.

[0062] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify the instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it must be understood that the present invention is not limited thereto, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0063] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, the data to be written to the rewritable non-volatile memory module 43 will be converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences can include a write instruction sequence for indicating data writing, a read instruction sequence for indicating data reading, an erase instruction sequence for indicating data erasure, and corresponding instruction sequences for indicating various memory operations (such as changing the read voltage level or performing a garbage collection operation, etc.). These instruction sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences can include one or more signals, or data on the bus. These signals or data can include instruction codes or codes. For example, in the read instruction sequence, information such as the read identification code and the memory address will be included.

[0064] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correcting circuit 54, a buffer memory 55, and a power management circuit 56.

[0065] The error checking and correcting circuit 54 is coupled to the memory management circuit 51 and is used to perform error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 51 receives a write instruction from the host system 11, the error checking and correcting circuit 54 will generate a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to this write instruction, and the memory management circuit 51 will write the data corresponding to this write instruction and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. After that, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, it will simultaneously read the error correcting code and / or error detecting code corresponding to this data, and the error checking and correcting circuit 54 will perform error checking and correcting operations on the read data based on this error correcting code and / or error detecting code.

[0066] The buffer memory 55 is coupled to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is coupled to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0067] In an exemplary embodiment,Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In an exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In an exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0068] Figure 6 is a schematic diagram showing the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0069] Please refer to Figure 6 , the memory management circuit 51 may logically group the physical units 610(0) to 610(B) in the rewritable non-volatile memory module 43 into a storage area 601 and a spare area 602. One physical unit refers to a virtual block (VB). A virtual block may include multiple physical programmed units. For example, a virtual block may contain one or more physical units.

[0070] The physical units 610(0) to 610(A) in the storage area 601 are used to store user data (such as user data from Figure 1 the host system 11). For example, the physical units 610(0) to 610(A) in the storage area 601 may store valid data and invalid data. The physical units 610(A + 1) to 610(B) in the spare area 602 do not store data (such as valid data). For example, if a certain physical unit does not store valid data, this physical unit may be associated (or added) to the spare area 602. In addition, the physical units in the spare area 602 (or physical units that do not store valid data) may be erased. When writing new data, one or more physical units may be extracted from the spare area 602 to store this new data. In an exemplary embodiment, the spare area 602 is also referred to as a free pool.

[0071] The memory management circuit 51 may configure the logical units 612(0) to 612(C) to map the physical units 610(0) to 610(A) in the storage area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units.

[0072] Note that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, it means that the data stored in this physical unit currently contains valid data. Conversely, if a physical unit is not currently mapped by any logical unit, it means that the data stored in this physical unit does not contain any valid data.

[0073] The memory management circuit 51 can record management data (also referred to as logical-to-physical mapping information) that describes the mapping relationship between logical units and physical units in at least one logical-to-physical mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can perform data access operations on the memory storage device 10 according to the information in this logical-to-physical mapping table.

[0074] In an exemplary embodiment, physical units in the storage area 601 that are not fully written are called open physical units (open blocks). During the operation of the memory storage device 10, a power failure may occur at any time, causing the data stored in the open physical units to be in an unstable state, resulting in the problem of data loss.

[0075] The conventional approach is to re-read the open physical units after power-on to confirm the data correctness. Specifically, when the memory management circuit 51 reads the data stored in an open physical unit, it will simultaneously read the error correction code (ECC) corresponding to this data, and the error checking and correction circuit 54 will perform an error checking (ECC check) operation on the read data according to this error correction code to confirm the data correctness.

[0076] However, since the open physical units that are not fully written are in an unstable state, when reading this open physical unit after power-on, part of the data in this open physical unit may have a dancing situation, resulting in unexpected error bits and reducing the accuracy of the error checking operation.

[0077] In view of this, the present invention provides a power-on detection method that can avoid the dancing problem and thus improve the data stability of open physical units. Specifically, the power-on detection method provided by the present invention can, before performing an error checking operation on an open physical unit, read the data stored in the word line immediately preceding the first blank physical unit (for example, an unwritten physical programming unit or an unwritten physical page) in the open physical unit, and write this data as padding data into the open physical unit, and then continue to perform the error checking operation.

[0078] Figure 7is a flowchart of a power-on detection method shown in an exemplary embodiment of the present invention; Figure 8 is a schematic diagram of an open entity unit meeting the first condition shown in an exemplary embodiment of the present invention; Figure 9 is a schematic diagram of an open entity unit meeting the second condition shown in an exemplary embodiment of the present invention; Figure 10 is a schematic diagram of an open entity unit not meeting the first condition and the second condition shown in an exemplary embodiment of the present invention. Please refer to Figures 7 to 10 . In an exemplary embodiment, the rewritable non-volatile memory module 43 may include a three-level cell (TLC) NAND flash memory module, so three entity programming units (i.e., an upper entity programming unit, a middle entity programming unit, and a lower entity programming unit) may be included in one word line. Additionally, the rewritable non-volatile memory module 43 may also include other flash memory modules or other memory modules with the same characteristics, which are not limited in the present invention.

[0079] When powering on again after power-off, the memory management circuit 51 may execute Figure 7 the power-on detection method to confirm the correctness of the data stored in the open entity unit OB (also referred to as the first entity unit) and improve the data stability of the first entity unit OB.

[0080] In step S701, the memory management circuit 51 may determine whether there is fill start and end information corresponding to the first entity unit OB. In an exemplary embodiment, the fill start and end information may be stored, for example, in a system entity unit (such as a system block), and the fill start and end information is used to indicate the start entity programming unit P_S and the end entity programming unit P_E for storing fill data in the first entity unit OB.

[0081] The memory management circuit 51 may determine whether there is fill start and end information corresponding to the first entity unit OB in the system block. If there is no fill start and end information corresponding to the first entity unit OB, it means that the first entity unit OB has not been written with fill data previously, and the process proceeds to step S703. On the contrary, if there is fill start and end information corresponding to the first entity unit OB, it means that the first entity unit OB has been written with fill data previously. The memory management circuit 51 may obtain the fill start and end information corresponding to the first entity unit OB from the system block and proceed to step S702.

[0082] In step S702, the memory management circuit 51 may determine whether the first physical unit OB meets the first condition or the second condition based on the filling start and end information. Specifically, the filling start and end information may reflect the actual storage location of the latest filling data (i.e., the last written filling data) in the first physical unit OB. Therefore, the memory management circuit 51 may decide whether to write the filling data into the first physical unit OB through the filling start and end information.

[0083] If the first physical unit OB meets the first condition or the second condition, the memory management circuit 51 may determine that it is necessary to write the filling data into the first physical unit OB and proceed to step S703. In contrast, if the first physical unit OB does not meet the first condition and the second condition, the memory management circuit 51 may determine that it is not necessary to write the filling data into the first physical unit OB and proceed to step S706.

[0084] In an exemplary embodiment, the starting physical programming unit P_S for storing the filling data in the first physical unit OB is the Xth physical programming unit in the first physical unit OB, the ending physical programming unit P_E for storing the filling data in the first physical unit OB is the Yth physical programming unit in the first physical unit OB, and the first unwritten physical programming unit P_N in the first physical unit OB is the Nth physical programming unit in the first physical unit OB, where X, Y, and N are all positive integers.

[0085] In an exemplary embodiment, as Figure 8 shown, X is less than Y and Y is not equal to N - 1, indicating that after the filling data was written into the Xth physical programming unit (i.e., the starting physical programming unit P_S) to the Yth physical programming unit (i.e., the ending physical programming unit P_E) of the first physical unit OB in the previous time, user data from the host system 11 was written into the first physical unit OB. The memory management circuit 51 may determine that it is necessary to write the filling data into the first physical unit OB. In this regard, the memory management circuit 51 may determine that the first physical unit OB meets the first condition and proceed to step S703.

[0086] In an exemplary embodiment, as Figure 9 shown, X is greater than Y. At this time, the filling data in the ending physical programming unit P_E was written into the first physical unit OB earlier than the filling data in the starting physical programming unit P_S, indicating that the power failure occurred during the previous writing of the filling data into the first physical unit OB. Therefore, it is necessary to continue to execute the unfinished operation (i.e., write the filling data into the first physical unit OB) to maintain the data stability of the first physical unit OB. In this regard, the memory management circuit 51 may determine that the first physical unit OB meets the second condition and proceed to step S703.

[0087] In an exemplary embodiment, as Figure 10 shown, X is less than Y and Y is equal to N - 1, indicating that after the previous writing of padding data to the Xth to Yth physical programming units of the first physical unit OB, no user data from the host system 11 has been written to the first physical unit OB. The memory management circuit 51 can determine that there is no need to write padding data to the first physical unit OB. In this regard, the memory management circuit 51 can determine that the first physical unit OB does not meet the first condition and the second condition, and enter step S706.

[0088] In step S703, the memory management circuit 51 can perform a read operation on the first word line WL_P of the first physical unit OB. In an exemplary embodiment, the first word line WL_P is the previously written word line before the first unwritten physical programming unit P_N of the first physical unit OB, where the first word line WL_P can be used to store user data, for example.

[0089] In step S704, the memory management circuit 51 can determine whether the read operation performed on the first word line WL_P meets the third condition. In an exemplary embodiment, the memory management circuit 51 can determine whether an uncorrectable error correction code (UECC) is generated during this read operation. Specifically, the dancing problem mostly occurs in the physical programming units of the first physical unit OB that are later used to store data (for example, the first word line WL_P). Generally speaking, the dancing problem only causes minor errors, meaning that only a few bits in the data change. Therefore, if the first word line WL_P is only affected by the dancing problem, the error bits can be corrected during the reading of the first word line WL_P, and no UECC will be generated. In other words, if a UECC is generated, it means that the first word line WL_P is severely worn and the data stored in it is unreliable.

[0090] Accordingly, if a UECC is generated, the memory management circuit 51 can determine that this read operation does not meet the third condition and enter step S709. In contrast, if no UECC is generated, the memory management circuit 51 can determine that this read operation meets the third condition and enter step S705.

[0091] In step S705, the memory management circuit 51 can use the data stored in the first word line WL_P as padding data, write the padding data to the first physical unit OB, and update the padding start and end information.

[0092] In an exemplary embodiment, if the first physical unit OB meets the first condition, the memory management circuit 51 may use the data read from the first word line WL_P as padding data, and write the padding data into the first physical unit OB starting from the physical programming unit P_N, that is, write the padding data into the Nth to the (N + 2)th physical programming units in the first physical unit OB, thereby improving the data stability of the first physical unit OB and reducing the possibility of data loss.

[0093] Subsequently, the memory management circuit 51 may update the padding start and end information corresponding to the first physical unit OB in the system block based on the relevant information (such as physical addresses) of the Nth and (N + 2)th physical programming units in the first physical unit OB.

[0094] In an exemplary embodiment, if the first physical unit OB meets the second condition, the memory management circuit 51 can know the position where the previous padding data was interrupted (that is, Figure 9 the starting physical programming unit P_S) through the padding start and end information, use part of the data read from the first word line WL_P (that is, the middle and lower physical programming units of the first word line WL_P) as padding data, and write the padding data into the Nth and (N + 1)th physical programming units in the first physical unit OB, thereby improving the data stability of the first physical unit OB and reducing the possibility of data loss.

[0095] Subsequently, the memory management circuit 51 may update the padding start and end information corresponding to the first physical unit OB in the system block based on the relevant information (such as physical addresses) of the Xth and (N + 1)th physical programming units in the first physical unit OB.

[0096] In step S706, the memory management circuit 51 may perform an error check operation on the first physical unit OB. Specifically, the memory management circuit 51 may perform corresponding error check operations on different forms of the first physical unit OB. The memory management circuit 51 may perform an error check operation on the first physical programming unit of the first physical unit OB to the last physical programming unit used to store user data in the first physical unit OB.

[0097] In an exemplary embodiment, the error checking operation includes a first error checking operation and a second error checking operation. The first error checking operation may be, for example, an error checking operation performed on the first to the (N - 1)th physical programming units of the first physical unit OB. The second error checking operation may be, for example, an error checking operation performed on the first to the (X - 1)th physical programming units of the first physical unit OB. Specifically, the memory management circuit 51 may perform the first error checking operation on the first physical unit OB that meets the first condition as shown in Figure 8 In addition, the memory management circuit 51 may perform the second error checking operation on the first physical unit OB that meets the second condition as shown in Figure 9 and the first physical unit OB that does not meet the first and second conditions as shown in Figure 10 .

[0098] In step S707, the memory management circuit 51 may determine whether the error checking operation is successful. In an exemplary embodiment, the memory management circuit 51 may, for example, determine whether the error checking operation is successful by determining whether there are any error bits in the error checking operation. If the error checking operation is successful (i.e., there are no error bits), the process proceeds to step S708. In contrast, if the error checking operation fails (i.e., there are error bits), the process proceeds to step S709.

[0099] In step S708, the memory management circuit 51 may perform subsequent access operations on the first physical unit OB. Specifically, since the error checking operation is successful, the memory management circuit 51 may determine that the first physical unit OB has a high reliability. Therefore, the memory management circuit 51 may continue to use the first physical unit OB to perform subsequent access operations.

[0100] On the other hand, in step S709, the memory management circuit 51 may perform a refresh operation on the first physical unit OB. Specifically, since the error checking operation fails, the memory management circuit 51 may determine that the first physical unit OB has a low reliability. Therefore, the memory management circuit 51 may perform a refresh operation on the first physical unit OB. Further, the memory management circuit 51 may, for example, select a physical unit with a higher reliability from the idle area 602, move the data stored in the first physical unit OB to this physical unit, and use this physical unit to perform subsequent access operations.

[0101] According to the above, Figure 7The power-on detection method can be implemented through the following two ways: (1.) Write padding data into the open body unit OB; and (2.) Perform an update operation on the open body unit OB in a timely manner to improve the data stability and correctness of the open body unit OB, avoid jitter problems, and reduce the possibility of data loss.

[0102] Figure 11 is a flowchart of the power-on detection method shown in an exemplary embodiment of the present invention. Please refer to Figure 11 . In step S1101, when power is restored after power-off, obtain the filling start and end information corresponding to the first physical unit. In step S1102, based on the filling start and end information, determine whether the first physical unit meets the first condition or the second condition. In step S1103, if it meets the first condition or the second condition, perform a read operation on the first word line of the first physical unit, and determine whether the read operation meets the third condition. In step S1104, if it meets the third condition, use the data stored in the first word line as padding data, write the padding data into the first physical unit, and update the filling start and end information. In step S1105, perform an error check operation on the first physical unit. In step S1106, if the error check operation fails, perform an update operation on the first physical unit.

[0103] However, Figure 11 The steps in have been described in detail above and will not be elaborated here. It should be noted that Figure 11 The steps in can be implemented as multiple pieces of code or circuits, which are not limited in the present invention. In addition, Figure 11 The method of can be used in combination with the above embodiments or alone, which is not limited in the present invention.

[0104] In summary, the power-on detection method and the memory storage device proposed in the exemplary embodiments of the present invention can, when power is restored after power-off, write the data stored in a specific word line as padding data into the open body unit before performing an error check operation on the open body unit, thereby reducing the occurrence of jitter problems and improving the data stability and correctness of the rewritable non-volatile memory module. In addition, an update operation can be performed on the open body unit in a timely manner to improve the reliability of the rewritable non-volatile memory module.

[0105] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power-on detection method, characterized in that: For a rewritable non-volatile memory module, the rewritable non-volatile memory module includes a plurality of physical units, and the power-on detection method includes: When power is turned on again after power failure, the filling start and end information corresponding to the first entity unit is obtained; Based on the filling start and end information, determining whether the first entity unit meets the first condition or the second condition; If the first condition or the second condition is met, performing a read operation on the first word line of the first physical unit, and determining whether the read operation meets a third condition; If the third condition is met, the data stored in the first word line is used as filling data, the filling data is written into the first physical unit, and the filling start and end information is updated; performing an error checking operation on the first physical unit; and If the error checking operation fails, an updating operation is performed on the first physical unit.

2. The power-on detection method according to claim 1, further comprising: If the filling start and end information does not exist, the read operation is performed on the first word line.

3. The power-on detection method according to claim 1, further comprising: If the third condition is not met, the update operation is performed on the first entity unit.

4. The power-on detection method according to claim 1, further comprising: If the error checking operation is successful, a subsequent access operation is performed on the first physical unit. 5 . The power-on detection method according to claim 1 , wherein the filling start and end information is used to indicate a starting physical programming unit and an ending physical programming unit in the first physical unit for storing the filling data.

6. The power-on detection method according to claim 5, wherein the starting physical programming unit is the Xth physical programming unit in the first physical unit, the ending physical programming unit is the Yth physical programming unit in the first physical unit, the first unwritten physical programming unit in the first physical unit is the Nth physical programming unit in the first physical unit, and X, Y and N are all positive integers. The step of determining whether the first entity unit meets the first condition or the second condition comprises: If X is less than Y and Y is not equal to N-1, it is determined that the first condition is met; as well as If X is greater than Y, it is determined that the second condition is met.

7. The power-on detection method according to claim 6, wherein the error checking operation comprises a first error checking operation and a second error checking operation, The first error checking operation is performed on the first physical programming unit to the N-1th physical programming unit of the first physical unit, and The second error checking operation is performed on the first physical programming unit to the X-1th physical programming unit of the first physical unit.

8. The power-on detection method according to claim 7, wherein If the first condition is met, the error checking operation is the first error checking operation, and If the second condition is met, the error checking operation is the second error checking operation.

9. The power-on detection method according to claim 7, further comprising: If the first condition and the second condition are not met, the second error checking operation is performed on the first physical unit.

10. The power-on detection method according to claim 1, wherein the step of determining whether the read operation meets the third condition comprises: If no uncorrectable error correction code is generated, it is determined that the third condition is met. 11 . The power-on detection method according to claim 1 , wherein the first word line is a previous written word line of a first unwritten physical programmed cell of the first physical cell. 12 . The power-on detection method according to claim 1 , wherein the first entity unit is an open entity unit.

13. A memory storage device, characterized in that: include: A connection interface unit for coupling to a host system; A rewritable non-volatile memory module includes a plurality of physical units; as well as A memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: When power is turned on again after power failure, the filling start and end information corresponding to the first entity unit is obtained; Based on the filling start and end information, determining whether the first entity unit meets the first condition or the second condition; If the first condition or the second condition is met, performing a read operation on the first word line of the first physical unit, and determining whether the read operation meets a third condition; If the third condition is met, the data stored in the first word line is used as filling data, the filling data is written into the first physical unit, and the filling start and end information is updated; performing an error checking operation on the first physical unit; as well as If the error checking operation fails, an updating operation is performed on the first physical unit. 14 . The memory storage device according to claim 13 , wherein if the fill start and end information does not exist, the memory control circuit unit is further configured to perform the read operation on the first word line. 15 . The memory storage device according to claim 13 , wherein if the third condition is not met, the memory control circuit unit is further configured to perform the update operation on the first physical unit. 16 . The memory storage device according to claim 13 , wherein if the error checking operation is successful, the memory control circuit unit is further configured to perform a subsequent access operation on the first physical unit. 17 . The memory storage device according to claim 13 , wherein the filling start and end information is used to indicate a starting physical programming unit and an ending physical programming unit in the first physical unit for storing the filling data.

18. The memory storage device of claim 17, wherein the starting physical programming unit is the Xth physical programming unit in the first physical units, the ending physical programming unit is the Yth physical programming unit in the first physical units, the first unwritten physical programming unit in the first physical units is the Nth physical programming unit in the first physical units, and X, Y and N are all positive integers. in, If X is less than Y and Y is not equal to N-1, the memory control circuit unit is further configured to determine that the first physical unit meets the first condition, and If X is greater than Y, the memory control circuit unit is further configured to determine whether the first physical unit meets the second condition.

19. The memory storage device of claim 18, wherein the error checking operation comprises a first error checking operation and a second error checking operation, The first error checking operation is performed on the first physical programming unit to the N-1th physical programming unit of the first physical unit, and The second error checking operation is performed on the first physical programming unit to the X-1th physical programming unit of the first physical unit.

20. The memory storage device of claim 19, wherein If the first condition is met, the error checking operation is the first error checking operation, and If the second condition is met, the error checking operation is the second error checking operation.

21. The memory storage device of claim 19, wherein if the first condition and the second condition are not met, the memory control circuit unit is further configured to perform the second error checking operation on the first physical unit.

22. The memory storage device according to claim 13, wherein if an uncorrectable ECC is not generated, the memory control circuit unit is further configured to determine that the read operation meets the third condition. 23 . The memory storage device of claim 13 , wherein the first word line is a previous written word line of a first unwritten physical programmed cell of the first physical cell.

24. The memory storage device of claim 13, wherein the first solid cell is an open solid cell.

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