Error checking and correcting circuit and memory

Abstract

The invention provides an error checking and correcting circuit and a memory, and the circuit comprises a first time sequence regulation and control circuit, a second time sequence regulation and control circuit, a reading amplification circuit, an operational circuit, a time sequence matching circuit and a latch circuit, the time delay and the wiring time delay of the first time sequence regulation and control circuit, the reading amplification circuit and the operation circuit are matched through the second time sequence regulation and control circuit and the time sequence matching circuit, so that the time delays of control signals and operation time in the circuits are basically close under different process angle, voltage and temperature conditions, and the waiting time can be shortened; the read-out error correction efficiency of the circuit is improved while asynchronous data signal acquisition is completed, the circuit structure is simple, the used circuit area is small, and the time sequence matching circuit does not involve winding on the circuit layout, so that the time delay effect close to the circuit can be obtained on the premise that wiring matching is not performed, and the circuit reliability is improved. And meanwhile, a part of area is saved, and the flexibility is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of memories, and particularly to an error checking and correcting circuit and a memory. Background Art

[0002] Error Checking and Correcting (ECC, also known as "error correction code") circuits have been widely used in memories. They can not only detect memory errors, but also indicate the position of the error in the data (i.e., the bit position), and correct it to the correct value. Specifically, when writing data, the ECC circuit calculates information called "error correction code (ECC)" for the written data, and the calculated ECC is stored in the storage space of the memory. When reading data, the ECC circuit checks and corrects the error of the read data with reference to the pre-calculated ECC. Since the operation time of ECC is generally long, in order to prevent the encoding and error correction processes from having too much impact on the read and write time, how to accurately match the ECC control signal and the ECC result to reduce the waiting time is a key factor in improving the efficiency of the ECC circuit and is also one of the hot issues that those skilled in the art urgently need to solve. Summary of the Invention

[0003] The purpose of the present invention is to provide an error checking and correcting circuit and a memory, which can improve the circuit efficiency.

[0004] To achieve the above purpose, the present invention provides an error checking and correcting circuit, which includes:

[0005] A first timing control circuit, whose input terminal is coupled to a first reading signal, and whose output terminal outputs a second reading signal with a delay relative to the first reading signal;

[0006] A sense amplifier circuit, whose input terminal is coupled to the output terminal of the first timing control circuit, whose first output terminal outputs the read data signal, and whose second output terminal outputs the corresponding error correction code signal;

[0007] A second timing control circuit, whose input terminal is coupled to the first reading signal or the second reading signal, and whose output terminal outputs a first control signal, the first control signal having a delay relative to the first reading signal and matching the data output time of the sense amplifier circuit;

[0008] An arithmetic circuit, whose first input terminal is coupled to the first output terminal of the sense amplifier circuit, whose second input terminal is coupled to the second output terminal of the sense amplifier circuit, and whose output terminal outputs the data signal after error correction code checking and error correction;

[0009] A timing matching circuit, whose input end is coupled to the output end of the second timing regulation circuit, and whose output end outputs a second control signal, where the second control signal has a delay relative to the first control signal and matches the operation time of the arithmetic circuit;

[0010] A latch circuit, whose data input end is coupled to the output end of the arithmetic circuit, whose clock input end is coupled to the output end of the timing matching circuit, and whose output end outputs a data signal that has been checked and error-corrected by the error correction code signal under the control of the second control signal.

[0011] Optionally, the first timing regulation circuit includes at least two cascaded first timing regulation units, and the first timing regulation unit includes a first multiplexer and a first delay chain. The input end of the first delay chain is the input end of the first timing regulation unit and is coupled to the first input end of the first multiplexer, the output end of the first delay chain is coupled to the second input end of the first multiplexer, and the output end of the first multiplexer is the output end of the first timing regulation unit.

[0012] Optionally, the second timing regulation circuit includes a third delay chain and at least two cascaded second timing regulation units. The second timing regulation unit includes a second multiplexer and a second delay chain. The input end of the second delay chain is the input end of the second timing regulation unit and is coupled to the first input end of the second multiplexer, the output end of the second delay chain is coupled to the second input end of the second multiplexer, and the output end of the second multiplexer is the output end of the second timing regulation unit. Moreover, the output end of the last second timing regulation unit is further coupled to the input end of the third delay chain, and the output end of the third delay chain is the output end of the second timing regulation circuit.

[0013] Optionally, the arithmetic circuit includes an encoding circuit and a decoding circuit. The input end of the encoding circuit is coupled to the first output end of the sense amplifier circuit, the output end of the encoding circuit is coupled to the second input end of the decoding circuit, the first input end of the decoding circuit is coupled to the second output end of the sense amplifier circuit, and the output end of the decoding circuit is the output end of the arithmetic circuit.

[0014] Optionally, the encoding circuit and / or the decoding circuit is composed of at least one stage of exclusive-OR gates.

[0015] Optionally, the encoding circuit includes first to sixth exclusive-OR gates. Two input terminals of the first to third exclusive-OR gates are both coupled to the first output terminal of the sense amplifier circuit. The output terminal of the first exclusive-OR gate is coupled to the first input terminal of the fourth exclusive-OR gate. The output terminal of the second exclusive-OR gate is coupled to the second input terminal of the fourth exclusive-OR gate and the first input terminal of the fifth exclusive-OR gate. The output terminal of the third exclusive-OR gate is coupled to the second input terminal of the fifth exclusive-OR gate. The output terminal of the fourth exclusive-OR gate is coupled to the first input terminal of the sixth exclusive-OR gate. The output terminal of the fifth exclusive-OR gate is coupled to the second input terminal of the sixth exclusive-OR gate. The output terminal of the sixth exclusive-OR gate is coupled to the second input terminal of the decoding circuit.

[0016] Optionally, the decoding circuit includes a seventh exclusive-OR gate. The first input terminal of the seventh exclusive-OR gate is the first input terminal of the decoding circuit. The second input terminal of the seventh exclusive-OR gate is the second input terminal of the decoding circuit. The output terminal of the seventh exclusive-OR gate is the output terminal of the decoding circuit.

[0017] Optionally, the timing matching circuit includes a fourth delay chain, and its delay matches the operation time of the arithmetic circuit.

[0018] Optionally, the first timing control circuit, the second timing control circuit, the sense amplifier circuit, the arithmetic circuit, and the timing matching circuit are all constructed using MOS transistors. The MOS transistors in the first timing control circuit and the second timing control circuit have a first threshold voltage, and the MOS transistors in the timing matching circuit and the arithmetic circuit have a second threshold voltage. The first threshold voltage is higher than the second threshold voltage.

[0019] Optionally, the MOS transistors in the arithmetic circuit have a first channel length, and the MOS transistors in the timing matching circuit have a second channel length. The first channel length is less than the second channel length.

[0020] Based on the same inventive concept, the present invention also provides a memory, which includes a storage array and the error checking and correcting circuit as described in the present invention coupled thereto.

[0021] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0022] 1. Using less circuit area and a simple circuit structure, a better match can be obtained between the second control signal (i.e., a kind of ECC control signal) and the output of the arithmetic circuit (i.e., the ECC result), thereby reducing the waiting time and improving the circuit efficiency.

[0023] 2. The timing matching circuit is used to match the signal trace delay and operation delay in the reading amplifier circuit and the operation circuit. Moreover, the timing matching circuit does not involve wire winding in the circuit layout. Thus, without performing trace matching, a delay effect close to that of the circuit itself can be obtained, while saving a part of the area and enhancing flexibility.

[0024] 3. For the sake of operation speed, the MOS transistors with low threshold voltage are used in the operation circuit of ECC. Therefore, the same type of MOS transistors are also used in the timing matching circuit for matching its delay.

[0025] 4. A delay chain is provided in the corresponding circuit. Furthermore, the delay length of the delay chain can be adjusted by adjusting the number of MOS transistors connected thereto, thus enabling convenient adjustment and having good flexibility.

[0026] 5. On the premise of equal delay, the MOS transistor length of the timing matching circuit is relatively increased compared with that of the operation circuit. This requires a smaller circuit area than increasing the number of MOS transistors, and the convergence of different process corners is also better. In addition, choosing MOS transistors with longer length to implement the delay chain has the following advantages: (1) The convergence of the formed delay chain is close to the overall convergence of ECC calculation + trace; (2) It is relatively easy to construct delay modules that are integer multiples of 100 ps, which is convenient for circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0028] Figure 1 is a schematic diagram of an example architecture of the error checking and correcting circuit in a specific embodiment of the present invention.

[0029] Figure 2 is a schematic diagram of an example circuit structure of the first timing control circuit in the error checking and correcting circuit in a specific embodiment of the present invention.

[0030] Figure 3A and Figure 3B are respectively two schematic diagrams of example circuit structures of the second timing control circuit in the error checking and correcting circuit in a specific embodiment of the present invention.

[0031] Figure 4 is a schematic diagram of an example circuit structure of the operation circuit in the error checking and correcting circuit in a specific embodiment of the present invention.

[0032] Figure 5 is a schematic diagram of an example circuit structure of the timing matching circuit in the error checking and correcting circuit in a specific embodiment of the present invention.

[0033] Figure 6 It is a schematic diagram of an example circuit structure of a latch circuit in the error checking and correcting circuit of a specific embodiment of the present invention.

[0034] Figure 7 It is a schematic diagram of a signal timing sequence of an error checking and correcting circuit of a specific embodiment of the present invention.

[0035] Figure 8 It is a schematic diagram of another example architecture of an error checking and correcting circuit of a specific embodiment of the present invention.

[0036] Figure 9 It is a schematic diagram of an example architecture of a memory of a specific embodiment of the present invention. Specific embodiments

[0037] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete, and to fully convey the scope of the present invention to those skilled in the art. Like reference numerals refer to like elements throughout. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0038] Please refer to Figure 1 , an embodiment of the present invention provides an error checking and correcting circuit, which includes a first timing control circuit 11, a second timing control circuit 12, a sense amplifier circuit (which can be abbreviated as "SSA") 13, an arithmetic circuit 14, a timing matching circuit 15 and a latch circuit 16. The arithmetic circuit 14 includes an encoding circuit 141 and a decoding circuit 142.

[0039] Among them, please combine Figure 1, the input terminal of the first timing control circuit 11 is coupled to the first reading signal DPAPB, and the output terminal of the first timing control circuit 11 is coupled to the input terminal of the reading amplifier circuit 13. The first timing control circuit 11 is configured to generate and output a second reading signal RDSSA based on the received first reading signal DPAPB, and the second reading signal RDSSA has a delay relative to the first reading signal DPAPB. Please refer to Figure 7 , in an example, the rising edge of the second reading signal RDSSA is delayed by t1 compared to the falling edge of the first reading signal DPAPB.

[0040] Please combine with Figure 1 , the reading amplifier circuit 13 has a first output terminal and a second output terminal. The first output terminal of the reading amplifier circuit 13 is coupled to the input terminal of the encoding circuit 141 in the arithmetic circuit 14, and the second output terminal of the reading amplifier circuit 13 is coupled to the input terminal of the decoding circuit 141 in the arithmetic circuit 14. In an example, the information stored in the memory includes data bits and error correction code bits. The reading amplifier circuit 13 can be a string of sense amplifiers (SA), which generally includes a sense amplifier (not shown) capable of outputting a data signal DATA (i.e., the value on the data bit) based on the second reading signal RDSSA and a sense amplifier (not shown) capable of outputting an error correction code signal DATA_ECC_RD (i.e., the value on the error correction code bit) based on the second reading signal RDSSA. Thus, the reading amplifier circuit 13 can output the read data signal DATA from its first output terminal and the read error correction code signal DATA_ECC_RD from its second output terminal according to the second reading signal RDSSA. It should be understood that the reading amplifier circuit 13 itself will introduce a delay effect, that is, the output signal will have a certain delay relative to the received signal. Please refer to Figure 7 , the data signal DATA and the error correction code signal DATA_ECC_RD output by the reading amplifier circuit 13 are synchronously output, and both have a delay of t2 compared to the rising edge of the second reading signal RDSSA.

[0041] The input terminal of the second timing control circuit 12 is coupled to the output terminal of the first timing control circuit 11, and the output terminal of the second timing control circuit 12 is coupled to the output terminal of the timing matching circuit 15. The second timing control circuit 12 is configured to match the delay difference of the reading amplifier circuit 13 itself during the chip production process and the delay generated when the reading amplifier circuit 13 is working, and is configured to generate and output a first control signal RDECC based on the received second reading signal RDSSA. Thus, the first control signal RDECC has a delay compared to the first reading signal DPAPB, and this delay can match the output time of the reading amplifier circuit 13. Please refer to Figure 7, the rising edge of the first control signal RDECC has a delay t5 relative to the falling edge of the first reading signal DPAPB, that is, the rising edge of the first control signal RDECC is advanced or delayed by |t5 - t1| relative to the rising edge of the second reading signal RDSSA. In other embodiments of the present invention, please refer to Figure 8 , the input end of the second timing control circuit 12 can be directly coupled to the first reading signal DPAPB, and thus the first control signal RDECC is directly generated according to the first reading signal DPAPB.

[0042] The input end of the encoding circuit 141 in the arithmetic circuit 14 serves as the first input end of the arithmetic circuit 14 and is coupled to the first output end of the sense amplifier circuit 13. The output end of the encoding circuit 141 is coupled to the second input end of the decoding circuit 142 in the arithmetic circuit 14. The encoding circuit 141 is used to generate an error correction code encoding signal ECC_ENCODE according to the data signal DATA read by the sense amplifier circuit 13, and the error correction code encoding signal ECC_ENCODE has a delay relative to the data signal DATA. Please refer to Figure 7 , the rising edge of the error correction code encoding signal ECC_ENCODE has a delay t3 relative to the data signal DATA.

[0043] The first input end of the decoding circuit 142 serves as the second input end of the arithmetic circuit 14 and is coupled to the second output end of the sense amplifier circuit 13. The output end of the decoding circuit 142 serves as the output end of the arithmetic circuit 14 and is coupled to the data input end of the latch circuit 16. The decoding circuit 142 uses the error correction code signal DATA_ECC_RD read by the sense amplifier circuit 13 to check and correct the error correction code encoding signal ECC_ENCODE output by the encoding circuit 141, thereby completing the check and correction of the error in the data signal DATA read by the sense amplifier circuit 13, and then generating and outputting a data signal ECC_FLX that has been checked and corrected by the error correction code signal DATA_ECC_RD. Please refer to Figure 7 , the data signal ECC_FLX output by the decoding circuit 142 has a delay t4 relative to the error correction code encoding signal ECC_ENCODE.

[0044] The output end of the timing matching circuit 15 is coupled to the clock input end of the latch circuit 16. The arithmetic circuit 14 usually involves relatively long signal traces, which will generate two parts of delay: the arithmetic time and the signal trace time. The main purpose of setting the timing matching circuit 15 is to match the arithmetic time of the arithmetic circuit 14. Specifically, the timing matching circuit 15 is used to generate and output a second control signal RD_ECC_DONE according to the first control signal RDECC received by it. The second control signal RD_ECC_DONE has a delay compared to the first control signal RDECC, and this delay can match the arithmetic time of the arithmetic circuit 14. Please refer to Figure 7, the rising edge of the second control signal RD_ECC_DONE has a delay t6 compared to the rising edge of the first control signal RDECC. Among them, ensuring that t5 + t6 is slightly greater than t1 + t2 + t3 + t4 can maximize the working efficiency of the error checking and correcting circuit, reduce the blank time between the end of the operation of the arithmetic circuit 14 and the start of the work of the second control signal RD_ECC_DONE. Thus, it can make the second control signal RD_ECC_DONE and the operation result output by the arithmetic circuit 14 (i.e., ECC_FLX) obtain a better matching effect under different process corners, voltages, and temperatures, reduce the waiting time of the error checking and correcting circuit, and improve the working efficiency of the error checking and correcting circuit.

[0045] The latch circuit 16 is used to release the data signal ECC_FLX under the control of the second control signal RD_ECC_DONE.

[0046] Please combine Figures 1 to 6 and Figure 7 , the working principle of the error checking and correcting circuit of this embodiment is: when the reading signal DRAPB is sent from the first timing control circuit 11, one path passes through the reading amplifier circuit 13 and the arithmetic circuit 14 for data checking and error correction, and the total time of this path is t1 + t2 + t3 + t4. Another path passes through the second timing control circuit 12 and the timing matching circuit 15 for timing matching. The second timing control circuit 12 can match the output time of the reading amplifier circuit 13, and the timing matching circuit 15 can match the exclusive OR gate calculation time in the arithmetic circuit 14. The total time of this path is t5 + t6. Ensuring that t5 + t6 is slightly greater than t1 + t2 + t3 + t4 can finally make the second control signal RD_ECC_DONE received by the clock input terminal of the latch circuit 16 stably acquire the correct data, thereby maximizing the working efficiency of the error checking and correcting circuit and reducing the blank time between the end of the operation of the arithmetic circuit 14 and the start of the work of the second control signal (i.e., reducing the waiting time of the error checking and correcting circuit).

[0047] It should be understood that in this embodiment, the first timing control circuit 11, the second timing control circuit 12, the reading amplifier circuit 13, the encoding circuit 141, the decoding circuit 142, the timing matching circuit 15, and the latch circuit 16 can adopt any suitable circuit design, and the present invention does not make specific limitations on this.

[0048] Preferably, the first timing control circuit 11, the second timing control circuit 12, the reading amplifier circuit 13, the encoding circuit 141, the decoding circuit 142, the timing matching circuit 15, and the latch circuit 16 all use MOS transistors to construct logic gates, thereby realizing their corresponding functions and delays.

[0049] In one example, the widths of the MOS transistors in each circuit are the same. The MOS transistors in the first timing control circuit 11 and the second timing control circuit 12 have a high threshold voltage, slow response but low leakage. The MOS transistors in the arithmetic circuit 14 and the timing matching circuit 15 have a low threshold voltage. That is, the MOS transistors used in the first timing control circuit 11 and the second timing control circuit 12 are high-threshold-voltage MOS transistors (i.e., ntnm transistors), which have a first threshold voltage VTH1. The MOS transistors used in the timing matching circuit 15 and the arithmetic circuit 14 are low-threshold-voltage MOS transistors (i.e., ntnlv transistors), which have a second threshold voltage VTH2, and VTH1 > VTH2. That is, for the consideration of the arithmetic speed, all the MOS transistors used in the arithmetic circuit 14 are low-threshold-voltage MOS transistors. Therefore, the timing matching circuit 15 used to match its delay also uses the same type of MOS transistors. Thus, the arithmetic speed of the arithmetic circuit 14 can be guaranteed, and on the path from the first reading signal DPAPB to the output of the second control signal RD_ECC_DONE, a part of high-threshold-voltage MOS transistors are mixed to trim the overall delay of the error checking and correcting circuit, and a delay amount close to the gate-level delay and routing delay of the mixed devices can be obtained under different process corners, voltages and temperatures. Furthermore, the latch circuit in the error checking and correcting circuit can accurately collect the target data under the control of the second control signal RD_ECC_DONE, improving the working efficiency of the error checking and correcting circuit.

[0050] Furthermore, the MOS transistors in the arithmetic circuit 14 have a first channel length L1 (for example, 200 nm), and the MOS transistors in the timing matching circuit 15 have a second channel length L2 (for example, 380 nm), and L1 < L2. Thus, on the premise of equal delay, the channel length of the MOS transistors in the timing matching circuit 15 is relatively increased compared with that of the arithmetic circuit 14. This requires a smaller circuit area compared with increasing the number of MOS transistors, and the convergence of different process corners is also better. In addition, when the timing matching circuit 15 selects MOS transistors with a longer length to implement the delay chain, the following advantages can also be achieved: (1) The convergence of the delay chain composed of MOS transistors in the timing matching circuit 15 is close to the convergence of the arithmetic circuit 14 and the overall routing; (2) It is relatively easy to construct a delay chain that is an integer multiple of 100 ps, which is convenient for circuit design.

[0051] That is to say, in the timing matching circuit 15, MOS transistors with a larger length and a lower threshold voltage (i.e., ntnlv transistors) are used to construct a delay chain, so that the overall timing matching circuit 15 does not involve wire routing in the circuit layout, and the gate-level delay can be used to match the operation time and the wiring delay in the arithmetic circuit 14. Furthermore, a delay effect close to that of the circuit itself can be obtained without performing wire routing matching, and the convergence of different process corners is also better. In addition, on the premise of equal delay, increasing the length of the MOS transistor requires a smaller circuit area than increasing the number of MOS transistors. Therefore, a part of the circuit area is also saved, and the flexibility is improved.

[0052] Optionally, please refer to Figure 2 , the first timing control circuit 11 includes at least two cascaded first timing control units 11a. The first timing control unit 11a includes a first multiplexer Mux1 and a first delay chain 110. The input end of the first delay chain 110 is the input end of the first timing control unit 11a and is coupled to the first input end "0" of the first multiplexer Mux1 in the first timing control unit 11a. The output end of the first delay chain 110 is coupled to the second input end "1" of the first multiplexer Mux1 in the first timing control unit 11a. The output end of the first multiplexer Mux1 is the output end of the first timing control unit 11a. Among them, the first delay chain 110 may include at least two cascaded delay circuits ta.

[0053] Further optionally, each delay circuit ta is a CMOS logic gate (such as a NOT gate, etc.) constructed by MOS transistors with a high threshold voltage, slow response, and small leakage. Thus, by adjusting the number of MOS transistors connected in the first delay chain 110, different delay magnitudes of the first delay chain 110 can be obtained. In an example, the first timing control circuit 11 includes at least two cascaded first timing control units 11a, and the first delay chain 110 in each first timing control unit 11a also includes at least two delay circuits ta.

[0054] Further optionally, the first multiplexer Mux1 is a CMOS logic gate constructed by MOS transistors with a high threshold voltage, slow response, and small leakage, and it can be an AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate, an XNOR gate, etc.

[0055] Optionally, in an example, please refer to Figure 3A, the second timing control circuit 12 includes a third delay chain 121 and at least two cascaded second timing control units 12a. The second timing control unit 12a includes a second multiplexer Mux2 and a second delay chain 120. The input end of the second delay chain 120 is the input end of the second timing control unit 12a and is coupled to the first input end "0" of the second multiplexer Mux2 in the second timing control unit 12a. The output end of the second delay chain 120 is coupled to the second input end "1" of the second multiplexer Mux2 in the second timing control unit 12a. The output end of the second multiplexer Mux2 is the output end of the second timing control unit 12a and is coupled to the input end of the third delay chain 121. The output end of the third delay chain 121 is the output end of the second timing control circuit 12. The input end of the second delay chain 120 in the first-stage second timing control unit 12a is the input end of the second timing control circuit 12 (this input end receives a reading signal, such as the first reading signal DPAPB or the second reading signal RDSSA as described above). Among them, both the second delay chain 120 and the third delay chain 121 may include at least two cascaded delay circuits tb; among them, the number of stages of the delay circuit tb in the third delay chain 121 matches the delay of the sense amplifier circuit 13.

[0056] Further optionally, each delay circuit tb is a CMOS logic gate (such as an inverter, etc.) constructed by MOS transistors with a high threshold voltage, slow response, and low leakage. Thus, by adjusting the number of MOS transistors connected in the second delay chain 120, different delay magnitudes of the second delay chain 120 can be obtained. By adjusting the number of MOS transistors connected in the third delay chain 121, different delay magnitudes of the third delay chain 121 can be obtained. In one example, the second timing control circuit 12 includes at least two cascaded second timing control units 12a. The second delay chain 120 in each second timing control unit 12a also includes at least two delay circuits tb, and the third delay chain 121 also includes at least two delay circuits tb. In one example, the circuit design of the delay circuit tb is the same as that of the above-mentioned delay circuit ta. Further, in Figure 8 the embodiment where the input end of the second timing control circuit 12 shown receives the first reading signal DPAPB, the delay design of the second timing control unit 12a is to match the delay of the first timing control circuit 11 and the delay difference of the sense amplifier circuit 13 itself during the chip production process. In Figure 3A the embodiment where the input end of the second timing control circuit 12 shown receives the second reading signal RDSSA, the delay design of the second timing control unit 12a is to only match the delay difference of the sense amplifier circuit 13 itself during the chip production process.

[0057] Further optionally, the second multiplexer Mux2 may be a CMOS logic gate constructed by MOS transistors with a high threshold voltage, slow response, and low leakage. It may be an AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate, an XNOR gate, etc. In one example, the second multiplexer Mux2 and the above-mentioned first multiplexer Mux1 adopt the same circuit design.

[0058] In another example, please refer to Figure 3B , and according to the need for delay matching, the second timing control unit 12a may also be omitted in the second timing control circuit 12, and only the third delay chain 121 is provided. In this example, the length of the third delay chain 121 needs to match the delay generated from the input of the first reading signal to the first timing control circuit 11 to the output of the data signal DATA by the reading amplifier circuit 13 (i.e., the sum of the delay of the first timing control circuit 11, the delay difference of the reading amplifier circuit 13 itself during chip production, and the delay of the reading amplifier circuit 13). That is, the third delay chain 121 may include at least two stages of delay circuits tb, and the number of stages of the delay circuits tb of the third delay chain 121 matches the delay generated from the input of the first reading signal to the first timing control circuit 11 to the output of the data signal DATA by the reading amplifier circuit 13 (i.e., the sum of the delay of the first timing control circuit 11, the delay difference of the reading amplifier circuit 13 itself during chip production, and the delay of the reading amplifier circuit 13).

[0059] In one example, please refer to Figure 4 , the encoding circuit 141 includes first to sixth exclusive-OR gates XOR1 to XOR6, and the decoding circuit 142 includes a seventh exclusive-OR gate XOR7. Among them, both input terminals of the first to third exclusive-OR gates XOR1 to XOR3 are coupled to the first output terminal of the reading amplifier circuit 13. The output terminal of the first exclusive-OR gate XOR1 is coupled to the first input terminal of the fourth exclusive-OR gate XOR4. The output terminal of the second exclusive-OR gate XOR2 is coupled to the second input terminal of the fourth exclusive-OR gate XOR4 and the first input terminal of the fifth exclusive-OR gate XOR5. The output terminal of the third exclusive-OR gate XOR3 is coupled to the second input terminal of the fifth exclusive-OR gate XOR5. The output terminal of the fourth exclusive-OR gate XOR4 is coupled to the first input terminal of the sixth exclusive-OR gate XOR6. The output terminal of the fifth exclusive-OR gate XOR5 is coupled to the second input terminal of the sixth exclusive-OR gate XOR6. The output terminal of the sixth exclusive-OR gate XOR6 is coupled to the second input terminal of the seventh exclusive-OR gate XOR7. The first input terminal of the seventh exclusive-OR gate XOR7 is the first input terminal of the decoding circuit 141, the second input terminal of the seventh exclusive-OR gate XOR7 is the second input terminal of the decoding circuit 142, and the output terminal of the seventh exclusive-OR gate XOR7 is the output terminal of the decoding circuit 142 (which is also the output terminal of the arithmetic circuit 14).

[0060] Optionally, the first to seventh XOR gates XOR1 to XOR7 are all constructed by the same MOS transistors with a low threshold voltage and a relatively small gate length (e.g., 200 nm).

[0061] Optionally, refer to Figure 5 , the timing matching circuit 15 includes a fourth delay chain 15a. The fourth delay chain 15a may include at least two cascaded delay circuits tc. The length of the fourth delay chain 15a of the timing matching circuit 15 needs to match the delay of the arithmetic circuit 15 (including the delay generated by its signal routing and its arithmetic time). Further optionally, each delay circuit tc is a CMOS logic gate (e.g., an inverter, etc.) constructed by MOS transistors with a low threshold voltage and a relatively long gate length. Thus, by adjusting the number of MOS transistors connected in the fourth delay chain 15a, different delay magnitudes of the fourth delay chain 15a can be obtained. In one example, the fourth delay chain 15a includes four cascaded delay circuits tc.

[0062] Among them, the encoding circuit 141 and the decoding circuit 142 in the arithmetic circuit 14 involve relatively long signal routes. When using MOS transistors with a low threshold voltage, the overall convergence is better than that of the high threshold voltage MOS transistors in the first timing control circuit 11, and the arithmetic speed is relatively good. Selecting MOS transistors with a low threshold voltage and a larger gate length (L) to construct the delay chain in the timing matching circuit 15 can obtain a delay effect close to that of the circuit itself without performing routing matching. At the same time, it saves a part of the area and improves flexibility. Moreover, it can make the overall timing matching circuit 15 not involve wire routing in the circuit layout. Thus, on the premise of equal delay, increasing the gate length of the MOS transistor requires less area than increasing the number of MOS transistors. At the same time, it can be verified that when the timing matching circuit 15 is constructed by MOS transistors with a relatively long gate length and a low threshold voltage, its delay has very close convergence to the delay of the arithmetic circuit 14 under different process corners (P), voltages (V), and temperatures (T), and can better match the arithmetic time of the arithmetic circuit 15.

[0063] Optionally, refer to Figure 6 , the latch circuit 16 includes a D flip-flop.

[0064] Optionally, some of the MOS transistors in the sense amplifier circuit 13 use the same MOS transistors as those in the first timing control circuit 11, and some of the MOS transistors use the same MOS transistors as those in the arithmetic circuit 14.

[0065] In summary, the error checking and correction circuit of the present invention can match the delays of the first timing control circuit, the sense amplifier circuit, and the arithmetic circuit and the routing delay through the second timing control circuit and the timing matching circuit, so that the delay of the output of the timing matching circuit (i.e., the second control signal) and the output of the arithmetic circuit (i.e., the operation result of the arithmetic circuit, or, the data signal after error checking and correction) is substantially close under different process corners, voltages, and temperature conditions, which can reduce the waiting time, improve the readout error correction efficiency of the circuit while completing asynchronous data signal acquisition, and the circuit structure is simple, the circuit area used is small, and the timing matching circuit does not involve routing in the circuit layout. Therefore, a delay effect close to that of the circuit itself can be obtained without performing routing matching, and at the same time, a part of the area is saved and the flexibility is improved. In addition, a delay chain is provided in the corresponding circuit, and thus, the delay length of the delay chain can be adjusted by adjusting the number of MOS transistors connected thereto, so as to achieve convenient adjustment and have good flexibility.

[0066] Based on the same inventive concept, please refer to Figure 9 , an embodiment of the present invention further provides a memory, which includes a memory array 2 and the error checking and correction circuit 1 as described in the present invention coupled thereto.

[0067] Since the memory of the present invention adopts the error checking and correction circuit described in the present invention, the circuit efficiency is improved.

[0068] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure are within the protection scope of the technical solution of the present invention.

Claims

1. An error checking and correcting circuit, characterized in that, Comprising: A first timing control circuit, whose input terminal is coupled to a first reading signal, and whose output terminal outputs a second reading signal with a delay relative to the first reading signal; A reading amplifier circuit, whose input terminal is coupled to the output terminal of the first timing control circuit, whose first output terminal outputs the read data signal, and whose second output terminal outputs a corresponding error correction code signal; A second timing control circuit, whose input terminal is coupled to the first reading signal or coupled to the second reading signal, and whose output terminal outputs a first control signal, the first control signal having a delay relative to the first reading signal and matching the data output time of the reading amplifier circuit; An arithmetic circuit, whose first input terminal is coupled to the first output terminal of the reading amplifier circuit, whose second input terminal is coupled to the second output terminal of the reading amplifier circuit, and whose output terminal outputs a data signal after being checked and error-corrected by the error correction code signal; A timing matching circuit, whose input terminal is coupled to the output terminal of the second timing control circuit, and whose output terminal outputs a second control signal, the second control signal having a delay relative to the first control signal and matching the arithmetic time of the arithmetic circuit; A latch circuit, whose data input terminal is coupled to the output terminal of the arithmetic circuit, whose clock input terminal is coupled to the output terminal of the timing matching circuit, and whose output terminal outputs a data signal after being checked and error-corrected by the error correction code under the control of the second control signal.

2. The error checking and correcting circuit according to claim 1, characterized in that, The first timing control circuit includes at least two cascaded first timing control units, the first timing control unit includes a first multiplexer and a first delay chain, the input terminal of the first delay chain is the input terminal of the first timing control unit and is coupled to the first input terminal of the first multiplexer, the output terminal of the first delay chain is coupled to the second input terminal of the first multiplexer, and the output terminal of the first multiplexer is the output terminal of the first timing control unit.

3. The error checking and correcting circuit according to claim 1, characterized in that, The second timing control circuit includes a third delay chain and at least two cascaded second timing control units, the second timing control unit includes a second multiplexer and a second delay chain, the input terminal of the second delay chain is the input terminal of the second timing control unit and is coupled to the first input terminal of the second multiplexer, the output terminal of the second delay chain is coupled to the second input terminal of the second multiplexer, the output terminal of the second multiplexer is the output terminal of the second timing control unit, and the output terminal of the last second timing control unit is further coupled to the input terminal of the third delay chain, and the output terminal of the third delay chain is the output terminal of the second timing control circuit.

4. The error checking and correcting circuit according to claim 1, characterized in that The arithmetic circuit includes an encoding circuit and a decoding circuit, the input terminal of the encoding circuit is coupled to the first output terminal of the reading amplifier circuit, the output terminal of the encoding circuit is coupled to the second input terminal of the decoding circuit, the first input terminal of the decoding circuit is coupled to the second output terminal of the reading amplifier circuit, and the output terminal of the decoding circuit is the output terminal of the arithmetic circuit.

5. The error checking and correcting circuit according to claim 4, characterized in that, The encoding circuit and / or the decoding circuit is composed of at least one stage of exclusive-OR gates.

6. The error checking and correcting circuit according to claim 5, characterized in that, The encoding circuit includes first to sixth exclusive-OR gates. Two input terminals of the first to third exclusive-OR gates are both coupled to the first output terminal of the sense amplifier circuit. The output terminal of the first exclusive-OR gate is coupled to the first input terminal of the fourth exclusive-OR gate. The output terminal of the second exclusive-OR gate is coupled to the second input terminal of the fourth exclusive-OR gate and the first input terminal of the fifth exclusive-OR gate. The output terminal of the third exclusive-OR gate is coupled to the second input terminal of the fifth exclusive-OR gate. The output terminal of the fourth exclusive-OR gate is coupled to the first input terminal of the sixth exclusive-OR gate. The output terminal of the fifth exclusive-OR gate is coupled to the second input terminal of the sixth exclusive-OR gate. The output terminal of the sixth exclusive-OR gate is coupled to the second input terminal of the decoding circuit.

7. The error checking and correcting circuit according to claim 5, characterized in that, The decoding circuit includes a seventh exclusive-OR gate. The first input terminal of the seventh exclusive-OR gate is the first input terminal of the decoding circuit. The second input terminal of the seventh exclusive-OR gate is the second input terminal of the decoding circuit. The output terminal of the seventh exclusive-OR gate is the output terminal of the decoding circuit.

8. The error checking and correcting circuit according to claim 1, wherein The timing matching circuit includes a fourth delay chain, and its delay is matched with the operation time of the arithmetic circuit.

9. The error checking and correcting circuit according to any one of claims 1-8, characterized in that, The first timing control circuit, the second timing control circuit, the sense amplifier circuit, the arithmetic circuit, and the timing matching circuit all use MOS transistors to construct logic gates. And the MOS transistors in the first timing control circuit and the second timing control circuit have a first threshold voltage, the MOS transistors in the timing matching circuit and the arithmetic circuit have a second threshold voltage, and the first threshold voltage is higher than the second threshold voltage.

10. The error checking and correcting circuit according to any one of claims 1-8, characterized in that, The MOS transistors in the arithmetic circuit have a first channel length, and the MOS transistors in the timing matching circuit have a second channel length, and the first channel length is less than the second channel length.

11. A memory, characterized in that, It includes a memory array and the error checking and correcting circuit as described in any one of claims 1-10 coupled thereto.

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