Analog-to-digital converter circuit, corresponding system and method

Abstract

Embodiments of this disclosure relate to analog-to-digital converter circuits, corresponding systems, and methods. In one embodiment, a circuit includes N sensing channels. Each channel includes a pair of first primary sensing nodes and second redundant sensing nodes. N analog-to-digital converters (ADCs) are coupled to the first sensing nodes, wherein digital processing circuitry is coupled to the N ADCs. A pair of multiplexers are coupled to the second sensing nodes and to the N ADCs, wherein another ADC is coupled to the output of the second multiplexer. Error checking circuitry is coupled to the output of the second multiplexer, and the other ADC compares a first digital value with a second digital value at each of a series of N time windows, the digital value being generated by a digital conversion of an analog sensing signal at one of the first sensing nodes and an analog sensing signal at a second sensing node paired with the selected first sensing node.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Italian Patent Application No. 102020000026678, filed on 9 November 2020, which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to electronic systems and methods, and in particular embodiments to an analog-to-digital converter (ADC) circuit, a corresponding system, and a method. Background Technology

[0004] High levels of safety can be expected in integrated circuits (ICs) used in drive and braking applications in the automotive industry, such as for thermal sensors.

[0005] Specifications such as ISO 26262 – Functional safety for road vehicles define risk classification schemes known as ASIL (Automotive Safety Integrity Level), which help define safety specifications that comply with ISO 26262.

[0006] ASIL (Autonomous Safety Index) protocols are established by performing a risk analysis of potential hazards by examining the severity, exposure, and controllability of the vehicle's operating scenarios.

[0007] There are currently four ASIL categories: ASIL A, ASIL B, ASIL C, and ASIL D, where ASIL D indicates the highest integrity specification and ASIL A indicates the lowest.

[0008] The conventional implementation of thermal sensors is based on an architecture that combines a small BJT (bipolar junction transistor) sensor with a high-resolution ADC, which converts a voltage signal proportional to temperature into a temperature code.

[0009] These thermal sensors can be configured, for example, to measure the temperature in the IC die and the current in the valve driver block, and provide real-time temperature information to the interpolator to achieve the desired target accuracy.

[0010] Current measurement in the valve actuator block can benefit from the independence of the low-side (LS) path and the high-side (HS) path.

[0011] To this end, the entire measurement chain, including the thermal sensor, can be made completely independent, which involves implementing redundant “thermal” ADCs, resulting in double (2x) complexity for each channel. Summary of the Invention

[0012] Some embodiments address the problems previously outlined while avoiding the increased complexity discussed above.

[0013] Some embodiments involve security checks in devices such as analog-to-digital converters (ADCs).

[0014] One or more embodiments can be applied in the automotive industry, for example, in transmission control units and brake control units for current measurement in valve actuator blocks.

[0015] One or more embodiments may relate to corresponding systems. A multi-channel valve actuator system for drive and braking applications in the automotive industry can be an example of such a system.

[0016] One or more embodiments may involve corresponding methods.

[0017] One or more embodiments may advantageously provide an architecture for measuring temperature in an IC die (e.g., in a valve driver block).

[0018] Compared to existing technologies (where N channels involve 2xN ADCs), in one or more embodiments, the ADC is associated with a corresponding master temperature sensor for each channel, and redundant temperature sensors are associated with a single shared ADC using a multiplexer.

[0019] In one or more embodiments, “redundant” temperature measurements for each redundant sensor are provided in a corresponding time frame, and real-time measurements from the main temperature sensor are provided such that N channels involve only N+1 ADCs. Attached Figure Description

[0020] For a more complete understanding of the invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein:

[0021] Figure 1 This is a block diagram illustrating an implementation of an independent HS / LS current measurement path;

[0022] Figure 2 This is a block diagram illustrating a scheme of a driver channel having a high-side FET and a low-side FET in a valve driver according to an embodiment illustrated herein; and

[0023] Figure 3 This is a possible combined block diagram example of an embodiment in the transmission control unit. Detailed Implementation

[0024] In the following description, one or more specific details are illustrated to provide a thorough understanding of examples of embodiments described herein. Embodiments may be obtained without one or more of these specific details or by utilizing other methods, components, materials, etc. In other instances, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of the embodiments will not be difficult to understand.

[0025] The reference to "embodiment" or "one embodiment" within the framework of this invention description is intended to indicate that a particular configuration, structure, or feature described with respect to an embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment," which may appear at one or more points in the description of this invention, do not necessarily refer to one or the same embodiment.

[0026] Furthermore, in one or more embodiments, a particular construction, structure, or characteristic may be combined in any suitable manner.

[0027] The headings / references used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0028] As discussed in the introductory section, drive control and brake control units for automotive applications can benefit from high safety levels (up to ASIL-D), in which a safe (alarm) state is asserted in the event of a component failure in the control unit.

[0029] It is expected that all components in the control unit, especially the ICs that provide the foundation for the entire system, will conform to such system-level specifications. In ASIL-D ICs used in drive and braking applications, as considered in this paper with the aid of examples, thermal sensors should be expected to be the first to meet this safety level.

[0030] Figure 1 This is a block diagram example of a conventional implementation of such a sensor arrangement, including sensors S1 and S2 (e.g., small CSA-certified – BJT sensors) for the high-side (HS) and low-side (LS) respectively. Sensors S1 and S2 cooperate with (high-resolution) ADCs ADC HS and ADC LS to convert a temperature-proportional voltage, as provided by sensors S1 and S2, into a temperature code.

[0031] Such thermal sensors can be configured to measure the die temperature of an integrated circuit IC (not visible in the diagram) and the current measurement in a valve actuator block to provide real-time temperature to the interpolator, thereby contributing to achieving the target accuracy.

[0032] In current measurements of the valve actuator block, the independence between the LS and HS paths can be desirable.

[0033] For this reason, such as Figure 1 The (single channel) measurement chain (i.e., including sensors S1 and S2) shown in the diagram includes (completely) independent signal paths.

[0034] like Figure 1 The independent HS and LS paths illustrated in the diagram help achieve ASIL-D compliance and independence of redundant current monitoring (where HS and LS are comparable in between).

[0035] This involves implementing independent temperature interpolation for two paths (S1, ADC HS and S2, ADC LS) in a single analog channel as illustrated, and the inherent redundancy of the temperature sensor arrangement.

[0036] For example, for a (single) digital channel to be coupled to an analog channel including two sensors S1, S2 and two ADCs (i.e., ADC HS and ADC LS), such as Figure 1 The layout shown in the diagram includes:

[0037] ADC logic circuit devices 10H (high) and 10L (low),

[0038] Filter circuit devices 12H and 12L, and

[0039] The calibration circuit devices 14H and 14L are intended to work in conjunction with the (external) calibration temperature sources 16H and 16L.

[0040] like Figure 1 The arrangement shown in the figure also includes a multiplexer 18 driven by an on-off (pulse width modulation) signal PWM to alternately supply outputs from the previously discussed high-side and low-side branches (essentially outputs from calibration circuit devices 14H and 14L) to a controller 20 (e.g., a proportional-integral or PI controller), which is sensitive to the current setpoint CS and is configured to generate the signal PWM.

[0041] The (average) value of the output from multiplexer 18 indicates the average current 18 provided by the high-side branch and low-side branch discussed earlier, and thus indicates the average temperature sensed by sensors S1 and S2, as indicated by block 22.

[0042] As illustrated, the PWM monitor circuit 24 receives the PWM feedback signal from the input analog channel to verify that the PWM signal at the output of the valve driver conforms to (e.g., is equivalent to) having a value imposed by the controller block 20 (e.g., a PI controller) with a certain error limit.

[0043] This signal can be provided by an analog comparator that compares its output voltage to the supply (battery) voltage. This can occur, for example, if the threshold has a value that is half the battery value.

[0044] This additional safety feature helps to comply with the ASIL-D specification according to ISO 26262.

[0045] The device can be configured to provide (e.g., on the SPI register) the duty cycle measured by block 24, and the microcontroller can compare it at the system level with a theoretical value set by block 20 (which can also be read from the SPI register). If the difference exceeds a certain threshold, the microcontroller can then put the system into a "safe" state.

[0046] As illustrated, comparator circuit device 26 can be coupled to the outputs from the previously discussed high-side branch and low-side branch (outputs from calibration circuit devices 14H and 14L), and has the ability to compare these two outputs (and thus the temperature values ​​sensed by sensors S1 and S2).

[0047] As illustrated, the information provided by block 24 is also used by block 26 (high-side, low-side comparison) for diagnostic purposes.

[0048] Transmission control units (TCUs) and brake control units for automotive applications can involve a high degree of architectural diversity, such as Figure 1 As shown in the diagram.

[0049] This, in turn, has a significant impact on die size. In fact, N channels involve 2xN thermal sensors (more specifically, 2xN BJT sensors, such as S1 and S2, multiplied by 2xN ADCs, such as ADC HS and ADC LS).

[0050] like Figure 1 The arrangement shown in the diagram involves the HS and LS paths, which are (completely) independent of each other to facilitate ASIL-D compliance, as well as independent redundant current monitors (e.g., to facilitate HS-LS comparison at 26) plus independent temperature interpolators for both paths.

[0051] Figure 2 The schematic diagram includes an embodiment of a valve driver with N channels, which have high-side (HS) and low-side (LS) field-effect transistors (FETs).

[0052] This drive (which can be separately retained) Figure 1 Some features of the arrangement shown in the diagram can be incorporated into, for example, the transmission control unit of passenger cars (PV) and commercial vehicles (CV). A valve actuation stage implemented in a transmission and braking control unit is an example of such a possible application.

[0053] It should also be noted that the references to which this may be applied are merely exemplary and not limiting of the embodiments. One or more embodiments can indeed be applied to circuits where a high level of safety (e.g., up to ASIL-D) is desired, which may result in redundancy for each function.

[0054] In other words, the accuracy of achieving the target entity (e.g., current) can be improved by calibrating and temperature interpolating the thermal sensor through a high-accuracy and high-resolution ADC (analog-to-digital converter).

[0055] In one or more embodiments, this ADC can be implemented redundantly by providing “physical” redundancy to the (entire) ADC structure (e.g., which helps to meet ASIL-D requirements).

[0056] One or more embodiments can achieve (full) redundancy (therefore no physical redundancy of the entire ADC) via digital signal processing, which provides benefits in terms of die size and test time savings as well as increased diagnostic coverage.

[0057] like Figure 2 The embodiment illustrated in the figure may include a number of N channels (channel 1 to channel N), each channel including two sensors S_CH_1, S_CN_1R to S_CH_N, S_CN_NR.

[0058] These sensors can be, for example, BJT (bipolar junction transistor) thermal sensors. This option can be advantageous because of its contribution to reducing the thermal sensor area, especially when compared to the larger contribution to the entire thermal sensor area provided by an ADC (i.e., ADC_1 to ADC_N), where only one ADC is used for each channel, such as... Figure 2 Zhongsuo.

[0059] The sensors in each pair can be considered as including first sensors S_CH_1 to S_CH_N and second sensors S_CN_1R to S_CN_NR, thereby providing safe redundancy for (e.g., temperature) sensing, as indicated by SR.

[0060] like Figure 2 As illustrated, the outputs from the first sensors S_CH_1 to S_CH_N are applied to the corresponding ADCs (i.e., ADC_1 to ADC_N), which can be configured to provide, for example, analog sigma-delta quantizer and digital decimator functions.

[0061] like Figure 2 As illustrated, the outputs from the second redundant sensors S_CH_1R to S_CH_NR are applied to a single common ADC (i.e., ADC_R), which can also be configured to provide, for example, analog sigma-delta quantizer and digital decimator functions.

[0062] like Figure 2As illustrated, the outputs from redundant sensors S_CH_1R to S_CH_NR are supplied to the analog-to-digital converter ADC_R via multiplexer MUX1. Multiplexer MUX1 is sensitive to a selector signal SS, which can be generated (in a manner known to those skilled in the art, via a time window selector circuit STW) to indicate a time window.

[0063] In this way, the hardware of the analog-to-digital converter (ADC_R) can be shared by N channels, each of which is adapted to be processed in a corresponding time window, as discussed below.

[0064] Due to processing in the analog-to-digital converters ADC_1 to ADC_N and ADC_R, the analog (e.g., temperature) signals from sensors S_CH_1 to S_CH_N and S_CH_1R to S_CH_NR are converted into corresponding digital signals (e.g., 8-bit codes) TEMP_CODE_1 to TEMP_CODE_N (from the converters ADC_1 to ADC_N, which are individually coupled to sensors S_CH_1 to S_CH_N) and TEMP_CODE_RED (from the common converter ADC_R, which is coupled to sensors S_CH_1R to S_CH_NR via multiplexer MUX1).

[0065] Reference numerals 101 and 102 denote two interpolators (HS and LS, respectively) that receive digital signals TEMP_CODE_1 to TEMP_CODE_N from converters ADC_1 to ADC_N. Interpolators 101 and 102 can be of any type known to those skilled in the art for the desired drive function of corresponding electrical loads such as field-effect transistors HS FET (high-side) and LS FET (low-side).

[0066] The outlines of such field-effect transistors are shown in dashed lines because these field-effect transistors (and any other electrical load driven by circuit 100) can be elements that differ from those in the embodiment.

[0067] With the help of an example, blocks 101 and 102 (which can be considered the same) can provide an error value as an output, which assumes that the measurement of the actuation current supplied to the load associated with the corresponding channel is affected at a certain temperature.

[0068] The inputs to (each) block 101, 102 may include a matrix T(C) of the current error for a certain temperature and a current value regarded as a reference, such as possibly derived from a memory block (e.g., two RAM banks) that is not visible in the figures for simplicity.

[0069] These reference values ​​can be different for each channel and differ for the high and low sides.

[0070] With the aid of examples, blocks 101 and 102 can be configured to calculate (in a manner known to those skilled in the art) the error values ​​at general temperature and current by interpolating the error values ​​starting from the reference values.

[0071] The same blocks 101 (and 102) can be repeated to scan N channels in a continuous manner. The same blocks can be repeated in 101 and 102 to provide independent calculations for the high-side (HS) and low-side (LS). In this way, two independent HS and LS measurements are available, which can be compared to confirm whether any misalignment (error) has occurred.

[0072] It will also be understood that the embodiments are very “transparent” to the specific types of processing performed in blocks such as 101 and 102.

[0073] Furthermore, regardless of the specific driving functions that may be implemented therein (in a manner known to those skilled in the art), the two interpolators 101 and 102 use the same (temperature) sensors S_CH_1 to S_CH_N and analog-to-digital converters ADC_1 to ADC_N.

[0074] like Figure 2 As shown in the diagram, the circuit operates by monitoring its common "redundant" analog-to-digital converter (ADC_R).

[0075] In one or more embodiments, this redundant converter ADC_R can be placed at the top level of an IC with the capability to multiplex via multiplexer MUX1, where signals from redundant sensors S_CH_1R to S_CH_NR are presented in each of the N channels for a certain time, which is selected (e.g., set via signal SS) to provide appropriate (e.g., temperature) measurements and to help achieve the desired FTTI (Error Tolerance Time Interval).

[0076] like Figure 2 As illustrated, digital processing circuit block 103 is configured to act as a safety ADC checker and compares the (temperature) values ​​read by the "primary" sensors S_CH_1 to S_CH_N with the corresponding values ​​read by the "redundant" sensors S_CH_1R to S_CH_NR. In principle, assuming the primary and redundant sensors are placed in corresponding locations (e.g., the same location in a semiconductor die), the values ​​should be the same.

[0077] In some embodiments, the ADC checker circuit 103 serves to reveal errors affecting any of the channels 1 to N and to indicate appropriate responses (e.g., setting the channel to a tri-state off / low-power condition). In some embodiments, the ADC checker circuit 103 may include a digital comparator.

[0078] like Figure 2As shown in the diagram, the safety ADC checker circuit 103 is configured to function for the following (compare the following):

[0079] The (digital) signal TEMP_CODE_RED is generated by the analog-to-digital conversion (at the converter ADC_D) of one of the "redundant" sensors S_CH_1R to S_CH_NR selected by the multiplexer MUX1, and varies according to the time window selection signal SS from the time window selector circuit STW.

[0080] The (digital) signal TEMP_CODE selected by the multiplexer MUX2 varies according to the time window selection signal SS from the time window selector circuit STW in the (digital) signals TEMP_CODE_1 to TEMP_CODE_N. The (digital) signals TEMP_CODE_1 to TEMP_CODE_N are generated by analog-to-digital conversion (at converters ADC_1 to ADC_N) of the signals from the "master" sensors S_CH_1 to S_CH_N.

[0081] In such Figure 2 In the circuit shown in the diagram, the operations of multiplexers MUX1 and MUX2 can be coordinated in this way: at a certain time window j (within a series of N windows in one cycle), the safety ADC checker circuit 103 compares:

[0082] The signal TEMP_CODE_j comes from the j-th master sensor S_CH_j, where j = 1,…,N, and

[0083] The signal TEMP_CODE_RED corresponds to the signal from the j-th redundant sensor S_CH_jR, where j = 1, ..., N.

[0084] As stated, the signals should theoretically be identical. In practice, the comparison at the safety ADC checker circuit 103 can result in N (digital) non-zero error signals error_CH_1 to error_CH_N (i.e., error_CH_j, where j = 1, ..., N).

[0085] As discussed, these error signals error_CH_1 to error_CH_N can reveal errors affecting any of the channels 1 to N and prompt appropriate responses: for example, channels found to be affected by errors and set to a three-state off / low power condition.

[0086] Error signals error_CH_1 to error_CH_N (which can indicate inconsistencies in the measurement of die temperature) can be transmitted from circuit 100 (e.g., on the "error" pin) and / or stored in an internal register that can be accessed by, for example, a microcontroller.

[0087] This mismatch error in temperature measurement can be applied to both the valve channel and the bare plate; that is, the N channels illustrated in this paper can be considered to include both the valve and the bare plate.

[0088] One or more embodiments may include temperature control functionality for the temperature of the entire die.

[0089] Note that one or more embodiments are actually very "transparent" to the intended use of signals from blocks 101, 102 and signals error_CH_1 to error_CH_N from block 103.

[0090] like Figure 2 The circuit shown in the diagram helps to achieve independence in compliance with specifications, such as ASIL-D requirements that reduce the impact of die size.

[0091] like Figure 2 The circuit shown in the diagram includes N+1 analog-to-digital converters (ADC_1 to ADC_N plus ADC_R) and 2xN sensors (N main sensors S_CH_1 to S_CH_N and N redundant sensors S_CH_1R to S_CH_NR).

[0092] This advantage in terms of die size becomes even more pronounced as the number of channels N increases.

[0093] Figure 3 Example of a possible combined block diagram of an embodiment of a transmission control unit 1000 for passenger vehicles (PV) and commercial vehicles (CV).

[0094] The following names are applicable Figure 3 Some blocks visible in the middle:

[0095] 1002 – Charge Pump

[0096] 1008 – SPI Interface

[0097] 1020 – Internal Power Supply

[0098] 1022 – Auxiliary Oscillator

[0099] 1024 – Master Oscillator

[0100] 1026 and 1028 – Primary and Auxiliary Bandgap Voltage References and Auxiliary Bandgap Voltage References

[0101] 1038 – Temperature monitor (in conjunction with the N-channel current control driver 100 as previously discussed)

[0102] FET – Field-effect transistor driven by driver 100

[0103] L – Load powered by the FET.

[0104] Those skilled in the relevant field will pay additional attention, such as Figure 3 The transmission control unit 1000 illustrated in the figure may include various other blocks / elements that are conventional in the art and are not explicitly mentioned and / or referenced because they are not particularly important in the embodiment.

[0105] The circuit illustrated herein (e.g., 100) may include:

[0106] Multiple N sensing channels, each channel including a pair of first sensing nodes (e.g., S_CH_1 to S_CH_N) and second sensing nodes (e.g., S_CH_1R to S_CH_NR), wherein each first sensing node has a paired second sensing node (e.g., S_CH_1R is paired with S_CH_1, etc.).

[0107] Multiple N analog-to-digital converters (e.g., ADC_1 to ADC_N), each of the N analog-to-digital converters being coupled to a corresponding first sensing node (e.g., S_CH_1 to S_CH_N) in multiple N sensing channels.

[0108] A first digital processing circuit device (e.g., 101) and a second (e.g., 102) digital processing circuit device are coupled to a plurality of N analog-to-digital converters and configured to perform digital processing on N first digital signals.

[0109] A first multiplexer (e.g., MUX1) is coupled to a second sensing node in a plurality of N sensing channels; a second multiplexer (e.g., MUX2) is coupled to the outputs of a plurality of N analog-to-digital converters; and another analog-to-digital converter (e.g., ADC_R) is coupled to the output of the second multiplexer.

[0110] An error checking circuit (e.g., 103) is coupled to the output of the second multiplexer and also coupled to the output of the other analog-to-digital converter.

[0111] in:

[0112] The first and second multiplexers are configured to operate within a series of N time windows and apply to an error checking circuit. At each of these N time windows, a first digital value (e.g., TEMP_CODE) is generated by digital conversion of an analog sensing signal at a selected first sensing node within the corresponding first sensing node, and a second digital value (e.g., TEMP_CODE_RED) is generated by digital conversion of an analog sensing signal at a second sensing node, which is paired with the selected first sensing node within the corresponding first sensing node.

[0113] The error checking circuit is configured to compare a first digital value with a second digital value at each of a series of N time windows, and to generate N sensing error signals (e.g., error_CH_1, ..., error_CH_N) based on the difference between the first digital value and the second digital value within the series of N time windows.

[0114] In the circuit illustrated herein, a first digital processing circuit device and a second digital processing circuit device coupled to a plurality of N analog-to-digital converters can be configured to perform interpolation digital processing on N first digital signals, which vary according to a set of reference signals (e.g., T(C)) received at the first and second (102) digital processing circuit devices.

[0115] The circuit illustrated may include:

[0116] A first high-side digital processing circuit device (e.g., 101) is configured to drive a high-side electrical load (e.g., an HS FET), and

[0117] A second low-side digital processing circuit device (e.g., 102) is configured to drive a low-side electrical load (e.g., an LS FET).

[0118] In the circuit illustrated herein, a first digital processing circuit device and a second digital processing circuit device may be configured to continuously scan a plurality of N analog-to-digital converters (e.g., ADC_1 to ADC_N) to obtain the N first digital signals therefrom, thereby performing digital processing on the N first digital signals.

[0119] The circuit illustrated in this article can be configured as follows:

[0120] The circuit transmits the N sense error signals (e.g., error_CH_1, ..., error_CH_N), and / or

[0121] N sensing error signals are stored in circuit (100).

[0122] In the circuit illustrated herein, each of the plurality of N sensing channels may include at least one thermal sensor that provides a temperature sensing signal to one of a pair of first sensing nodes (e.g., S_CH_1 to S_CH_N) and second sensing nodes (e.g., S_CH_1R to S_CH_NR).

[0123] The circuit illustrated herein may include a first sensor that supplies a first sensing signal to a first sensing node and a second sensor that supplies a second sensing signal to a second sensing node paired therewith.

[0124] Systems illustrated herein (e.g., transmission control units 1000 for passenger and commercial vehicles, such as 1000) may include:

[0125] As illustrated in the circuit in this article,

[0126] At least one power switch (e.g., HS FET, LS FET; FET) is coupled to a first digital processing circuit device and a second digital processing circuit device and is configured to be driven by the first digital processing circuit device and the second digital processing circuit device, and

[0127] At least one electrical load (e.g., L) is controllably powered via at least one power switch (e.g., HS FET, LS FET; FET).

[0128] Methods for operating circuits or systems, as illustrated in this document, may include:

[0129] The corresponding sensing signals are collected through multiple N sensing channels.

[0130] The first and second (102) digital processing circuit systems are operated to perform digital processing on N first digital signals, which vary according to N sensed error signals (e.g., error_CH_1, ..., error_CH_N) generated by an error checking circuit device (e.g., 103) within a series of N time windows.

[0131] Without prejudice to the fundamental principles, the details and embodiments may, and even obviously, change relative to the details and embodiments described by way of example only, without departing from the scope of protection.

[0132] The scope of protection is determined by the appended claims.

Claims

1. An electronic circuit comprising: N sense channels and N pairs of sense nodes, each of the N sense channels comprising one of the N pairs of sense nodes, and each pair of sense nodes comprising a first sense node and a second sense node, wherein N is a positive integer greater than 1; N analog-to-digital converters, each of the N analog-to-digital converters having an input coupled to a respective first sense node of the N sense channels; a first multiplexer having inputs coupled to the second sense nodes of N sense channels, respectively; a second multiplexer having inputs coupled to outputs of the N analog-to-digital converters, respectively; a further analog-to-digital converter having an input coupled to an output of the first multiplexer; and an error check circuit coupled to an output of the second multiplexer and coupled to an output of the further analog-to-digital converter, wherein: the first multiplexer and the second multiplexer are configured to operate over a series of N time windows and to apply to the error check circuit, at each time window of the series of N time windows, a first digital value resulting from a digital conversion of an analog sense signal at a selected one of the respective first sense nodes of the N pairs of sense nodes, and a second digital value resulting from a digital conversion of an analog sense signal at the second sense node of the N pairs of sense nodes paired with the selected one of the respective first sense nodes, and the error check circuit is configured to compare the first digital value to the second digital value at each time window of the series of N time windows, and to produce, over the series of N time windows, N sense error signals as a function of variations in differences between the first digital value and the second digital value.

2. The electronic circuit of claim 1, further comprising first and second digital processing circuits coupled to the N analog-to-digital converters.

3. The electronic circuit of claim 2, wherein the first and second digital processing circuits are configured to perform interpolation digital processing on N of the first digital values as a function of a set of reference signals received at the first and second digital processing circuits.

4. The electronic circuit of claim 2, wherein the first digital processing circuit is configured to drive a high-side electrical load, and wherein the second digital processing circuit is configured to drive a low-side electrical load.

5. The electronic circuit of claim 2, wherein the first digital processing circuit is coupled to a high-side field effect transistor (FET), and wherein the second digital processing circuit is coupled to a low-side FET.

6. The electronic circuit of claim 2, wherein the first and second digital processing circuits are configured to continuously scan the N analog-to-digital converters to obtain N of the first digital values from the N analog-to-digital converters to perform digital processing on N of the first digital values. ​ 7. The electronic circuit of claim 1, wherein the electronic circuit is configured to transmit the N sense error signals from the electronic circuit.

8. The electronic circuit of claim 1, wherein the electronic circuit is configured to store the N sense error signals in the electronic circuit.

9. The electronic circuit of claim 1, wherein each of the N sense channels comprises a pair of thermal sensors configured to provide respective temperature sense signals to the first and second sense nodes of the respective pair of sense nodes.

10. The electronic circuit of claim 9, wherein each thermal sensor of the N sense channels comprises a bipolar junction transistor.

11. The electronic circuit of claim 1, further comprising: a first sensor configured to supply a first sense signal to the first sense node of a pair of sense nodes of the N sense channels; and a second sensor configured to supply a second sense signal to the second sense node of the pair of sense nodes.

12. Circuitry comprising: a power switch; an electrical load configured to be controllably powered via the power switch; and an electronic circuit configured to control the power switch, the electronic circuit comprising: N sense channels and N pairs of sense nodes, each of the N sense channels comprising a pair of sense nodes of the N pairs of sense nodes, and each pair of sense nodes comprising a first sense node and a second sense node, wherein N is a positive integer greater than 1, N analog-to-digital converters, each of the N analog-to-digital converters having an input coupled to a respective first sense node of the N sense channels, a first multiplexer having inputs respectively coupled to the second sense nodes of the N sense channels, a second multiplexer having inputs respectively coupled to outputs of the N analog-to-digital converters, a further analog-to-digital converter having an input coupled to an output of the first multiplexer, and an error check circuit coupled to an output of the second multiplexer and coupled to an output of the further analog-to-digital converter, wherein: the first and second multiplexers are configured to operate over a series of N time windows and to apply to the error check circuit, at each time window of the series of N time windows, a first digital value resulting from a digital conversion of an analog sense signal at a selected first sense node of the respective first sense nodes of the N pairs of sense nodes, and a second digital value resulting from a digital conversion of an analog sense signal at the second sense node of the N pairs of sense nodes paired with the selected first sense node of the respective first sense nodes, and the error check circuit is configured to compare the first digital value to the second digital value at each time window of the series of N time windows, and to produce, over the series of N time windows, N sense error signals as a function of variations in differences between the first digital value and the second digital value. ​ ​ 13. The system of claim 12, wherein the system is a transmission control unit of a motor vehicle.

14. The system of claim 12, further comprising: a charge pump circuit; an oscillator circuit; a bandgap circuit; a temperature monitor; and a serial peripheral interface (SPI) type communication interface.

15. A method of operating circuitry, comprising: collecting, at each time window of a series of N time windows, a first digital value from a selected one of N analog-to-digital converters, wherein each of the N analog-to-digital converters has an input coupled to a respective first sense node of a respective pair of sense nodes of N sense channels, and wherein N is a positive integer greater than 1 ; collecting, at each time window of the series of N time windows, a second digital value from another analog-to-digital converter coupled to N second sense nodes of the N sense channels, wherein, at each time window of the series of N time windows, the second digital value produced by the another analog-to-digital converter results from a digital conversion of an analog sense signal at a selected second sense node of the N sense channels, and wherein the selected second sense node is paired with the first sense node coupled to the selected analog-to-digital converter; comparing, at each time window of the series of N time windows, the first digital value to the second digital value to produce a sense error signal as a function of a difference between the first digital value and the second digital value; and operating first and second digital processing circuits to perform digital processing on N of the first digital values produced over the series of N time windows as a function of N of the sense error signals produced over the series of N time windows.

16. The method of claim 15, further comprising: providing an actuation current to a load with a power transistor; and controlling the power transistor based on the N sense error signals.

17. The method of claim 16, wherein controlling the power transistor is further based on a set of reference signals received by the first and second digital processing circuits.

18. The method of claim 15, further comprising storing the N sense error signals in a memory.

19. The method of claim 15, further comprising: producing N first analog sense signals at respective N first sense nodes of the N sense channels having N respective first thermal sensors; and producing N second analog sense signals at respective N second sense nodes of the N sense channels having N respective second thermal sensors.

20. The method of claim 15, wherein the N analog-to-digital converters, the another analog-to-digital converter, the first and second digital processing circuits, and the N sense channels are part of an electronic circuit, the method further comprising using the electronic circuit for current measurement in a valve driver of a motor vehicle. ​

Images