Scan optimization across memory array word lines using data selection

Abstract

The present disclosure relates to scan optimization using data selection across word lines of a memory array. A system includes a memory array having sub-blocks, each sub-block having a group of memory cells. A processing device operatively coupled with the memory array is to perform an operation including performing a scan on a word line after the word line is programmed through the sub-blocks. The scan includes selecting a first group of the group of memory cells of a first one of the sub-blocks to sample first data of the word line, selecting a second group of the group of memory cells of a second one of the sub-blocks to sample second data of the word line, simultaneously reading the first data from the first group of the group of memory cells and the second data from the second group, and performing an error check on the word line using the first data and the second data.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to scan optimization using data selection across word lines of a memory array. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this disclosure relates to a system comprising: a memory array including a plurality of sub-blocks, each of the plurality of sub-blocks including a group of memory cells; and a processing means operatively coupled to the memory array, the processing means performing operations including: performing a scan of word lines after programming word lines through the plurality of sub-blocks, wherein the scan includes: selecting a first group of memory cell groups of a first sub-block of the plurality of sub-blocks to sample first data of the word lines; selecting a second group of memory cell groups of a second sub-block of the plurality of sub-blocks to sample second data of the word lines; simultaneously reading the first data from the first group of memory cell groups and reading the second data from the second group; and performing an error check on the word lines using the first data and the second data.

[0004] In another aspect, this disclosure relates to a system comprising: a memory array including a plurality of sub-blocks, each of the plurality of sub-blocks including a group of memory cells; and a processing means operatively coupled to the memory array, the processing means performing operations including: causing a first word line to be programmed through the plurality of sub-blocks having a mask by: causing the following to be programmed to a first voltage level: a first group of memory cell groups of the first sub-blocks in the plurality of sub-blocks; and a second group of memory cell groups of a second sub-block in the plurality of sub-blocks; and causing the remaining portions of the memory cell groups of the first and second sub-blocks that are not programmed to the first voltage level to be programmed to a second voltage level; and performing a scan on a second word line that has been programmed and coupled to the first word line, wherein performing the scan includes: causing a custom word line voltage to be applied to the second word line, the custom word line voltage selecting a group of memory cells corresponding to the group of memory cells programmed to the first voltage level of the first word line, and deselecting a group of memory cells corresponding to the group of memory cells programmed to the second voltage level of the first word line; simultaneously reading data from the selected group of memory cells of the second word line; and performing an error check on the second word line using the data.

[0005] In another aspect, this disclosure relates to a method comprising: causing a first word line to be programmed through a plurality of masked sub-blocks of a memory array by: causing the following to be programmed to a first voltage level: a first group of memory cell groups of a first sub-block in the plurality of sub-blocks; and a second group of memory cell groups of a second sub-block in the plurality of sub-blocks; and causing the remaining portions of the memory cell groups of the first and second sub-blocks that are not programmed to the first voltage level to be programmed to a second voltage level; and performing a scan on a programmed second word line coupled to the first word line, wherein performing the scan comprises: causing a custom word line voltage to be applied to the second word line, the custom word line voltage selecting a group of memory cell groups corresponding to the first word line programmed to the first voltage level, and deselecting a group of memory cell groups corresponding to the first word line programmed to the second voltage level; and simultaneously reading data from the selected group of memory cell groups of the second word line; and performing an error check on the second word line using the data. Attached Figure Description

[0006] This disclosure will be more fully understood from the following detailed description and the accompanying drawings of some embodiments thereof.

[0007] Figure 1 This describes an instance computing system including a memory subsystem according to some embodiments.

[0008] Figure 2A This is an example illustration of data selection from multiple sub-blocks of a word line for performing a scan on the word line, according to some embodiments.

[0009] Figure 2B This is another example of data selection from multiple sub-blocks of a word line for performing a scan on the word line, according to some embodiments.

[0010] Figure 3A This is an example illustration of using masked word lines to select data from multiple sub-blocks of word lines for performing a scan on the word lines, according to some embodiments.

[0011] Figure 3B According to the embodiments Figure 3A Example gate diagram version of the schematic diagram.

[0012] Figure 4A A graph illustrating the first set of read voltage levels used in mask mode for writing to the memory array according to an embodiment.

[0013] Figure 4B A graph illustrating the second set of read voltage levels used in data mode for writing to the memory array according to an embodiment.

[0014] Figure 5 This is a flowchart of an example method for selecting data from multiple sub-blocks of a word line to perform a scan on the word line, according to some embodiments.

[0015] Figure 6 This is a flowchart of an example method, according to some embodiments, of employing a mask to select data from multiple sub-blocks of a word line for performing a scan on the word line.

[0016] Figure 7 A block diagram of an example computer system operable according to embodiments of the present disclosure. Detailed Implementation

[0017] Embodiments of this disclosure are scan optimizations for word line usage data selection across a memory array. The memory subsystem may be a memory device, a memory module, or a hybrid of a memory device and a memory module. The following description, in conjunction with... Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem, which includes one or more components, such as memory devices for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0018] The memory device may be a non-volatile memory device. An example of a non-volatile memory device is a NAND flash memory device. The following section will discuss this further. Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. Planes may be divided into logic units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits being stored. Logic states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of such values.

[0019] Memory devices can consist of bits arranged in a two-dimensional grid, also known as memory arrays. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells in a memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of a memory cell.

[0020] Various access operations can be performed on memory cells. For example, data can be written to, read from, and erased from memory cells. Memory cells can be divided into write units (e.g., pages). For some types of memory devices, a page is the smallest write unit. A word line can have multiple pages grouped into sub-blocks on the same word line. Sub-blocks are typically accessed at any given time. Although each sub-block has its own set of bit lines, sub-blocks share a common page buffer or sense amplifier.

[0021] In conventional memory systems such as NAND flash memory, the controller (e.g., a processing device) uses scans to check the integrity of pages. These pages are marked by sub-block boundaries of each word line, and are therefore referred to as sub-blocks below. Because defects can manifest themselves locally within a sub-block, a defect or non-defect scan is performed on each individual sub-block of the word line. For example, data can be read sequentially from each sub-block of the word line, and error checking can be performed on the data. In the case of a non-defect scan, a scan can be performed in conjunction with a temporary RAIN parity scheme (e.g., outside the defect blast radius if a defect is detected), other types of error detection, and / or the inherent stress of the memory cells used to inspect each sub-block. If the scanned sub-block is error-free, its integrity is intact and no corrective action is required. Performing a scan on each sub-block of the word line requires significant processing overhead and is therefore costly. For example, such scans consume resources of the memory subsystem controller and bandwidth of the local media controller of the memory device (e.g., NAND flash memory).

[0022] The present disclosure addresses the above and other drawbacks by the following operation: when scanning a memory device, a specific group of memory cells in each sub-block of a plurality of sub-blocks of a word line is selected to sample data, and error checking is performed on the sampled data. In one embodiment, each group of memory cells corresponds to a bit line or column in a memory array. The selected groups of memory cells across the plurality of sub-blocks may, for example, be numbered sequentially to change the selected groups of memory cells from each corresponding sub-block. Other types of rotation numbering schemes for the sampled groups of memory cells are envisioned. In one embodiment, a group of sense amplifiers multiplexed across sub-blocks (e.g., to read each sub-block one at a time) is reused such that each sense amplifier in the group of sense amplifiers samples a different group of memory cells from each corresponding sub-block of the plurality of sub-blocks. In this way, the type of pseudo-page is selected across the plurality of sub-blocks to be read at the same time (e.g., simultaneously), thus reducing the overhead associated with multiple reads of individual sub-blocks and corresponding error checking for each sub-block. Because at least one data block is sampled from each sub-block, all the plurality of sub-blocks are efficiently scanned as a group (e.g., pseudo-pages).

[0023] In alternative embodiments, it may be impossible to reuse the sense amplifier to sample groups of memory cells across multiple sub-blocks, where each entire sub-block shares a select gate enable signal for the sense amplifier group. In such embodiments, word lines are selected potentially from hundreds of word lines, resulting in mask programming. The mask allows selected groups of memory cells from each respective sub-block to be programmed at a first voltage level, and other groups of memory cells from the multiple sub-blocks to be programmed at a second voltage level. In one embodiment, the first voltage level is lower than the second voltage level, but in another embodiment, the opposite voltage level may be correct.

[0024] In an alternative embodiment, when scanning is performed on a second word line (or some word lines other than the mask word line) coupled to the mask word line, the processing device causes a custom word line voltage to be applied to the second word line. The custom word line voltage is adjusted to select memory cell groups across a plurality of sub-blocks of the second word line corresponding to a group of memory cells programmed to a first voltage level on the mask word line, and to deselect memory cell groups of a plurality of sub-blocks corresponding to a group of memory cells programmed to a second voltage level on the mask word line. The processing device can then simultaneously read data from the selected memory cell groups of the second word line and ignore data from the unselected memory cell groups. The processing device can then use the data to perform word line error checking while reading data from the selected memory cell groups. In this way, for error detection purposes, referring to the first embodiment, as previously described and as will be discussed, sampling of a plurality of sub-blocks is performed while bypassing the select gate enable signal.

[0025] Therefore, the advantages of the systems and methods implemented according to some embodiments of this disclosure include, but are not limited to, significantly reducing (e.g., by about 75%) the overhead cost of reading data from each individual sub-block (e.g., a page) by sampling only the group of memory cells from each sub-block during a scan. The principles of this disclosure reduce the number of read operations required to perform a scan on each word line, and also reduce the amount of data that needs to be processed during error checking of data read from word lines. Not only are the resources required for the memory subsystem controller to perform the scan reduced, but the bandwidth consumption of the local media controller of the memory device is also reduced. Other advantages of scanning programmable word lines within the memory subsystem discussed below will be apparent to those skilled in the art.

[0026] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0027] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0028] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0029] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0030] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and read data from memory subsystem 110.

[0031] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0032] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0033] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory cells can perform bit storage based on changes in volume resistance in conjunction with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0034] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, and MLC portions, TLC portions, QLC portions, or PLC portions. The memory cells of the memory device 130 may be grouped into pages that may refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0035] While describing non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND flash memory (e.g., 2D NAND, 3D NAND), memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0036] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic that performs the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0037] The memory subsystem controller 115 may include a processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0038] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may actually rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0039] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations, such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0040] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0041] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is a raw memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0042] In some embodiments, controller 115 includes scanner 113 that performs cross-word line data selection and scanning as described herein. Scanner 113 may also include, for example, an error correction code (ECC) encoder / decoder. The ECC encoder / decoder may perform ECC encoding on data written to word lines of memory device 130 and ECC decoding on data read from word lines of memory device 130. ECC decoding may be performed to decode ECC codewords to correct errors in the original read data, and in many cases, also to report the number of bit errors in the original read data. The scanner may also take other corrective actions in response to error detection. In an alternative embodiment, the control logic of scanner 113 is also located at least partially within local media controller 135 of memory device 130.

[0043] Figure 2A This is an example illustration of data selection from multiple sub-blocks of a word line for performing a scan of the word line according to some embodiments. In one embodiment, a memory portion 130A of the memory device 130 contains multiple pages (e.g., page 0, page 1, page 2, page 3) corresponding to multiple sub-blocks (e.g., SB0, SB1, SB2, SB3, respectively). The memory portion 130A is illustrated as having four sub-blocks, but in different embodiments, fewer or more sub-blocks may define a word line (WL0). Each sub-block SB0, SB1, SB2, and SB3 respectively contains multiple cell groups 201, 202, 203, and 204.

[0044] In some embodiments, the controller 115 (e.g., a processing device) selects a first group 202A of memory cell group 201 of a first sub-block (SB0) of the plurality of sub-blocks to sample first data of word lines (WL0). The controller 115 further selects a second group 202B of memory cell group 202 of a second sub-block (SB1) of the plurality of sub-blocks to sample second data of word lines (WL0). The controller 115 further selects a third group of memory cell group 203 of a third sub-block (SB2) of the plurality of sub-blocks to sample third data of word lines (WL0). The controller further selects a fourth group of memory cell group 204 of a fourth sub-block (SB3) of the plurality of sub-blocks to sample fourth data of word lines (WL0).

[0045] In this manner, the selected memory cell groups in each sub-block are staggered within the corresponding cell groups of each respective sub-block. While the illustrated embodiments sequentially stagger the selected cell groups, such as the first, second, third, and fourth groups of memory cells 201A, 202B, 203C, and 204D, other embodiments may stagger the selected memory cell groups in different ways (including randomly). Figure 2A In one embodiment, the controller 115 may further read the first data, the second data, the third data, and the fourth data simultaneously, and use the first data, the second data, the third data, and the fourth data to perform error checking on the word line to complete the scanning of the word line (WL0).

[0046] Figure 2B This is a schematic diagram of another example of data selection from multiple sub-blocks of a word line for performing a scan of the word line, according to some embodiments. In another embodiment, a memory portion 130B of the memory device 130 contains multiple pages corresponding to multiple sub-blocks. In one embodiment, the memory portion 130B is a reference... Figure 2A A more detailed version of the memory section 130A discussed herein. Memory section 130A is described as having four sub-blocks (numbered 0, 1, 2, and 3 for illustrative purposes), but in different embodiments, fewer or more sub-blocks may define multiple word lines (WL0…WL3). Memory section 130A can be understood as illustrating an implementation where each sub-block is 16 kilobytes (KB) in size, each sub-block containing four groups of memory cells, each memory cell being 4 KB in size, but different sizes for each sub-block and each group of sub-blocks are contemplated.

[0047] In various embodiments, each memory cell group includes a selection gate that can be individually enabled (e.g., turned on) to read data from the memory cell group at once or disabled (e.g., turned off) to prevent any data from being read. Thus, for example, a first sub-block includes a first selection gate (SG 0A), a second selection gate (SG 0B), a third selection gate (SG 0C), and a fourth selection gate (SG 0D) for a first memory cell group. Furthermore, a second sub-block includes a first selection gate (SG 1A), a second selection gate (SG 1B), a third selection gate (SG 1C), and a fourth selection gate (SG 1D) for a second memory cell group. Additionally, a third sub-block includes a first selection gate (SG 2A), a second selection gate (SG 2B), a third selection gate (SG 2C), and a fourth selection gate (SG 2D) for a third memory cell group. Finally, a fourth sub-block includes a first selection gate (SG 3A), a second selection gate (SG 3B), a third selection gate (SG 3C), and a fourth selection gate (SG 3D) for a fourth memory cell group.

[0048] exist Figure 2B In one embodiment, the memory section 130B includes four sense amplifiers 215 capable of reading data sub-blocks at once. To stagger data sub-blocks within a word line during scanning, the scanner 113 selectively activates (or deactivates) the first selection gate (SG 0A) of the first sub-block, the second selection gate (SG 1B) of the second sub-block, the third selection gate (SG 2C) of the third sub-block, and the fourth selection gate (SG 3D) of the fourth sub-block to simultaneously read data from the first memory cell group of the first sub-block, the second memory cell group of the second sub-block, the third memory cell group of the third sub-block, and the fourth memory cell group of the fourth sub-block, respectively. Simultaneous scanning of 4KB memory cell groups from different sub-blocks (one per sub-block of the four sub-blocks) replaces four separate read operations. This reduction in scanning reduces read overhead by 75%.

[0049] In this manner, the selected memory cell groups are sequentially staggered across the four sub-blocks of the word line's positive scan defect. The select gates can be enabled by the scanner 113 via corresponding sense amplifiers SA-A, SA-B, SA-C, and SA-D, which are multiplexed, each for the select gate of each of the four sub-blocks. In other embodiments, the selection of memory cell groups is in reverse order or ordered in a different manner within the memory cell groups, including randomly. Therefore, embodiments that sequentially select memory cell groups across multiple sub-blocks are for ease of illustration and explanation.

[0050] Figure 3AThis is an example illustration of using a masked word line to select data from multiple sub-blocks of the word line for performing a scan on the word line, according to some embodiments. According to another embodiment, in the memory portion 130C of the memory device 130, there is a common select gate enable signal for each of the select gates that enable (open) the sub-blocks, for example... Figure 3B The enable signals VSG0, VSG1, and VSG2 are used. Therefore, for a specific sub-block, scanner 113 can enable or disable all memory cell groups. This shared select gate enable signal architecture allows the reference... Figure 2A-2B The described implementation becomes impossible.

[0051] To provide an alternative embodiment in this type of architecture, scanner 113 may cause word lines (MWLs) to be programmed using a mask. To program the mask word lines (MWLs), control logic of memory device 130 causes each corresponding group of memory cells across alternating word lines to be programmed to a first voltage level (first VL). Thus, memory device 130 for programming the mask can program the first group (first group) of memory cells in a first sub-block (SB0) of a plurality of sub-blocks, the second group (second group) of memory cells in a second sub-block (SB1) of a plurality of sub-blocks, the third group (third group) of memory cells in a third sub-block (SB2) of a plurality of sub-blocks, and the fourth group (fourth group) of memory cells in a fourth sub-block (SB3) of a plurality of sub-blocks to the first voltage level. Similarly, while the first, second, third, and fourth groups of memory cells selected across the four sub-blocks (SB0, SB1, SB2, SB3) are numbered sequentially, other embodiments select memory cell groups in reverse order, randomly, or otherwise. As part of the programming mask, the memory device 130 further enables the remainder of the memory block group to be programmed to a second voltage level.

[0052] In a first embodiment, the first voltage level is a low (e.g., the digital "0") voltage level, and the second voltage level is a high (e.g., the digital "1") voltage level, but different voltage values ​​are envisioned, wherein the second voltage level is higher than the first voltage level. The low voltage level causes the gate at the cell to open and thus transmit data, while the high voltage level causes the gate to close and thus acts as a disconnect circuit. In a second embodiment, the first voltage level is a high voltage level, and the second voltage level is a low voltage level, wherein selecting the gate causes a switching opposite to that in the first embodiment.

[0053] When scanning word lines, controller 115 can cause custom word line voltages to be applied to the word lines (e.g., WL0, WL1, WL2, WL3, etc.). The custom word line voltages can be applied to select groups of memory cells corresponding to memory cell groups programmed to a first voltage level and to deselect groups of memory cells corresponding to memory cell groups programmed to a second voltage level. As illustrated, this selects the darker "1st VL" group of memory cells and deselects the lighter "2nd VL" group. This means that 75% of the memory cell groups across multiple sub-blocks are not selected. Controller 115 can further simultaneously read data from the selected memory cell groups of the second word line, while the unselected memory cell groups are not read because they are open circuits. Controller 115 can then use the data to perform error checking on the second word line.

[0054] Figure 3B According to the embodiments Figure 3A This is an example gate diagram version of the schematic diagram. For illustrative purposes, this schematic diagram is for reference only. Figure 3A The memory section 103C comprises three sub-blocks: a first sub-block (SB0), a second sub-block (SB1), and a third sub-block (SB2). A row of switches 318 (e.g., transistors) in the memory array 302 contains select gates previously designated SG0A…SG0D, SG1A…SG1D, and SG2A…SG2D, which selectively enable data reading from corresponding groups of memory cells within these sub-blocks. A set of switches 318 for the first sub-block (SB0) is enabled by a VSG0 gate enable signal, a set of switches for the second sub-block (SB1) is enabled by a VSG1 gate enable signal, and a set of switches for the third sub-block (SB2) is enabled by a VSG2 gate enable signal, where VSGx enables a specific sub-block indicated by "x". In this way, a set of switches 318 can initiate and deactivate access to each of the groups of memory cells coupled to the set of switches 318.

[0055] In various embodiments, the mask word line (mask WL) is as described in the reference. Figure 3A The discussed (using a low voltage level in bold L and a high voltage level in bold H) is programmed and coupled to each group of switches 318. The patterned mask programmed into the mask word line can act as a next-level selector signal to enable (or activate) sampling selection across different memory cell groups across multiple sub-blocks.

[0056] In these embodiments, multiple sub-blocks of mask word lines are coupled between each set of switches 318 and multiple sub-blocks of the second word line, such as the selected data word line (WLZ) applied by a custom word line voltage (VWL). Unselected data word lines (WLX, WLY) can be applied with a conventional voltage (VPASSR), which typically turns on the unselected word lines. Selected word lines are selected for scanning, while unselected word lines are enabled to ensure that the unselected word lines are on, and the transistors on the selected word lines act as transparent devices.

[0057] In various embodiments, after programming and scanning the remaining word lines, the unmasked portion of the mask word line (MWL) can be programmed using user data. In other words, after scanning multiple word lines that constitute part of the memory array, controller 115 can enable unselected groups of memory cells to be programmed using data (e.g., user data). Using this method, instead of wasting full word lines used for masking, a portion of the word lines can be restored to the stored user data, thus avoiding the waste of 75% of the mask word lines.

[0058] Figure 4A A graph illustrating the first set of read voltage levels used in mask mode for writing to memory array 302 according to an embodiment. See reference... Figures 3A-3B As discussed, a low voltage level may correspond to a selected mask word line portion, while a high voltage level may correspond to an unselected mask word line portion (however, in other embodiments, these voltage levels may be reversed to encode the opposite selection). In one embodiment, mask portions erased or programmed to a low voltage level are 4KB per subblock, and mask portions programmed to a high voltage level are 12KB per subblock.

[0059] Before programming and scanning the remaining word lines, the data word lines can be used in mask mode to provide templates for custom word line voltages, as discussed. Before the physical block is closed (where the sub-block is a portion), the controller 115 can cause the memory device 130 to switch to a data mode for programming the mask word lines, where the voltage threshold (Vt) definition changes to correspond to the normal data level. Figure 4B The graph illustrating the second set of read voltage levels used in the data mode for writing to the memory array according to the embodiment is provided for illustrative purposes only. In the illustrated embodiment, there are three data voltage levels: a first low data voltage level for 2KB memory cells per sub-block, a second low voltage level for 6KB memory cells per sub-block, and a high voltage level for 8KB memory cells per sub-block.

[0060] Therefore, in some embodiments, the controller 115 causes the memory device 130 containing the memory array 302 to operate in mask mode while simultaneously performing a scan of multiple word lines that are part of the memory array, wherein a first voltage level is at a first threshold voltage level and a second voltage level is at a second threshold voltage level. In these embodiments, the controller 115 further causes the memory device 130 to operate in data mode after the scan is completed. Data mode causes the memory cells of the first word line to be programmed using a set of threshold voltage levels designed for subsequent read operations at multiple data levels different from the first and second threshold voltage levels, for example, implying normal read operations.

[0061] Figure 5 This is a flowchart of an example method 500 for selecting data from multiple sub-blocks of a word line for performing a scan on the word line, according to some embodiments. Method 500 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 Scanner 113 executes the process. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0062] At operation 510, the processing logic selects the first data of the memory cell group of the first sub-block in a plurality of sub-blocks to sample the first data of the word line.

[0063] At operation 520, the processing logic selects a second group of memory cells in the second sub-block of a plurality of sub-blocks to sample the second data of the word line.

[0064] At operation 530, the processing logic may optionally also select a third group of memory cell groups of a third sub-block among multiple sub-blocks to sample the third data of the word line.

[0065] At operation 540, the processing logic may optionally also select a fourth group of memory cell groups of a fourth sub-block among a plurality of sub-blocks to sample the fourth data of the word line.

[0066] At operation 550, the processing logic simultaneously reads first data from the first group of memory cell groups, reads second data from the second group, and optionally reads third data from the third group of memory cell groups and reads fourth data from the fourth group in the word line.

[0067] At operation 560, the processing logic performs error checking on the word line using the first data, the second data, and optionally also the third and fourth data. Method 500 may further include taking corrective action in response to detecting defects in the word line based on the results of the error checking.

[0068] Figure 6 This is a flowchart of an example method 600, which employs a mask to select data from multiple sub-blocks of a word line for performing a scan on the word line, according to some embodiments. Method 600 may be executed by processing logic, which may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing means), or a combination thereof. In some embodiments, method 600 is performed by… Figure 1 Scanner 113 executes the process. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0069] At operation 610, the processing logic causes the first word line to be programmed through a plurality of masked sub-blocks of the memory array by causing two or more of the memory cell groups to be programmed, the memory cell groups being included in a first group of memory cell groups of a first sub-block of the plurality of sub-blocks at operation 615, and a second group of memory cell groups of a second sub-block of the plurality of sub-blocks at operation 620. The programming of the mask can be optionally extended by causing a third group of memory cell groups of a third sub-block of the plurality of sub-blocks at operation 625 and a fourth group of memory cell groups of a fourth sub-block of the plurality of sub-blocks at operation 630 to be programmed to a first voltage level. The optional programming of the third and fourth groups of memory cells is indicated by dashed lines.

[0070] At operation 635, the mask programming further includes processing logic that causes the remaining portions of the memory cell groups of the first sub-block, the second sub-block, and optionally the third and fourth blocks that were not programmed to the first voltage level to be programmed to the second voltage level.

[0071] At operation 640, the processing logic performs a scan on the second word line, which is programmed and coupled to the first word line. The scan can be performed in operations 645, 650, and 655.

[0072] At operation 645, the processing logic causes a custom word line voltage to be applied to the second word line. The custom word line voltage can select a group of memory cells corresponding to the group of memory cells programmed to the first voltage level for the first word line, and deselect a group of memory cells corresponding to the group of memory cells programmed to the second voltage level for the first word line.

[0073] At operation 650, the processing logic simultaneously reads data from the selected group of memory cells on the second word line executed at operation 645.

[0074] At operation 655, the processing logic uses data to perform an error check on the second word line. Method 600 may further include taking a corrective action in response to detecting a defect in the second word line based on the result of the error check.

[0075] Figure 7 An example machine illustrating computer system 700 is described, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein can be executed. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of scanner 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer (or distributed) network machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0076] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions that will take a specified action by said machine. Furthermore, although a single machine is described, it should be understood that the term "machine" also includes any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0077] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 710 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0078] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 728 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 712 for communication via network 720.

[0079] Data storage system 718 may include machine-readable storage medium 724 (also referred to as computer-readable medium) on which one or more instruction sets 728 or software embodying any one or more of the methods or functions described herein are stored. The instructions 728 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, which also constitute machine-readable storage medium. Machine-readable storage medium 724, data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0080] In one embodiment, instruction 726 includes instructions for implementing a scanner (e.g., Figure 1 The instructions for the function of the scanner 113). Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing a machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0081] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and are generally considered, a self-consistent sequence of operations that produce the desired result. Operations are those that require physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0082] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0083] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0084] The algorithms and displays presented herein are inherently independent of any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0085] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0086] In the foregoing description, embodiments of this disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications can be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than restrictive.

Claims

1. A memory system, comprising: a memory array comprising a plurality of sub-blocks, each sub-block of the plurality of sub-blocks comprising a group of memory cells; and a processing device operably coupled with the memory array, the processing device performing operations comprising: performing a scan on a word line after the word line is programmed through the plurality of sub-blocks, wherein the scan comprises: selecting a first group of the group of memory cells of a first sub-block of the plurality of sub-blocks to sample first data of the word line; selecting a second group of the group of memory cells of a second sub-block of the plurality of sub-blocks to sample second data of the word line; reading the first data from the first group of the group of memory cells and the second data from the second group simultaneously; and performing an error check on the word line using the first data and the second data.

2. The memory system of claim 1, wherein the second group is sequentially numbered after the first group of the group of memory cells.

3. The memory system of claim 1, wherein the operations to scan the word line further comprise: selecting a third group of the group of memory cells of a third sub-block of the plurality of sub-blocks to sample third data of the word line; selecting a fourth group of the group of memory cells of a fourth sub-block of the plurality of sub-blocks to sample fourth data of the word line; and reading the first data, the second data, the third data, and the fourth data simultaneously; and performing the error check on the word line using the first data, the second data, the third data, and the fourth data.

4. The memory system of claim 3, wherein each sub-block of the plurality of sub-blocks comprises a page of data, and wherein the first data, the second data, the third data, and the fourth data comprise pages of data.

5. The memory system of claim 3, wherein the group of memory cells of each sub-block of the plurality of sub-blocks comprises a respective sequentially numbered first group, second group, third group, and fourth group of memory cells.

6. The memory system of claim 1, wherein the operations further comprise taking a corrective action in response to detecting a defect in the word line based on a result of the error check.

7. A memory system, comprising: a memory array comprising a plurality of sub-blocks, each sub-block of the plurality of sub-blocks comprising a group of memory cells; and a processing device operably coupled with the memory array, the processing device performing operations comprising: causing a first word line to be programmed through the plurality of sub-blocks with a mask by: causing the following to be programmed to a first voltage level: a first group of the group of memory cells of a first sub-block of the plurality of sub-blocks; and a second group of the group of memory cells of a second sub-block of the plurality of sub-blocks; and causing a remaining portion of the memory cell groups of the first sub-block and the second sub-block that are not programmed to the first voltage level to be programmed to a second voltage level; and performing a scan on a second word line that has been programmed and is coupled to the first word line, wherein performing a scan comprises: causing a custom word line voltage to be applied to the second word line, the custom word line voltage selecting a group of memory cells corresponding to a group of memory cells of the first word line programmed to the first voltage level and deselecting a group of memory cells corresponding to a group of memory cells of the first word line programmed to the second voltage level; simultaneously reading data from the selected group of memory cells of the second word line; and performing an error check on the second word line using the data.

8. The memory system of claim 7, wherein the first voltage level is lower than the second voltage level.

9. The memory system of claim 7, wherein the operations to cause the first word line to program further comprise: causing the following to be programmed to the first voltage level: a third group of the memory cell groups of a third sub-block of the plurality of sub-blocks; and a fourth group of the memory cell groups of a fourth sub-block of the plurality of sub-blocks, and causing a remaining portion of the memory cell groups of the third sub-block and the fourth sub-block to be programmed to the second voltage.

10. The memory system of claim 9, wherein the memory cell groups of each sub-block of the plurality of sub-blocks comprise a first, second, third, and fourth sequentially numbered group of memory cells.

11. The memory system of claim 7, further comprising a set of switches to enable and disable access to each of the groups of memory cells, wherein the plurality of sub-blocks of the first word line are coupled between each set of switches and the plurality of sub-blocks of the second word line.

12. The memory system of claim 7, wherein the operations further comprise taking a corrective action in response to detecting a defect in the second word line based on a result of the error check.

13. The memory system of claim 7, wherein the operations further comprise causing unselected groups of memory cells to be programmed with data after performing the scan on a plurality of word lines included by the memory array.

14. A method for performing memory operations, comprising: causing a first word line to be programmed through a plurality of sub-blocks of a memory array with a mask by: causing the following to be programmed to a first voltage level: a first group of memory cell groups of a first sub-block of the plurality of sub-blocks; and a second group of memory cell groups of a second sub-block of the plurality of sub-blocks; and causing a remaining portion of the memory cell groups of the first sub-block and the second sub-block that are not programmed to the first voltage level to be programmed to a second voltage level; and performing a scan on a second word line that has been programmed and is coupled to the first word line, wherein performing a scan comprises: causing a custom word line voltage to be applied to the second word line, the custom word line voltage selecting a group of memory cells corresponding to a group of memory cells of the first word line programmed to the first voltage level and deselecting a group of memory cells corresponding to a group of memory cells of the first word line programmed to the second voltage level; simultaneously reading data from the selected group of memory cells of the second word line; and performing an error check on the second word line using the data. causing a custom word line voltage to be applied to the second word line, the custom word line voltage selecting a group of memory cells corresponding to a group of memory cells of the first word line programmed to the first voltage level and deselecting a group of memory cells corresponding to a group of memory cells of the first word line programmed to the second voltage level; and simultaneously reading data from the selected group of memory cells of the second word line; and performing an error check on the second word line using the data.

15. The method of claim 14, wherein the first voltage level is lower than the second voltage level.

16. The method of claim 14, wherein causing the first word line to program further comprises: causing the following to be programmed to the first voltage level: a third group of the group of memory cells of a third sub-block of the plurality of sub-blocks; and a fourth group of the group of memory cells of a fourth sub-block of the plurality of sub-blocks, and causing a remainder of the group of memory cells of the third sub-block and the fourth sub-block to be programmed to the second voltage.

17. The method of claim 16, wherein the group of memory cells of each sub-block of the plurality of sub-blocks comprises a respective sequentially numbered first group, second group, third group, and fourth group of memory cells.

18. The method of claim 14, further comprising taking a corrective action in response to detecting a defect in the second word line based on a result of the error check.

19. The method of claim 14, further comprising causing unselected groups of memory cells to program using data after performing the scan on a plurality of word lines included by the memory array.

20. The method of claim 14, further comprising: causing a memory device containing the memory array to operate in a mask mode while performing the scan on a plurality of word lines included by the memory array, wherein the first voltage level is at a first threshold voltage level and the second voltage level is at a second threshold voltage level; and causing the memory device to operate in a data mode after completing the scan, the data mode causing the memory cells of the first word line to program using a set of threshold voltage levels designed for subsequent read operations at a plurality of data levels different from the first threshold voltage level and the second threshold voltage level.

21. The method of claim 14, wherein the first voltage level is at a first threshold voltage level and the second voltage level is at a second threshold voltage level.

22. The method of claim 14, wherein the first word line is a first word line of a plurality of word lines included by the memory array, and the second word line is a second word line of the plurality of word lines.

23. The method of claim 14, wherein the first word line is a first word line of a plurality of word lines included by the memory array, and the second word line is a second word line of the plurality of word lines.

24. The method of claim 14, wherein the first word line is a first word line of a plurality of word lines included by the memory array, and the second word line is a second word line of the plurality of word lines.

25. The method of claim 14, wherein the first word line is a first word line of a plurality of word lines included by the memory array, and the second word line is a second word line of the plurality of word lines.

26. The method of claim 14, wherein the first word line is a first word line of a plurality of word lines included by the memory array, and the second word line is a second word line of the plurality of word lines.

27. The method of claim 14, wherein the first word line is a first word line of a plurality of word lines included by the memory array, and the second word line is a second word line of the plurality of word lines.

28. The method of claim 14, wherein the first word line is a first word line of a plurality of word lines included by the memory array, and the second word line is a second word line of the plurality of word lines.

29. The method of claim 14, wherein the first word line is a first word line of a plurality of word lines included by the memory array, and the second word line is a second word line of the plurality of word lines.

30. The method of claim 14, wherein the first word line is a first word line of a plurality of word lines included by the memory array, and the second word line is a second word line of the plurality of word lines.

Images