A test system and test method for a memory

Abstract

The present invention provides a test system and a test method for a memory. The test system includes: a tester for generating and sending test commands; a test board to which a memory is connected; the test board is configured to receive the test commands; the memory performs corresponding operation behaviors according to the test commands; a protocol analyzer communicatively connected to the test board; the protocol analyzer is configured to capture the data stream of the memory when performing the operation behaviors; wherein, the tester is also communicatively connected to the protocol analyzer, and the tester is further configured to analyze the data stream and generate an analysis result. Through the test system and the test method for a memory provided by the present invention, the test efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage, and particularly to a test system and a test method for a memory. Background Art

[0002] In the field of memory research and development and testing, protocol analyzers are widely used to detect the compatibility between electronic devices and memories. By capturing the behavioral data of memories in specific scenarios (such as factory reset, sleep wake-up) and analyzing their functions, design hidden dangers can be quickly identified. In the current industrial and research environments, the test machine data test system is the core means to verify the device performance and ensure the product quality.

[0003] The existing technologies highly rely on manual operations, including manually executing test items, copying data, and screening key information from the massive data (such as hundreds of thousands of lines) of the protocol analyzer, resulting in low test efficiency and insufficient result accuracy. These defects severely restrict the practicality and large-scale application of the test system. Therefore, there is room for improvement. Summary of the Invention

[0004] The purpose of the present invention is to provide a test system and a test method for a memory, which can improve the test efficiency.

[0005] To solve the above technical problems, the present invention is realized through the following technical solutions:

[0006] The present invention provides a test system for a memory, including:

[0007] A test machine, configured to generate and send test commands;

[0008] A test board, on which a memory is connected; the test board is configured to receive the test commands; the memory executes corresponding operation behaviors according to the test commands;

[0009] A protocol analyzer, communicatively connected to the test board; the protocol analyzer is configured to capture the data stream of the memory when it executes operation behaviors;

[0010] Wherein, the test machine is also communicatively connected to the protocol analyzer, and the test machine is further configured to analyze the data stream and generate an analysis result;

[0011] The test machine includes:

[0012] An instruction generation module, configured to generate and send corresponding test commands according to a preset test task;

[0013] A data acquisition module, configured to receive the data stream captured by the protocol analyzer;

[0014] A data processing module, configured to associate the test command with the corresponding data stream; the data processing module is further configured to screen the associated data stream according to a preset condition;

[0015] A data analysis module, configured to analyze the memory according to the screened data stream and generate an analysis result.

[0016] In an embodiment of the present invention, the data analysis module is further configured to extract the fields of the CMD parameters of the data stream and determine the operation behavior of the memory based on the extracted fields;

[0017] The data analysis module is further configured to perform a base conversion process on the fields of the CMD parameters of the data stream and determine the operation behavior of the memory based on the CMD parameters after the base conversion;

[0018] The data analysis module is further configured to extract the CMD timestamp of the data stream, calculate the time difference of the operation behavior executed by the memory when receiving consecutive and identical test commands based on the extracted CMD timestamp, and determine the performance of the memory based on the calculated time difference.

[0019] In an embodiment of the present invention, the test board further includes:

[0020] A power supply module, configured to provide a power supply to the memory;

[0021] A switch module, configured to control the power supply module to supply power / cut off power according to the power supply instruction / power off instruction in the test command.

[0022] In an embodiment of the present invention, the power supply module includes:

[0023] A power supply unit, configured to provide a power supply;

[0024] A filtering unit, configured to filter the power supply;

[0025] A first interface unit, configured to receive the filtered power supply.

[0026] In an embodiment of the present invention, the power supply module further includes a power-on prompt unit, whose input end is connected to the power supply unit and whose output end is grounded; the power-on prompt unit is configured to generate corresponding prompt information according to the state of the power supply.

[0027] In an embodiment of the present invention, the switch module includes:

[0028] A switch unit, connected to the first interface unit, configured to receive the filtered power supply; the switch unit is further configured to receive a power supply instruction / power off instruction, perform a closing action according to the power supply instruction, and perform an opening action according to the power off instruction;

[0029] A second interface unit, whose input end is connected to the output end of the switching unit, and whose output end is connected to the power supply interface of the memory.

[0030] In an embodiment of the present invention, the switching unit includes:

[0031] A first switching unit, connected to the output end of the first interface unit, for receiving the filtered power supply; the first switching unit is further configured to receive a power supply instruction / power-off instruction, and perform a closing action according to the power supply instruction, and perform an opening action according to the power-off instruction;

[0032] A second switching unit, connected to the output end of the first switching unit; when the first switching unit performs a closing action, the second switching unit performs a closing action; when the first switching unit performs an opening action, the second switching unit performs an opening action.

[0033] In an embodiment of the present invention, the switching module further includes a power-on detection unit, whose input end is connected to the second switching unit, and whose output end is grounded; the power-on detection unit is configured to detect the pin voltage of the second switching unit to determine the working state of the second switching unit.

[0034] The present invention also discloses a method for testing a memory, including:

[0035] Generating and sending a corresponding test command through a tester according to a preset test task;

[0036] Receiving the test command through a test board and transmitting the test command to the memory; the memory performs corresponding operation behaviors according to the test command;

[0037] Capturing the data stream of the memory when performing the operation behavior through a protocol analyzer;

[0038] Receiving the data stream captured by the protocol analyzer through the tester;

[0039] The tester associates the test command with the corresponding data stream;

[0040] The tester filters the associated data stream according to preset conditions;

[0041] The tester analyzes the memory according to the filtered data stream and generates an analysis result.

[0042] As described above, the present invention provides a test system and a test method for a memory. Through automated testing and real-time signal data capture, it realizes the rapid analysis and problem location of the compatibility between the test board and the memory, significantly improves the test efficiency and accuracy, and reduces the test cost. This solution reduces data analysis errors caused by human operation errors, shortens the test cycle, optimizes resource management, and supports multi-dimensional report analysis.

[0043] Of course, it is not necessary for any product implementing the present invention to achieve all the above-mentioned advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0045] Figure 1 Schematic diagram of the test system for the memory in an embodiment of the present invention;

[0046] Figure 2 Schematic diagram of the tester and the memory in an embodiment of the present invention;

[0047] Figure 3 Schematic diagram of the tester in an embodiment of the present invention;

[0048] Figure 4 Schematic diagram of the test board in an embodiment of the present invention;

[0049] Figure 5 Circuit diagram of the power supply module in an embodiment of the present invention;

[0050] Figure 6 Circuit diagram of the switch module in an embodiment of the present invention;

[0051] Figure 7 Flowchart of the test method for the memory in an embodiment of the present invention.

[0052] In the figure: 100, tester; 110, instruction generation module; 120, data acquisition module; 130, data processing module; 140, data analysis module; 150, data storage module; 160, data display module; 170, report generation module; 200, protocol analyzer; 300, test board; 310, power supply module; 320, switch module; 400, memory. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0053] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0054] Please refer to Figure 1 , the present invention discloses a test system for a memory. The test system can perform automated tests on the memory 400 to test the performance of the memory 400 when performing different operations. The test system may include a tester 100, a protocol analyzer 200, and a test board 300.

[0055] In some embodiments, when testing the memory 400, first, the tester 100 can be used to generate and send test commands. Subsequently, the test board 300 can receive the test commands, and the memory 400 connected to the test board 300 can perform corresponding operation behaviors according to the test commands. Subsequently, the protocol analyzer 200 can capture the data stream when the memory is performing the operation behavior. Finally, the tester 100 can analyze the data stream and generate an analysis result.

[0056] Please refer to Figure 1 and Figure 2 , in some embodiments, the test board 300 can be a hardware component for transmitting test commands to the memory 400. There are multiple test pins on the test board 300. After the memory 400 is installed on the test board 300, the test pins of the test board 300 are correspondingly connected to the signal pins of the memory 400. The test pins of the test board 300 can be used to transmit test commands and receive operation behavior signals. The memory 400 performs corresponding operation behaviors according to the test commands. The MMC_CCLK test pin on the test board 300 can be connected to the CLK signal pin of the memory 400 for transmitting a clock signal to control the timing of data transmission. The MMC_CMD test pin on the test board 300 can be connected to the CMD signal pin of the memory 400 for transmitting a command signal to instruct the memory 400 to perform a specific operation. The MMC_DAT0 test pin on the test board 300 can be connected to the DAT0 signal pin of the memory 400 for transmitting data signals. The MMC_DAT1 test pin on the test board 300 can be connected to the DAT1 signal pin of the memory 400 for transmitting data signals. The MMC_DAT2 test pin on the test board 300 can be connected to the DAT2 signal pin of the memory 400 for transmitting data signals. The MMC_DAT3 test pin on the test board 300 can be connected to the DAT3 signal pin of the memory 400 for transmitting data signals.

[0057] Please refer to Figure 1 and Figure 2 In some embodiments, the protocol analyzer 200 can be an instrument for capturing and analyzing digital signals. The protocol analyzer 200 can be communicatively connected to the signal pins of the memory 400 through the test pins of the test board 300, and is used to capture the data stream of the memory 400 when performing an operation behavior. The protocol analyzer 200 can monitor the signal pins of the memory 400 in real time, capture the data stream generated by the memory 400 when executing a test command, and these data streams can be used for subsequent analysis and debugging. The protocol analyzer 200 can be connected to the RESET, CMD, DAT0, DAT1, DAT2, and DAT3 signal pins of the memory 400 through the test pins of the test board 300 to capture the signals on these pins. The RESET signal pin is used to reset the memory 400, the CMD signal pin is used to capture command signals, and the DAT0-DAT3 signal pins are used to capture data signals. The RESET signal pin of the memory 400 can be grounded through a common capacitor C0.

[0058] Please refer to Figure 3 In some embodiments, the tester 100 may include an instruction generation module 110, a data acquisition module 120, a data processing module 130, a data analysis module 140, a data storage module 150, a data display module 160, and a report generation module 170.

[0059] In some embodiments, the instruction generation module 110 can generate and send test commands according to preset test tasks. The test commands can include a power supply command, a power-off command, a wake-up command, a sleep command, a programming command, a read / write command, a factory reset command, etc. Among them, the power supply command can be used to supply power to the memory 400 to simulate device startup. The power-off command can be used to cut off the power supply of the memory 400 to simulate device shutdown. The wake-up command can be used to restore the memory 400 from the low-power state to the normal working state. The sleep command can be used to put the memory 400 into the low-power state. The programming command can be used to write data to the memory 400 to simulate the data storage process. The read / write command can be used to read data from or write data to the memory 400 to simulate the data access process. The factory reset command can be used to restore the memory 400 to the factory state to simulate device reset. Through these test commands, the memory 400 can execute specific operation behaviors to simulate actual usage scenarios.

[0060] In some embodiments, the data acquisition module 120 can be used to acquire data streams. The data streams can be the data captured by the protocol analyzer 200 when the memory 400 performs operation behaviors according to test commands. The data streams can include CMD timestamps, CMD commands, CMD parameters, CMD frequencies, etc. The CMD timestamp refers to the time point when the command is executed. The CMD command refers to the specific command being executed. The CMD parameter refers to the parameter of the command, such as the data content being written. The CMD frequency refers to the frequency at which the command is executed, reflecting the data transmission rate. By collecting the detailed data generated during the test process, the data acquisition module 120 can provide the raw materials for subsequent data processing and analysis.

[0061] In some embodiments, the data processing module 130 can be used to associate the test commands with the corresponding data streams and filter the associated data streams according to preset conditions. Among them, the filtering conditions can include time range, command type, parameter value, etc. For example, only process all CMD06 commands, or process all CMD21 commands, etc. The data processing module 130 can ensure the accuracy and relevance of the data, remove irrelevant or redundant data, and provide a clearer data set for analysis.

[0062] In some embodiments, the data analysis module 140 can be used to analyze the filtered data streams and generate analysis results. The analysis content can include performance metrics (such as read / write speed), stability, error rate, etc. By analyzing the data, the data analysis module 140 draws conclusions about the performance and behavior of the memory 400, providing a basis for optimization and decision-making.

[0063] In some embodiments, the data analysis module 140 can be used to extract the fields of the CMD parameters of the data streams and determine the operation behavior of the memory 400 based on the extracted fields. For example, the data analysis module 140 can process all CMD06 commands in the data stream. For the CMD06 command, the data analysis module 140 will analyze the 3rd to 8th bits of its CMD parameter (data). If the value of these 6 bits is "03 21", it is determined that the memory 400 has a Cache behavior, that is, the Cache is in the enabled state (Enable). Among them, "03 21" can be used to identify whether the Cache function of the memory is enabled. The data analysis module 140 determines the behavior of the memory 400 by checking the value of this specific field. The Cache function being enabled means that the memory 400 starts the buffer.

[0064] In some embodiments, the data analysis module 140 can be used to perform a base conversion process on the fields of the CMD parameters of the data stream, and determine the operation behavior of the memory 400 based on the fields of the CMD parameters after the base conversion. For example, the data analysis module 140 can process all CMD23 commands of the data stream. For the CMD23 command, the data analysis module 140 can convert the fields of the CMD parameters from hexadecimal to binary. If the 31st bit in the binary representation is 1, then it is determined that Packed is Enable, otherwise it is Disable. If the total binary length is 32 bits and the 31st bit is 0, then it is determined that Reliable_Write is Enable, otherwise it is Disable. For example, converting the hexadecimal "40000000" to the binary "1000000000000000000000000000000"; another example, converting the hexadecimal "60000000" to the binary "11000000000000000000000000000000". Among them, determining that Packed is Enable means that the memory 400 enters a specific operation mode. In this mode, data is stored or processed in a compact and efficient manner. By packing multiple data items together, the space required for data storage is reduced, or the efficiency of data transmission and processing is improved; conversely, determining that Packed is Disable means that the memory 400 does not enter a specific operation mode. Determining that Reliable_Write is Enable means that the memory 400 has enabled the reliable write operation mode. The reliable write operation mode can ensure that data can be accurately written into the memory 400 by adopting some additional verification and error correction mechanisms to ensure the integrity and reliability of the data; conversely, determining that Reliable_Write is Disable means that the memory 400 has disabled the reliable write operation mode.

[0065] In some embodiments, the data analysis module 140 can be used to extract the CMD timestamps of the data stream, calculate the time difference of the operation behaviors executed by the memory when receiving consecutive and identical test commands based on the extracted CMD timestamps, and determine the performance of the memory based on the calculated time difference. For example, the data analysis module 140 can process all the CMD21 commands in the data stream. For the CMD21 commands, the data analysis module 140 will analyze the timestamps of two consecutive CMD21 commands and calculate the time difference between them. These time differences are used to measure the Tuning speed of the memory. Among them, the CMD timestamp provides the specific time point when the command is executed. By comparing the timestamps of consecutive commands, the time required to execute each command can be calculated. These time difference data can be used to evaluate the performance of the memory, such as the Tuning speed. If the time difference between two consecutive CMD21 commands is very small, it indicates that the memory has a fast response speed and good performance.

[0066] In some embodiments, the data storage module 150 can be used to store the filtered data stream and analysis results, and the storage format can include databases, file systems, etc. The data storage module 150 can save the important data and analysis results during the test for future reference or further analysis.

[0067] In some embodiments, the data display module 160 can be used to display the test analysis results in real time and perform monitoring and display. The display content of the data display module 160 can include real-time charts, status indicators, alarm information, etc. The data display module 160 can enable users to timely understand the test status and results, enhancing the transparency and real-time nature of the test process.

[0068] In some embodiments, the report generation module 170 can be used to present the analysis results in the form of a report, including matrix tables, charts, etc. The report content of the report generation module 170 can include a test overview, detailed analysis results, suggestions, and conclusions, etc. The report generation module 170 can provide users with test results that are easy to understand and use, helping users make decisions based on the test objectives.

[0069] Please refer to Figure 4 , in some embodiments, the test board 300 may further include a power supply module 310 and a switch module 320. Among them, the power supply module 310 can be used to provide a power supply to the memory. The switch module 320 can be used to control the power supply module 310 to supply power / cut off power according to the power supply instruction / power-off instruction in the test command to complete the restart test of the memory 400.

[0070] Please refer to Figure 5, in some embodiments, the power supply module 310 may include a power supply unit, a filtering unit, a protection unit, a power supply switch unit, a first interface unit, and a power-on prompt unit. Among them, the power supply unit can be used to provide a 5V DC power supply. The filtering unit can be used to filter the power supply. The protection unit can be used to protect the power supply module 310. The power supply switch unit can be used to control the on / off of the power supply. The first interface unit can be used to receive the filtered power supply. The power-on prompt unit can be used to generate corresponding prompt information according to the state of the power supply.

[0071] Please refer to Figure 5 , in some embodiments, the filtering unit may include an electrolytic capacitor C1 and a common capacitor C2. The input end of the electrolytic capacitor C1 can be connected to the output end of the power supply unit, and the input end of the common capacitor C2 can be connected to the output end of the power supply unit. The output ends of the electrolytic capacitor C1 and the common capacitor C2 can be grounded. The electrolytic capacitor C1 and the common capacitor C2 can be used for decoupling and filtering. The electrolytic capacitor C1 and the common capacitor C2 can effectively filter out high-frequency noise, smooth the power signal, and ensure the stability of the circuit. The model of the electrolytic capacitor C1 can be CASE_C, and its capacitance can be 100 μF. The model of the common capacitor C2 can be C0603, and its capacitance can be 0.1 μF.

[0072] Please refer to Figure 5 , in some embodiments, the protection unit can be a fuse FU, and its model can be FUSE-MSMD350. Among them, the fuse can be used to prevent the circuit from being damaged when the current is too large. The fuse interrupts the current by melting when the current exceeds its rated value, thereby protecting the circuit from overload or short circuit damage.

[0073] Please refer to Figure 5 , in some embodiments, the input end of the power supply switch unit can be electrically connected to the output end of the protection unit. The power supply switch unit can be a double-pole double-throw switch (DPDT), and its model can be SW DPDT_6P_TS-11P-A1. Among them, the power supply switch unit can have 6 pins, and the 6 pins can be divided into two groups. Each group has a common pin and two switching pins, and the connection of the pins can select different circuit paths according to needs.

[0074] Please refer to Figure 5 , in some embodiments, the first interface unit can be a pluggable power interface, and its model can be DC_DC_061DHA_2d0. The input end (pin 1) of the first interface unit can be electrically connected to the output end of the power supply switch unit. The shrapnel (pins 2 and 3) of the first interface unit can be grounded.

[0075] Please refer to Figure 5 , in some embodiments, the power-on prompt unit may include a resistor R1 and an LED lamp. Among them, the input end of the resistor R1 may be connected to the output end of the power supply unit, the output end of the resistor R1 may be connected to the input end of the LED lamp, and the output end of the LED lamp may be grounded. Among them, the resistor R1 can play a role in reducing voltage so that the power supply after voltage reduction can supply power to the LED lamp. When the power supply is normal, the LED lamp can be constantly on. When the power supply is abnormal, the LED lamp may flash, the brightness may decrease, or the lamp may go out. The model of the LED lamp may be DV1 LED SMT 0603 GREEN.

[0076] Please refer to Figure 6 , in some embodiments, the switch module 320 may include a switch unit, a second interface unit, and a power-on detection unit. Among them, the switch unit may be connected to the first interface unit for receiving the filtered power supply; the switch unit is also used for receiving a power supply instruction / power-off instruction and performing a closing action according to the power supply instruction, and performing an opening action according to the power-off instruction. The second interface unit, its input end is connected to the output end of the switch unit, and its output end is connected to the power supply interface of the memory 400.

[0077] Please refer to Figure 6 , in some embodiments, the switch unit may include a first switch unit and a second switch unit. The first switch unit may be connected to the output end of the first interface unit for receiving the filtered power supply; the first switch unit is also used for receiving a power supply instruction / power-off instruction and performing a closing action according to the power supply instruction, and performing an opening action according to the power-off instruction. The second switch unit may be connected to the output end of the first switch unit; when the first switch unit performs a closing action, the second switch unit performs a closing action; when the first switch unit performs an opening action, the second switch unit performs an opening action.

[0078] Please refer to Figure 6 , in some embodiments, the first switch unit may include a resistor R2, a resistor R3, an NPN transistor Q1, an NPN transistor Q2, and a common capacitor C3. Among them, the model of the NPN transistor Q1 may be LS3407PG. The model of the NPN transistor Q2 may be MMBT3904.

[0079] In some embodiments, one end of resistor R2 can be connected to a USB serial port module of the tester 100 for receiving the power supply instruction (PORT 1_ON) and the power-off instruction (PORT 1_OFF) sent by the tester 100. The other end of resistor R2 can be connected to the base of NPN transistor Q2. The emitter of NPN transistor Q2 can be grounded. The collector of NPN transistor Q2 can be respectively connected to one end of resistor R3 and the pin 1 (GATE, gate) of NPN transistor Q1. The other end of resistor R3 and the pin 2 (SOURCE, source) of NPN transistor Q1 can be respectively connected to the power output terminal of the power supply module 310 to receive a 5V DC voltage. The pin 3 (DRAIN, drain) of NPN transistor Q1 can be used as the output pin. The power output terminal of the first interface unit of the power supply module 310 can be simultaneously connected to the pin 3 of NPN transistor Q1 and one end of the ordinary capacitor C3, and the other end of the ordinary capacitor C3 can be grounded.

[0080] In some embodiments, after the tester 100 issues the power supply instruction (PORT 1_ON), the power output terminal of the first interface unit of the power supply module 310 will send a 3.3V DC voltage to the base of NPN transistor Q2. After receiving this DC voltage, NPN transistor Q2 can be turned on. At this time, the collector of NPN transistor Q2 will send a signal to the gate of NPN transistor Q1 to control NPN transistor Q1 to turn on. After NPN transistor Q1 is turned on, the 5V DC voltage received by its source can be output from the drain to the second switch unit. Among them, the resistance value of resistor R3 can be 47KΩ. The resistance value of resistor R2 can be 1KΩ. The capacitance of the ordinary capacitor C3 can be 1μF.

[0081] Please refer to Figure 6 , in some embodiments, the second switch unit can include a relay and an interface. Among them, the relay can be electrically connected to the output terminal of the first switch unit. When the first switch unit is closed, the relay is also in the closed state. When the first switch unit is opened, the relay is in the open state. One end of the relay can be connected with an interface. The input end of the interface can be electrically connected to the output end of the relay, and the output end of the interface can be connected to the power supply interface of the memory 400. Among them, the model of the relay can be JQC-3FF-005-1ZS, which has 5 pins. The model of the interface can be WI500V, which has 3 pins.

[0082] In some embodiments, the pin 1 (positive pin) of the relay can be connected to the drain of the NPN transistor Q1 to receive a 5V DC voltage. The pin 3 (COM pin) of the relay can be connected to the pin 2 of the interface. The pin 2 (negative pin) of the relay can be grounded. The pin 4 (Normally Closed, NC) of the relay can be connected to the pin 3 of the interface. The pin 5 (Normally Open, NO) of the relay can be connected to the pin 1 of the interface. The pin 1 and pin 3 of the interface can be respectively connected to the power supply interface of the memory 400.

[0083] In some embodiments, when the testing machine 100 sends a power supply instruction to the first switch unit, the first switch unit is in a closed state at this time and outputs a 5V DC voltage to the pin 1 of the relay. Subsequently, the internal circuit of the relay is conducted, and the power supply passes through the pin 2 of the interface, the pin 3 of the relay, the pin 5 of the relay, and the pin 1 of the interface in sequence, and then supplies power to the power supply interface of the memory 400.

[0084] In some embodiments, when the testing machine 100 sends a power-off instruction to the first switch unit, the first switch unit is in an open state at this time, and the internal circuit of the relay is also in an open state. At this time, the power supply cannot pass through the relay and cannot supply power to the power supply interface of the memory 400.

[0085] In some embodiments, the input end of the power-on detection unit can be connected to the second switch unit, and its output end is grounded; the power-on detection unit is used to detect the pin voltage of the second switch unit to judge the working state of the second switch unit. Among them, the power-on detection unit can include a resistor R4, a resistor R5, and a common capacitor C4. One end of the resistor R4 can be connected to the pin 3 (COM pin) of the relay and the pin 2 of the interface. The other end of the resistor R4 can be connected to one end of the resistor R5 and the common capacitor C4. The other ends of the resistor R5 and the common capacitor C4 can be grounded. By detecting whether there is a voltage between the resistor R4 and the resistor R5, it is possible to judge whether the relay fails. The resistance value of the resistor R4 can be 100KΩ. The resistance value of the resistor R5 can be 10KΩ. The capacitance of the common capacitor C3 can be 100nF.

[0086] It can be seen that in the above solution, through automated testing and real-time signal data capture, the rapid analysis and problem location of the compatibility between the test board and the memory are realized, the test efficiency and accuracy are significantly improved, and the test cost is reduced. This solution reduces the data analysis errors caused by human operation errors, shortens the test cycle, optimizes resource management, and supports multi-dimensional report analysis.

[0087] Please refer to Figure 7, the present invention also provides a method for testing a memory, and this testing method can be applied to the above-mentioned testing system. The testing method may include the following steps:

[0088] Step S10: Generate and send corresponding test commands through a tester according to a preset test task;

[0089] Step S20: Receive the test commands through a test board and transmit the test commands to the memory; the memory performs corresponding operation behaviors according to the test commands;

[0090] Step S30: Capture the data stream of the memory when performing operation behaviors through a protocol analyzer;

[0091] Step S40: Receive the data stream captured by the protocol analyzer through the tester;

[0092] Step S50: The tester associates the test commands with the corresponding data stream;

[0093] Step S60: The tester filters the associated data stream according to preset conditions;

[0094] Step S70: The tester analyzes the memory according to the filtered data stream and generates an analysis result.

[0095] The embodiments of the present invention disclosed above are only used to help explain the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principle and practical application of the present invention, so that those skilled in the art in the relevant technical field can understand and utilize the present invention well. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A test system for a memory, characterized in that, Comprising: A test machine, configured to generate and send test commands; A test board, to which a memory is connected; The test board is configured to receive the test commands; The memory performs corresponding operation behaviors according to the test commands; A protocol analyzer, communicatively connected to the test board; the protocol analyzer is configured to capture the data stream when the memory is performing operation behaviors; Wherein, the test machine is also communicatively connected to the protocol analyzer, and the test machine is further configured to analyze the data stream and generate an analysis result; The test machine includes: An instruction generation module, configured to generate and send corresponding test commands according to a preset test task; A data acquisition module, configured to receive the data stream captured by the protocol analyzer; A data processing module, configured to associate the test commands with the corresponding data stream; the data processing module is further configured to screen the associated data stream according to preset conditions; A data analysis module, configured to analyze the memory according to the screened data stream and generate an analysis result; The data analysis module is further configured to extract the fields of the CMD parameters of the data stream and determine the operation behaviors of the memory based on the extracted fields; The data analysis module is further configured to perform a radix conversion process on the fields of the CMD parameters of the data stream and determine the operation behaviors of the memory based on the CMD parameters after radix conversion; The data analysis module is further configured to extract the CMD timestamps of the data stream, calculate the time difference of the operation behaviors performed by the memory when receiving consecutive and identical test commands based on the extracted CMD timestamps, and determine the performance of the memory based on the calculated time difference.

2. The test system for a memory according to claim 1, wherein The test board further includes: A power supply module, configured to provide a power supply to the memory; A switch module, configured to control the power supply module to supply power / cut off power according to the power supply instruction / power off instruction in the test command.

3. The test system for a memory according to claim 2, wherein, The power supply module includes: A power supply unit, configured to provide a power supply; A filtering unit, configured to filter the power supply; A first interface unit, configured to receive the filtered power supply.

4. The test system for a memory according to claim 3, characterized in that, The power supply module further includes a power-on prompt unit, whose input end is connected to the power supply unit and whose output end is grounded; the power-on prompt unit is configured to generate corresponding prompt information according to the state of the power supply.

5. The test system for a memory according to claim 3, characterized in that, The switch module includes: A switch unit, connected to the first interface unit, configured to receive the filtered power supply; the switch unit is further configured to receive a power supply instruction / power off instruction and perform a closing action according to the power supply instruction, and perform an opening action according to the power off instruction; A second interface unit, whose input end is connected to the output end of the switch unit and whose output end is connected to the power supply interface of the memory.

6. The test system for a memory according to claim 5, wherein, The switch unit includes: A first switch unit, connected to the output end of the first interface unit, configured to receive the filtered power supply; the first switch unit is further configured to receive a power supply instruction / power off instruction and perform a closing action according to the power supply instruction, and perform an opening action according to the power off instruction; A second switch unit, connected to the output end of the first switch unit; when the first switch unit performs a closing action, the second switch unit performs a closing action; when the first switch unit performs an opening action, the second switch unit performs an opening action.

7. The test system for a memory according to claim 6, wherein, The switch module further includes a power-on detection unit, whose input end is connected to the second switch unit and whose output end is grounded; the power-on detection unit is used to detect the pin voltage of the second switch unit to determine the working state of the second switch unit.

8. A testing method for a memory, characterized in that, Including: According to a preset test task, generate and send corresponding test commands through a test machine; Receive the test commands through a test board and transmit the test commands to a memory; The memory performs corresponding operation behaviors according to the test commands; Capture the data stream of the memory when it performs operation behaviors through a protocol analyzer; Receive the data stream captured by the protocol analyzer through the test machine; The test machine associates the test commands with the corresponding data streams; The test machine filters the associated data streams according to preset conditions; The test machine analyzes the memory according to the filtered data streams and generates an analysis result; Extract the fields of the CMD parameters of the data stream and determine the operation behavior of the memory based on the extracted fields; Perform a base conversion process on the fields of the CMD parameters of the data stream and determine the operation behavior of the memory based on the CMD parameters after base conversion; Extract the CMD timestamp of the data stream, calculate the time difference of the operation behaviors performed by the memory when receiving consecutive and identical test commands based on the extracted CMD timestamp, and determine the performance of the memory based on the calculated time difference.

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