Semiconductor device package with integrated laminated transformer

Abstract

The invention relates to a semiconductor device package with an integrated laminated transformer. Described examples include: a package substrate (Fig. 5H, 521) including a mounting pad (535), at least one die pad (531), a first set of conductive leads (510), and a second set of conductive leads (511) spaced apart from the first set of conductive leads; a semiconductor die (506) mounted to the at least one die pad with a first die bonding material; a laminated transformer (453) having an integrated magnetic material mounted on the mounting pad with a second die bonding material; a wire bond or a first electrical connection with a bond (519) between a bond pad of the semiconductor die and the first set of conductive wires; and a second electrical connection (519) with a wire bond or a bond between the bond pad of the semiconductor die and the laminated transformer with the integrated magnetic material.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor device packages having semiconductor dies and including integrated transformers. Background Art

[0002] Semiconductor device circuits for power applications typically include transformers having coils that are isolated from each other by a core of dielectric material but are magnetically coupled to each other. In one example application, a transformer can be used to transfer power across an electrical isolation barrier. By applying an alternating current (AC) signal to a primary coil, a corresponding AC signal is induced in a secondary coil by magnetic coupling, enabling power transfer across the isolation barrier. Recently, transformers have been integrated within semiconductor device packages.

[0003] In one method, a transformer including isolated coils is formed on a laminated substrate of dielectric material having a package substrate that can be mounted onto mounting pads. First, a bottom magnetic sheet material is mounted to a die pad of the package substrate, the laminate is mounted to the bottom magnetic sheet, and a top magnetic sheet is mounted to the laminate. The magnetic sheets and the laminate are assembled using a die attach film (DAF) material. A semiconductor die is also mounted to the package substrate on additional die pads that are spaced apart from the transformer, and electrical connections can be made between the semiconductor die and the transformer to form a circuit while the semiconductor dies remain electrically isolated from each other. A molding compound can be used to form a package body of the integrated device to be provided in the semiconductor device package.

[0004] The method of mounting magnetic sheets and laminated transformers in the method described above requires multiple die attach depositions and die attach thermal curing steps. Additionally, the magnetic sheets are spaced apart from the coils in the transformer by die attach materials and are spaced apart from each other by these materials and by the laminate, which can result in AC winding losses in the transformer, thereby limiting the effective power transfer through the transformer.

[0005] In another method, a "on-die" transformer is formed on a dielectric layer directly deposited on a device side surface of a semiconductor die. This method improves device integration, but has a high manufacturing cost, requires special processing in the semiconductor die manufacturing process, and the resulting transformer has a relatively low efficiency. The size of the on-die transformer is also limited by the size of the semiconductor die, or alternatively, the use of the on-die transformer requires an increase in the semiconductor die area, thereby increasing the die cost.

[0006] There is a need for a reliable and robust semiconductor device package integrating a transformer for power applications, which has high efficiency and relatively low cost. Summary of the Invention

[0007] In the described example, a method includes: forming an encapsulation substrate having a board side surface and an opposing top surface, the encapsulation substrate having a first set of conductive leads, a second set of conductive leads electrically isolated from the first set of conductive leads, at least one die pad for mounting a semiconductor die, and a mounting pad spaced apart from the at least one die pad for mounting a transformer; mounting the semiconductor die on the at least one die pad using a first die attach material; mounting a laminated transformer having an integral magnetic material on the mounting pad using a second die attach material; forming a wire bond or a tape bond electrical connection between a bond pad of the semiconductor die and the first set of conductive leads on the encapsulation substrate; forming a wire bond or a tape bond electrical connection between the bond pad of the semiconductor die and the laminated transformer having an integral magnetic material; and covering the electrical connections, the semiconductor die, the laminated transformer having an integral magnetic material, and portions of the encapsulation substrate with a molding compound.

[0008] In another described example, a method includes: forming a first conductor layer on a first surface of a dielectric core and forming a second conductor layer on a second surface of the dielectric core opposite the first surface; patterning the first conductor layer to form a first coil on the first surface and patterning the second conductor layer to form a second coil on the second surface; depositing a magnetic material on the first surface in contact with the first coil and depositing a magnetic material on the second surface in contact with the second coil; and forming a laminated layer of dielectric material over the first surface and the second surface, the laminated layer of dielectric material covering the first coil and the magnetic material above the first coil and covering the second coil and the magnetic material above the second coil.

[0009] In another described example, a device includes: an encapsulation substrate including a mounting pad, at least one die pad, a first set of conductive leads, and a second set of conductive leads spaced apart from the first set of conductive leads; a semiconductor die mounted to the at least one die pad using a first die attach material; a laminated transformer having an integral magnetic material mounted on the mounting pad using a second die attach material; a first electrical connection of a wire bond or a tape bond between a bond pad of the semiconductor die and the first set of conductive leads; a second electrical connection of a wire bond or a tape bond between the bond pad of the semiconductor die and the laminated transformer having an integral magnetic material; and a molding compound covering the electrical connections, the semiconductor die, the laminated transformer having an integral magnetic material, and portions of the encapsulation substrate.

[0010] In another described example, a transformer includes: a first coil formed in a first conductor layer on a first surface of a dielectric core, and a second coil formed in a second conductor layer on a second surface of the dielectric core opposite the first surface; magnetic material located on the first surface in contact with the first coil, and magnetic material located on the second surface in contact with the second coil; and a laminate layer of dielectric material located above the first surface and the second surface, the laminate layer of dielectric material covering the first coil and the magnetic material above the first coil, and covering the second coil and the magnetic material above the second coil. Description of the Drawings

[0011] Figures 1A to 1B A semiconductor wafer and individual semiconductor die are shown, respectively.

[0012] Figures 2A to 2B A semiconductor device package that can be used for an arrangement is shown in a top-side projection view and a board-side projection view, respectively.

[0013] Figure 3 An example circuit that can be formed within an arranged semiconductor device package is shown in block diagram form.

[0014] Figures 4A to 4E Selected steps for forming a laminated transformer with an integral magnetic material for various arrangements are shown in a series of cross-sectional views.

[0015] Figures 5A to 5H Selected steps for forming an example semiconductor device package for an arrangement are shown in a series of views including a plan view and an end view.

[0016] Figure 6 An example method for forming a semiconductor device package for an arrangement is shown in flowchart form.

[0017] Figure 7 An example method for forming a laminated transformer with an integral magnetic material for an arrangement is shown in another flowchart. Detailed Description

[0018] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding parts. The figures are not necessarily drawn to scale.

[0019] Elements are described herein as "coupled". The term "coupled" includes elements that are directly connected and elements that are indirectly connected, and even elements that are electrically connected through intermediate elements or wires that are coupled.

[0020] The term "semiconductor die" is used herein. A semiconductor die can be, for example, a discrete semiconductor device such as a bipolar transistor, several discrete devices such as a pair of power FET switches fabricated together on a single semiconductor die, or a semiconductor die can be an integrated circuit having multiple semiconductor devices, such as multiple capacitors in an A / D converter. A semiconductor die can include passive devices such as resistors, inductors, filters, sensors, etc., or active devices such as transistors. A semiconductor die can be an integrated circuit having hundreds or thousands of transistors with functional circuits coupled to form, for example, a microprocessor or a memory device. In an example arrangement, a semiconductor device package can include one or more semiconductor dies mounted on a package substrate. In a specific example, two semiconductor dies are mounted on the package substrate and are electrically isolated from each other. A transformer is mounted to the package substrate, and the transformer can transfer power between the semiconductor dies across an isolation barrier.

[0021] The term "semiconductor device package" is used herein. A semiconductor device package has at least one semiconductor die electrically coupled to terminals and has a package body that protects and covers the semiconductor die. In some arrangements, multiple semiconductor dies can be packaged together. For example, a power metal oxide semiconductor (MOS) field effect transistor (FET) semiconductor die and a logic semiconductor die (e.g., a gate driver die or a controller die) can be packaged together to form a single packaged electronic device. Additional components such as passive elements can be included in the packaged electronic device.

[0022] A semiconductor die is mounted to a package substrate that provides conductive leads; a portion of the conductive leads forms terminals for the packaged device. A semiconductor die can be mounted to the package substrate such that the device side surface faces away from the substrate and the back side surface faces a die pad of the package substrate and is mounted to the die pad. In a wire-bonded semiconductor device package, bonding wires couple the conductive leads of the package substrate to bond pads on the semiconductor die. A semiconductor device package can have a package body formed of a molding compound, which is a thermosetting epoxy resin formed in a molding process, or is formed by using an epoxy resin, plastic, or resin that is liquid at room temperature and subsequently cures. The package body can provide a hermetic enclosure for the packaged device. The package body can be formed in a mold using an encapsulation process; however, a portion of the leads of the package substrate is not covered during encapsulation, and these exposed lead portions provide the terminals for the semiconductor device package.

[0023] When encapsulating a semiconductor device, a molding compound can be used to partially cover the encapsulation substrate, cover the semiconductor die, and cover the electrical connections from the semiconductor die to the encapsulation substrate. This can be referred to as the "encapsulation" process, but some portions of the encapsulation substrate are not covered by the molding compound during encapsulation. For example, the terminals and leads are exposed from the molding compound. Encapsulation is typically a compression molding process, where a thermosetting molding compound such as an epoxy resin can be used. A room temperature solid or powder molding compound can be heated to a liquid state, and then molding can be performed by pressing the liquid molding compound into a mold. Transfer molding can be used. Unit molds shaped to surround individual devices can be used, or alternatively, block molding can be used to form encapsulations for several devices simultaneously from the molding compound. The devices can be arranged in an array of several, hundreds, or even thousands of devices in rows and columns to be molded together. After molding, in a sawing operation, the individual encapsulated devices are cut from each other by cutting through the molding compound and the encapsulation substrate in the sawing channels formed between the devices.

[0024] The term "encapsulation substrate" is used herein. An encapsulation substrate is a substrate that is arranged to receive a semiconductor die and support the semiconductor die in a completed semiconductor device package. Encapsulation substrates that can be used for the arrangement include conductive lead frames, which can be formed from copper, aluminum, stainless steel, steel, and alloys (e.g., alloy 42 and copper alloys). The lead frames can be provided in strips or arrays. The conductive lead frames can be provided as panels in the form of strips or arrays having unit device portions in rows and columns. The semiconductor die can be placed on the corresponding unit device portions within the strip or array. The semiconductor die can be placed on a die mounting area for each encapsulation device, and die attach or die adhesive can be used to mount the semiconductor die to the die mounting area. In a wire bond encapsulation, bond wires can couple bond pads on the semiconductor die to the leads of the lead frame. The lead frame can have a plated portion in the area designated for wire bonding, for example, silver plating can be used. After the bond wires are in place, a protective material such as a molding compound can be used to cover a portion of the encapsulation substrate, the semiconductor die, and at least a portion of the die pads.

[0025] The term "electrically isolated" is used herein. In an example arrangement, a package substrate has a first set of conductive leads and a second set of conductive leads, and has a first die pad for a semiconductor die, a second die pad spaced apart from the first die pad for a second semiconductor die, and a mounting pad spaced apart from the second die pad for a transformer. By spacing apart conductive elements and grouping the conductive leads into a first set and a second set, two electrically isolated voltage schemes are formed, one for connection to the first semiconductor die and one for connection to the second semiconductor die. Each voltage scheme has its own voltage and ground potential connections that are not connected to the voltage and ground potential of the other voltage scheme, thereby providing electrical isolation between the input side and the output side of the packaged device. In an example arrangement using a transformer and an electrically isolated lead frame to mount two isolated semiconductor dies, the transformer is electrically isolated from the package substrate while one coil of the transformer is coupled to one of the semiconductor dies and the other coil of the transformer is coupled to the other of the semiconductor dies, thereby allowing energy to be transferred across the isolation barrier formed by the transformer core using electromagnetic coupling between the coils. The two semiconductor dies are coupled to voltage and ground in the two isolated voltage schemes.

[0026] The term "scribe lane" is used herein. A scribe lane is a portion of a semiconductor wafer between semiconductor dies. Sometimes the term "saw street" is used in the related literature. Once semiconductor processing is complete and the semiconductor devices are finished, the semiconductor devices are separated into individual semiconductor dies by cutting the semiconductor wafer along the scribe lanes. The separated dies can then be individually removed and processed for further processing. This process of removing the dies from the wafer is called "singulation" or sometimes called "dicing". The scribe lanes are arranged on the four sides of the semiconductor dies and form rectangular semiconductor dies when the dies are singulated from each other.

[0027] The term "saw cut lane" is used herein. A saw cut lane is an area between molded electronic devices that is used to allow a saw, such as a mechanical blade, laser, or other cutting tool, to pass between the molded electronic devices to separate the devices from each other. This process is another form of singulation. When the molded electronic devices are provided in the form of a strip with one device adjacent to another along the strip, the saw cut lanes are parallel and perpendicular to the length of the strip. When the molded electronic devices are provided in the form of an array of devices in rows and columns, the saw cut lanes include two sets of parallel saw cut lanes that are perpendicular to each other, and thus the saw will traverse the molded electronic devices in two different directions to cut the packaged electronic devices in the array apart from each other.

[0028] In this document, the term "quad flat no-lead" or "QFN" is used for a type of electronic device package. A QFN package has conductive leads that coextend with the sides of the molded package body, and in a quad package, the leads are located on four sides. Alternative flat no-lead packages can have leads on two sides or on only one side. These can be referred to as "small outline no-lead" or "SON" packages. Leadless packaged electronic devices can be surface mounted to a board. Leaded packages can be used with an arrangement in which the leads extend away from the package body and are shaped to form portions for soldering to the board. Small outline packages (SOPs) can be used with such an arrangement. The leads for leaded packages are arranged for solder mounting to the board. The leads can be shaped to extend toward the board and form a mounting surface. Gull-wing leads, J-shaped leads, and other lead shapes can be used. Small outline integrated circuit (SOIC) packages with leads can be used with such an arrangement. Wide SOIC packages can be used with such an arrangement. Dual in-line packages (DIPs) can be used. In a DIP, the lead ends in the pin-shaped portions can be inserted into conductive holes formed in the circuit board, and solder is used to couple the leads to the conductors within the holes.

[0029] The term "magnetic material" is used herein. Magnetic materials that can be used for such an arrangement include iron oxide Fe 2 O 3 , additional available examples include nickel ferrite (NiFe), nickel zinc ferrite (NiZnFe), and manganese zinc ferrite (MnZnFe). Ferrites are ferrimagnetic and become magnetized in the presence of a magnetic field.

[0030] The term "laminated transformer with an integral magnetic material" is used herein. In an example arrangement, a transformer including at least a primary coil and a secondary coil is formed on a first surface and a second opposite surface of a dielectric core. The term "planar coil" is used herein. A planar coil is a conductor coil formed by a continuous conductor that forms a coil in a common plane (e.g., a horizontal or vertical plane). In an example arrangement, the primary or first coil and the secondary or second coil are conductors patterned to form a planar coil, and the conductor can be, for example, copper or a copper alloy that forms a planar coil. The first coil and the second coil can be aligned with each other to form a transformer. A laminate layer of additional dielectric material covers both surfaces of the dielectric core and the coils to complete the laminated transformer. In an example arrangement, a magnetic material is deposited over the first coil and the second coil and in contact with the coil conductors. In an example arrangement, the magnetic material is deposited as a magnetic paste or magnetic ink using a stencil, drop-on-demand, or inkjet printing technique. Among the advantages of the arrangement, the magnetic material is deposited on and in contact with the coil conductors without any intervening material or space (compared to existing methods that use magnetic films or sheets mounted above the surface of the laminated transformer).

[0031] In an example arrangement, a lead frame having isolated lead portions can be used as a package substrate. The lead frame has two electrically isolated portions, where a first set of conductive leads is configured to couple a DC output voltage to a load, and where a second set of conductive leads is configured to couple to a DC input voltage. The laminated transformer with an integral magnetic material of the arrangement is mounted to mounting pads of the lead frame, and provides an isolation barrier between a device coupled to the DC input voltage and a device coupled to provide the DC output voltage. A primary side drive circuit is disposed on a first semiconductor die on a first die pad mounted to the lead frame, and a secondary side rectifying circuit is disposed on a second semiconductor die on a second die pad mounted to the lead frame, and the two semiconductor dies are electrically isolated from each other. Electrical connections are made between the semiconductor dies and the coils of the transformer to form an integrated DC-DC converter as a packaged semiconductor device with an integrated laminated transformer. In the arrangement, the laminated transformer includes an integral magnetic material within the dielectric layer of the laminated transformer. As shown in the example arrangement described below, the laminated transformer is a passive component that can be effectively used within a semiconductor device package. Alternatively, the laminated transformer can be mounted on or to a semiconductor device package, or mounted to a board or module to provide a transformer.

[0032] Figures 1A to 1B A semiconductor wafer and individual semiconductor dies are shown in two projection views. In Figure 1AIn [the figure], semiconductor wafer 101 is shown as having an array of semiconductor dies 105 arranged in rows and columns. The semiconductor dies 105 are formed using a manufacturing process in a semiconductor manufacturing facility, the manufacturing process including ion implantation for dopant carrier, annealing, oxidation, dielectric and conductor deposition, lithography, patterning, etching, chemical mechanical polishing (CMP), electroplating, damascene electroplating, and other processes for manufacturing semiconductor devices. Devices are formed on the device side surface of the semiconductor die. Scribing lanes 103 and 104 that are perpendicular to each other and extend across the semiconductor wafer 101 in parallel groups separate the rows and columns of the completed semiconductor dies 105, and provide areas for dividing the semiconductor wafer 101 to separate the semiconductor dies 105 from each other.

[0033] Figure 1B A single semiconductor die 105 having bonding pads 108 is illustrated, the bonding pads being conductive pads electrically coupled to devices (not shown for simplicity) formed in the semiconductor die 105. After the semiconductor wafer is completed in a semiconductor factory, the semiconductor dies 105 are separated from the semiconductor wafer 101 by wafer dicing, or singulated from each other using the scribing lanes 103, 104 (see Figure 1A ). Wafer dicing can be performed by a mechanical saw, by ablative laser cutting, by a stealth laser process that forms stress dislocation regions along the scribing lanes, or by etching through or partially through the semiconductor wafer along the scribing lanes using a plasma cutting process. When the wafer is etched partially or processed using stealth laser cutting, an expanding cutting tape can be used, and the dies can be pulled apart along the scribing lanes to complete singulation.

[0034] Figures 2A to 2B Example semiconductor device packages 200 that can be used in conjunction with the arrangement are illustrated in a top side projection view and a board side projection view, respectively. In Figure 2A , the view is from the top side of the semiconductor device package 200, and the molding compound 223 forms the package body while terminals 210 and 211 are shown. In this example semiconductor device package 200, portions of the terminals 210, 211 are shaped to form leads that extend outside the molding compound 223 forming the package body, and the leads are shaped to provide leg portions for mounting the semiconductor device package 200 to a board or module, for example, by using a surface mount technology (SMT) soldering process.

[0035] In Figure 2BIn [the figure], a board side view of a semiconductor device package 200 is shown. The molding compound 223 is shown as having a first set of leads 210 shown on one side of the leaded package and a second set of leads 211 shown on the opposite side of the two sides of the leaded package. In an alternative arrangement, a "leadless" package, such as a quad flat no-lead (QFN) package, can be used. Compared with a leaded package (such as the semiconductor device package 200) in which the leads extend from the molded compound package to reach the board or module, a leadless package can be surface-mounted to a circuit board using a smaller board area surface because the terminals are formed within the boundary of the molded compound package.

[0036] Figure 3 A circuit 300 that can be used with an example arrangement is shown in block diagram. Circuit 300 includes devices configured to be coupled to a power supply voltage VIN and ground GNDP in a first voltage scheme 351, and devices configured to be coupled to an output voltage VDD and ground or a negative voltage VEE in a second voltage scheme 355. A primary side driver 361 is coupled to the primary coil of a transformer 353, while a secondary side driver 363 is coupled to the secondary coil of the transformer 353. An isolation barrier 354 ( Figure 3 the dashed line in [the figure]) indicates that the input side (in the first voltage scheme 351) and the output side (in the second voltage scheme 355) of the circuit 300 are electrically isolated. The example circuit 300 forms a DC-DC converter. Applications of the DC-DC converter 300 include charging a battery in an automotive system, charging an electric vehicle, and serving as a power supply for various portable devices, including devices with batteries such as laptop computers, mobile phones, smart tablet computers, web browsing devices, games, video and audio equipment, meters, and many other devices that require electrical isolation between different levels of DC voltage.

[0037] In Figure 3 [the figure], the primary side driver 361 includes active devices Q1 to Q4, which can be, for example, power FET devices, a spread spectrum modulation (SSM) oscillator 377, a gate driver and a voltage level shifter 371, and a primary side controller 373. In operation, the active devices Q1 to Q4 are selectively turned on and off at a relatively high frequency to supply an alternating current (AC) to the primary side coil of the transformer 353. For example, an AC current can be generated from a DC power supply voltage at the input terminal VIN. A feedback receiver amplifier 375 provides an output voltage monitoring system so that the primary side controller 373 can use the oscillator 377 to control the active devices Q1 to Q4 using pulse width modulation or frequency modulation to increase or decrease the power to the transformer 353 and regulate the output, the DC voltage VDD.

[0038] The secondary - side driver 363 is a passive rectifier with diodes D1 to D4, which provides a DC output from the AC current flowing in the secondary coil of the transformer 353. The secondary - side regulator 381 controls the switch to regulate the output voltages VDD and VEE. The feedback inputs FBVEE, FBVDD are used to monitor the output voltages for regulation. The feedback emitter amplifier 382 is capacitively coupled across the isolation barrier 354 to the feedback receiver amplifier 375.

[0039] In an embodiment used in the example arrangement, the primary - side driver 361 is disposed in a first semiconductor die, the secondary - side driver 363 is disposed in a second semiconductor die, and the transformer 353 is arranged as a laminated transformer with an integral magnetic material. The three devices are then mounted to a package substrate, such as a lead frame with electrical isolation, and used to form a semiconductor device package together with the integrated laminated transformer.

[0040] In an additional alternative arrangement, a laminated transformer with an integral magnetic material can be mounted to the package substrate, and at least one semiconductor die can be mounted to the package substrate and electrically connected to the transformer. Then an integrated semiconductor device package with the laminated transformer is formed.

[0041] Figures 4A to 4E Selected steps for forming a laminated transformer with an integral magnetic material for various arrangements are shown in a series of cross - sectional views. The laminated transformer with an integral magnetic material forms a passive component, which can also be used as a transformer component in various applications.

[0042] In Figure 4AIn [the figure], the substrate 490 is shown in a cross-sectional view. The substrate 490 has a dielectric core 492, which can be a bismaleimide triazine (BT) core in one example. Alternative materials for the dielectric core 492 include Ajinomoto Build-up Film (ABF), which is a dielectric film for forming circuit boards and can be purchased from Ajinomoto Fine Techno Co., Inc. in Tokyo, Japan. The dielectric core 492 can also be formed of ceramic, semiconductor, or epoxy resin. Embedded Trace Substrate (ETS) materials can be used, including ABF or BT resin as the core 492, and prepreg (“prepreg”) isolation materials for other dielectric layers. The first conductor layer 491 is formed on the first surface of the core 492, while the second conductor layer 493 is formed on the second opposite surface. The conductor layers 491, 493 can be formed by plating or by film deposition. Copper conductor layers or copper alloy conductor layers can be used. A direct bond copper (DBC) substrate having copper deposited on opposite sides of a ceramic core can be used to form the core 492 and the conductor layers 491, 493. Ajinomoto Build-up Film (ABF) can be used to form a multi-layer package substrate, where copper conductor layers are on opposite sides of a core formed of ABF dielectric. Alternatively, ABF can be used to form a dielectric material above a coil, as described below, where a BT resin or other dielectric forms the core 492.

[0043] In Figure 4B [the figure], the substrate 490 is shown after the first conductor layer 491 and the second conductor layer 492 (see Figure 4A 491, 492 in Figure 4A ) have been patterned. The first conductor layer 491 (see Figure 4A ) is patterned to form the first coil (e.g., the primary side coil) 495 of a laminated transformer, and the second conductor layer 492 ( Figure 4A ) is patterned to form the second coil 496 (e.g., the secondary side coil) of the laminated transformer. The coils 495 and 496 can be, for example, planar coils having a spiral pattern and can be aligned with each other to operate as a transformer. The coils 495, 496 are formed on opposite surfaces of the core 492, which is a dielectric material, and the coils are electrically isolated from each other by the dielectric core 492. Additional conductors, such as 497, 498, are patterned to provide electrical connections to the coils 495, 496. For example, vias, such as via 493, can be formed to provide a connection on one side of the core 492 for connection to the coils on the opposite side of the core 492.

[0044] Figure 4C Another cross-sectional view shows the component after magnetic material is deposited on the substrate 490. As Figure 4B shown in Figure 4CAs shown, a magnetic material layer 482 is deposited on the first coil 495, and a magnetic material layer 484 is deposited on the second coil 496. The core 492, conductors 497, 498, and the vias such as 493 are again as shown in Figure 4B as shown. The magnetic material layers 482 and 484 are of the same material.

[0045] In an example configuration, the magnetic material layers 482, 484 are magnetic pastes. For example, the magnetic paste that can be used in the arrangement can be purchased from Ajinomoto Fine-Techno Co., Inc. of Japan. The magnetic paste can be supplied as an ink with a solvent or as a liquid, and can be deposited by vacuum screen printing, screen printing, through a stencil, by inkjet printing, or by drop-on-demand deposition. The magnetic material used in the example arrangement is compatible with laminated films and prepreg processes such as ABF.

[0046] Figure 4D Another cross-sectional view shows the Figure 4C components after additional processing. In Figure 4D shown, dielectric layers 486, 488 are shown as being formed over the surface of the core 492 and covering the magnetic material 482 over the first coil 495 and the magnetic material 484 over the second coil 496. In one example process, the Ajinomoto Build-up Film (ABF) available from Ajinomoto Fine-Techno Co., Inc. of Japan can be used. The ABF film can be applied by positioning the film over the substrate 490, applying heat to soften the film, and applying a vacuum that conforms the softened film to the structure below the film. The ABF can then be cured to form a solid layer, and the solid ABF can be processed by grinding to planarize the outer surface, and plating can be performed thereon. The ABF can be applied in multiple layers by repeating the process. Conductor seed layer deposition, lithography, plating, and patterning can be used to form conductor layers between or over the layers of the ABF film. Through-holes can be formed through the dielectric layers formed by the ABF film. In an alternative process, a prepreg material can be used to form the layers 486, 488 over the substrate 490. In a prepreg laminate, a glass-reinforced woven fabric is coated with a resin to form a prepreg (“prepreg”) film, which can be applied over the substrate and then cured to form a dielectric layer. Copper foil can be applied to the prepreg dielectric to form conductor layers, which can be patterned to form traces.

[0047] Figure 4E Another cross-sectional view shows the Figure 4D components after additional process steps to form a laminated transformer 453 with an integral magnetic material that can be used with the example arrangement. In Figure 4EIn [the figure], transformer 453 includes a first coil 495 and a second coil 496 on opposite sides of the dielectric core 492 of substrate 490. Magnetic material layers 482, 484 are shown deposited on and in contact with the first coil 495 and the second coil 496 respectively. Dielectric layers 486 and 488 cover the magnetic materials. Conductive traces 487, 488 form connection points of the coils 495, 496 and may include conductive vias extending vertically through the dielectric layers 486, 488. In an example arrangement, an ABF process is used to form the dielectric layers 486, 488. Metal plating and patterning can be used, including depositing a seed layer, patterning the seed layer, and plating metal to form the conductors 487, 488. Transformer 453 can be one of many units formed simultaneously on substrate 490, which can be divided into unit transformers arranged in rows and columns and spaced apart from each other by saw streets. Because the magnetic material is integral with the laminated transformer, this arrangement provides a relatively thin transformer (compared to mounting a magnetic sheet or film on the outer surface of a laminated transformer). In an example, a laminated transformer including an integral magnetic material has a thickness of 380 to 420 microns, enabling a relatively thin semiconductor device package incorporating the laminated transformer.

[0048] A laminated transformer such as 453 can be formed at a different time and location from the semiconductor die used in a semiconductor device package. For example, transformer 453 can be formed by a substrate manufacturer and delivered for use in a panel or array that can be singulated at the package site. Alternatively, a transformer such as 453 can be provided as a component in individual units ready for substrate mounting.

[0049] Although transformer 453 is shown mounted within a semiconductor device package in the example arrangement described herein, transformer 453 is a passive component and can be externally mounted on or attached to the semiconductor device package, can be used in a stacked package arrangement, or can be mounted on a circuit board or module to provide a transformer component.

[0050] Figures 5A to 5H Selected steps for forming a semiconductor device package with an integrated laminated transformer in an example arrangement are shown in a series of plan views and end views.

[0051] Figures 5A to 5B Example cutting steps are shown for singulating unit transformers (e.g., see the transformer 453 in Figure 4E ) from a substrate panel having multiple unit transformers such as 453, and the unit transformers are formed using steps such as those shown in Figures 4A to 4E and described above. In Figure 5A , a cutting frame 502 is shown on which a substrate 590 is mounted (e.g., similar to Figure 4EThe substrate 490). The substrate 590 has unit transformers 453 formed in rows and columns, and each unit transformer 453 is a laminated transformer including an integral magnetic material above the coil (for example, see Figure 4E the magnetic material layers 482, 484 above the first coil 495 and the second coil 496 in

[0052] In Figure 5B it shows Figure 5A the components, and at the same time shows a sawing operation to cut a single unit transformer 453 from the substrate 590. In Figure 5B the substrate 590 is cut into individual units 453 by a mechanical saw 511, the mechanical saw cuts through the substrate 590 and traverses the substrate 590 along the sawing lanes between the units. The cutting frame 502 holds and supports the individual unit transformers 453 after the sawing operation, so that a pick-and-place tool can take out the unit transformers 453 from the cutting frame 502 for further processing.

[0053] Figures 5A to 5B The singulation step shown in Figures 5C to 5H can be performed asynchronously with respect to the encapsulation step shown in

[0054] Figures 5C to 5H Selected steps for forming an example arrangement of a semiconductor device package including a transformer with an integral magnetic material are shown in a series of side views and plan views.

[0055] In Figure 5C it shows the encapsulation substrate in a plan view observed from the board side. In this example, it has a lead frame 521 with electrically isolated parts. The line 530 indicates that only a part of the lead frame 521 is shown, where the leads 510, 511 are shown as extending to the line 530, and these parts of the leads 510, 511 will be covered by the molding compound described below, and the remaining parts of the leads 510, 511 are not shown in Figures 5C to 5F but see Figures 5F to 5G510 and 511 in). Leads 510 and 511 are configured to couple to an isolated voltage scheme such that these conductive leads are not electrically coupled. During an example process, lead frame 521 can be a unit device that is part of an array or strip of lead frames, where many unit devices are spaced apart from each other and temporarily connected together with connecting bars (not shown). By simultaneously processing multiple units during a packaging process, throughput is increased and costs are reduced. Once the semiconductor device packaging is complete, the lead frame strip or lead frame array is cut into unit semiconductor device packages by cutting through the saw streets between the completed devices.

[0056] Semiconductor dies 505 and 506 are shown mounted to die pads 533 and 531 on package substrate 521, respectively. Semiconductor dies 505, 506 can be mounted using a die attach material (e.g., a conductive die attach film (CDAF) or a conductive die attach paste) (note that the die attach material is not visible in Figure 5C because it is under semiconductor dies 505, 506). For example, semiconductor dies 505, 506 can be similar to Figures 1A to 1B the semiconductor die 105 in. Semiconductor die 505 can implement a primary side driving device similar to Figure 3 the primary side driver 361 in. Semiconductor die 506 implements a second side driving device similar to Figure 3 the secondary side driver 363 in. After using die attach to mount semiconductor dies 505, 506, the die attach can be cured in a thermal process using, for example, an oven. Since lead frame 521 has two isolated die pads 533, 531 for mounting semiconductor dies 505, 506, the two die pads 533, 531 can be coupled to an isolated ground or other potential to provide a potential coupled to the back side of semiconductor dies 505, 506. Mounting pads 535 are also shown, which are configured to receive a laminated transformer such as transformer 453 (not shown, see Figure 4E ).

[0057] Figure 5D The elements of Figure 5C after an additional process step are shown in an end view. In Figure 5D , lead frame 521 is shown from an end view, where line 530 indicates that it is a partial view of the lead frame. Transformer 453 is shown as having a dielectric material (e.g., see Figure 4EThe core 492), spaced coils 495, 496, and magnetic materials 482, 484 above the coils 495, 496 in the transformer 453. The transformer 453 is mounted to the mounting pad 535 using a non-conductive die attach film (NCDAF) or non-conductive die attach paste 537. After mounting the transformer 453, die attach curing is performed, for example, in an oven. The lead 511 extends to one side of the lead frame 521, while the lead 510 extends to the other side of the lead frame 521 and is electrically isolated from the lead 510 and the mounting pad 535. One or more of the leads 511 may be coupled to the mounting pad 535. However, by using the non-conductive die attach film 537, the transformer 453 is electrically isolated from the mounting pad 535.

[0058] Figure 5E Shown from the board side in another plan view after additional processing Figure 5D of the components. In Figure 5E the first set of wire bonds 519 is shown electrically coupling the semiconductor die 505 to the lead 511 and electrically coupling to the transformer 453. Additional wire bonds 519 are shown coupling the semiconductor die 506 to the lead 510 and coupling to the transformer 453. The dashed line 530 indicates that the lead frame 521 is shown in a partial view, and the leads 510, 511 are shown ending at the line 530 but extending beyond the line 530 as described below. The semiconductor dies 505, 506 and the leads 510, 511 are electrically isolated from each other. The transformer 453 and the lead frame provide an isolation barrier.

[0059] To transition from the components as shown in Figure 5D to the wire bond components as shown in Figure 5E several processes are performed. After the transformer 453 is mounted to the mounting pads as shown in Figure 5D a cleaning step is performed to prepare the components for the wire bonding process. In an example, plasma cleaning is performed to remove debris, excess die attach, and unwanted particles from the device. A wire bonder tool is then used to form the wire bonds 519 between the semiconductor dies 505, 506 and the transformer 453 and between the semiconductor dies 505, 506 and the leads 510, 511.

[0060] In an example of using a thermo - ultrasonic wire bonding tool, the bonding wire extends a short distance through an opening in a capillary. The capillary can be, for example, ceramic. A bonding wire feeder, such as an automatic spool, can supply the bonding wire fed into the capillary. A flame or arc is applied to the exposed end of the bonding wire. This melts the end of the bonding wire and forms a ball at the end of the bonding wire, which is called an "airless ball". The molten ball is placed in contact with a bonding pad on a semiconductor device. The capillary vibrates by the application of acoustic energy to the capillary, while the molten ball is simultaneously mechanically pressed against the bonding pad. A thermal process is used by a heating device during wire bonding. Thus, a combination of thermal energy, mechanical pressure, and acoustic energy is used to form a "ball bond" between the molten ball and the bonding pad. Then, the capillary moves away from the ball bond, allowing the bonding wire to extend through the capillary opening as the capillary moves. By using a clamp that can grasp the bonding wire and then release it, and by the movement of the capillary relative to the device, the bonding wire can be shaped and formed into an arc shape extending from the ball bond above the device. The capillary moves the bonding wire to a conductive pad on a transformer or to the conductive part of a lead for another connection of the wire bonding. A "stitch bond" is formed by pressing the bonding wire against the conductive pad or against the lead and applying mechanical pressure, acoustic energy, and again applying thermal energy. The capillary then moves a short distance from the stitch bond, and the bonding wire is broken or cut to form a new exposed end extending from the capillary. This bonding cycle is automatic and can be repeated several times per second to quickly form the required wire - bonding connections between two semiconductor die, leads, and transformers.

[0061] In an effective example, the bonding wire 519 can be copper, copper alloy, palladium - coated copper (PCC), gold, silver, and aluminum. When using a copper bonding wire or PCC, the wire bonding tool can have an oxygen - deficient atmosphere, which helps prevent the oxidation and corrosion of the copper bonding wire (which can be accelerated at the high temperatures used in wire bonding).

[0062] An alternative to wire bonding includes tape bonding to form electrical connections between a semiconductor die and a lead and between a semiconductor die and a transformer. In tape bonding, a conductive tape is placed on the bonding pads and conductive leads and bonded to them to form an electrical connection.

[0063] Figure 5F Shown in end view after additional processing Figure 5E of the component. For ease of illustration, Figure 5F the board side of the lead frame 521 is shown facing up. In Figure 5F , the molding compound 523 is shown as being formed above the lead frame 521 and covering the transformer 453 and portions of the leads 510 and 511. The molding compound also covers the semiconductor die 505, 506 that are not visible in the Figure 5F view (see Figure 5E505 and 506 in). It should be noted that in Figure 5F for simplicity of illustration, the wire bond 519 is not shown (for example, see Figure 5E the wire bond 519 in).

[0064] The molding compound 523 can be formed in a transfer molding process using a thermosetting epoxy molding compound, which is sometimes referred to as "EMC" or "electronic molding compound". During the example process, the lead frame 521 and other components attached thereto, including the semiconductor dies 505, 506, bond wires 419, and transformer 453, are placed in the recesses of the transfer molding tool. During the example process, the molding compound can be provided in a solid state as a powder or as a disk of solid material (solid at room temperature). The molding compound is placed in the molding tool and heated to a liquid, and using hydraulic pressure, the liquid molding compound is forced through the runner into the cavity of the mold recess and surrounds the lead frame 521 and other components, while the outer portions of the leads 510, 511 ( Figure 5F not shown in, see below Figure 5G ) are positioned so as to remain uncovered by the molding compound. The molding compound is then cured to form a solid encapsulation body.

[0065] Figure 5G Shown in the other end view are the components after additional process steps for forming the semiconductor device package 500 of the example arrangement. It should be noted that in Figure 5F the lead frame 521, for example, is rotated relative to Figure 5G . In Figure 5F . In Figure 5G the lead frame 521 is now shown with the board side facing down, oriented such that the semiconductor device package 500 will be mounted to a board or module. Since the lead frame 521 is shaped to rise away from the board side surface when traversing from the ends of the leads 510 or 511 to the interior of the package, it can be referred to as an "upset" type lead frame. In an alternative arrangement, the device can be mounted on the top surface of a "downset" lead frame, which is shaped to fall towards the board side surface when traversing from the ends of the leads to the interior of the package. The transformer 453 is shown facing the board side of the semiconductor device package 500 and is mounted to the mounting pad 535 through the non-conductive die attach film 537. It should be noted that the semiconductor devices 505, 506 are not visible in the Figure 5G end view (see Figure 5H where the semiconductor devices 505 and 506 are shown in a projection view). The leads 510, 511 have portions outside the encapsulation body formed by the molding compound 523, and the example semiconductor device package 500 is a leaded device package. In an alternative arrangement, a "leadless" package, such as a quad flat no-lead (QFN) package, can be used. InFigure 5G In the example shown in, the leads 510, 511 have been shaped in a "trim forming" tool to have ends that are arranged for surface mount technology (SMT) mounting to a board using solder. For example, the ends of the leads 510, 511 are mounted to conductive traces on a circuit board. The transformer 453 includes coils 495, 496 covered by magnetic materials 482, 484, and the magnetic materials 482 and 484 are covered by a laminated dielectric material such that the transformer 453 is a laminated transformer with an integral magnetic material. By using the arrangement, the magnetic materials 482, 484 are advantageously in contact with the coils 495, 496, which improves performance compared to existing methods where a magnetic film or sheet is applied over the laminated transformer but is spaced apart from the coils, and the magnetic materials in those prior methods are spaced apart from the coils and from each other by the laminated dielectric and by the die attach layer, thereby degrading the performance of the transformer. As Figure 5G shown in, the semiconductor device package has a thickness labeled "T2". In the example, the thickness T2 can be in the range between 2.3 millimeters and 3.2 millimeters and includes the laminated transformer and the lead frame. Since the laminated transformer with an integral magnetic material has a relatively low thickness (see Figure 4E , the thickness "T1", which can be in the range between 380 microns and 420 microns), using the arrangement advantageously enables a relatively thin semiconductor device package.

[0066] Using a laminated transformer with an integral magnetic material advantageously substantially reduces the steps required to assemble the semiconductor device package 500 and reduces the cost of assembly compared to existing methods, while also improving the device performance compared to existing methods. The thickness of the semiconductor device package 500 can be reduced because the magnetic material is integral with the laminated transformer 453 rather than being applied over the laminated transformer assembly. During package assembly, the number of die attach and curing steps required to assemble the semiconductor device package using the arrangement is reduced (when compared to existing methods of applying a magnetic film or strip to the laminated transformer), thereby reducing costs.

[0067] Figure 5H The semiconductor device package 500 is shown in a projection view as viewed from the board side Figure 5G and is shown with a molded compound 523 shown as transparent, so that the internal components are visible.

[0068] The molding compound 523 forms a package body for the semiconductor device package 500 and covers the semiconductor die 505, semiconductor die 506, transformer 453, die pads 531 and 533, wire bonds 519, and mounting pad 537. The lead 511 is configured to couple to one voltage scheme, and the lead 510 is electrically isolated from the lead 511 and is configured to couple to a second voltage scheme. The die pad 533 on which the semiconductor die 505 is mounted is in electrical contact with one of the semiconductor die 505 and the lead 511 and can be coupled to a ground potential. The die pad 531 on which the semiconductor die 506 is mounted is in contact with one of the semiconductor die 506 and the lead 510 and can be coupled to another ground potential different from the ground potential coupled to the semiconductor die 505. The transformer 453 is mounted to the mounting pad 537 with a non-conductive die attach film (not visible) and is electrically isolated from the leads. The transformer 453 provides a first coil that can be electrically coupled to the semiconductor die 506 and a second coil that can be electrically isolated from the first coil and coupled to the semiconductor die 505. In one example application, a current can be applied to the first coil, and by inducing a current corresponding to the current applied to the first coil in the second coil, energy can be transferred across the isolation barrier formed by the transformer and delivered to the second semiconductor die. The semiconductor device package 500 can be used to package a device to implement a DC-DC converter function, such as Figure 3 the circuit 300 in. Other circuits using transformers can be formed using the arranged transformers and can be packaged in semiconductor device packages. For example, AC-DC converters, battery chargers, and power supplies can be implemented using the arranged transformers. When compared to existing methods that do not use the arrangement, the laminated transformer with an integral magnetic material provides a low-cost assembly for semiconductor device packages with an integral transformer.

[0069] Although the laminated transformer with an integral magnetic material 453 can be used in semiconductor device packages, as Figures 5C to 5H shown in, in additional alternative arrangements, the laminated transformer can be used as a component mounted to a semiconductor device package, as part of a stacked package assembly, or mounted to a module or circuit board to provide a transformer component.

[0070] Figure 6 Selected steps for forming an arranged semiconductor device package are illustrated in a flowchart.

[0071] In Figure 6 , at step 601, the method begins by forming a package substrate having a board side surface and an opposing top surface, the package substrate having a first set of conductive leads, a second set of conductive leads electrically isolated from the first set of conductive leads, at least one die pad for mounting a semiconductor die, and a mounting pad spaced apart from the at least one die pad for mounting a transformer (see Figure 5CThe lead frame 521 therein, for example, has die pads 531, mounting pads 535, a first set of conductive leads 510, and a second set of conductive leads 511.)

[0072] At step 603, the method continues by mounting a semiconductor die on at least one die pad using a first die attach material (see, for example, Figure 5C , where the semiconductor die 505 is mounted on the die pad 533. Note that the die attach material is not visible as it is beneath the semiconductor die).

[0073] At step 605, a laminated transformer having an integral magnetic material is mounted on the mounting pad using a second die attach material. (See, for example, the laminated transformer 453 mounted to the mounting pad 535 by the die attach material 537 in Figure 5D .) In an example arrangement, the second die attach material is a non-conductive die attach film. In an alternative arrangement, a non-conductive die attach epoxy or paste may be used. Depending on the type of die attach material selected, thermal curing or other curing is performed.

[0074] At step 607, a wire bond or a tape bond electrical connection is formed between the leads on the package substrate and the bond pads of at least one semiconductor die. (See, for example, the wire bond 519 formed between the semiconductor die 505 and the lead 511 of the package substrate 521 in Figure 5E .)

[0075] At step 609, a wire bond or a tape bond electrical connection is formed between the laminated transformer and at least one semiconductor die. (See, for example, the wire bond 519 between the semiconductor die 505 and the laminated transformer 453 in Figure 5E .) In an example arrangement, the semiconductor die 505 is coupled to one of the coils in the laminated transformer (e.g., see the circuit 300 in Figure 3 , where the transformer 353 has two coils and one coil is coupled to the primary side driver 361). It should be noted that the wire bond steps 607, 609 can be performed in any order or can be performed in parallel.

[0076] At step 611, the method is completed by covering the electrical connections, the semiconductor die, the laminated transformer having an integral magnetic material, and a portion of the package substrate with a molding compound. (See, for example, Figure 5F , which shows the molding compound 523, and see Figure 5H , where the leads 510 and 511 of the lead frame are shown to be partially covered by the molding compound 523.) Although Figure 6The method shows mounting at least one semiconductor die and a transformer to a package substrate, but the example shown demonstrates mounting two semiconductor dies and a transformer to the package substrate to increase integration and provide a complete circuit within the semiconductor device package. Additional alternative arrangements may be formed, for example, a third semiconductor die or additional passive components, including a second laminated transformer, capacitor, resistor, diode sensor, or inductor, may be mounted to the package substrate.

[0077] Figure 7 A series of selected steps are shown in a flowchart, a method for manufacturing a laminated transformer with an integral magnetic material for use in an arrangement as described above. The method begins at step 701 by forming a first conductor layer on a first surface of a dielectric core and a second conductor layer on a second surface of the dielectric core opposite the first surface. (See, for example, Figure 4A core 492 and first conductor layer 491 and second conductor layer 493 in

[0078] At step 703, the method continues by patterning the first conductor layer to form a first coil on the first surface and patterning the second conductor layer to form a second coil on the second surface. (See, for example, Figure 4B first coil 495 and second coil 496 on opposite sides of core 492 in

[0079] At step 705, the method continues by depositing magnetic material on the first surface in contact with the first coil and depositing magnetic material on the second surface in contact with the second coil. (See, for example, Figure 4C magnetic material 482 on first coil 495 on conductor 492 and magnetic material 484 on second coil 496 on conductor 492 in

[0080] At step 707, a laminated layer of dielectric material is formed over the first surface and the second surface, the laminated layer of dielectric material covering the first coil and the magnetic material above the first coil, and covering the second coil and the magnetic material above the second coil. (See, for example, Figure 4D laminated layer 486 and laminated layer 488 in Figure 4E ). The laminated layer may be formed by using ABF or prepreg layers, and conductors may be formed in the layer or above the outer surface to bring traces into contact with coils 495, 496 (see

[0081] A laminated transformer with an integral magnetic material (see Figure 4E laminated transformer 453 in Figures 5C to 5HAs shown. In additional alternative arrangements, the laminated transformer can be used as a component mounted to or on a semiconductor device package, as part of a stacked package assembly, or mounted on a module or board to provide a transformer.

[0082] While the illustrated examples shown in the figures and described herein show a laminated transformer with an integral magnetic material mounted in a leaded semiconductor device package, in additional alternative arrangements, a laminated transformer with an integral magnetic material and one or more semiconductor die can be mounted in a leadless semiconductor device package such as a QFN. Dual in-line packages (DIP), small outline IC packages (SOIC), and wide SOIC packages can be used to form additional arrangements.

[0083] Within the scope of the claims, modifications can be made to the described arrangements, and other alternative arrangements are possible.

Claims

1. A method for forming a semiconductor device package, comprising: forming a package substrate having a board side surface and an opposite top surface, the package substrate having a first set of conductive leads, a second set of conductive leads electrically isolated from the first set of conductive leads, at least one die pad for mounting a semiconductor die, and a mounting pad spaced apart from the at least one die pad; mounting a semiconductor die on the at least one die pad using a first die attach material; mounting a laminated transformer having an integral magnetic material on the mounting pad using a second die attach material; forming a first electrical connection of a wire bond or a tape bond between a bonding pad of the semiconductor die and the first set of conductive leads on the package substrate; forming a second electrical connection of a wire bond or a tape bond between the bond pad of the semiconductor die and the laminated transformer having integral magnetic material; and The first and second electrical connections, the semiconductor die, the laminated transformer with integral magnetic material, and portions of the package substrate are covered with a molding compound.

2. The method of claim 1 , wherein mounting a semiconductor die on the at least one die pad further comprises: mounting the semiconductor die as a first semiconductor die on the at least one die pad; and mounting a second semiconductor die on a second die pad electrically isolated from the at least one die pad.

3. The method of claim 2, wherein forming a first electrical connection of a wire bond or a tape bond between the bonding pad of the semiconductor die and the first set of conductive leads on the package substrate comprises forming the first electrical connection between the bonding pad of the first semiconductor die and the first set of leads, and the method further comprises: A third electrical connection of a wire bond or a tape bond is formed between a bond pad of the second semiconductor die and the second set of leads on the package substrate.

4. The method of claim 3 , wherein forming a second electrical connection of a wire bond or a tape bond between the bonding pad of the semiconductor die and the laminated transformer with integral magnetic material comprises forming the second electrical connection between the bonding pad of the first semiconductor die and the laminated transformer with integral magnetic material, and further comprises forming a fourth electrical connection between the bonding pad of the second semiconductor die and the laminated transformer with integral magnetic material.

5. The method of claim 4, wherein mounting a laminated transformer having an integral magnetic material on the mounting pad using a second die attach material further comprises mounting a laminated transformer comprising: A first coil located on a first surface of a core of dielectric material and a second coil located on a second surface of the core opposite to the first coil, a magnetic material deposited on the first coil on the first surface of the core and on the second coil on the second surface of the core, and a laminated layer of dielectric material formed above the magnetic material and the first coil on the first surface of the core and above the magnetic material and the second coil on the second surface of the core.

6. The method according to claim 5, wherein the laminated layer of dielectric material is Ajinomoto built-up film ABF or a prepreg material.

7. The method according to claim 5, wherein the core of the dielectric material is bismaleimide triazine BT resin, Ajinomoto build-up film ABF or prepreg material.

8. The method of claim 5, wherein forming a second electrical connection using a wire bond or a tape bond between the bonding pad of the semiconductor die and the laminated transformer having an integral magnetic material comprises forming the second electrical connection between the bonding pad of the first semiconductor die and the first coil, and further comprises forming the fourth electrical connection between the bonding pad of the second semiconductor die and the second coil of the laminated transformer having an integral magnetic material.

9. The method of claim 1 , wherein the packaging substrate is a lead frame having the first group of conductive leads and the second group of conductive leads, and wherein covering the electrical connections, the semiconductor die, the laminated transformer having integral magnetic material, and a portion of the packaging substrate with a molding compound further comprises covering a portion of the first group of conductive leads and a portion of the second group of conductive leads with a molding compound while another portion of the first group of conductive leads and another portion of the second group of conductive leads remain exposed from the molding compound, thereby forming terminals for a leaded semiconductor device package. 10 . The method of claim 1 , wherein the first die attach material is a conductive die attach material and the second die attach material is a non-conductive die attach material. 11 . The method according to claim 10 , wherein the conductive die attach material is a conductive die attach film, and the non-conductive die attach material is a non-conductive die attach film.

12. A method for forming a transformer, comprising: forming a first conductor layer on a first surface of a dielectric core, and forming a second conductor layer on a second surface of the dielectric core opposite to the first surface; patterning the first conductor layer to form a first coil on the first surface, and patterning the second conductor layer to form a second coil on the second surface; depositing a magnetic material on the first surface in contact with the first coil, and depositing the magnetic material on the second surface in contact with the second coil; and A laminate layer of dielectric material is formed over the first surface and the second surface, the laminate layer of dielectric material covering the first coil and the magnetic material over the first coil, and covering the second coil and the magnetic material over the second coil.

13. The method of claim 12, wherein patterning the first conductor layer to form a first coil on the first surface and patterning the second conductor layer to form a second coil on the second surface further comprises patterning the first conductor to form the first coil as a planar coil and patterning the second conductor to form the second coil as a planar coil aligned with the first coil, and wherein the first coil, the second coil, and the dielectric core form a transformer.

14. The method of claim 12, wherein forming a laminate layer of dielectric material over the first surface and the second surface to cover the first coil and the magnetic material over the first coil and to cover the second coil and the magnetic material over the second coil further comprises forming a laminate layer of Ajinomoto build-up film (ABF) or forming a laminate layer of prepreg material.

15. The method of claim 14, further comprising forming a first conductor over the laminate layer, the first conductor coupled to the first coil on the first surface, and forming a second conductor over the laminate layer coupled to the second coil on the second surface.

16. The method of claim 12, wherein depositing a magnetic material further comprises depositing a magnetic paste or depositing a magnetic ink.

17. A semiconductor device package, comprising: a package substrate comprising mounting pads, at least one die pad, a first set of conductive leads, and a second set of conductive leads spaced apart from the first set of conductive leads; a semiconductor die mounted to the at least one die pad using a first die attach material; a laminated transformer having an integral magnetic material mounted on the mounting pad using a second die attach material; a first electrical connection of a wire bond or a tape bond between a bond pad of the semiconductor die and the first set of conductive leads on the package substrate; a second electrical connection of a wire bond or a tape bond between the bond pad of the semiconductor die and the laminated transformer having integral magnetic material; and A molding compound covers the electrical connections, the semiconductor die, the laminated transformer with integral magnetic material, and portions of the package substrate.

18. The semiconductor device package of claim 17, wherein the magnetic material is a magnetic paste or a magnetic ink deposited in contact with the first coil and the second coil.

19. A semiconductor device package according to claim 17, wherein the at least one die pad of the package substrate is a first die pad, and the semiconductor die mounted on the at least one die pad is a first semiconductor die, and the semiconductor device package further includes a second die pad located on a lead frame and electrically isolated from the first die pad, and further includes a second semiconductor die mounted to the second die pad through the first die bonding material.

20. The semiconductor device package of claim 19, wherein the first semiconductor die, the second semiconductor die, and the stacked transformer are coupled to implement a DC-DC converter function.

21. A transformer, comprising: a first coil formed in a first conductor layer on a first surface of a dielectric core, and a second coil formed in a second conductor layer on a second surface of the dielectric core opposite to the first surface; a magnetic material located on the first surface in contact with the first coil, and the magnetic material located on the second surface in contact with the second coil; and A laminate layer of dielectric material is located over the first surface and the second surface, the laminate layer of dielectric material covers the first coil and the magnetic material over the first coil, and covers the second coil and the magnetic material over the second coil.

22. The transformer of claim 21, wherein the magnetic material comprises a magnetic material formed of a magnetic paste deposited over the first surface and the second surface.

23. The transformer of claim 21, wherein the magnetic material comprises a magnetic material formed of magnetic ink deposited over the first surface and the second surface.

24. The transformer of claim 21, wherein the laminate layer is Ajinomoto built-up film ABF or a prepreg material.

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