Semiconductor packaging structure

Abstract

A semiconductor package structure includes a package substrate. The package substrate includes a first core structure, a plurality of first dielectric layers, a plurality of first metal layers, a plurality of second dielectric layers, and a plurality of second metal layers. The first core structure has a first surface and a second surface opposite the first surface. The first dielectric layers and the first metal layers are alternately stacked on the first surface of the first core structure. The second dielectric layers and the second metal layers are alternately stacked on the second surface of the first core structure. The number of the second dielectric layers is less than the number of the first dielectric layers.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and more particularly to a semiconductor package structure including a package substrate. Background Art

[0002] In addition to providing protection for semiconductor chips from environmental contaminants, semiconductor package structures can also provide electrical connections between the semiconductor chips encapsulated therein and a substrate (such as a printed circuit board (PCB)).

[0003] Although existing semiconductor package structures generally meet requirements, they are not entirely satisfactory in all aspects. For example, due to the demand for high electrical signal performance, an increasing number of metal layers are required in the package substrate. However, as the size of the semiconductor package structure increases and the number of stacked layers in the package substrate increases, the mismatch in the coefficient of thermal expansion (CTE) between the package substrate and the chip module can cause severe warping, which results in low yield problems in surface mount technology (SMT). Therefore, there is a need to further improve semiconductor package structures. Summary of the Invention

[0004] The present invention provides a semiconductor package structure. An exemplary embodiment of a semiconductor package structure includes a package substrate. The package substrate includes a first core structure, a plurality of first dielectric layers, a plurality of first metal layers, a plurality of second dielectric layers, and a plurality of second metal layers. The first core structure has a first surface and a second surface opposite to the first surface. The first dielectric layers and the first metal layers are alternately stacked on the first surface of the first core structure. The second dielectric layers and the second metal layers are alternately stacked on the second surface of the first core structure. The number of the second dielectric layers is less than the number of the first dielectric layers.

[0005] Another embodiment of a semiconductor package structure includes a package substrate. The package substrate includes a core structure, a plurality of first dielectric layers, a plurality of first metal layers, a plurality of second dielectric layers, and a plurality of second metal layers. The first dielectric layers and the first metal layers are alternately stacked under the core structure. The second dielectric layers and the second metal layers are alternately stacked above the core structure. The thickness of each second metal layer is different from the thickness of each first metal layer. Brief Description of the Drawings

[0006] The present invention can be more fully understood by reading the following detailed description and referring to the examples in the accompanying drawings, in which:

[0007] Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9, Figure 10 , Figure 11 , Figure 12 are cross-sectional views of an exemplary encapsulation substrate in accordance with some embodiments of the present disclosure;

[0008] Figure 13 , Figure 14 , Figure 15 , Figure 16 are cross-sectional views of an exemplary semiconductor encapsulation structure including an encapsulation substrate in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0009] The following description is made for the purpose of illustrating the general principles of the present invention and should not be construed in a limiting sense. The scope of the present invention is best determined by reference to the appended claims.

[0010] The present disclosure will be described with reference to specific embodiments and certain drawings, but the present disclosure is not limited thereto and is only defined by the claims. The drawings are only illustrative and not restrictive. In the drawings, for illustrative purposes, the sizes of some elements may be exaggerated and are not drawn to scale. The dimensions and relative dimensions do not correspond to the actual dimensions in the practice of the present disclosure.

[0011] Based on the embodiments described below, additional elements may be added. For example, the description "the first element is on / covers the second element" may include embodiments where the first element is in direct contact with the second element, and may also include embodiments where additional elements are provided between the first element and the second element such that the first element and the second element are not in direct contact.

[0012] The spatial relative descriptors of the first element and the second element may change depending on the operation or use of the structure in different directions. In addition, the present disclosure may repeat reference numerals and / or letters in various embodiments. This repetition is for simplicity and clarity and does not itself prescribe the relationship between the various embodiments discussed.

[0013] A semiconductor encapsulation structure is described in accordance with some embodiments of the present disclosure, including an encapsulation substrate. The encapsulation substrate includes different numbers of layers and / or different thicknesses of layers on opposite sides. Thus, the warpage problem can be alleviated without reducing the number of metal layers. In addition, the thickness of the core structure in the encapsulation substrate can be reduced to avoid affecting the electrical signal performance.

[0014] Figure 1 is a cross-sectional view of an encapsulation substrate 100 in accordance with some embodiments of the present disclosure. Additional features may be added to the encapsulation substrate 100. Some of the features described below may be replaced or omitted to accommodate different embodiments. For simplicity of the drawing, only a part of the encapsulation substrate 100 is shown.

[0015] AsFigure 1 As shown, according to some embodiments, a core structure 102 is provided. The core structure 102 may be formed of an organic material, a glass material, a ceramic material, a semiconductor material, a combination of the above materials, etc. The organic material may include glass fiber resin (e.g., FR4), bismaleimide triazine (BT) resin, a combination of the above materials, etc. The semiconductor material may include silicon, germanium, or a composite material including silicon germanium, silicon carbide, gallium arsenide, silicon germanium carbide, a combination of the above materials, etc. One or more vias (not shown) may be formed in the core structure 102.

[0016] According to some embodiments, a plurality of dielectric layers 106 and a plurality of metal layers 104 are alternately stacked below the core structure 102, and a plurality of dielectric layers 110 and a plurality of metal layers 108 are alternately stacked above the core structure 102.

[0017] The dielectric layers 106 and 110 may be formed of a dielectric material, including Ajinomoto build-up film (ABF) or other suitable materials. The dielectric layers 106 and 110 may be formed by a lamination process, a coating process, or other suitable processes. The metal layers 104 and 108 may be formed of copper, nickel, aluminum, tungsten, an alloy of the above materials, or a combination thereof. The metal layers 104 and 108 may be formed by an electroplating process, an electroless process, or other suitable processes.

[0018] As Figure 1 shown, the number of metal layers 108 may be different from the number of metal layers 104, and the number of dielectric layers 110 may be different from the number of dielectric layers 106. Therefore, the package substrate 100 may be an unbalanced layer count substrate to alleviate the warping problem. In addition, the thickness of the core structure 102 may be reduced. For example, the thickness of the core structure 102 may be in the range of about 200 μm to about 1400 μm, such as about 1240 μm.

[0019] The number of metal layers 108 may be greater than the number of metal layers 104, and the number of dielectric layers 110 may be greater than the number of dielectric layers 106. It should be noted that the number of metal layers 104 and 108 and dielectric layers 106 and 110 is for illustrative purposes only and may be more or less than Figure 1 that shown. In some embodiments, the ratio of the number of metal layers 108 to the number of metal layers 104 is in the range of 10 to 0.1, such as 2. In some embodiments, the ratio of the number of dielectric layers 110 to the number of dielectric layers 106 is in the range of 10 to 0.1, such as 2. If the ratio is greater than 10, the initial warping of the package substrate 100 may be too large and may cause cold joint problems.

[0020] According to some embodiments, a protective layer 112 is disposed above the metal layer 108 and below the metal layer 104 to protect the surfaces of the metal layers 104 and 108. The protective layer 112 may include a solder barrier layer. The protective layer 112 may be formed of a resin material (such as a thermosetting resin, a photosensitive resin, etc.), an ink material, a tape material (such as a polyimide tape, a kapton tape, etc.), a combination of the above materials, etc. The protective layer 112 may be formed by printing, coating, or other suitable methods.

[0021] Figure 2 is a cross-sectional view of a packaging substrate 200 according to some embodiments of the present disclosure. It should be noted that the packaging substrate 200 may include components that are the same as or similar to those of the Figure 1 packaging substrate 100 shown in, and for simplicity, these components will not be discussed in detail.

[0022] As Figure 2 shown, the number of metal layers 104 may be greater than the number of metal layers 108, and the number of dielectric layers 106 may be greater than the number of dielectric layers 110. Therefore, the packaging substrate 200 may be an unbalanced layer count substrate, and warping can be alleviated. By adjusting the number of layers on different sides, for example, as arranged in the Figure 1 packaging substrate 100 or Figure 2 packaging substrate 200, the warping behavior of the packaging substrate can be controlled.

[0023] In certain embodiments, the ratio of the number of metal layers 104 to the number of metal layers 108 is in the range of 10 to 0.1, for example, 2. In certain embodiments, the ratio of the number of dielectric layers 106 to the number of dielectric layers 110 is in the range of 10 to 0.1, for example, 2. If the ratio is greater than 10, the initial warping of the packaging substrate 200 may be too large and may cause cold joint problems.

[0024] Figure 3 is a cross-sectional view of a packaging substrate 300 according to certain embodiments of the present disclosure. It should be noted that the packaging substrate 300 may include components that are the same as or similar to those of the Figure 1 packaging substrate 100 shown in, and for simplicity, these components will not be discussed in detail. In the following embodiments, the thicknesses of the metal layer and / or the dielectric layer are different on opposite sides of the core structure.

[0025] As Figure 3As shown, a plurality of dielectric layers 304 and a plurality of metal layers 302 may be alternately stacked below the core structure 102, and a plurality of dielectric layers 308 and a plurality of metal layers 306 may be alternately stacked above the core structure 102. The thickness of each of the dielectric layers 304 may be different from the thickness of each of the dielectric layers 308. The thickness of each of the metal layers 302 may be different from the thickness of each of the metal layers 306. Therefore, the package substrate 300 may be an unbalanced layer thickness substrate, and warpage can be alleviated.

[0026] The thickness of each of the dielectric layers 304 may be greater than the thickness of each of the dielectric layers 308. For example, the ratio of the thickness of one of the dielectric layers 304 to the thickness of one of the dielectric layers 308 may be in the range of about 1.05 to about 1.30, such as about 1.20. The thickness of each of the metal layers 306 may be greater than the thickness of each of the metal layers 302. For example, the ratio of the thickness of one of the metal layers 306 to the thickness of one of the metal layers 302 may be in the range of about 1.05 to about 1.30, such as about 1.20. If the ratio is greater than 1.30, the initial warpage of the package substrate 300 may be excessive and may cause cold joint problems.

[0027] Although the thicknesses of the dielectric layers and the metal layers are different, the present disclosure is not limited thereto. For example, the thickness of each of the dielectric layers 304 may be greater than the thickness of the dielectric layer 308, and the thickness of each of the metal layers 306 may be substantially equal to the thickness of the metal layer 302. In another example, the thickness of each of the metal layers 306 may be greater than the thickness of each of the metal layers 302, and the thickness of each of the dielectric layers 304 may be substantially equal to the thickness of each of the dielectric layers 308.

[0028] The total thickness of the metal layer 302 and the dielectric layer 304 may be different from the total thickness of the metal layer 306 and the dielectric layer 308. The total thickness of the metal layer 306 and the dielectric layer 308 may be greater than, substantially equal to, or less than the total thickness of the metal layer 302 and the dielectric layer 304.

[0029] As Figure 3 shown, the number of the metal layers 306 may be equal to the number of the metal layers 302, and the number of the dielectric layers 308 may be equal to the number of the dielectric layers 304. The present disclosure is not limited thereto. The number of the metal layers 306 may be greater than or less than the number of the metal layers 302, and the number of the dielectric layers 308 may be greater than or less than the number of the dielectric layers 304 to further alleviate warpage.

[0030] In addition, it should be noted that the numbers of the metal layers 302 and 306 and the dielectric layers 304 and 308 are for illustrative purposes only and may be more or less than Figure 3 shown.

[0031] Figure 4FIG. 400 is a cross-sectional view of an encapsulated substrate 400 according to certain embodiments of the present disclosure. It should be noted that the encapsulated substrate 400 may include components that are the same as or similar to those of the encapsulated substrate 300 shown in Figure 3 For simplicity, these components will not be discussed in detail.

[0032] As shown in Figure 4 each of the dielectric layers 308 may have a thickness greater than that of each of the dielectric layers 304. Each of the metal layers 302 may have a thickness greater than that of each of the metal layers 306. Therefore, the encapsulated substrate 400 may be an unbalanced layer thickness substrate, and warping can be alleviated. The total thickness of the metal layer 302 and the dielectric layer 304 may be greater than, substantially equal to, or less than the total thickness of the metal layer 306 and the dielectric layer 308.

[0033] For example, the ratio of the thickness of one of the dielectric layers 308 to the thickness of one of the dielectric layers 304 may be in the range of about 1.05 to about 1.30, such as about 1.20. For example, the ratio of the thickness of one of the metal layers 302 to the thickness of one of the metal layers 306 may be in the range of about 1.05 to about 1.30, such as about 1.20. If the ratio is greater than 1.30, the initial warping of the encapsulated substrate 400 may be excessive and may cause cold joint problems.

[0034] Figure 5 FIG. 500 is a cross-sectional view of an encapsulated substrate 500 according to certain embodiments of the present disclosure. It should be noted that the encapsulated substrate 500 may include components that are the same as or similar to those of the encapsulated substrate 100 shown in Figure 1 For simplicity, these components will not be discussed in detail. In the following embodiments, a plurality of prepreg layers are disposed near the core structure.

[0035] As shown in Figure 5 a plurality of prepreg layers 502 are alternately stacked with some of the metal layers 104 according to certain embodiments. Therefore, the encapsulated substrate 500 may be an unbalanced multi-layer core substrate, and warping can be alleviated. The prepreg layer 502 may be made of a prepreg material, which may be a composite material made of prepreg fibers (including silica fillers, glass fibers, or the like) and a polymer matrix (including epoxy resins, phenolic resins, or the like), such as FR4 epoxy resin, M6 epoxy resin, the like, or a combination thereof.

[0036] The prepreg layer 502 can be disposed below the core structure 102. That is to say, some of the dielectric layers 106 can be replaced by the prepreg layer 502. Therefore, the coefficient of thermal expansion (CTE) mismatch can be reduced, which helps to reduce warping. In other words, the prepreg layer 502 can be alternately stacked with some of the metal layers 104 and may not be alternately stacked with the metal layer 108. Therefore, the number of dielectric layers 110 may be greater than the number of dielectric layers 106.

[0037] The prepreg layer 502 can be disposed beside the core structure 102 and away from the protective layer 112. In particular, the minimum distance between the core structure 102 and the dielectric layer 106 (i.e., the distance between the core structure 102 and the uppermost dielectric layer 106) may be greater than the maximum distance between the core structure 102 and the prepreg layer 502 (i.e., the distance between the core structure 102 and the lowermost prepreg layer 502).

[0038] It should be noted that the numbers of the prepreg layer 502, the metal layers 104 and 108, and the dielectric layers 106 and 110 given are for illustrative purposes only and may be more or less than Figure 5 those shown. For example, the number of the metal layers 104 may be equal to the number of the metal layers 108 as shown. In another example, the number of the metal layers 108 may be greater than or less than the number of the metal layers 104 to further alleviate warping. The number of the prepreg layer 502 can be adjusted accordingly.

[0039] In addition, the prepreg layer 502 can be respectively disposed in Figure 3 the package substrate 300 of Figure 4 or the package substrate 400 of

[0040] Figure 6 is a cross-sectional view of a package substrate 600 according to some embodiments of the present disclosure. It should be noted that the package substrate 600 may include components the same as or similar to those shown in Figure 5 the package substrate 500, and for simplicity, these components will not be discussed in detail again. In the following embodiments, a plurality of prepreg layers are disposed above the core structure.

[0041] As shown in Figure 6As shown, according to some embodiments, the prepreg layer 502 and some metal layers 108 are alternately stacked. Thus, the encapsulation substrate 600 may be an unbalanced multi-layer core substrate, and warpage can be alleviated. By changing the position of the prepreg layer 502, the shape of the encapsulation substrate 600 (such as concave or convex) can be adjusted. The prepreg layer 502 can be disposed above the core structure 102. In particular, some dielectric layers 110 can be replaced by the prepreg layer 502. That is, the prepreg layer 502 can be alternately stacked with some metal layers 108 and may not be alternately stacked with the metal layer 104.

[0042] Figure 7 is a cross-sectional view of an encapsulation substrate 700 according to some embodiments of the present disclosure. It should be noted that the encapsulation substrate 700 may include components that are the same as or similar to those shown in Figure 5 the encapsulation substrate 500 shown, and for simplicity, these components will not be discussed in detail again. In the following embodiments, a plurality of prepreg layers are disposed away from the core structure.

[0043] As Figure 7 shown, according to some embodiments, the prepreg layer 502 and some metal layers 104 are alternately stacked. Thus, the encapsulation substrate 700 may be an unbalanced multi-layer core substrate, and warpage can be alleviated. The prepreg layer 502 can be disposed beside the protective layer 112 and away from the core structure 102. Since the coefficient of thermal expansion (CTE) of the prepreg layer 502 is lower than that of a conventional metal layer, as the distance of the prepreg layer 502 from the center increases, warpage can be further reduced. When the prepreg layer 502 is away from the bonding interface, adjusting the overall CTE of the encapsulation substrate 700 to reduce the substrate-component CTE mismatch will be more effective.

[0044] In particular, the maximum distance between the core structure 102 and the dielectric layer 106 (i.e., the distance between the core structure 102 and the lowermost dielectric layer 106) may be less than the minimum distance between the core structure 102 and the prepreg layer 502 (i.e., the distance between the core structure 102 and the uppermost prepreg layer 502).

[0045] It should be noted that the number of prepreg layers 502, metal layers 104 and 108, and dielectric layers 106 and 110 given is for illustrative purposes only and may be more or less than that shown in Figure 7 For example, the number of metal layers 104 may be equal to the number of metal layers 108, as shown in the figure. In another example, the number of metal layers 108 may be greater than or less than the number of metal layers 104 to further alleviate the warpage problem. The number of prepreg layers 502 can be adjusted accordingly.

[0046] Figure 8is a cross-sectional view of an encapsulation substrate 800 according to some embodiments of the present disclosure. It should be noted that the encapsulation substrate 800 may include components that are the same as or similar to those of the encapsulation substrate 700 shown in Figure 7 For simplicity, these components will not be discussed in detail. In the following embodiments, a plurality of prepreg layers are disposed above the core structure.

[0047] As Figure 8 shown, according to some embodiments, the prepreg layers 502 and some metal layers 108 are alternately stacked. Therefore, the encapsulation substrate 800 may be an unbalanced multi-layer core substrate, and warpage can be alleviated. The prepreg layers 502 may be disposed above the core structure 102. In particular, some dielectric layers 110 may be replaced by the prepreg layers 502. That is, the prepreg layers 502 may be alternately stacked with some metal layers 108 and may not be alternately stacked with the metal layer 104.

[0048] Figure 9 is a cross-sectional view of an encapsulation substrate 900 according to some embodiments of the present disclosure. It should be noted that the encapsulation substrate 900 may include components that are the same as or similar to those of the encapsulation substrate 100 shown in Figure 1 For simplicity, these components will not be discussed in detail. In the following embodiments, two core structures are vertically stacked.

[0049] As Figure 9 shown, according to certain embodiments, core structures 102 and 902 are provided. The core structure 902 may be similar to the core structure 102 and will not be described in detail. By stacking two core structures, the thickness of each of the core structures 102 and 902 can be reduced. In certain embodiments, the thickness of the core structure 902 is in the range of about 200 microns to about 1400 microns, such as about 1240 microns. In certain embodiments, the thickness of the core structure 102 is in the range of about 200 microns to about 1400 microns, such as about 1240 microns. The thickness of the core structure 902 may be the same as or different from the thickness of the core structure 102. Since the multi-core substrate has more layers compared to the single-core substrate, the overall coefficient of thermal expansion (CTE) will be lower, and the CTE mismatch between the encapsulation substrate 900 and the chip-on-wafer (CoW) component formed thereon can be reduced.

[0050] A plurality of dielectric layers 106 and a plurality of metal layers 104 may be alternately stacked below the core structure 102, and a plurality of dielectric layers 110 and a plurality of metal layers 108 may be alternately stacked above the core structure 102. Similarly, a plurality of dielectric layers 908 and a plurality of metal layers 906 may be alternately stacked below the core structure 902, and a plurality of dielectric layers 912 and a plurality of metal layers 910 may be alternately stacked above the core structure 902. The dielectric layers 908 and 912 may be similar to the dielectric layers 106 and 110, and the metal layers 906 and 910 may be similar to the metal layers 104 and 108, which will not be elaborated here.

[0051] The number of the metal layers 906 may be different from the number of the metal layers 910, and the number of the dielectric layers 908 may be different from the number of the dielectric layers 912. For example, the number of the metal layers 906 may be greater than the number of the metal layers 910, and the number of the dielectric layers 908 may be greater than the number of the dielectric layers 912, as shown in the figure.

[0052] The core structures 102 and 902 may be vertically stacked by bonding the topmost metal layer 910 and the bottommost metal layer 104 together. Thus, the processing yield of the package substrate 900 can be improved. For example, a plurality of bump structures 903 may be formed on the topmost metal layer 910 and / or the bottommost metal layer 104. The bump structures 903 may include micro-bumps, such as copper pillar bumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, etc., or a combination thereof.

[0053] The bump structures 903 may be made of a metal, such as tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, etc., their alloys, or a combination thereof. In some embodiments, the bump structures 903 may be made of a material similar to the metal layer 910 or the metal layer 104. In these embodiments, conductor-to-conductor bonding may be employed, which may be direct metal-to-metal bonding, such as direct copper-to-copper bonding, to connect the bump structures 903.

[0054] A filling material 904 is formed between the topmost metal layer 910 and the bottommost metal layer 104, according to Figure 9 certain embodiments shown therein. The filling material 904 may surround each bump structure 903 and may fill the gaps between the bump structures 903 to provide structural support. In some embodiments, the filling material 904 includes a polymer, such as epoxy resin. The filling material 904 may be dispensed by capillary action and then cured by any suitable curing process.

[0055] The number of metal layers 906 may be different from the total number of metal layers 104 and 910, and the number of dielectric layers 908 may be different from the total number of dielectric layers 106 and 912. Additionally, the number of metal layers 108 may be different from the total number of metal layers 104 and 910, and the number of dielectric layers 110 may be different from the total number of dielectric layers 106 and 912. Accordingly, the package substrate 900 is a multi-chip substrate with copper layer-to-copper layer connections, thereby reducing warpage.

[0056] As Figure 9 shown, in some embodiments, the number of metal layers 906 is greater than the total number of metal layers 104 and 910, and the number of dielectric layers 908 is greater than the total number of dielectric layers 106 and 912. In these embodiments, the number of metal layers 108 is greater than the total number of metal layers 104 and 910, and the number of dielectric layers 110 is greater than the total number of dielectric layers 106 and 912.

[0057] However, the present disclosure is not limited thereto. In some other embodiments, the total number of metal layers 104 and 910 is greater than the number of metal layers 906, and the total number of dielectric layers 106 and 912 is greater than the number of dielectric layers 908. In these embodiments, the total number of metal layers 104 and 910 is greater than the number of metal layers 108, and the total number of dielectric layers 106 and 912 is greater than the number of dielectric layers 110. Other arrangements may be employed.

[0058] Then, a protective layer 112 may be disposed above the metal layer 108 and below the metal layer 906 to protect the surfaces of the metal layers 108 and 906.

[0059] Although the thicknesses of the metal layers 104, 108, 906, and 910 are substantially the same, and the thicknesses of the dielectric layers 106, 110, 908, and 912 are substantially the same, as shown, the present disclosure is not limited thereto. The thicknesses of the metal layers 104, 108, 906, and 910 may be different, and the thicknesses of the dielectric layers 106, 110, 908, and 912 may be different to further reduce warpage.

[0060] Additionally, although the number of metal layers 108 and 906 is the same, and the number of dielectric layers 110 and 908 is the same, as shown, the present disclosure is not limited thereto. The number of metal layers 108 and 906 may be different, and the number of dielectric layers 110 and 908 may be different to further reduce warpage.

[0061] Additionally, a plurality of prepreg layers (such as Figure 5The prepreg layer 502) may be alternately stacked with some of the metal layers 104, 108, 906, and 910 to replace some of the dielectric layers 106, 110, 908, and 912, further reducing warping. The prepreg layer may be disposed beside the core structure 102 and / or the core structure 902, or beside one or both of the protective layers 112, as Figures 5 to 8 discussed therein.

[0062] Figure 10 is a cross-sectional view of an encapsulation substrate 1000 according to certain embodiments of the present disclosure. It should be noted that the encapsulation substrate 1000 may include components that are the same as or similar to those of the encapsulation substrate 900 shown in Figure 9 and, for simplicity, these components will not be discussed in detail. In the following embodiments, the metal layers are connected by solder layers.

[0063] As Figure 10 shown, according to certain embodiments, a solder layer 1002 is formed between the topmost metal layer 910 and the bottommost metal layer 104. The solder layer 1002 can be formed by forming solder balls (not shown) on the topmost metal layer 910 and the bottommost metal layer 104. Then, a reflow process or other appropriate process can be performed to form the solder layer 1002 and connect the metal layers 910 and 104. Any other appropriate connection method can be employed.

[0064] Figure 11 is a cross-sectional view of an encapsulation substrate 1100 according to certain embodiments of the present disclosure. It should be noted that the encapsulation substrate 1100 may include components that are the same as or similar to those of the encapsulation substrate 900 shown in Figure 9 and, for simplicity, these components will not be discussed in detail. In the following embodiments, the core structures are vertically stacked by bonding dielectric layers.

[0065] As Figure 11 shown, the core structures 102 and 902 can be vertically stacked by bonding the topmost dielectric layer 912 and the bottommost dielectric layer 106. The dielectric layer 912 and the dielectric layer 106 can be bonded from dielectric layer to dielectric layer, and then the bonded dielectric layer 1102 is formed. The bonded dielectric layer 1102 can be formed by the topmost dielectric layer 912 and the bottommost dielectric layer 106 and may have a thickness greater than the thickness of one of the dielectric layers 912 and the thickness of one of the dielectric layers 106.

[0066] The number of metal layers 906 may be greater than the total number of metal layers 104 and 910, and the number of dielectric layers 908 may be greater than the total number of dielectric layers 106 and 912. The number of metal layers 108 may be greater than the total number of metal layers 104 and 910, and the number of dielectric layers 110 may be greater than the total number of dielectric layers 106 and 912. Thus, the package substrate 1100 is a multi-chip substrate that builds layer-to-layer connections to mitigate warping.

[0067] Figure 12 is a cross-sectional view of a package substrate 1200 in accordance with certain embodiments of the present disclosure. It should be noted that the package substrate 1200 may include components that are the same as or similar to those of the Figure 11 package substrate 1100 shown in, and for the sake of simplicity, these components will not be discussed in detail. In the following embodiments, the dielectric layers are bonded by an adhesive layer.

[0068] As Figure 12 shown, in accordance with certain embodiments, an adhesive layer 1202 is formed between the topmost dielectric layer 912 and the bottommost dielectric layer 106. The adhesive layer 1202 may be formed on the topmost dielectric layer 912, the bottommost dielectric layer 106, or both the topmost dielectric layer 912 and the bottommost dielectric layer 106. Any other suitable connection method may be employed.

[0069] Exemplary semiconductor package structures include Figures 1 to 12 some of the package substrates shown in, which will be discussed with reference to Figures 13 to 16 below.

[0070] Figure 13 is a cross-sectional view of a semiconductor package structure 1300 in accordance with certain embodiments of the present disclosure. Additional features may be added to the semiconductor package structure 1300. Some of the features described below may be replaced or eliminated for different embodiments. For the sake of simplicity in the figures, only a portion of the semiconductor package structure 1300 is shown. The semiconductor package structure 1300 may include components that are the same as or similar to those of the Figure 1 package substrate 100 shown in, and for the sake of simplicity, these components will not be discussed in detail.

[0071] As Figure 13 shown, in accordance with certain embodiments, the semiconductor package structure 1300 includes a package substrate 1302. The package substrate 1302 may include a core structure 102, a plurality of dielectric layers 106 and 110, and a plurality of metal layers 104 and 108. The number of metal layers 108 may be different from the number of metal layers 104, and the number of dielectric layers 110 may be different from the number of dielectric layers 106. Thus, the package substrate 1302 may be a substrate with an unbalanced number of layers to mitigate warping.

[0072] The package substrate 1302 may be similar toFigure 1 The packaged substrate 100 shown in. That is, the number of metal layers 108 may be greater than the number of metal layers 104, and the number of dielectric layers 110 may be greater than the number of dielectric layers 106, as shown. Alternatively, the packaged substrate 1302 may be similar to Figure 2 The packaged substrate 200 shown in. That is, the number of metal layers 108 may be less than the number of metal layers 104, and the number of dielectric layers 110 may be less than the number of dielectric layers 106.

[0073] A plurality of conductive terminals 1304 may be disposed under the packaged substrate 1302. The conductive terminals 1304 may include microbumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, etc., or combinations thereof. The conductive terminals 1304 may be made of a metal such as tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, etc., alloys thereof, or combinations thereof.

[0074] The semiconductor package structure 1300 includes an interconnector 1308 disposed above the packaged substrate 1302, according to some embodiments. The interconnector 1308 may include a bulk semiconductor, a compound semiconductor, an alloy semiconductor, etc., or combinations thereof. The interconnector 1308 may be made of any suitable semiconductor material such as silicon or germanium. The interconnector 1308 may include a wiring structure (not shown).

[0075] The interconnector 1308 may be electrically connected to the packaged substrate 1302 through a plurality of bump structures 1306. The bump structures 1306 may include microbumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, etc., or combinations thereof. The bump structures 1306 may be made of a metal such as tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, etc., alloys thereof, or combinations thereof.

[0076] According to some embodiments, semiconductor chips 1314, 1316, and 1318 are disposed above the interconnect 1308. In some embodiments, each of the semiconductor chips 1314, 1316, and 1318 independently includes a system-on-chip (SoC) chip, a logic device, a memory device, a radio frequency (RF) device, a similar device, or a combination thereof. For example, the semiconductor chips 1314, 1316, and 1318 may each include a micro control unit (MCU) chip, a microprocessor unit (MPU) chip, a power management integrated circuit (PMIC) chip, a radio frequency frontend (RFFE) chip, an accelerated processing unit (APU) chip, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, an input-output (IO) chip, a dynamic random access memory (DRAM) controller, a static random-access memory (SRAM), a high bandwidth memory (HBM), an application processor (AP) chip, an application specific integrated circuit (ASIC) chip, a similar device, or a combination thereof.

[0077] The semiconductor chips 1314, 1316, and 1318 may include the same or different devices. The semiconductor package structure 1300 may include fewer or more semiconductor chips and may also include one or more passive components disposed above the interconnect 1308, such as resistors, capacitors, or inductors.

[0078] The semiconductor chips 1314, 1316, and 1318 may be electrically connected to the interconnect 1308 through a plurality of bump structures 1312. The bump structures 1312 may include micro - bumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, similar devices, or combinations thereof. The bump structures 1312 may include the materials discussed above and will not be repeated.

[0079] According to some embodiments, a fill material 1320 extends between the interconnect 1308 and the semiconductor chips 1314, 1316, and 1318. The fill material 1320 may surround the bump structures 1312 and may fill the gaps between the bump structures 1312 to provide structural support. In some embodiments, the fill material 1320 includes a polymer, such as an epoxy resin. The fill material 1320 may be dispensed by capillary force and then may be cured by any suitable curing process.

[0080] According to some embodiments, the semiconductor package structure 1300 includes a molding material 1322 disposed over the interconnect 1308. The molding material 1322 may surround the semiconductor chips 1314, 1316, 1318, the bump structures 1312, and the fill material 1320 to protect these components from the environment, thereby preventing them from being damaged by stress, chemicals, and moisture. The molding material 1322 may be composed of a non - conductive material, including a moldable polymer, an epoxy resin, a resin, similar materials, or combinations thereof.

[0081] The sidewall of the molding material 1322 may be substantially coplanar with the sidewall of the interconnect 1308. In some embodiments, the top surfaces of the semiconductor chips 1314, 1316, 1318 are exposed by the molding material 1322 as shown.

[0082] According to some embodiments, a fill material 1310 extends between the interconnect 1308 and the package substrate 1302. The fill material 1310 may surround the bump structures 1306 and may fill the gaps between the bump structures 1306 to provide structural support. The fill material 1310 may cover the sidewalls of the interconnect 1308 and may partially cover the sidewalls of the molding material 1322. In some embodiments, the fill material 1310 includes a polymer, such as an epoxy resin. The fill material 1310 may be dispensed by capillary force and then may be cured by any suitable curing process.

[0083] According to some embodiments, the frame 1326 is attached to the encapsulation substrate 1302 through the adhesive layer 1324. The frame 1326 may be an annular structure. The frame 1326 may be disposed along the sidewall of the encapsulation substrate 1302 to reduce warping, prevent bending, and maintain the flatness of the encapsulation substrate 1302. The frame 1326 may surround the interconnect 1308 and the semiconductor chips 1314, 1316, 1318. The frame 1326 and the adhesive layer 1324 may be separated from the gap filling layer 1310 by a gap. Accordingly, a part of the top surface of the encapsulation substrate 1302 is thus exposed.

[0084] Figure 14 is a cross-sectional view of a semiconductor package structure 1400 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 1400 may include components that are the same as or similar to those of the semiconductor package structure 1300 shown in Figure 13 . For simplicity, these components will not be discussed in detail. In the following embodiments, the thickness of the metal layer and / or the thickness of the dielectric layer are different on opposite sides of the core structure.

[0085] As Figure 14 shown, according to some embodiments, the semiconductor package structure 1400 includes an encapsulation substrate 1402. The encapsulation substrate 1402 may include a core structure 102, a plurality of dielectric layers 304 and 308, and a plurality of metal layers 302 and 306. The thickness of each dielectric layer 304 may be different from the thickness of each dielectric layer 308. The thickness of each metal layer 302 may be different from the thickness of each metal layer 306. Accordingly, the encapsulation substrate 1402 may be an unbalanced layer thickness substrate so that warping can be alleviated.

[0086] The encapsulation substrate 1402 may be similar to Figure 3 the encapsulation substrate 300 shown in. That is, the thickness of each dielectric layer 304 may be greater than the thickness of each dielectric layer 308, and the thickness of each metal layer 306 may be greater than the thickness of each metal layer 302, as shown. Alternatively, the encapsulation substrate 1402 may be similar to Figure 4 the encapsulation substrate 400 shown in. That is, the thickness of each dielectric layer 308 may be greater than the thickness of each dielectric layer 304, and the thickness of each metal layer 302 may be greater than the thickness of each metal layer 306.

[0087] Figure 15 is a cross-sectional view of a semiconductor package structure 1500 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 1500 may include components that are the same as or similar to those of the semiconductor package structure 1300 shown in Figure 13 . For simplicity, these components will not be discussed in detail. In the following embodiments, a plurality of prepreg layers are alternately stacked with partial metal layers.

[0088] As shown Figure 15 in FIG. 2, the semiconductor package structure 1500 includes a package substrate 1502, according to some embodiments. The package substrate 1502 may include a core structure 102, a plurality of dielectric layers 106 and 110, a plurality of metal layers 104 and 108, and a plurality of prepreg layers 502. The prepreg layers 502 may be alternately stacked with some of the metal layers 104. Thus, the package substrate 1502 may be an unbalanced multi-layer core substrate, thereby reducing warping.

[0089] The package substrate 1502 may be similar to Figure 7 the package substrate 700 shown in FIG. 3. That is, the prepreg layers 502 may be alternately stacked with some of the metal layers 104 and may be away from the core structure 102, as shown. Alternatively, the package substrate 1502 may be similar to Figure 5 the package substrate 500 shown in FIG. 4. That is, the prepreg layers 502 may be close to the core structure 102.

[0090] In another example, the package substrate 1502 may be similar to Figure 6 the package substrate 600 shown in FIG. 5. That is, the prepreg layers 502 may be alternately stacked with some of the metal layers 108 and may be close to the core structure 102. Alternatively, the package substrate 1502 may be similar to Figure 8 the package substrate 800 shown in FIG. 6. That is, the prepreg layers 502 may be alternately stacked with some of the metal layers 108 and may be away from the core structure 102.

[0091] Figure 16 FIG. 7 is a cross-sectional view of a semiconductor package structure 1600 according to some embodiments of the present disclosure. It should be noted that the semiconductor package structure 1600 may include components that are the same as or similar to those of the semiconductor package structure 1300 shown in Figure 13 FIG. 8. For simplicity, these components will not be discussed in detail. In the following embodiments, two core structures are vertically stacked.

[0092] As shown Figure 16As shown, semiconductor package structure 1600 includes a package substrate 1602, according to some embodiments. The package substrate 1602 may include core structures 102 and 902, a plurality of dielectric layers 106, 110, 908, 912, and a plurality of metal layers 104, 108, 906, 910. The number of metal layer 108 may be different (e.g., more) from the total number of metal layers 104 and 910, and the number of dielectric layer 110 may be different (e.g., more) from the total number of dielectric layers 106 and 912. The number of metal layer 906 may be different (e.g., more) from the total number of metal layers 104 and 910, and the number of dielectric layer 908 may be different (e.g., more) from the total number of dielectric layers 106 and 912. Thus, the package substrate 1602 is a multi-chip substrate, which can reduce warpage.

[0093] The package substrate 1602 may be similar to Figure 10 the package substrate 1000 shown in. That is, a solder layer 1002 may be used to connect the metal layers 104 and 910. Alternatively, the package substrate 1602 may be similar to Figure 9 the package substrate 900 shown in. That is, a bump structure may be used to connect the gold layers 104 and 910.

[0094] In another example, the package substrate 1602 may be similar to Figure 11 the package substrate 1100 shown in. That is, a bonded dielectric layer including dielectric layers 106 and 912 may be formed by dielectric-to-dielectric bonding. Alternatively, the package substrate 1602 may be similar to Figure 12 the package substrate 1200 shown in. That is, an adhesive layer may be used to connect the dielectric layers 106 and 912.

[0095] In summary, the semiconductor package structure according to the present disclosure includes a package substrate, which is an unbalanced substrate structure, an unbalanced layer thickness substrate, an unbalanced multi-layer core substrate, or a multi-chip substrate. The package substrate includes different numbers of layers and / or different thicknesses of layers on opposite sides. Thus, the warpage problem can be reduced without reducing the number of metal layers. In addition, the thickness of the core structure in the package substrate can be reduced to avoid affecting the electrical signal performance.

[0096] In some embodiments, the package substrate further includes a prepreg layer to reduce the warpage problem. The position of the prepreg layer can be adjusted to obtain the desired warpage behavior. In some embodiments, two substrates are vertically stacked to improve the process yield.

[0097] While the present invention has been described by way of example and preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and similar arrangements (which would be apparent to those skilled in the art). Accordingly, the scope of the appended claims should be accorded the broadest interpretation so as to cover all such modifications and similar arrangements.

Claims

1. A semiconductor packaging structure, comprising: A packaging substrate, comprising: a first core structure having a first surface and a second surface opposite the first surface; A plurality of first dielectric layers and a plurality of first metal layers are alternately stacked on the first surface; A plurality of second dielectric layers and a plurality of second metal layers are alternately stacked on the second surface, The number of the second dielectric layers is less than the number of the first dielectric layers.

2. The semiconductor package structure according to claim 1, wherein the package substrate further comprises: A plurality of prepreg layers and a portion of the second metal layer are alternately stacked. 3 . The semiconductor package structure as claimed in claim 2 , wherein the number of the second metal layers is equal to the number of the first metal layers. 4 . The semiconductor package structure as claimed in claim 2 , wherein a minimum distance between the first core structure and the second dielectric layer is greater than a maximum distance between the first core structure and the prepreg layer. 5 . The semiconductor package structure as claimed in claim 2 , wherein a maximum distance between the first core structure and the second dielectric layer is smaller than a minimum distance between the first core structure and the prepreg layer. The semiconductor package structure as claimed in claim 1 , wherein the number of the second metal layers is less than the number of the first metal layers.

7. The semiconductor package structure as claimed in claim 1, wherein the package substrate further comprises: a second core structure having a third surface adjacent to the second metal layer and a fourth surface opposite to the third surface; A plurality of third dielectric layers and a plurality of third metal layers are alternately stacked on the fourth surface. 8 . The semiconductor package structure as claimed in claim 1 , further comprising a plurality of bump structures disposed between two of the second metal layers. 9 . The semiconductor package structure as claimed in claim 1 , wherein one of the second dielectric layers is thicker than other second dielectric layers. 10 . The semiconductor package structure as claimed in claim 1 , wherein the package substrate further comprises a solder layer disposed between the two second metal layers. 11 . The semiconductor package structure as claimed in claim 1 , wherein the package substrate further comprises an adhesive layer disposed between the two second dielectric layers.

12. A semiconductor packaging structure, comprising: A packaging substrate, comprising: A core structure; A plurality of first dielectric layers and a plurality of first metal layers are alternately stacked below the core structure; A plurality of second dielectric layers and a plurality of second metal layers are alternately stacked above the core structure, The thickness of each of the second metal layers is different from the thickness of each of the first metal layers. 13 . The semiconductor package structure as claimed in claim 12 , wherein a thickness of each of the second metal layers is greater than a thickness of each of the first metal layers. 14 . The semiconductor package structure of claim 13 , wherein a ratio of a thickness of each of the second metal layers to a thickness of each of the first metal layers is in a range of about 1.05 to about 1.

30. 15 . The semiconductor package structure as claimed in claim 13 , wherein a thickness of each of the second dielectric layers is smaller than a thickness of each of the first dielectric layers. 16 . The semiconductor package structure as claimed in claim 15 , wherein a total thickness of the second metal layer and the second dielectric layer is greater than a total thickness of the first metal layer and the first dielectric layer. 17 . The semiconductor package structure as claimed in claim 12 , wherein a thickness of each of the second metal layers is smaller than a thickness of each of the first metal layers. 18 . The semiconductor package structure as claimed in claim 12 , wherein the package substrate further comprises a protection layer covering the plurality of first metal layers and the plurality of second metal layers.

19. The semiconductor package structure according to claim 12, further comprising: a semiconductor chip disposed on the packaging substrate; a frame surrounding the semiconductor chip; A plurality of conductive terminals are disposed below the packaging substrate.

20. The semiconductor package structure of claim 12, wherein a thickness of the core structure is in a range of about 200 microns to about 2000 microns.

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