System and method for gate current shaping for gate drivers

Abstract

Embodiments of the present disclosure relate to systems and methods for gate current shaping for a gate driver. Gate drivers, systems, and methods are described. The gate driver may generate a gate current for driving a power switch in the system. The circuit may define a waveform shape of the gate current. The defined waveform shape of the gate current may cause the current of the power switch to have a constant slew rate.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices. More specifically, the present disclosure relates to gate current shaping for a gate driver to reduce switching losses and ringing. Background Art

[0002] Gate drivers are used in switching converter applications such as DC / DC converters, inverters, motor drivers, etc. These systems can include a controller, one or more power switches, and a gate driver for each switch. The gate driver drives its power switch to an on state and an off state according to signals from the controller, and the system provides a desired output voltage or power to a load. Summary of the Invention

[0003] In one embodiment, a semiconductor device is generally described. The semiconductor device can include a driver circuit configured to drive a switch. The semiconductor device can also include a circuit configured to generate a gate current having a defined waveform shape at a switch transition. The defined waveform shape of the gate current can cause the current of the switch to have a constant slew rate during the switch transition.

[0004] In one embodiment, a system in a switching converter is generally described. The system can include at least one power switch and a gate driver. The gate driver can be configured to drive at least one power switch. The gate driver can also be configured to generate a gate current having a defined waveform shape at at least one power switch transition. The defined waveform shape of the gate current causes the current of the switch to have a constant slew rate during the at least one power switch transition.

[0005] In one embodiment, a method for operating a switching converter is generally described. The method can include generating a gate current for driving a switch in the switching converter. The method can also include defining a waveform shape of the gate current. The defined waveform shape of the gate current can cause the current of the power switch to have a constant slew rate during the power switch transition.

[0006] The foregoing summary is illustrative only and is not intended to be limiting in any way. In addition to the above - described illustrative aspects, embodiments, and features, other aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description. In the drawings, like reference numerals indicate identical or functionally similar elements. Brief Description of the Drawings

[0007] Figure 1A is a diagram showing a system in which gate current shaping of a gate driver can be implemented in one embodiment.

[0008] Figure 1BIt is a diagram showing another system that can achieve gate current shaping in a gate driver in one embodiment.

[0009] Figure 1C It is a diagram showing another system that can achieve gate current shaping in a gate driver in one embodiment.

[0010] Figure 1D It is a diagram showing another system that can achieve gate current shaping in a gate driver in one embodiment.

[0011] Figure 1E It is a diagram showing another system that can achieve gate current shaping in a gate driver in one embodiment.

[0012] Figure 2A It is a diagram illustrating the operation of a power switch that may cause ringing.

[0013] Figure 2B It is another diagram illustrating the operation of a power switch that may cause ringing.

[0014] Figure 2C It is another diagram illustrating the operation of a power switch that may cause ringing.

[0015] Figure 2D It is a diagram illustrating the ringing that may be caused by the operation of a power switch.

[0016] Figure 3A It is a diagram showing the operation of a power switch during the transition between the on state and the off state.

[0017] Figure 3B It is another diagram showing the operation of a power switch during the transition between the on state and the off state.

[0018] Figure 4A It is a diagram showing different scenarios of disabling and enabling gate current shaping in one embodiment.

[0019] Figure 4B It is a diagram showing the implementation of gate current shaping of a gate driver in one embodiment.

[0020] Figure 4C It is a diagram showing another implementation of gate current shaping of a gate driver in one embodiment.

[0021] Figure 4D It is a diagram showing another implementation of gate current shaping of a gate driver in one embodiment.

[0022] Figure 5A It is a diagram showing an example implementation of a current shaping circuit in one embodiment.

[0023] Figure 5B It is a diagram showing another exemplary implementation of the current shaping circuit in an embodiment.

[0024] Figure 5C It is a diagram showing another exemplary implementation of the current shaping circuit in an embodiment.

[0025] Figure 5D It is a diagram showing another exemplary implementation of the current shaping circuit in an embodiment.

[0026] Figure 5E It is a diagram showing another exemplary implementation of the current shaping circuit in an embodiment.

[0027] Figure 5F It is a diagram showing another exemplary implementation of the current shaping circuit in an embodiment.

[0028] Figure 6A It is a diagram showing an exemplary implementation of a voltage-to-current converter of a current shaping circuit that can be used in a gate driver in an embodiment.

[0029] Figure 6B It is a diagram showing another exemplary implementation of a voltage-to-current converter of a current shaping circuit that can be used in a gate current shaping circuit.

[0030] Figure 6C It is a diagram showing another exemplary implementation of a voltage-to-current converter of a current shaping circuit that can be used in a gate current shaping circuit.

[0031] Figure 7 It is a diagram showing different waveforms with different shapes due to the implementation of the current shaping circuit of the gate driver in one or more embodiments.

[0032] Figure 8A It is a diagram showing a system with adaptive control for gate current shaping in an embodiment.

[0033] Figure 8B It is a diagram showing another system with adaptive control for gate current shaping in an embodiment.

[0034] Figure 9A It is a diagram showing an implementation of feedback control in an embodiment.

[0035] Figure 9B It is a diagram showing an implementation of feedback control in an embodiment.

[0036] Figure 9CFIG. is a diagram showing an implementation of feedback control in one embodiment.

[0037] Figure 10 FIG. is a diagram showing an implementation using temperature estimation in one embodiment.

[0038] Figure 11 FIG. is a flowchart illustrating a process of implementing gate current shaping of a gate driver in one embodiment. DETAILED DESCRIPTION

[0039] In the following description, numerous specific details are set forth, such as specific structures, components, materials, dimensions, processing steps, and techniques, in order to provide an understanding of the various embodiments of the present application. However, those skilled in the art will understand that the various embodiments of the present application can be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0040] Figure 1A FIG. is a diagram showing a system 100 that can implement gate current shaping of a gate driver in one embodiment. Applications of the system 100 may include, but are not limited to, solenoid drivers, buck converters, boost converters, etc. The system 100 may at least include a controller 102, one or more power switches 108, and a gate driver 104 (e.g., a gate driver circuit) for each of the one or more power switches 108. Each gate driver 104 in the gate driver 104 may be configured to drive a corresponding power switch among the power switches 108 to an on state or an off state using a gate current Igate. The gate driver 104 may generate the gate current Igate according to a signal 101 (e.g., a pulse width modulation (PWM) signal or a pulse frequency modulation (PFM) signal) provided by the controller 102. The system 100 may convert an input voltage Vin into an output voltage Vout or power to a load 107, where the output voltage Vout may provide the amount of power required or demanded by the load 107. Figure 1A The illustrated system 100 may be a buck converter, where the output voltage Vout is less than the input voltage Vin. In one embodiment, the power switch 108 may be a field effect transistor (FET), such as a metal oxide semiconductor field effect transistor (MOSFET). In other embodiments, the power switch 108 may be an insulated gate bipolar transistor (IGBT). As will be described in more detail below, the gate driver 104 may include components and circuitry configured to control the shape of the gate current Igate for driving the power switch 108. Controlling the shape of the gate current Igate may address ringing generated by the power switch 108.

[0041] Figure 1BFIG. is a diagram showing another system 110 in which gate current shaping of a gate driver can be implemented. In system 110, the gate driver 104 can include a gate driver for driving a power switch 108, and system 110 can include a diode 109. Figure 1B The illustrated gate driver 104 can include components and circuitry configured to control the shape of the gate current Igate for driving Figure 1B the power switch 108 therein. Controlling the shape of the gate current Igate can address ringing generated by the power switch 108.

[0042] Figure 1C FIG. is a diagram showing another system 120 in which gate current shaping of a gate driver can be implemented. System 120 can be a boost converter where the output voltage Vout is greater than the input voltage Vin. Figure 1C The illustrated gate driver 104 can include components and circuitry configured to control the shape of the gate current Igate for driving Figure 1C the power switch 108 therein. Controlling the shape of the gate current Igate can address ringing generated by the power switch 108. Figure 1D FIG. is a diagram showing another system 130 in which gate current shaping of a gate driver can be implemented. System 130 can be a power factor correction (PFC) converter. Figure 1D The gate driver 104 shown therein can include components and circuitry configured to control the shape of the gate current Igate for driving Figure 1D the power switch 108 therein. Controlling the shape of the gate current Igate can address ringing generated by the power switch 108.

[0043] Figure 1E FIG. is a diagram showing another system 140 in which gate current shaping of a gate driver can be implemented. System 140 can be part of an inverter, a motor driver, a multiphase DC / DC converter, etc. Figure 1E The illustrated gate driver 104 can include components and circuitry configured to control the shape of the gate current Igate for driving Figure 1E the power switch 108 therein. Controlling the shape of the gate current Igate can address ringing generated by the power switch 108.

[0044] Figures 2A to 2C FIG. is a diagram illustrating the operation of a power switch that can cause ringing. In Figure 2A it, the switch node SW between two power switches 108 (labeled HS switch and LS switch) can alternately operate in two states. The first state of SW is as Figure 2Bas shown, where HS is turned on and LS is turned off. The second state of SW is as Figure 2C shown, where HS is turned off and LS is turned on. In an embodiment where a power switch 108 is implemented with a diode 109 (see Figure 1B and Figure 1D ), the on state of the diode 109 means that the diode 109 is forward conducting. As Figure 2B and Figure 2C shown, due to stray inductance and capacitance, LC resonance may exist. As shown in the following Figure 2D figure, the LC resonance is observed as ringing in the current or voltage. The ringing amplitude depends on multiple factors, such as the Figure 2D transition time shown.

[0045] Figure 2D is a figure illustrating the ringing that may occur from the operation of the power switch. In one aspect, large ringing may damage the power switch 108 due to overvoltage. Moreover, the ringing may cause the system including the power switch 108 (e.g., see Figures 1A to 1E ) to emit unwanted radio frequency noise, such as electromagnetic interference (EMI). Therefore, it is desirable to reduce the ringing. However, there is a trade-off between ringing and energy loss. If the driver 104 drives HS and LS at a relatively fast rate, the efficiency of the system 100 can be increased, thereby reducing losses, but the ringing may increase. If the gate driver 104 drives HS and LS at a relatively slow rate, the efficiency of the system can be reduced, thereby increasing losses, but the ringing may decrease. As will be described in more detail below, the gate driver 104 may include components and circuitry configured to control the shape of the gate current Igate used to drive the power switch 108 (such as HS and LS) to reduce the ringing generated by the operation of the power switch 108.

[0046] Figure 3A and 3B are figures showing the operation of the power switch during the transition between the on state and the off state. The gate driver 104 can provide a pull-up ( Figure 3A ) or pull-down ( Figure 3B ) gate current (Igate) 103. The Igate 103 can drive the power device 108, and its state changes between on and off during the transition. Figure 3A and Figure 3B the current Ids in can be the current flowing through the power switch 108. The transition time depends on the gate current 103 provided by the gate driver 104. The Igate 103 can be controlled to achieve a good balance of the aforementioned trade-off, for example, by placing a current limiting resistor between the gate driver 104 and the power switch 108.

[0047] Figure 4AFIG. 0 is a diagram showing different scenarios of disabling and enabling gate current shaping in one embodiment. As mentioned above, the ringing amplitude depends on the transition time. In other words, it depends on the slew rate of the power switch current such as Igate. A constant slew rate of the switch current during the transition is an object of the present disclosure. The constant slew rate can achieve a faster transition without increasing ringing, i.e., lower power loss and ringing than the trade-off in the prior art. The gate current shaping described herein can be applied to small to large load currents. Moreover, a system that adjusts the gate current depending on the load current level is not required.

[0048] For example, in an embodiment where a MOSFET is used as the power switch 108, the gate current can be given by: I ds ∝(V gs -V th ) 2 , where V gs =∫I gate dt / C gs . If Ids is a constant slew rate, then I ds ∝t, where t is time. Based on these relationships between the drain-source current I ds , time t, the gate-source voltage V gs and the threshold voltage V th , the gate current shape (e.g., the waveform shape of Igate) required to turn on the MOSFET used as the power switch 108 can be expressed as: I gate ∝t -0.5 . To turn on the MOSFET used as the power switch 108, the gate current shape can be reflected in terms of time. As Figure 4A shown, when the gate current shaping is disabled, the slew rate of the gate current Igate is not constant. When the gate current shaping is enabled, the slew rate of the gate current Igate becomes constant. In addition, as Figure 4A shown, the constant slew rate generated by the gate current shaping described herein can shorten the transition time. Various implementations of performing gate current shaping in the gate driver 104 will be described in more detail below.

[0049] Figure 4B 、 Figure 4C and Figure 4DFIG. 0 is a diagram illustrating an implementation of gate current shaping in various embodiments. In one or more embodiments, the gate driver 104 described herein may include a current shaping circuit 106. The current shaping circuit 106 may provide a current having a curved shape. In one embodiment, the controller 102 may communicate with the gate driver 104 to configure the waveform of the signal generated by the current shaping circuit 106. In one embodiment, the gate driver 104 may be configured to control the waveform of the signal output by the current shaping circuit 106. The current shaping circuit 106 may be used for pull-up and pull-down, as Figure 4B shown, or combined with a pull-up / pull-down circuit on only one side, as Figure 4C and Figure 4D shown. In some embodiments, the system may include multiple gate drivers 104, and each of the multiple gate drivers 104 may include a different configuration or implementation of the current shaping circuit 106.

[0050] Figure 5A FIG. 10 is a diagram illustrating an example implementation of a current shaping circuit in one embodiment. In one embodiment, the current shaping circuit 106 may generate a curved shape for Igate by performing interpolation of two signal levels through the settling of an operational amplifier. In the example embodiment of Figure 5A , the current shaping circuit 106 may include voltage references V1 and V2, an operational amplifier 502, at least a resistor R, and a driver transistor M1. When the data input signal (DIN) is low, the driver transistor M1 may turn off (e.g., a transition from on to off). Initially, when DIN goes high (e.g., a transition from off to on), the current shaping circuit 106 may generate an output current of: I gate = V 1 / R. After a specific time, the switch 501 changes the non-inverting input of 502. Assuming this time point is "t = 0", then the output current is given by: I gate = A exp(-t / τ) + B, where A = (V 1 - V 2 ) / R, and B = V 2 / R. The waveform shape of Igate can be configured by parameters such as: V 1 , V 2 , R, τ. In one embodiment, the timing of t = 0 may be generated from DIN by a delay circuit. In another embodiment, the timing may be generated by the GATE voltage, i.e., a comparator may detect that the GATE voltage exceeds a threshold 108, where 108 starts to flow the switching current Ids. In another embodiment, the timing may be generated by current sensing described later.

[0051] Figure 5B FIG. Another exemplary implementation of the current shaping circuit in one embodiment is shown. In one embodiment, the current shaping circuit 106 may generate the curve shape of Igate by performing interpolation of two signal levels through the stabilization of an R-C circuit. The current shaping circuit 106 may include voltage references V1 and V2, a voltage-to-current converter 215, a switching circuit for changing the input voltage Vs of 215, and R-C components, as illustrated. The operation may be the same as that of Figure 5A the embodiment shown. At t = 0, Vs begins to change from V1 to V2, and C and the R placed between V2 and C define the stabilization time, which results in a curve shape of: V s = A exp(-t / τ) + B, where A = V 1 - V 2 , B = V 2 , τ = RC. In one embodiment, the output current Igate may be proportional to Vs. In other embodiments, Igate may be further modulated according to the transfer function of the voltage-to-current converter 215.

[0052] Figure 5C FIG. Another exemplary implementation of the current shaping circuit in one embodiment is shown. In one embodiment, the current shaping circuit 106 may generate the curve shape of Igate by performing interpolation of multiple signal levels through the stabilization of an R-C circuit. As illustrated, the current shaping circuit 106 may include voltage references V1, V2, etc., a voltage-to-current converter 215, a switching circuit for changing the input voltage Vs of the voltage-to-current converter 215, and R-C components. The operation may be the same as that of Figure 5B the embodiment in. By cascading multiple curves, a relatively complex curve shape may be generated, as illustrated.

[0053] Figure 5D FIG. Another exemplary implementation of the current shaping circuit in one embodiment is shown. Figure 5D The embodiment in may provide a relatively more complex or precise configuration in terms of curve shape by combining multiple current shaping circuits. Multiple segments 302 and 304 of the current shaping circuit (e.g., Figures 5A to 5C any embodiment in) may be implemented in the Figure 5D embodiment shown.

[0054] Figure 5E FIG. Another exemplary implementation of the current shaping circuit in one embodiment is shown. The current shaping circuit 106 may include a digital pattern generator 402 and a current digital-to-analog converter 404. The output current Igate may be configured to have any curve shape.

[0055] Figure 5F FIG. is a diagram showing another exemplary implementation of a current shaping circuit in an embodiment. The current shaping circuit 106 may include a digital pattern generator 402, a voltage-to-current converter 215, and a voltage digital-to-analog converter 404. The output current Igate may be configured to have any curve shape.

[0056] Figure 6A FIG. is a diagram showing an exemplary implementation of a voltage-to-current converter of a current shaping circuit that can be used in a gate driver in an embodiment. The current shaping circuit 106 may include various implementations of the voltage-to-current converter 215. In Figure 6A the example shown, the voltage-to-current converter 215 may include a high-speed operational amplifier 204, a MOSFET M1, and a resistor Rs (see Figure 5A M1 and R in). Note that the operational amplifier 204 may be configured to operate relatively faster than the operational amplifier 502. The output current is given by: I out = V in / R s . The voltage-to-current converter 215 may further include a switch S1 to quickly turn off M1.

[0057] Figure 6B FIG. is a diagram showing another exemplary implementation of a voltage-to-current converter of a current shaping circuit that can be used in a gate driver in an embodiment. In Figure 6B another example shown, the voltage-to-current converter 215 may include a MOSFET M1 and a resistor Rs. Additionally, the voltage-to-current converter 215 may further include a switch S1 to quickly turn off M1. The output current is given by: I out = (V in - V th ) / R s , where V th is the threshold voltage of M1.

[0058] Figure 6C FIG. is a diagram showing another exemplary implementation of a voltage-to-current converter of a current shaping circuit that can be used in a gate driver in an embodiment. In Figure 6C another example shown, the voltage-to-current converter 215 may include a MOSFET M1. Additionally, the voltage-to-current converter 215 may further include a switch S1 to quickly turn off M1. The output current is given by: I out = K(V in - V th ) 2 , where K is a parameter depending on M1.

[0059] Figure 7is a diagram showing different waveforms with different shapes due to the implementation of the current shaping circuit of the gate driver in one or more embodiments. In Figure 7 the waveform labeled Igate_simple is generated by the implementation of the embodiments in Figure 5A and Figure 5B The waveform labeled Iout1+Iout2 is generated by the implementation of the embodiments in Figure 5C which is closer to the ideal curve and better results can be expected, i.e., lower losses and lower ringing.

[0060] Figure 8A and Figure 8B are diagrams showing a system with adaptive control for gate current shaping in one or more embodiments. The shape of the gate current shaped by the current shaping circuit 106 can be but is not limited to any of the current shaping circuit implementations seen above. The system can also have feedback control from the sensing circuit 110. In Figure 8A the system can include a current sensor 112 and perform feedback by observing the slew rate of the current in the power switch 108. The sensing circuit 110 can configure the current shaping circuit 106 to keep the slew rate of the switch current constant during the transition. The sensing circuit 110 can know the slew rate of the current by calculating dI / dt. The sensing circuit 110 can also optimize the gate current shaping for better results. Moreover, the sensing current 110 can detect when the switch current starts to flow for the timing generation of the current shaping circuit 106. In Figure 8B the current sensor 112 can be implemented by an inductor 111. The inductor 111 is in series with the power switch 108. In one embodiment, the inductor 111 can have a stray inductance L of the current path from the power switch 108 to the sensing circuit 110. In another embodiment, the power switch 108 can include the inductor 111. The voltage at SNS is the slew rate of the switch current and is given by: SNS = -L dI / dt. The control method is the same as the implementation shown in Figure 8A

[0061] Figure 9A 、 Figure 9B and Figure 9C are diagrams showing different implementations of feedback control in one or more embodiments. In Figure 9A the waveform shape of the gate current Igate is ideal. In Figure 9B the waveform shape of the gate current Igate is relatively steep. In Figure 9C the waveform shape of the gate current Igate is relatively flat. SNS is Figure 8B ​The voltage shown. As illustrated by the dashed circle, the time or amplitude or subsequent ringing amplitude within the dashed circle can indicate whether the curve in the waveform shape of Igate is steep or flat. Thus, the system can optimize the curve by changing the parameters of the current shaping circuit 106, such as Figure 5A and Figure 5B "tau" in.

[0062] Figure 10 FIG. is a diagram showing an implementation using temperature estimation in one embodiment. Generally, the characteristics of the power switch 108 vary depending on its junction temperature TJ, i.e., the optimal gate current shape is slightly different from TJ. If the system is optimizing gate current shaping, the resulting gate current shape reflects TJ. Thus, TJ can be estimated from the gate current shape (i.e., the parameters of the current shaping circuit 106). TJ estimation can be used for safety purposes in the system.

[0063] Figure 11 FIG. illustrates a flowchart of a process for implementing gate current shaping of a gate driver in one embodiment. The process can include one or more operations, actions, or functions, as illustrated by one or more of block 1102 and / or block 1104. Although illustrated as discrete blocks, depending on the desired implementation, the various blocks can be divided into additional blocks, combined into fewer blocks, eliminated, executed in a different order, or executed in parallel.

[0064] Process 1100 can be performed by, for example, a driver (e.g., driver 104) and a waveform shaping circuit (e.g., circuit 106) described herein. Process 1100 can begin at block 1102. In block 1102, the gate driver can generate a gate current for driving the power switch. Process 1100 can proceed from block 1102 to block 1104. In block 1104, the gate driver can define the waveform shape of the gate current, wherein the defined waveform shape of the gate current causes the current of the switch to have a constant slew rate during the power switch transition.

[0065] In one embodiment, the gate driver can sense the current at the power switch and perform a feedback loop to optimize the waveform shape of the gate current based on the sensed current. In one embodiment, the gate driver can use the waveform shape of the gate current to estimate the junction temperature of the power switch.

[0066] In one embodiment, the gate driver can generate a digital signal including a digital pattern that represents the waveform shape of the gate current and convert the digital signal into an analog signal that defines the waveform shape of the gate current.

[0067] In one embodiment, the gate driver may output a gate current at a first amplitude. The gate driver may also switch an operational amplifier to output a gate current at a second amplitude. The operational amplifier may define the waveform shape of the gate current, and the waveform shape of the gate current depends on the settling speed of the operational amplifier.

[0068] In one embodiment, the gate driver may use at least one voltage source to generate a voltage and use a resistor-capacitor (RC) network to change the voltage generated by the voltage source, wherein the waveform shape of the gate current may be defined by the RC network.

[0069] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions that includes one or more executable instructions for implementing the specified (multiple) logical functions. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, in fact, two blocks shown in succession may be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by a system based on dedicated hardware that performs the specified functions or acts or a combination of dedicated hardware and computer instructions.

[0070] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the invention. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0071] All of the components or steps in the following claims, plus the corresponding structures, materials, acts, and equivalents of the functional elements (if any), are intended to include any structure, material, or act for performing the function in combination with other claimed elements specifically claimed. The disclosed embodiments of the present invention have been presented for purposes of illustration and description, but are not intended to be exhaustive or to limit the invention to the disclosed form. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described to best explain the principles of the invention and its practical application, and to enable others skilled in the art to understand the invention for various embodiments having various modifications suited to the particular use contemplated.

Claims

1. A semiconductor device, comprising: a driver circuit configured to drive the switch; as well as A circuit is configured to generate a gate current having a defined waveform shape at a transition of the switch, wherein the defined waveform shape of the gate current enables the current of the switch to have a constant slew rate during the transition of the switch.

2. The semiconductor device according to claim 1, wherein the circuit comprises: a pattern generator configured to generate a digital signal including a digital pattern, wherein the digital pattern represents the waveform shape of the gate current; as well as The digital-to-analog converter DAC is configured to convert the digital signal into an analog signal defining the waveform shape of the gate current.

3. The semiconductor device according to claim 1, wherein: The circuit includes an operational amplifier configured to output the gate current at a first amplitude; The circuit is configured to switch the operational amplifier to output the gate current at a second amplitude; The operational amplifier defines the waveform shape of the gate current; and The waveform shape of the gate current depends on the settling speed of the operational amplifier.

4. The semiconductor device according to claim 1, wherein the circuit comprises: at least one voltage source configured to generate a voltage; as well as A resistor-capacitor RC network includes at least one resistor and at least one capacitor, the RC network being configured to change the voltage generated by the voltage source, wherein the waveform shape of the gate current is defined by the RC network.

5. The semiconductor device according to claim 1, wherein the circuit is among a plurality of current waveform shaping circuits.

6. The semiconductor device according to claim 1, further comprising a sensing circuit configured to: sensing a current at the switch; and A feedback loop is implemented to optimize the waveform shape of the gate current based on the sensed current.

7. The semiconductor device according to claim 6, further comprising: A junction temperature circuit is configured to estimate a junction temperature of the switch using the waveform shape of the gate current.

8. A system comprising: at least one power switch; as well as The gate driver is configured as: driving the at least one power switch; A gate current having a defined waveform shape is generated at a transition of the at least one power switch, wherein the defined waveform shape of the gate current causes a current of the switch to have a constant slew rate during the transition of the at least one power switch.

9. The system of claim 8, further comprising a sensing circuit configured to: sensing a current at the at least one power switch; and A feedback loop is implemented to optimize the waveform shape of the gate current based on the sensed current.

10. The system according to claim 9, further comprising: A junction temperature circuit is configured to estimate a junction temperature of the at least one power switch using the waveform shape of the gate current.

11. The system of claim 8, wherein the gate driver comprises: a pattern generator configured to generate a digital signal including a digital pattern, wherein the digital pattern represents the waveform shape of the gate current; as well as The digital-to-analog converter DAC is configured to convert the digital signal into an analog signal defining the waveform shape of the gate current.

12. The system of claim 8, wherein: The gate driver includes an operational amplifier configured to output the gate current at a first amplitude; The gate driver is configured to switch the operational amplifier to output the gate current at a second amplitude; The operational amplifier defines the waveform shape of the gate current; and The waveform shape of the gate current depends on the settling speed of the operational amplifier.

13. The system of claim 8, wherein the gate driver comprises: at least one voltage source configured to generate a voltage; as well as A resistor-capacitor RC network includes at least one resistor and at least one capacitor, the RC network being configured to change the voltage generated by the voltage source, wherein the waveform shape of the gate current is defined by the RC network.

14. The system of claim 8, wherein the at least one power switch is among a plurality of power switches, and the gate driver comprises a plurality of current waveform shaping circuits.

15. A method for a gate driver, the method comprising: generating a gate current for driving a power switch; as well as At the transition of the switch, a waveform shape of the gate current is defined, wherein the defined waveform shape of the gate current enables the current of the power switch to have a constant slew rate during the transition of the power switch.

16. The method according to claim 15, further comprising: sensing a current at the power switch; as well as A feedback loop is implemented to optimize the waveform shape of the gate current based on the sensed current.

17. The method according to claim 16, further comprising: The junction temperature of the power switch is estimated using the waveform shape of the gate current.

18. The method according to claim 15, further comprising: generating a digital signal including a digital pattern, the digital pattern representing the waveform shape of the gate current; as well as The digital signal is converted into an analog signal that defines the waveform shape of the gate current.

19. The method according to claim 15, further comprising: outputting the gate current with a first amplitude; as well as The operational amplifier is switched to output the gate current at a second amplitude, wherein the operational amplifier defines the waveform shape of the gate current, and the waveform shape of the gate current depends on a settling speed of the operational amplifier.

20. The method of claim 15, further comprising: generating a voltage using at least one voltage source; as well as The voltage generated by the voltage source is varied using a resistor-capacitor (RC) network, wherein the waveform shape of the gate current is defined by the RC network.

Images