Circuit and method for reducing backward flow stress

Abstract

The invention provides a circuit and method for reducing backward flow stress, and the circuit comprises a function module which is used for reducing backward flow stress and comprises a first voltage generation unit, a second voltage generation unit, a primary side pulse width judgment unit and a synchronous rectification logic enabling unit. The output end of the first voltage generation unit and the output end of the second voltage generation unit are connected with the input end of the primary side pulse width judgment unit, and the output end of the primary side pulse width judgment unit is connected with the synchronous rectification logic enabling unit. Based on the soft start function of the primary side, the synchronous rectification is started when the pulse width of the primary side is maximum, the pulse width of the synchronous rectification at the starting moment is greatly reduced compared with the pulse width of the synchronous rectification at the starting stage, the backward current is remarkably reduced, meanwhile, the turn-off stress of the synchronous rectification MOS is remarkably reduced, and the system reliability is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of bridge topologies, and particularly relates to a circuit and method for reducing backflow stress. Background Art

[0002] In recent years, bridge topologies have been widely used in industries such as industrial, aerospace, and ordnance. In the application of bridge systems, synchronous rectification technology is generally adopted on the secondary side to improve the efficiency of the system. However, when a capacitive load is present or the system is quickly turned on and off, the output terminal has no time to discharge, and there will be a residual voltage on the output capacitor; and at this time, if the system starts working again and the synchronous rectification is turned on, reverse flow of the secondary side current will occur, damaging the synchronous rectifier tube.

[0003] A bridge power control system generally outputs drive signals for the primary side and drive signals for synchronous rectification. To ensure the optimal system efficiency, the drive signal for synchronous rectification can be regarded as complementary to the corresponding drive signal for the primary side. During the startup process, due to the presence of a soft-start circuit, the switching pulse width of the primary-side power switch tube on the half-bridge gradually increases. When it is just turned on, since the pulse width of the primary-side duty cycle is very small, it will cause the synchronous rectification to conduct for a long time; if there is still a residual voltage at the output, the output capacitor will discharge to the ground through the synchronous rectifier tube, resulting in a large negative current; and when a cycle ends and the synchronous rectifier tube is turned off, a high stress will appear at the source-drain terminal of this tube.

[0004] In existing systems, there are few solutions to this application problem. The optimization solutions on the market mostly involve adding PIN pins, designing complex logic detection circuits or anti-backflow circuits. Similar solutions increase the packaging cost and the design difficulty; each system design requires separate design of delay parameters, increasing the difficulty in application. Summary of the Invention

[0005] In order to solve the problems of the existing technology, the technical solution adopted by the present invention is: A circuit for reducing backflow stress, the circuit comprising: a functional module for reducing backflow stress; The functional module for reducing backflow stress comprises: a first voltage generation unit, a second voltage generation unit, a primary-side pulse width determination unit, and a synchronous rectification logic enabling unit.

[0006] Preferably, the output ends of the first voltage generation unit and the second voltage generation unit are respectively connected to the first and second input ends of the primary-side pulse width determination unit, and the output end of the primary-side pulse width determination unit is connected to the synchronous rectification logic enabling unit.

[0007] Preferably, the first voltage generation unit is used to generate a soft-start voltage.

[0008] Preferably, the first voltage generating unit includes a current source and a capacitor. Preferably, the soft start voltage is generated by charging the capacitor with the current source.

[0009] Preferably, the positive pole of the current source is connected to the power supply, and the negative pole is connected to the ground through the capacitor.

[0010] Preferably, the second voltage generating unit is used to generate a feedback voltage.

[0011] Preferably, the feedback voltage is generated by the current passing through an internal resistor in the feedback loop.

[0012] Preferably, the primary side pulse width determination unit includes a wide-swing high-precision comparator.

[0013] Preferably, the non-inverting input terminal of the wide-swing high-precision comparator is the soft start voltage, the inverting input terminal is the feedback voltage, and the output terminal is connected to the synchronous rectification logic enabling unit.

[0014] The present invention also discloses a method for reducing the reverse injection stress, including: After the half-bridge system is powered on, the system determines whether each protection logic is triggered. When any one of the protection logics is triggered, the synchronous rectification logic driving module does not work; When none of the protection logics is triggered, the soft start module starts soft start, the half-bridge system starts to work, and the pulse width of the primary side gate drive signal output gradually increases from the minimum value. At this time, the synchronous rectification logic driving module is not turned on temporarily; The multiplexed soft start module is used to generate a soft start voltage and determine whether the pulse width of the primary side gate drive signal output reaches the maximum value. When the maximum value is not reached, the synchronous rectification enabling signal is continuously pulled low, and the synchronous rectification logic driving module is not turned on; When the pulse width of the primary side gate drive signal output reaches the maximum value, the synchronous rectification enabling signal flips to high, and the synchronous rectification logic driving module is turned on; Since the pulse width of the primary side gate drive signal output reaches the maximum value at this time, the pulse width of the synchronous rectification is significantly reduced compared with when the system is just powered on, and the reverse injection current and the turn-off stress of the MOSFET of the synchronous rectification are significantly reduced.

[0015] The technical advantages of the present invention are as follows: The present invention proposes an optimized circuit for reverse injection stress for a half-bridge circuit. Based on the soft start function on the primary side, the synchronous rectification is turned on when the primary side pulse width is the largest. The pulse width of the synchronous rectification at the turn-on moment is significantly reduced compared with the initial startup stage of the system. The reverse injection current is significantly reduced, and at the same time, the turn-off stress of the synchronous rectification MOS is significantly reduced, improving the system reliability. Brief Description of the Drawings

[0016] Figure 1Block diagram of a half-bridge synchronous rectification PWM control system in an embodiment of the present invention; Figure 2 Flowchart of the functional module for reducing the reverse flow stress in an embodiment of the present invention; Figure 3 Structural diagram of the functional module for reducing the reverse flow stress in an embodiment of the present invention; Figure 4 Implementation circuit diagram of the primary pulse width unit and the synchronous rectification logic enabling unit in an embodiment of the present invention; Figure 5 Existing simulation waveform diagram in an embodiment of the present invention; Figure 6 Simulation waveform diagram of this solution in an embodiment of the present invention. Detailed implementation manner

[0017] The following will refer to the attached Figures 1 to 6 The specific embodiments of the present invention will be described in detail. Although the specific embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0018] It should be noted that certain terms are used in the specification and claims to refer to specific components. Those skilled in the art should understand that technicians may use different terms to refer to the same component. The specification and claims do not use the difference in terms as a way to distinguish components, but use the difference in the functions of components as the criterion for distinction. As mentioned throughout the specification and claims, "comprising" or "including" is an open-ended term and should be interpreted as "including but not limited to". The subsequent description of the specification is the preferred implementation manner for implementing the present invention, but the description is for the general purpose of the specification and is not intended to limit the scope of the present invention. The scope of protection of the present invention shall be defined by the appended claims.

[0019] For the convenience of understanding the embodiments of the present invention, the following will further explain with specific embodiments as examples in conjunction with the drawings, and each drawing does not constitute a limitation to the embodiments of the present invention.

[0020] The present invention provides a circuit and method for reducing the reverse flow stress. The circuit includes: a functional module for reducing the reverse flow stress; The functional module for reducing the reverse flow stress includes: a first voltage generation unit, a second generation unit, a primary pulse width determination unit, and a synchronous rectification logic enabling unit.

[0021] Preferably, the output terminals of the first voltage generating unit and the second voltage generating unit are connected to the input terminal of the primary-side pulse width judging unit, and the output terminal of the primary-side pulse width judging unit is connected to the synchronous rectification logic enabling unit.

[0022] Preferably, the first voltage generating unit is used to generate a soft start voltage.

[0023] Preferably, the soft start voltage is generated by charging a capacitor with a current source.

[0024] Preferably, the positive electrode of the current source is connected to the power supply, and the negative electrode is connected to the ground through a capacitor.

[0025] Preferably, the second voltage generating unit is used to generate a feedback voltage.

[0026] Preferably, the feedback voltage is generated by the current generated by the feedback loop passing through a resistor.

[0027] Preferably, the primary-side pulse width judging unit includes a wide-swing high-precision comparator.

[0028] Preferably, the non-inverting input terminal of the wide-swing high-precision comparator is the soft start voltage, the inverting input terminal is the feedback voltage, and the output terminal is connected to the synchronous rectification logic enabling unit.

[0029] In one embodiment, as Figure 1As shown in the figure, the half-bridge control chip includes: a power supply pin VCC, an UVLO pin, a soft start pin SS, a ground pin GND, a primary side gate drive high-side output pin HO, a primary side gate drive low-side output pin LO, a synchronous rectification high-side output pin SR1, a synchronous rectification low-side output pin SR2, and a feedback pin COMP. Inside the chip, there are an LDO module, a protection logic module, a PWM logic module, a soft start module, a primary side logic drive module, and a synchronous rectification logic drive module. The LDO module is mainly used to provide a reference voltage for the inside of the chip. Its input terminal is connected to the VCC pin of the chip, and its output terminal is connected to the protection logic module. The protection logic module is mainly used to identify the external conditions of the system and make the chip stop working when external conditions that may cause chip failure occur. The protection logic includes undervoltage protection, overvoltage protection, short-circuit protection, over-temperature protection, etc. The input terminal of the protection logic module is connected to the UVLO pin of the system, and its output terminal is connected to the PWM logic module. The output terminals of the PWM logic module are respectively connected to the primary side logic drive module and the synchronous rectification logic drive module. The PWM logic module is mainly used for pulse width modulation of the primary and secondary side drive signals and includes a primary side pulse width judgment unit inside. The soft start module is used to make the output voltage slowly reach the steady state at the initial stage of the half-bridge system startup. Its input terminal is connected to the SS pin, and its output terminal is connected to the PWM logic module. It includes a soft start voltage generation unit inside. The primary side logic drive module is used to output drive signals for HO and LO according to the PWM pulse width signal. The output terminals are respectively connected to the HO and LO pins of the chip. The synchronous rectification logic drive module is used to output drive signals for SR1 and SR2 according to the PWM pulse width signal. The output terminals are respectively connected to the SR1 and SR2 pins of the chip and include a synchronous rectification logic enable unit inside.

[0030] Working principle: Figure 1M1 and M2 in it are respectively the upper-bridge-arm tube and the lower-bridge-arm tube in the half-bridge system. When there is residual voltage at the output end of the half-bridge system, the half-bridge system restarts, the synchronous rectifier tubes M3 and M4 are turned on, and the secondary side VOUT of the half-bridge system discharges rapidly through synchronous rectification, forming a reverse current from the output to the ground; the magnitude of the total reverse current is positively correlated with the pulse width at the synchronous rectification starting moment. If the pulse width at the synchronous rectification starting moment is smaller, the generated reverse current is also smaller. Since the drive signal of the synchronous rectification of this half-bridge system is complementary to the corresponding primary-side drive signal, at the beginning of soft start, the duty cycle of the synchronous rectification pulse width almost reaches 100%, forming a huge reverse current. The reverse current may cause the power MOSFET device to bear a current exceeding its rated value, and the stress generated at the source-drain level when the MOSFET is turned off may cause the MOS to overheat or even be permanently damaged; therefore, synchronous rectification is turned on when the primary-side pulse width is the largest. The pulse width of synchronous rectification at the starting moment is significantly reduced compared with the just-started stage of the machine, the reverse current is significantly reduced, and at the same time, the turn-off stress of the synchronous rectification MOS is significantly reduced, improving the system reliability.

[0031] The present invention designs a wide-swing high-precision comparator, reuses the soft start module to generate a soft start voltage, detects the magnitude of the primary-side pulse width, turns on synchronous rectification when the primary-side pulse width is the largest to reduce the reverse current, and at the same time designs an enable signal for the synchronous rectification signal, and makes this signal have the effects of anti-interference and anti-mis-triggering.

[0032] In another embodiment, as Figure 2 shown, connect the VCC voltage, and the half-bridge system starts to power on. The chip first judges whether each protection logic is triggered. When any one of the protection logics is triggered, the protection logic module outputs a high level. There are many protections in the chip, such as undervoltage protection, overvoltage protection, short-circuit protection, over-temperature protection, etc. When any one of them is triggered, the protection logic outputs a high level, and both the primary-side logic drive module and the synchronous rectification logic drive module output low levels. When none of the protection logics is triggered, soft start begins, the half-bridge system starts to work, and the pulse widths of the primary-side gate drive signals HO and LO (primary-side pulse width) gradually increase from the minimum value. At the same time, the soft start module is reused to generate a soft start voltage to judge whether the primary-side pulse width reaches the maximum value. When the primary-side pulse width does not reach the maximum value, the synchronous rectification enable signal remains low, and the synchronous rectification logic drive module is not turned on; when it is judged that the primary-side pulse width reaches the maximum value, the synchronous rectification enable signal is high, the PWM logic module normally outputs the synchronous rectification logic signal, and the drive signals of SR1 and SR2 are output through the synchronous rectification logic drive module, and the synchronous rectifier tubes M3 and M4 start to work normally. At this time, since the primary-side pulse width reaches the maximum value, the pulse width of synchronous rectification is significantly reduced compared with when the machine is just started, and the reverse current and the turn-off stress of the synchronous rectification MOSFET are significantly reduced.

[0033] In another embodiment, asFigure 3 As shown, the functional module for reducing the backflow stress includes a soft-start voltage generation unit, a feedback modulation unit, a primary-side pulse width determination unit, and a synchronous rectification logic enabling unit. The output terminals of the soft-start voltage generation unit and the feedback modulation unit are connected to the input terminal of the primary-side pulse width determination unit, and the output terminal of the primary-side pulse width determination unit is connected to the synchronous rectification logic enabling unit. The soft-start voltage generation unit includes a current source I1 and a capacitor C1. The primary-side pulse width determination unit includes a comparator U1 with a wide swing and high precision. The synchronous rectification logic enabling unit includes an RS flip-flop U2. The feedback modulation unit includes a resistor R1 and an optocoupler. The feedback modulation unit is mainly used to modulate the output voltage into the voltage Vopto input to the optocoupler. The optocoupler can be of models such as 4N25, 4N35, 6N137, HCPL-2631, etc.

[0034] Furthermore, the soft-start voltage is generated by charging the external capacitor C1 with the internal current source I1. The positive terminal of the internal current source I1 is connected to the reference voltage Vdd, which is obtained by converting the input VCC voltage of the system through the LDO module. The negative terminal is connected to the ground through the capacitor C1. The feedback compensation voltage Vcomp is generated by stepping down the current generated by the feedback loop through the internal resistor R1. The first terminal of the resistor R1 is connected to the reference voltage Vdd, and the second terminal is connected to the COMP pin of the system. The first terminal of the optocoupler is connected to the voltage Vopto, where Vopto is obtained by dividing and modulating the system output voltage VOUT through the feedback loop, and the second terminal is connected to the ground. The primary-side pulse width determination unit includes a comparator with a wide swing and high precision. The non-inverting input terminal of the comparator with a wide swing and high precision is the soft-start voltage Vss, the inverting input terminal is the feedback compensation voltage Vcomp, and the output terminal is connected to the synchronous rectification logic enabling unit. The synchronous rectification logic enabling unit includes an RS flip-flop. The flip-flop outputs the SR_EN signal (synchronous rectification enabling signal) to control the synchronous rectification logic drive module and enable synchronous rectification. When the SR_EN is at a high level, it indicates that the synchronous rectification function is allowed to work; when the SR_EN is at a low level, it indicates that the synchronous rectification function is prohibited.

[0035] In another embodiment, Figure 4Provide an implementation circuit for a primary-side pulse-width determination unit and a synchronous rectification logic enabling unit. The primary-side pulse-width determination unit includes a wide-swing high-precision comparator. The wide-swing high-precision comparator includes P-type MOS transistors (PMOS transistors) MP1 - MP11, N-type MOS transistors (NMOS transistors) MN1 - MN14. The sources of MP1 - MP7 and MP10 are all connected to the reference voltage Vdd. The gate and drain of MP1 are shorted and then connected to the gates of MP2, MP3, MP4, MP5, MP6, and MP7. The drain of MP1 is connected to the drain of MN2. The drain of MP2 is connected to the sources of MP8 and MP9. The drain of MP8 is connected to the source of MN8. The drain of MP9 and the source of MN9 are connected. The gates of MP9 and MN6 are connected. The gates of MP8, MN7, and MN13 are connected to the drain of MN13. The drain of MP3 is connected to the drain of MN6. The drain of MP4 is connected to the drain of MN7. The sources of MN6 and MN7 are both connected to the drain of MN3. The gate and drain of MP10 are shorted and then connected to the gates of MP11 and MP12. The drain of MP10 is connected to the drain of MN4. The drain of MP5 and the source of MP11 are connected. The drain of MP11 and the drain of MN8 are connected. The source of MN8 and the drain of MN10 are connected. The drain of MP6 and the source of MP12 are connected. The drain of MP12 and the drain of MN9 are connected. The source of MN9 and the drain of MN11 are connected. The drain of MN12 is connected to the reference voltage Vdd. The source of MN12 is connected to the drain of MN5. The drain of MN13 is connected to the COMP pin of the system. The gates of MN13 and MN14 are connected to the source of MN12. The drain of MP7 is connected to the drain of MN14. The sources of MN1, MN2, MN3, MN4, MN10, MN11, MN5, MN13, and MN14 are all connected to the GND pin. The drain of MN1 is connected to a bias current source. The drain and gate of MN1 are shorted and then connected to the gates of MN2, MN3, MN4, and MN5; The synchronous rectification logic enabling unit includes a Schmidt trigger U3 and an RS flip-flop composed of a logic NOR gate. The input terminal of the Schmidt trigger U3 is connected to the drains of MP7 and MN14. The output terminal is connected to the input terminal of the RS flip-flop composed of U4 and U5. The output terminal of the RS flip-flop outputs the SR_EN signal to enable synchronous rectification.

[0036] Among them, MN1, MN2, MN3, MN4, and MN5 are all 5V NMOS transistors, forming an N-channel current mirror; MN6 and MN7 are both 5V NMOS transistors, forming a differential input pair; MN8, MN9, MN10, and MN11 are all 5V NMOS transistors, forming an active load; MN12 is a 5V NMOS transistor and is used as a source follower; MN13 and MN14 are both 5V NMOS transistors. MN14 is the current sampling transistor for MN13.

[0037] MP1, MP2, MP3, MP4, MP5, MP6, and MP7 are all 5V PMOS transistors and form a P - transistor current mirror; MP8 and MP9 are both 5V NMOS transistors and form a differential input pair; MP10, MP11, and MP12 are all 5V PMOS transistors. MP10 provides the gate bias, and MP11 and MP12 form a common - gate amplifier; Vss: The voltage of the SS PIN; Vcomp: The feedback compensation voltage.

[0038] Circuit working principle: The primary pulse width of the PWM is determined by the smaller value between the feedback compensation voltage Vcomp and the soft - start voltage Vss. When the system just starts, the feedback compensation voltage Vcomp is 5V, and the soft - start voltage Vss starts to increase from 0. The MN13 transistor in the comparator module turns on, clamping the feedback compensation voltage to the voltage of the SS pin. At this time, the primary pulse width is determined by the voltage Vss. As Vss increases, the primary pulse width gradually increases, and the output voltage gradually builds up; when the output voltage builds up to the set output voltage, the feedback compensation voltage Vcomp starts to decrease from 5V; when the output voltage is high enough at a certain moment, the feedback compensation voltage Vcomp will be lower than the soft - start voltage Vss, the MOS transistor MN13 turns off, the sampling current of MN14 is 0A, and the feedback compensation voltage Vcomp is no longer clamped, and its voltage value is determined by the feedback loop and the half - bridge system. From this moment on, the primary pulse width is determined by the feedback compensation voltage Vcomp and starts to gradually decrease as the Vcomp voltage decreases. This is the moment when the primary pulse width is the largest during the startup phase. The input of the Schmidt trigger U3 is at a high level, the SR_EN enable signal flips to a high level and is latched by the RS flip - flop, and the synchronous rectifier transistors M3 and M4 start to work normally. Since the primary pulse width is the largest at this moment, the pulse width of the synchronous rectification is the smallest, effectively suppressing the reverse current and reducing the turn - off stress of the synchronous rectifier transistors M3 and M4.

[0039] In another embodiment, Figure 3 The circuit shown can be implemented in one chip. The specific connection method is as Figure 1 shown, without additional PINs and without the need to design complex logic circuits additionally, simplifying the design and reducing the cost.

[0040] Figure 5The simulation waveform without using the reverse current optimization in the existing solution. The specific parameters of the used simulation system are as follows: input voltage is 48V, output voltage is 3.3V; output current range is 0 - 15A, transformer turns ratio is 4:1, and the switching frequency of the system is 200kHz. Figure 5 In the figure, the horizontal axis represents time, and the vertical axes represent voltage and current respectively. The blue waveform is the curve of the output voltage changing with time, the green one is the curve of the secondary side current changing with time, and the pink one is the curve of the stress of the secondary side synchronous rectifier SR1 changing with time (the two paths on the secondary side are symmetrical). It can be seen from the simulation diagram that when the residual voltage is 3V, the maximum value of the reverse current reaches 32A, and the maximum value of the stress of the synchronous rectifier MOS transistor is 37V. When the voltage borne by the MOS transistor exceeds its maximum rated voltage, it may cause a breakdown phenomenon, damaging the insulating layer inside the device. This kind of damage is usually irreversible and will cause the MOS transistor to fail permanently.

[0041] Figure 6 The simulation waveform obtained by using the solution of the present invention. In the figure, the horizontal axis represents time, and the vertical axes represent voltage and current respectively. The blue waveform is the curve of the output voltage changing with time, the green one is the curve of the secondary side current changing with time, and the pink one is the curve of the stress of the secondary side synchronous rectifier SR1 changing with time. It can be seen from the figure that by using the optimized circuit of the present invention, under the same working conditions and circuit parameters, the synchronous rectification is turned on when the primary side pulse width is detected to be the maximum. When the residual voltage is 3V, the maximum reverse current is 10A, and the maximum stress of the synchronous rectifier MOS is 20V, protecting the synchronous rectifier MOS transistor from being damaged.

[0042] The above general description of the invention involved in the present invention and the description of its specific implementation manners should not be construed as a limitation to the technical solution of the invention. Those skilled in the art can, based on the content disclosed by the present invention, without violating the constituent elements of the involved invention, add, subtract, or combine the technical features of the invention in the above general description or / and specific implementation manners (including embodiments) to form other technical solutions within the protection scope of the present invention.

Claims

1. A circuit for reducing backflow stress, characterized in that: The circuit comprises: a functional module for reducing backflow stress; The functional module for reducing backflow stress includes: a first voltage generating unit, a second voltage generating unit, a primary pulse width judging unit and a synchronous rectification logic enabling unit.

2. The circuit according to claim 1, characterized in that Preferably, the output ends of the first voltage generating unit and the second voltage generating unit are respectively connected to the first and second input ends of the primary pulse width judging unit, and the output end of the primary pulse width judging unit is connected to the synchronous rectification logic enabling unit.

3. The circuit according to claim 1, characterized in that The first voltage generating unit is used to generate a soft start voltage.

4. The circuit according to claim 3, characterized in that The first voltage generating unit includes a current source and a capacitor.

5. The circuit according to claim 4, characterized in that The soft start voltage is generated by a current source charging a capacitor.

6. The circuit according to claim 5, characterized in that The positive electrode of the current source is connected to the power supply, and the negative electrode is connected to the ground through the capacitor.

7. The circuit according to claim 3, characterized in that The second voltage generating unit is used to generate a feedback voltage.

8. The circuit according to claim 7, characterized in that The primary pulse width judgment unit includes a wide swing high precision comparator.

9. The circuit according to claim 8, characterized in that The non-inverting input terminal of the wide swing high-precision comparator is a soft start voltage, the inverting input terminal is a feedback voltage, and the output terminal is connected to a synchronous rectification logic enable unit.

10. A method for reducing backflow stress, comprising: After the half-bridge system is powered on, the system determines whether each protection logic is triggered. When any of the protection logics is triggered, the synchronous rectification logic drive module does not work; When all protection logics are not triggered, the soft start module starts soft start, the half-bridge system starts working, and the output pulse width of the primary gate drive signal gradually increases from the minimum value. At this time, the synchronous rectification logic drive module is temporarily not turned on; The multiplexing soft start module is used to generate a soft start voltage and determine whether the output pulse width of the primary gate drive signal has reached the maximum value. If it has not reached the maximum value, the synchronous rectification enable signal is continuously pulled low and the synchronous rectification logic drive module is not turned on. When the output pulse width of the primary gate drive signal reaches its maximum value, the synchronous rectification enable signal flips to high, and the synchronous rectification logic drive module is turned on; since the output pulse width of the primary gate drive signal reaches its maximum value at this time, the pulse width of the synchronous rectification is greatly reduced compared to when the power is just turned on, and the backflow current and the MOSFET turn-off stress of the synchronous rectification are significantly reduced.

Images