Doherty amplifier circuit and semiconductor device

Abstract

The invention provides a Doherty amplifier circuit and a semiconductor device. A Doherty amplifier circuit is provided with: a distributor that distributes an input signal that is input into a first signal, a second signal, and a third signal; the main amplifier is used for amplifying the first signal and outputting the amplified signal as a fourth signal; the first peak amplifier is used for amplifying the second signal and outputting the amplified signal as a fifth signal; the second peak amplifier is used for amplifying the third signal and outputting the amplified signal as a sixth signal; the synthesizer is used for synthesizing the fourth signal, the fifth signal and the sixth signal and outputting the synthesized signal to an output terminal as an output signal; and a semiconductor chip on which a main amplifier, a first peaking amplifier, and a second peaking amplifier are mounted, the input power of the input signal to which the second peaking amplifier is turned on being greater than the input power of the input signal to which the first peaking amplifier is turned on, and the main amplifier is adjacent to the first peaking amplifier.

Description

Technical Field

[0001] The present invention relates to a Doherty amplifier circuit and a semiconductor device. Background Art

[0002] There is known an N-way (N is 3 or more) Doherty amplifier circuit that uses a main amplifier and two or more peak amplifiers (for example, Patent Document 1, Patent Document 2). There is known a technique of providing a main amplifier and a peak amplifier on the same semiconductor chip (for example, Patent Document 3).

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: US Patent No. 8022760 Specification

[0006] Patent Document 2: US Patent No. 10601375 Specification

[0007] Patent Document 3: International Publication No. 2023 / 187921

[0008] When the difference in characteristics such as parasitic capacitance between the main amplifier and the multiple peak amplifiers is large, the phase between the amplifiers deviates from the desired difference, and characteristics such as gain deteriorate. In an N-way (N is 3 or more) Doherty amplifier circuit, it is unknown how to arrange the main amplifier and the multiple peak amplifiers to improve the characteristics. Summary of the Invention

[0009] An object of the present disclosure is to suppress deterioration of characteristics.

[0010] One embodiment of the present disclosure is a Doherty amplifier circuit including: a distributor that distributes an input signal input thereto into a first signal, a second signal, and a third signal; a main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal; a first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal; a second peak amplifier that amplifies the third signal and outputs the amplified signal as a sixth signal; a combiner that combines the fourth signal, the fifth signal, and the sixth signal and outputs the combined signal as an output signal to an output terminal; and a semiconductor chip on which the main amplifier, the first peak amplifier, and the second peak amplifier are mounted, wherein an input power of the input signal for turning on the second peak amplifier is greater than an input power of the input signal for turning on the first peak amplifier, and the main amplifier is adjacent to the first peak amplifier.

[0011] One embodiment of the present disclosure is a Doherty amplifier circuit, comprising: a distributor that distributes an input signal into a first signal, a second signal, and a third signal; a main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal; a first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal; a second peak amplifier that amplifies the third signal and outputs the amplified signal as a sixth signal; a combiner that combines the fourth signal, the fifth signal, and the sixth signal and outputs the combined signal as an output signal to an output terminal; a first semiconductor chip on which the main amplifier and the first peak amplifier are mounted; and a second semiconductor chip on which the second peak amplifier is mounted, the second semiconductor chip being a chip different from the first semiconductor chip, and the input power of the input signal for turning on the second peak amplifier being greater than the input power of the input signal for turning on the first peak amplifier.

[0012] One embodiment of the present disclosure is a semiconductor device for a Doherty amplifier circuit, comprising: a main amplifier that amplifies a first signal obtained by distributing an input signal and outputs the amplified signal as a fourth signal; a first peak amplifier that amplifies a second signal obtained by distributing the input signal and outputs the amplified signal as a fifth signal; a second peak amplifier that amplifies a third signal obtained by distributing the input signal and outputs the amplified signal as a sixth signal; and a semiconductor chip on which the main amplifier, the first peak amplifier, and the second peak amplifier are mounted, the input power of the input signal for turning on the second peak amplifier being greater than the input power of the input signal for turning on the first peak amplifier, and the main amplifier being adjacent to the first peak amplifier.

[0013] One embodiment of the present disclosure is a semiconductor device for a Doherty amplifier circuit, comprising: a main amplifier that amplifies a first signal obtained by distributing an input signal and outputs the amplified signal as a fourth signal; a first peak amplifier that amplifies a second signal obtained by distributing the input signal and outputs the amplified signal as a fifth signal; a second peak amplifier that amplifies a third signal obtained by distributing the input signal and outputs the amplified signal as a sixth signal; a first semiconductor chip on which the main amplifier and the first peak amplifier are mounted; and a second semiconductor chip on which the second peak amplifier is mounted, the second semiconductor chip being a chip different from the first semiconductor chip, and the input power of the input signal for turning on the second peak amplifier being greater than the input power of the input signal for turning on the first peak amplifier.

[0014] Effect of the Invention

[0015] According to the present disclosure, deterioration of characteristics can be suppressed. Description of the Drawings

[0016] Figure 1 It is a block diagram of the Doherty amplifier circuit of Embodiment 1.

[0017] Figure 2 It is a top view of the semiconductor device of Embodiment 1.

[0018] Figure 3 It is a cross-sectional view of the semiconductor chip of Embodiment 1.

[0019] Figure 4 It is a schematic diagram showing the probability with respect to Pout, the Pout of each amplifier with respect to Pin, the gain of each amplifier with respect to Pin, and the overall gain with respect to Pin in Embodiment 1.

[0020] Figure 5 It is a top view of the semiconductor device of Comparative Example 1.

[0021] Figure 6 It is a top view of the semiconductor device of Embodiment 2.

[0022] Description of Reference Numerals:

[0023] 10: Main amplifier;

[0024] 12 (first peak amplifier), 14 (second peak amplifier): Peak amplifiers;

[0025] 16: Divider;

[0026] 18: Combiner;

[0027] 20, 20a (first semiconductor chip), 20b, 20c (second semiconductor chip): Semiconductor chips;

[0028] 21, 21a, 21b, 21c: Substrates;

[0029] 22a (first input pad), 22b (second input pad), 22c (third input pad), 23a (first output pad), 23b (second output pad), 23c (third output pad): Pads;

[0030] 24a, 24b, 24c: Capacitive components;

[0031] 25: Dielectric substrate;

[0032] 26: Electrode;

[0033] 27a, 27b, 27c, 28a, 28b, 28c: Lead wires;

[0034] 30, 31, 32, 33, 34, 35: Matching circuits;

[0035] 36, 37, 38, 39: Bias circuits;

[0036] 40a: Substrate;

[0037] 40b: Semiconductor layer;

[0038] 41a, 41b, 41c: Source electrodes;

[0039] 42a, 42b, 42c: Gate electrodes;

[0040] 43a, 43b, 43c: Drain electrodes;

[0041] 44, 44a, 44b: Passive regions;

[0042] 45a, 45b, 45c: Active regions;

[0043] 46, 47, 48: Bonding wires;

[0044] 49: Insulating layer;

[0045] 50: Package;

[0046] 51: Substrate;

[0047] 100: Doherty amplifier circuit;

[0048] 102, 104, 110: Semiconductor devices;

[0049] S1 (First signal), S2 (Second signal), S3 (Third signal), S4 (Fourth signal), S5 (Fifth signal), S6 (Sixth signal): Signals;

[0050] Sin: Input signal;

[0051] Sout: Output signal;

[0052] Tin: Input terminal;

[0053] Tout: Output terminal;

[0054] G (Input terminal): Gate;

[0055] D (Output terminal): Drain. Detailed implementation manners

[0056] [Description of embodiments of the present disclosure]

[0057] First, the content of the embodiments of the present disclosure will be described by way of example.

[0058] (1) One embodiment of the present disclosure is a Doherty amplifier circuit, comprising: a distributor that distributes an input signal input thereto into a first signal, a second signal, and a third signal; a main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal; a first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal; a second peak amplifier that amplifies the third signal and outputs the amplified signal as a sixth signal; a synthesizer that synthesizes the fourth signal, the fifth signal, and the sixth signal and outputs the synthesized signal as an output signal to an output terminal; and a semiconductor chip on which the main amplifier, the first peak amplifier, and the second peak amplifier are mounted, wherein the input power of the input signal for turning on the second peak amplifier is greater than the input power of the input signal for turning on the first peak amplifier, and the main amplifier is adjacent to the first peak amplifier. Thereby, the difference in parasitic capacitance or the like between the main amplifier and the first peak amplifier can be reduced. Therefore, the phases of the fourth signal and the fifth signal can be matched, and thus the deterioration of characteristics can be suppressed.

[0059] (2) In the above (1), it may also be that the first peak amplifier is provided between the main amplifier and the second peak amplifier. Thereby, the deterioration of characteristics can be further suppressed.

[0060] (3) In the above (1) or (2), it may also be that the main amplifier and the first peak amplifier are adjacent in a first direction, and the distance between the main amplifier and the first peak amplifier is less than the width of the main amplifier in the first direction and also less than the width of the first peak amplifier in the first direction. Thereby, the deterioration of characteristics can be further suppressed.

[0061] (4) In any one of the above (1) to (3), it may also be that the Doherty amplifier circuit comprises: a first input pad provided on the semiconductor chip and electrically connected to an input terminal of the main amplifier; a second input pad provided on the semiconductor chip and electrically connected to an input terminal of the first peak amplifier; a third input pad provided on the semiconductor chip and electrically connected to an input terminal of the second peak amplifier; a first output pad provided on the semiconductor chip and electrically connected to an output terminal of the main amplifier; a second output pad provided on the semiconductor chip and electrically connected to an output terminal of the first peak amplifier; and a third output pad provided on the semiconductor chip and electrically connected to an output terminal of the second peak amplifier. Thereby, the main amplifier, the first peak amplifier, and the second peak amplifier can be electrically connected to the outside.

[0062] (5) In the above (4), it may also be that the main amplifier, the first peak amplifier, and the second peak amplifier are arranged in a first direction, the main amplifier is disposed between the first input pad and the first output pad in a second direction intersecting the first direction, the first peak amplifier is disposed between the second input pad and the second output pad in the second direction, and the second peak amplifier is disposed between the third input pad and the third output pad in the second direction. Thus, the main amplifier and the first peak amplifier can be made adjacent to each other.

[0063] (6) In any one of the above (1) to (5), it may also be that no passive element is provided on the semiconductor chip. Thus, the main amplifier and the first peak amplifier can be made adjacent to each other, and the first peak amplifier and the second peak amplifier can be made adjacent to each other.

[0064] (7) One embodiment of the present disclosure is a Doherty amplifier circuit, comprising: a splitter that splits an input signal input thereto into a first signal, a second signal, and a third signal; a main amplifier that amplifies the first signal and outputs the amplified signal as a fourth signal; a first peak amplifier that amplifies the second signal and outputs the amplified signal as a fifth signal; a second peak amplifier that amplifies the third signal and outputs the amplified signal as a sixth signal; a combiner that combines the fourth signal, the fifth signal, and the sixth signal and outputs the combined signal as an output signal to an output terminal; a first semiconductor chip on which the main amplifier and the first peak amplifier are mounted; and a second semiconductor chip on which the second peak amplifier is mounted, the second semiconductor chip being a chip different from the first semiconductor chip, and the input power of the input signal for turning on the second peak amplifier being greater than the input power of the input signal for turning on the first peak amplifier. Thus, deterioration of characteristics can be suppressed and the yield can be improved.

[0065] (8)One embodiment of the present disclosure is a semiconductor device for a Doherty amplifier circuit, comprising: a main amplifier that amplifies a first signal obtained by distributing an input signal and outputs the amplified signal as a fourth signal; a first peak amplifier that amplifies a second signal obtained by distributing the input signal and outputs the amplified signal as a fifth signal; a second peak amplifier that amplifies a third signal obtained by distributing the input signal and outputs the amplified signal as a sixth signal; and a semiconductor chip on which the main amplifier, the first peak amplifier, and the second peak amplifier are mounted, wherein the input power of the input signal for turning on the second peak amplifier is greater than the input power of the input signal for turning on the first peak amplifier, and the main amplifier is adjacent to the first peak amplifier. Thus, deterioration of characteristics can be suppressed.

[0066] (9)One embodiment of the present disclosure is a semiconductor device for a Doherty amplifier circuit, comprising: a main amplifier that amplifies a first signal obtained by distributing an input signal and outputs the amplified signal as a fourth signal; a first peak amplifier that amplifies a second signal obtained by distributing the input signal and outputs the amplified signal as a fifth signal; a second peak amplifier that amplifies a third signal obtained by distributing the input signal and outputs the amplified signal as a sixth signal; a first semiconductor chip on which the main amplifier and the first peak amplifier are mounted; and a second semiconductor chip on which the second peak amplifier is mounted, the second semiconductor chip being a chip different from the first semiconductor chip, wherein the input power of the input signal for turning on the second peak amplifier is greater than the input power of the input signal for turning on the first peak amplifier. Thus, deterioration of characteristics can be suppressed and the yield can be improved.

[0067] [Details of Embodiments of the Present Disclosure]

[0068] Hereinafter, specific examples of the Doherty amplifier circuit and the semiconductor device according to the embodiments of the present disclosure will be described with reference to the drawings. It should be noted that the present disclosure is not limited to these examples, but is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0069] [Example 1]

[0070] As the Doherty amplifier circuit, a high-output high-frequency amplifier circuit for a mobile communication base station will be described as an example. In this case, the frequency of the high-frequency signal is, for example, 0.5 GHz or more and 10 GHz or less. Figure 1 It is a block diagram of the Doherty amplifier circuit of Example 1.

[0071] As Figure 1 shown, in Doherty amplifier circuit 100, a main amplifier 10, a peak amplifier 12 (first peak amplifier), and a peak amplifier 14 (second peak amplifier) are connected in parallel between a splitter 16 and a combiner 18. Thus, Doherty amplifier circuit 100 is a three-way amplifier circuit. The Doherty amplifier circuit may also be an N-way Doherty amplifier circuit having three or more peak amplifiers.

[0072] A high-frequency signal is input as an input signal Sin to an input terminal Tin. Splitter 16 distributes the input signal Sin input to input terminal Tin into a signal S1 (first signal), a signal S2 (second signal), and a signal S3 (third signal). Splitter 16 is, for example, a Wilkinson type splitter.

[0073] The path of input signal S1 includes a matching circuit 30, a bias circuit 36, a main amplifier 10, a bias circuit 39, and a matching circuit 33. The path of input signal S2 includes a matching circuit 31, a bias circuit 37, a peak amplifier 12, and a matching circuit 34. The path of input signal S3 includes a matching circuit 32, a bias circuit 38, a peak amplifier 14, and a matching circuit 35.

[0074] Matching circuits 30 to 32 match the impedances when looking at matching circuits 30 to 32 from splitter 16 respectively with the impedances when looking at main amplifier 10, peak amplifier 12, and peak amplifier 14 from matching circuits 30 to 32 respectively. Bias circuits 36 to 38 supply gate bias voltages VG1 to VG3 to the gates G of main amplifier 10, peak amplifier 12, and peak amplifier 14 respectively, suppressing leakage of signals S1 to S3 to the bias terminal.

[0075] Main amplifier 10, peak amplifier 12, and peak amplifier 14 amplify signals S1, S2, and S3 respectively, and output the amplified signals S4 (fourth signal), S5 (fifth signal), and S6 (sixth signal) respectively. Bias circuit 39 supplies a drain bias voltage VD to the drains D of main amplifier 10, peak amplifier 12, and peak amplifier 14, suppressing leakage of signal S4 to the bias terminal. Matching circuits 33 to 35 match the impedances when looking at matching circuits 33 to 35 from main amplifier 10, peak amplifier 12, and peak amplifier 14 respectively with the impedances when looking at combiner 18 from matching circuits 33 to 35 respectively. Combiner 18 combines signals S4 to S6, and outputs the combined signal as an output signal Sout to an output terminal Tout.

[0076] The main amplifier 10, the peak amplifier 12, and the peak amplifier 14 each include transistors Q1 to Q3. The transistors Q1 to Q3 are, for example, FETs (Field Effect Transistors), such as GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) or LDMOSs (Laterally Diffused Metal Oxide Semiconductors). The sources S of the transistors Q1 to Q3 are grounded, the signals S1 to S3 are respectively input to the gates G, and the signals S4 to S6 are respectively output from the drains D. The transistors Q1 to Q3 are mounted on a semiconductor chip 20. The matching circuits 30 to 33 and the semiconductor chip 20 are mounted on a package 50.

[0077] Figure 2 is a top view of the semiconductor device of Example 1. In Figure 2 the cover of the package 50 is not shown. The thickness direction of the substrate 51 of the package 50 is defined as the Z direction, the direction from the leads 27a to 27c to the leads 28a to 28c is defined as the X direction (the second direction intersecting the first direction), and the direction orthogonal to the X direction and the Z direction is defined as the Y direction (the first direction).

[0078] As Figure 2 shown, in the semiconductor device 102, the package 50 has a conductive substrate 51 at least on its upper surface. The substrate 51 is, for example, a conductive substrate such as a laminated substrate of copper and molybdenum. A reference potential such as a ground potential is supplied to the substrate 51. The semiconductor chip 20 and the capacitive components 24a to 24c are mounted on the substrate 51.

[0079] The leads 27a to 27c are provided on the - side in the X direction of the substrate 51 with an insulating layer (not shown) interposed therebetween. The leads 28a to 28c are provided on the + side in the X direction of the substrate 51 with an insulating layer (not shown) interposed therebetween. The leads 27a to 27c and the leads 28a to 28c are, for example, metal layers or metal plates such as copper. The signals S1 to S3 are respectively input to the leads 27a to 27c, and the signals S4 to S6 are respectively output from the leads 28a to 28c.

[0080] The semiconductor chip 20 includes a substrate 21, transistors Q1 to Q3, pads 22a to 22c provided on the upper surface of the substrate 21, pads 23a to 23c, and electrodes (not shown) provided on the lower surface of the substrate 21. The pad 22a (first input pad), the pad 23a (first output pad), and the electrode on the lower surface are electrically connected to the gate G (input terminal), the drain D (output terminal), and the source S of the transistor Q1, respectively. The pad 22b (second input pad), 23b (second output pad), and the electrode on the lower surface are electrically connected to the gate G (input terminal), the drain D (output terminal), and the source S of the transistor Q2, respectively. The pad 22c (third input pad), the pad 23c (third output pad), and the electrode on the lower surface are electrically connected to the gate G (input terminal), the drain D (output terminal), and the source S of the transistor Q3, respectively.

[0081] The substrate 21 is a semiconductor substrate. When the transistors Q1 to Q3 are GaN HEMTs, the substrate 21 is, for example, a silicon carbide (SiC) substrate, a sapphire substrate, or a gallium nitride (GaN) substrate. When the transistors Q1 to Q3 are LDMOSs, the substrate 21 is, for example, a silicon (Si) substrate. The pads 22a to 22c, the pads 23a to 23c, and the electrodes on the lower surface are, for example, metal layers such as gold layers. Although the transistor Q1 is shown to be smaller than the transistors Q2 and Q3 (for example, smaller gate width, smaller saturation power when the gate bias voltage and the drain bias voltage are the same), the transistor Q1 can also be the same as the transistors Q2 and Q3 (for example, the same gate width, the same saturation power when the gate bias voltage and the drain bias voltage are the same).

[0082] The capacitive components 24a to 24c include a dielectric substrate 25, an electrode 26 provided on the upper surface of the dielectric substrate 25, and an electrode (not shown) provided on the lower surface of the dielectric substrate 25. A capacitor is formed by the electrode 26 and the electrode on the lower surface with the dielectric substrate 25 interposed therebetween. The dielectric substrate 25 is, for example, an alumina substrate or a barium titanate substrate. The electrode 26 is, for example, a metal layer such as a gold layer.

[0083] The bonding wires 46 electrically connect the leads 27a to 27c and the electrodes 26 of the capacitive components 24a to 24c, respectively. The bonding wires 47 electrically connect the electrodes 26 of the capacitive components 24a to 24c and the pads 22a to 22c, respectively. The bonding wires 48 electrically connect the pads 23a to 23c and the leads 28a to 28c, respectively. The bonding wires 46 to 48 are, for example, metal wires such as gold wires or aluminum wires.

[0084] Bond wires 46 and 47 function as inductors, and capacitive components 24a to 24c function as capacitors. Bond wires 46, 47, and capacitive components 24a to 24c correspond to at least a part of matching circuits 30 to 32 of the T-type LCL circuit.

[0085] Figure 3 is a cross-sectional view of the semiconductor chip of Example 1. As Figure 3 shown, the substrate 21 includes a substrate 40a and a semiconductor layer 40b provided on the substrate 40a. Regions where a part of the semiconductor layer 40b is inactivated by ion implantation or the like are a passive region 44, a passive region 44a, and a passive region 44b. Regions where the semiconductor layer 40b is not inactivated are active regions 45a to 45c. Transistors Q1 to Q3 are respectively provided on the active regions 45a to 45c. There is a passive region 44a between transistor Q1 and transistor Q2, and a passive region 44b between transistor Q2 and transistor Q3.

[0086] Transistor Q1 includes a source electrode 41a, a gate electrode 42a, and a drain electrode 43a arranged in the Y direction. Transistor Q2 includes a source electrode 41b, a gate electrode 42b, and a drain electrode 43b arranged in the Y direction. Transistor Q3 includes a source electrode 41c, a gate electrode 42c, and a drain electrode 43c arranged in the Y direction. An insulating layer 49 is provided on the substrate 21 so as to cover transistors Q1 to Q3. The insulating layer 49 is, for example, an organic insulating layer such as a polyimide layer or a BCB (Benzocycbutene) layer. At least a part of the insulating layer 49 may also be an inorganic insulating layer.

[0087] When transistors Q1 to Q3 are GaN HEMTs, the substrate 40a is, for example, a silicon carbide substrate, and the semiconductor layer 40b includes a gallium nitride transit layer and an aluminum gallium nitride barrier layer. The source electrodes 41a to 41c and the drain electrodes 43a to 43c are metal films, for example, a titanium film and an aluminum film starting from the semiconductor layer 40b side. The gate electrodes 42a to 42c are metal films, for example, a nickel film and a gold film starting from the semiconductor layer 40b side.

[0088] In transistors Q1 to Q3, the thicknesses of the respective layers of the semiconductor layer 40b are substantially the same. For example, in transistors Q1 to Q3, the thicknesses of the gallium nitride transit layers are the same as each other, and the thicknesses of the aluminum gallium nitride barrier layers are the same as each other. In addition, in transistors Q1 to Q3, the sizes of the source electrodes 41a to 41c are the same as each other, the sizes of the gate electrodes 42a to 42c are the same as each other, and the sizes of the drain electrodes 43a to 43c are the same as each other.

[0089] Therefore, the characteristics per unit gate width of transistors Q1 to Q3 are substantially the same as each other. For example, in transistors Q1 to Q3, the gate-source capacitance per unit gate width is substantially the same as each other, the drain-source capacitance per unit gate width is substantially the same, and the gate-drain capacitance per unit gate width is substantially the same.

[0090] Figure 4 is a schematic diagram showing the probability with respect to Pout, the Pout of each amplifier with respect to Pin, the gain of each amplifier with respect to Pin, and the overall gain with respect to Pin in the first embodiment.

[0091] The probability is the probability of the modulated wave signal of the high-frequency signal for mobile communication amplified by the Doherty amplifier circuit 100. That is, it is the probability that the Doherty amplifier circuit 100 outputs a certain output power Pout. Each Pout is the output power Pout of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14. Each gain is the power gain of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14, respectively. The overall gain is the power gain of the output power Pout of the output signal Sout with respect to the input power Pin of the input signal Sin. It should be noted that Pin and Pout are expressed in dB. The gain of the main amplifier 10 below the power P1 is greater than the gain of the peak amplifier 12 above the power P1 and below the power P2. That is, the slope of Pout of the main amplifier 10 below the power P1 with respect to the input power Pin is greater than the slope of Pout of the peak amplifier 12 above the power P1 and below the power P2 with respect to the input power Pin. However, Figure 4 is a schematic diagram showing that the slope of Pout of the main amplifier 10 below the power P1 with respect to the input power Pin is represented as less than the slope of Pout of the peak amplifier 12 above the power P1 and below the power P2 with respect to the input power Pin.

[0092] As Figure 4 shown, when the output power Pout is the power P0, the probability of the modulated wave is the highest. That is, in the case of outputting the signal of the modulated wave, the time when the output power Pout is the power P0 is the longest. The main amplifier 10 is a class A or AB class amplifier, and the peak amplifiers 12 and 14 are class C amplifiers. The input power Pin for turning on the peak amplifier 12 is greater than the input power Pin for turning on the main amplifier 10, and the input power Pin for turning on the peak amplifier 14 is greater than the input power Pin for turning on the peak amplifier 12. In order to operate in this way, it can be achieved by making the gate bias voltage VG2 of the transistor Q2 greater than the gate bias voltage VG1 of the transistor Q1 in the negative direction and making the gate bias voltage VG3 of the transistor Q3 greater than the gate bias voltage VG2 of the transistor Q2 in the negative direction.

[0093] As the input power Pin of the input signal Sin increases and exceeds the power P0 until the power P1, the main amplifier 10 operates, but the peak amplifiers 12 and 14 do not. When the input power Pin is below the power P1, if the input power Pin increases, the output power Pout of the main amplifier 10 increases linearly. Therefore, when the input power Pin is below the power P0, each gain and the overall gain are approximately fixed.

[0094] When the input power Pin is above the power P1 and below the power P2, the main amplifier 10 and the peak amplifier 12 operate, but the peak amplifier 14 does not. In this range, the main amplifier 10 saturates. Therefore, the gain of the main amplifier 10 decreases. The overall gain also decreases accordingly. The peak amplifier 12 operates in class C, so the gain of the peak amplifier 12 between the power P1 and the power P2 is lower than the gain of the main amplifier 10 below the power P1. In addition, the saturation power of the peak amplifier 12 is less than the saturation power of the main amplifier 10.

[0095] When the input power Pin is above the power P2 and below the power P3, the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 all operate. In this range, in addition to the main amplifier 10, the peak amplifier 12 also saturates. Therefore, the gain of the peak amplifier 12 decreases. The overall gain also decreases accordingly. The operating point of the peak amplifier 14 is greater than that of the peak amplifier 12 in the negative direction, so the gain of the peak amplifier 14 between the power P2 and the power P3 is lower than the gain of the peak amplifier 12 between the power P1 and the power P2. In addition, the saturation power of the peak amplifier 14 is less than the saturation power of the peak amplifier 12.

[0096] When the input power Pin is above the power P3, in addition to the main amplifier 10 and the peak amplifier 12, the peak amplifier 14 also saturates. Therefore, the gain of the peak amplifier 14 decreases. The overall gain also decreases accordingly.

[0097] The product of the probability and the overall gain corresponds to the gain of the modulated wave. To increase the gain of the modulated wave, the overall gain at the Pout with a high probability should be increased.

[0098] [Comparative Example 1]

[0099] Figure 5 is a top view of the semiconductor device of Comparative Example 1. As Figure 5As shown, in the semiconductor device 110 of Comparative Example 1, the transistors Q1 to Q3 are respectively mounted on different semiconductor chips 20a to 20c. The semiconductor chips 20a to 20c respectively include substrates 21a to 21c. When the semiconductor chips 20a to 20c are different, the parasitic capacitances (for example, gate-source capacitance, drain-source capacitance, and gate-drain capacitance) between the transistors Q1 to Q3 will be uneven due to manufacturing non-uniformity. For example, when the wafers from which the semiconductor chips 20a to 20c are obtained are different from each other, the parasitic capacitances of the transistors Q1 to Q3 are likely to be different. Even when the semiconductor chips 20a to 20c are obtained from the same wafer, when the positions within the wafer from which the semiconductor chips 20a to 20c are obtained are different from each other, the parasitic capacitances of the transistors Q1 to Q3 are also likely to be different. Therefore, it is difficult to match the phases of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14. When the phases of the signals S4 to S6 deviate from the desired relationship, the gain of the output signal Sout decreases.

[0100] [Description of Embodiment 1]

[0101] According to Embodiment 1, as Figure 2 shown, the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 are mounted on the same semiconductor chip 20. The difference in parasitic capacitances and the like between the transistors Q1 to Q3 provided in adjacent regions within the semiconductor chip 20 is small. Therefore, the phases of the signals S4 to S6 output from the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 can be matched. Therefore, a decrease in characteristics such as the gain of the output signal Sout can be suppressed.

[0102] As Figure 4 shown, if the input power Pin for the operation of the main amplifier 10 and the peak amplifier 12 is between the power P1 and the power P2, the probability of the modulation wave is high. Therefore, the gain of the modulation wave can be increased by making the phases of the main amplifier 10 and the peak amplifier 12 within the desired range. Therefore, as Figure 2 shown, the main amplifier 10 and the peak amplifier 12 are adjacent in the Y direction. The transistors Q1 and Q2 are adjacent, whereby the difference in parasitic capacitances and the like of the transistors Q1 and Q2 becomes small. Thereby, the phase difference between the main amplifier 10 and the peak amplifier 12 can be reduced. Therefore, deterioration of characteristics such as the gain of the modulation wave can be suppressed. It should be noted that the main amplifier 10 and the peak amplifier 12 being adjacent means that no other transistors, passive elements, or wirings are provided between the main amplifier 10 and the peak amplifier 12.

[0103] As Figure 4As shown, if the input power Pin for the operation of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 is equal to or higher than the power P2, the probability of the modulation wave is low. Therefore, the peak amplifier 14 does not affect the gain of the modulation wave as does the peak amplifier 12. Therefore, the peak amplifier 12 can also be provided between the main amplifier 10 and the peak amplifier 14.

[0104] As Figure 3 shown, the respective widths of the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 (i.e., the transistors Q1 to Q3) in the Y direction are set to W1, W2, and W3. The distance between the main amplifier 10 and the peak amplifier 12 is set to D1, and the distance between the peak amplifier 12 and the peak amplifier 14 is set to D2. When the distance D1 becomes smaller, the difference in parasitic capacitance between the transistors Q1 and Q2 becomes smaller. Therefore, deterioration of characteristics can be suppressed. From this viewpoint, the distance D1 can be set to be equal to or less than the width W1 and the width W2, can be set to be equal to or less than 0.5 times the width W1 and the width W2, and can be set to be equal to or less than 0.2 times. From the viewpoint of reducing the non-uniformity of parasitic capacitance between the transistors Q2 and Q3, the distance D2 can be set to be equal to or less than the width W2 and the width W3, can be set to be equal to or less than 0.5 times the width W2 and the width W3, and can be set to be equal to or less than 0.2 times.

[0105] As Figure 2 shown, pads 22a and 23a that are electrically connected to the input terminal and the output terminal of the main amplifier 10, respectively, are provided on the semiconductor chip 20. Pads 22b and 23b that are electrically connected to the input terminal and the output terminal of the peak amplifier 12, respectively, are provided on the semiconductor chip 20. Pads 22c and 23c that are electrically connected to the input terminal and the output terminal of the peak amplifier 14, respectively, are provided on the semiconductor chip 20. Thereby, the main amplifier 10, the peak amplifier 12, and the peak amplifier 14 can be electrically connected to external circuits such as the matching circuits 30 to 35.

[0106] The main amplifier 10, the peak amplifier 12, and the peak amplifier 14 are arranged in the Y direction. The main amplifier 10 is arranged in the X direction between the pad 22a and the pad 23a. The peak amplifier 12 is arranged in the X direction between the pad 22b and the pad 23b. The peak amplifier 14 is arranged in the X direction between the pad 22c and the pad 23c. Thereby, the pads 22a to 22c and the pads 23a to 23c are not provided between the main amplifier 10 and the peak amplifier 12 and between the peak amplifier 12 and the peak amplifier 14. Therefore, the main amplifier 10 and the peak amplifier 12 can be adjacent to each other, and the peak amplifier 12 and the peak amplifier 14 can be adjacent to each other.

[0107] No passive components such as inductors or capacitors are provided on the semiconductor chip 20. Accordingly, no passive components are provided between the main amplifier 10 and the peak amplifier 12 and between the peak amplifier 12 and the peak amplifier 14. Therefore, the main amplifier 10 can be adjacent to the peak amplifier 12, and the peak amplifier 12 can be adjacent to the peak amplifier 14.

[0108] [Embodiment 2]

[0109] Figure 6 is a top view of the semiconductor device of Embodiment 2. As Figure 6 shown, in the semiconductor device 104 of Embodiment 2, the transistor Q1 and the transistor Q2 are mounted on the semiconductor chip 20a, and the transistor Q3 is mounted on the semiconductor chip 20c. The semiconductor chip 20a and the semiconductor chip 20c each include a substrate 21a and a substrate 21c. The transistor Q1 and the transistor Q2 are adjacently provided on the substrate 21a. Other configurations are the same as those in Embodiment 1, and the description thereof is omitted.

[0110] To increase the gain of the modulated wave, it is effective to reduce the phase difference between the main amplifier 10 and the peak amplifier 12. Therefore, the main amplifier 10 and the peak amplifier 12 are mounted on the semiconductor chip 20a (first semiconductor chip). Accordingly, the phase difference between the main amplifier 10 and the peak amplifier 12 can be suppressed, and the gain of the modulated wave can be increased. On the other hand, as shown in Embodiment 1, when three amplifiers are provided on the same semiconductor chip 20, the semiconductor chip 20 is a qualified product when all three amplifiers are qualified products. Therefore, the yield of the semiconductor chip 20 is reduced. Therefore, the peak amplifier 14 that does not affect the gain of the modulated wave as the peak amplifier 12 is mounted on a semiconductor chip 20c (second semiconductor chip) different from the semiconductor chip 20a. Accordingly, the yields of the semiconductor chip 20a and the semiconductor chip 20c can be increased.

[0111] On the semiconductor chip 20a, the main amplifier 10 is adjacent to the peak amplifier 12. Accordingly, the difference in parasitic capacitance between the transistor Q1 and the transistor Q2 becomes small. Therefore, deterioration of characteristics can be suppressed. Refer to Figure 3 , in Modification 1 of Embodiment 1, the distance D1 in the Y direction between the main amplifier 10 and the peak amplifier 12 may be set to be equal to or less than the width W1 in the Y direction of the main amplifier 10 and equal to or less than the width W2 in the Y direction of the peak amplifier 12, may be set to be equal to or less than 0.5 times the widths W1 and W2, and may be set to be equal to or less than 0.2 times.

[0112] As Embodiment 1 and its modifications, a three-way Doherty amplifier circuit has been described as an example. However, in the case of an N-way Doherty amplifier circuit, only N - 1 peak amplifiers need to be provided.

[0113] The embodiments disclosed herein should be considered illustrative in all respects and not restrictive. The scope of the present disclosure is shown by the claims, rather than by the foregoing description, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A Doherty amplifier circuit, comprising: a distributor for distributing an input signal into a first signal, a second signal, and a third signal; a main amplifier, amplifying the first signal and outputting the amplified signal as a fourth signal; a first peak amplifier, amplifying the second signal and outputting the amplified signal as a fifth signal; a second peak amplifier, amplifying the third signal and outputting the amplified signal as a sixth signal; a synthesizer, which synthesizes the fourth signal, the fifth signal and the sixth signal, and outputs the synthesized signal as an output signal to an output terminal; as well as a semiconductor chip equipped with the main amplifier, the first peak amplifier, and the second peak amplifier, The input power of the input signal for the second peak amplifier to be turned on is greater than the input power of the input signal for the first peak amplifier to be turned on, The main amplifier is adjacent to the first peak amplifier.

2. The Doherty amplifier circuit according to claim 1, wherein: The first peak amplifier is disposed between the main amplifier and the second peak amplifier.

3. The Doherty amplifier circuit according to claim 1 or 2, wherein: The main amplifier is adjacent to the first peak amplifier in the first direction, and a distance between the main amplifier and the first peak amplifier is smaller than a width of the main amplifier in the first direction and also smaller than a width of the first peak amplifier in the first direction.

4. The Doherty amplifier circuit according to claim 1 or 2, comprising: A first input pad, provided on the semiconductor chip and electrically connected to an input terminal of the main amplifier; a second input pad, provided on the semiconductor chip and electrically connected to an input terminal of the first peak amplifier; a third input pad, provided on the semiconductor chip and electrically connected to an input terminal of the second peak amplifier; a first output pad, provided on the semiconductor chip and electrically connected to an output terminal of the main amplifier; a second output pad, provided on the semiconductor chip and electrically connected to an output terminal of the first peak amplifier; as well as The third output pad is provided on the semiconductor chip and is electrically connected to the output terminal of the second peak amplifier.

5. The Doherty amplifier circuit according to claim 4, wherein: The main amplifier, the first peak amplifier and the second peak amplifier are arranged in a first direction, The main amplifier is arranged between the first input pad and the first output pad in a second direction intersecting the first direction, The first peak amplifier is arranged between the second input pad and the second output pad in the second direction, The second peak amplifier is arranged between the third input pad and the third output pad in the second direction.

6. The Doherty amplifier circuit according to claim 1 or 2, wherein: No passive components are arranged on the semiconductor chip.

7. A Doherty amplifier circuit, comprising: a distributor for distributing an input signal into a first signal, a second signal, and a third signal; a main amplifier, amplifying the first signal and outputting the amplified signal as a fourth signal; a first peak amplifier, amplifying the second signal and outputting the amplified signal as a fifth signal; a second peak amplifier, amplifying the third signal and outputting the amplified signal as a sixth signal; a synthesizer, which synthesizes the fourth signal, the fifth signal and the sixth signal, and outputs the synthesized signal as an output signal to an output terminal; A first semiconductor chip equipped with the main amplifier and the first peak amplifier; as well as a second semiconductor chip equipped with the second peak amplifier, the second semiconductor chip being a chip different from the first semiconductor chip, An input power of the input signal for turning on the second peak amplifier is greater than an input power of the input signal for turning on the first peak amplifier.

8. A semiconductor device, which is a semiconductor device for a Doherty amplifier circuit, comprising: a main amplifier, amplifying a first signal obtained by dividing the input signal, and outputting the amplified signal as a fourth signal; a first peak amplifier, amplifying a second signal obtained by dividing the input signal, and outputting the amplified signal as a fifth signal; a second peak amplifier, amplifying a third signal obtained by dividing the input signal, and outputting the amplified signal as a sixth signal; as well as a semiconductor chip equipped with the main amplifier, the first peak amplifier, and the second peak amplifier, The input power of the input signal for the second peak amplifier to be turned on is greater than the input power of the input signal for the first peak amplifier to be turned on, The main amplifier is adjacent to the first peak amplifier.

9. A semiconductor device, which is a semiconductor device for a Doherty amplifier circuit, comprising: a main amplifier, amplifying a first signal obtained by dividing the input signal, and outputting the amplified signal as a fourth signal; a first peak amplifier, amplifying a second signal obtained by dividing the input signal, and outputting the amplified signal as a fifth signal; a second peak amplifier, amplifying a third signal obtained by dividing the input signal, and outputting the amplified signal as a sixth signal; A first semiconductor chip equipped with the main amplifier and the first peak amplifier; as well as a second semiconductor chip equipped with the second peak amplifier, the second semiconductor chip being a chip different from the first semiconductor chip, An input power of the input signal for turning on the second peak amplifier is greater than an input power of the input signal for turning on the first peak amplifier.

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