Multiplication-free fractional sampling rate conversion method based on multi-phase filtering

Abstract

The invention provides a multiplication-free fractional sampling rate conversion method based on multi-phase filtering, and belongs to the technical field of digital signal processing. According to the method, the fractional sampling rate conversion process based on multi-phase filtering is subjected to parallel processing, firstly, the coefficient hm (j) of each path of sub-filter is preprocessed, and I paths of multiplication-free sub-filters are designed; storing the parallel input D-path data into a shift register, and extracting the selected phase number l and the length L of a sub-filter according to multi-phase filtering to obtain I * L pieces of data to be calculated; and finally, according to the preprocessing rule of each phase of sub-filter, performing multiplication-free convolution operation on the to-be-operated data of the I sub-filters to obtain I paths of parallel output data y (m). According to the invention, the working clock of the filter is reduced, the sub-filter coefficient is preprocessed, the operation complexity is further reduced, logic resources are saved, the processing speed of the system is improved, the power consumption is reduced, and the method is suitable for high-speed transmission systems with various sampling rate conversions.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and particularly relates to a multiplication-free fractional sampling rate conversion method based on polyphase filtering. Background Art

[0002] In the field of digital signal processing, sampling rate conversion is a very important technology, which is widely used in audio, video processing, and communication systems. On the premise of ensuring that the signal does not distort, changing the sampling rate and the oversampling ratio of the signal can adapt to different processing requirements and avoid the waste of resources caused by signal processing at a high sampling rate. However, in many cases, the conversion of the sampling rate is not an integer multiple, but a fractional multiple conversion is required. Traditional fractional sampling rate conversion methods usually perform interpolation and decimation operations based on low-pass FIR filters. As Figure 1 shown, the FIR filter operates at the clock frequency after interpolation. For broadband signals, this frequency will be as high as several GHz, which is almost impossible to achieve on an FPGA. Therefore, a technology that combines polyphase filtering with the interpolation or decimation process is adopted to divide the filter into several sub-filters for parallel processing to reduce the working clock and processing delay of the filter. Assume that the frequency of the system input signal is f i , and the frequency of the desired output signal is f o , then the sampling rate conversion multiple is f o / f i = I / D, where I and D are the interpolation and decimation multiples respectively. The fractional sampling rate conversion method based on polyphase filtering is as Figure 2 shown. The polyphase filtering structure combined with the interpolator operates at the frequency f i , and no additional interpolation operation is required. For each input signal x(n), there are I-phase separate outputs, and then D-fold decimation is performed. Only 1 / D of the data is retained, and the rest of the filtering results are discarded, which will cause a huge waste of computing resources.

[0003] When a digital filter is implemented in hardware, it requires many multipliers. The number of multipliers used is related to the order of the filter, which greatly affects the performance of the entire digital system. However, multipliers consume a large amount of hardware resources, have a high computational complexity, and consume relatively high power. Therefore, a method for implementing a filter without multipliers has emerged. By using shift operations and adders to replace the multipliers that require a large amount of operations, and through various structural optimizations, the number of adders is reduced. For example, the distributed algorithm is often used in the design of FIR filters. This algorithm uses the look-up table structure in FPGAs to convert the multiply-accumulate operations with fixed coefficients into look-up table operations, replacing multipliers with simple additions. However, as the filter coefficients increase, the size of the look-up table increases by a factor of 2 to the power of the number of bits, which will occupy more resources for addressing and additional storage units. There is also a multiplierless filtering method based on Canonic Signed Digit (CSD) encoding that encodes the filter coefficients and represents the filter coefficients as the sum or difference of powers of 2, which can reduce the number of non-zero sign bits and reduce the number of addition operations in the calculation, thereby reducing the number of adders to a certain extent. However, when the filter order is high, a large number of addition resources are still required, which still cannot meet the requirements in a system with limited logic resources. Summary of the Invention

[0004] The object of the present invention is to provide a multiplierless fractional sampling rate conversion method based on polyphase filtering, which parallelizes the fractional sampling rate conversion process based on polyphase filtering to reduce the working clock of the filter; and fully utilizes the common relationship between the expressions after encoding the constant filter coefficients, searches for shared arithmetic units, further reduces the computational complexity, saves logic resources, improves the processing speed of the system, and reduces power consumption.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] A multiplierless fractional sampling rate conversion method based on polyphase filtering is used in a multi-channel parallel transmission mode, where the number of parallel input channels is D, the number of parallel output channels is I, and I and D are relatively prime to each other; the method includes the following steps:

[0007] Preprocess the coefficients of each sub-filter to obtain I sub-filters without multipliers;

[0008] Store the D channels of data input in parallel into a shift register, and obtain I*L data to be calculated according to the selected phase number l of polyphase filtering decimation and the length L of the sub-filter;

[0009] Use the operation rules of the I sub-filters without multipliers to perform multiplierless convolution operations on the data to be calculated respectively, and obtain I channels of parallel output data.

[0010] Further, the preprocessing of the coefficients of each sub-filter includes:

[0011] According to the number of phases l and the sub-filter number m selected by the preset polyphase filtering decimation, where m = 1, 2, …, I - 1 and 0 ≤ l < D, a sub-filter coefficient h of length L is obtained m (j) = h(jI + q m ), where q m = (mD + l) % I represents the initial position of the sub-filter coefficient, and h(jI + q m ) represents the complete filter coefficient, where j = 0, 1, …, L - 1;

[0012] Perform N-bit fixed-point quantization and CSD coding on the sub-filter coefficients to obtain the encoded sub-filter coefficient expression and the sign matrix C. The sign matrix C is composed of the sign bits c m (j, n) of the sub-filter coefficient expression at the bit positions; where c m (j, n) represents the sign bit at the nth bit position of the jth coefficient of sub-filter m;

[0013] According to the non-zero sign bits in different sub-filter coefficient expressions, find the shared operation units and judge the number of operation levels, and design a set of operation rules for the sub-filter without multiplication.

[0014] Further, the operation rules of the sub-filter without multiplication include:

[0015] For sub-filter m, the convolution formula to be operated is:

[0016]

[0017] where C represents the sign matrix at the bit positions after encoding the L filter coefficients of a single sub-filter, X represents the data of length L to be calculated input to a single sub-filter, E represents the shift vector of N bits, y(m) represents the convolution result of sub-filter m, x m (L - 1) represents the Lth input data of sub-filter m, and c m (L - 1, N - 1) represents the sign bit at the Nth bit position of the Lth coefficient of sub-filter m;

[0018] The steps of operating the above convolution formula are split into two steps. The first step is the multi-level operation based on the shared operation unit, and the second step is the shift operation;

[0019] In the multi-level operation based on the shared operation unit, according to the number of non-zero signs in each column of the sign matrix C, determine the maximum number of levels of the sub-filter hierarchical operation. If the maximum number of levels is greater than 1, multi-level operation is required, otherwise only the first-level operation is performed.

[0020] Further, the input data in the shift register is used to obtain the data to be calculated by the sub-filter through the following formula:

[0021] x m (j) = x(p m -j)

[0022]

[0023] where x m (j) represents the j-th input data of the sub-filter m, and x(p m -j) represents the (p m -j)-th input data in the shift register, and p m represents the starting position of the data to be calculated in the shift register.

[0024] Further, the first-level operation process is as follows:

[0025] In the symbol matrix C, all the shared operation units between any two filter coefficients are obtained according to the non-zero symbol bits, and a matrix B composed of b ij is obtained; where b ij represents the number of shared operation units between the sub-filter coefficients h m (i) and h m (j). This value is obtained by calculating the number of columns in the symbol matrix C where the non-zero symbol bits of the sub-filter coefficients h m (i) and h m (j) are the same or opposite. The adder or subtractor formed by the non-zero symbol bit corresponding to the column and the input data constitutes a shared operation unit; the adders or subtractors corresponding to the same or opposite non-zero symbol bits in different columns can be reused;

[0026] In the matrix B, a group of b ij combinations with the largest sum is selected. The row coordinates and column coordinates of b ij in this combination are not repeated; the adder or subtractor formed by the non-zero symbol bit corresponding to the selected b ij element and the input data is the first-level shared operation unit; according to the selected first-level shared operation unit, addition or subtraction calculation is performed to obtain the expression of the first-level operation result A 0 ; the expression of the first-level operation result A 0 is as follows:

[0027]

[0028] where A(0) to A(T 1 -1) is a group of T 1The result after addition or subtraction calculation by a first-level shared operation unit, A(T 1 ) to A(T 2 ) are a set of elements required for calculating the sum of each column when calculating the sum of each column except for the first-level shared operation unit. The calculation of the sum of each column refers to the multiplication and accumulation operation of the non-zero symbol bits in the symbol matrix C and the input data. The calculation results of the shared operation unit part in this multiplication and accumulation operation are included in the corresponding A(0) to A(T 1 -1), and the data to be calculated in the non-shared operation unit part is included in A(T 1 ) to A(T 2 ); is the symbol matrix of the first-level operation result;

[0029] In the symbol matrix C, if the j 2 th column and the j 3 th column contain the same shared operation unit A(i), and the corresponding symbol bits of the shared operation unit are the same, then the symbol bit in the i-th row of the symbol matrix of the first-level operation result has If the corresponding symbol bits of the shared operation unit are opposite, then If the result of this column operation does not include the result of this shared operation unit, then

[0030] Further, the multi-level operation process is as follows:

[0031] Regarding the symbol matrix of the first-level operation result as a new symbol matrix, using the same method as the first-level operation process, obtain the second-level shared operation unit required for the second-level operation and calculate the second-level operation result A 1 , and so on, until the maximum-level operation ends, obtain N parallel summation results of the matrix X*C, and then perform shifts on the N summation results respectively, and perform addition to obtain the convolution result of the sub-filter m.

[0032] Further, the convolution result of the sub-filter m is:

[0033]

[0034] Among them, y(m) represents the convolution result of the sub-filter m, N represents the number of bit positions, and A Lmax-1 (n) represents the nth parallel summation result obtained from the multi-level operation;

[0035] By performing N - 1 - n bit left shifts on the N parallel non-zero summation results A Lmax-1 (n) and then summing them, the final convolution result is obtained.

[0036] Furthermore, the maximum number of levels of the hierarchical operation of the sub-filter is expressed as:

[0037] L max = max(L n )

[0038]

[0039] where L max represents the maximum number of operation levels, and L n represents the ceiling value of the logarithmic result of the number d m (n) of non-zero symbols in each column of the non-zero symbol matrix C. n represents the nth bit, corresponding to the nth column in the non-zero symbol matrix C.

[0040] Furthermore, the length of the shift register is D + L - 1. In each clock cycle, D data are shifted out from the low address of the shift register, and the newly input D data are stored in the high address.

[0041] Furthermore, if there are symmetric sub-filter coefficients, only one of the sub-filter coefficients is preprocessed, and the other symmetric sub-filter coefficient uses the same preprocessing result and processes the input data in reverse order.

[0042] The beneficial effects of the present invention are as follows: The present invention parallelizes the fractional sampling rate conversion structure based on polyphase filtering and preprocesses each group of sub-filter coefficients, designing a group of sub-filters without multiplication. Its advantages are: 1) This polyphase filter combines the processes of interpolation and decimation at the same time. The data of the sub-filters that are not decimated are not operated, reducing the computational complexity and the working clock of the filter; 2) By preprocessing the sub-filter coefficients, according to the common relationship between the encoded coefficient expressions, shared operation units are found, and the convolution operation is simplified to addition or subtraction and shift operations, greatly saving DSP resources, improving the processing speed of the system, and reducing power consumption; 3) This filter coefficient preprocessing process can be widely applied to various different digital filters and signal processing processes, which is beneficial for FPGA implementation in resource-constrained systems. Description of the Drawings

[0043] Figure 1 is the traditional fractional sampling rate conversion method;

[0044] Figure 2 is the fractional sampling rate conversion method based on polyphase filtering;

[0045] Figure 3 is the schematic diagram of the parallel implementation method of the multiplication-free fractional sampling rate conversion based on polyphase filtering provided by the present invention;

[0046] Figure 4Schematic diagram of the preprocessing process of the sub-filter coefficients provided by the present invention;

[0047] Figure 5 Schematic diagram of the calculation method of the sub-filter without multiplication provided by the present invention;

[0048] Figure 6 Schematic diagram of the shift register update provided by the present invention;

[0049] Figure 7 Schematic diagram of the selection process of the data to be calculated by the sub-filter provided by the present invention. Detailed implementation manners

[0050] The present invention will be further described and explained below in conjunction with the detailed implementation manners. The described embodiments are only examples of the disclosed content and do not delimit the scope of limitation. The technical features of each embodiment of the present invention can be combined correspondingly without conflict.

[0051] The present invention provides a parallel implementation method for non-multiplication fractional sampling rate conversion based on polyphase filtering, as Figure 3 shown. First, according to the parallel processing structure of the fractional sampling rate conversion based on polyphase filtering, the coefficients of each sub-filter are obtained, and the coefficients of the sub-filter are preprocessed to design a set of non-multiplication operation rules for the sub-filter; then the D-channel data input in parallel is stored in the shift register, and according to the selected phase number l of the polyphase filtering decimation and the length L of the sub-filter, I*L data to be calculated are selected from the shift register; finally, according to the preprocessing rules of each sub-filter, non-multiplication convolution operations are respectively performed on the data to be operated by the I sub-filters to obtain I-channel parallel output data. The present invention parallelizes the fractional sampling rate conversion process based on polyphase filtering, reduces the working clock of the filter, and is applicable to high-speed transmission systems with various sampling rate conversions; and fully utilizes the common relationship between the encoded expressions of the constant filter coefficients to find shared operation units, further reducing the operation complexity, saving logic resources, improving the processing speed of the system, and reducing power consumption.

[0052] Assume that the total length of the filter is W = I*L, the original input sequence x(n) is interpolated by I times to obtain the sequence s(n), and the sequence after polyphase filtering is r(n), as shown in Equation (1):

[0053]

[0054] Perform 1 / D decimation on r(n), and the decimation phase number is l. The decimated sequence can be expressed by formula (2):

[0055]

[0056] For s(n), s(n) = x(n / I) if and only if n is divisible by I, and the rest of the values are 0. Therefore, setting mD + l = pI + q, the extracted sequence can be expressed by formula (3):

[0057]

[0058] where h(k) represents the k-th coefficient of the filter, j represents a natural number between 0 and L - 1, i represents a natural number between 0 and I - 1, L represents the length of the sub-filter, n represents the n-th point in the sequence, h m (j) represents the j-th coefficient of sub-filter m, x m (j) represents the j-th input data of sub-filter m, 0 ≤ q < I, p ≥ 0, 0 ≤ l < D. Therefore, the output data at each moment is generated by only one sub-filter. The parameter q m = (mD + l) % I, represents floor division, and "%" represents taking the remainder. When the decimation moment is m + I, the parameter q m+I = (mD + l) % I. It can be seen that the coefficients of the sub-filter at the moment m + I are the same as those of the sub-filter at the moment m, and the input data is delayed by D periods. Therefore, in a multi-channel parallel system, D input data are used as a group of data for parallel input, and I parallel outputs are obtained through I sub-filters. At each clock cycle, the coefficients of each sub-filter remain unchanged.

[0059] Through the above analysis, in the method proposed by the present invention, the number of parallel input channels is D, and the number of parallel output channels is I. In a specific implementation, the present invention mainly includes the following steps:

[0060] Step 1: According to the parallel processing structure of the fractional sampling rate conversion based on polyphase filtering, obtain the coefficients of each sub-filter, preprocess the coefficients of the sub-filter, and design a set of sub-filter operation rules without multiplication.

[0061] In this step, the preprocessing process of the coefficients of the sub-filter aims to convert the convolution operation of the sub-filter into addition or subtraction operations to save DSP resources and improve the operation efficiency. Since the coefficients of each sub-filter remain unchanged at each clock cycle, according to formula (3), when the decimation phase number is selected as l and m = 0, 1, 2,... I - 1, the j-th coefficient of the m-th sub-filter is determined as shown in formula (4):

[0062] h m (j) = h(jI + q m ), 0 ≤ j < L (4)

[0063] where hm (j) represents the j-th coefficient of the m-th sub-filter, h(.) represents the complete filter coefficients, and q m =(mD + l)%I represents the initial position of the sub-filter coefficients. CSD coding is a ternary numerical coding system, that is, signed numbers are represented by (-1, 0, 1). Its coding method is to start from the least significant bit, replace 11 with 0(-1), and carry forward until the most significant bit ends. For example, the two's complement of 31 is 011111, and after CSD coding, it is 10000(-1). Its feature is that in a CSD-coded data, there are no two consecutive non-zero bits, which can greatly reduce the non-zero bits represented by the two's complement, meaning reducing the product terms in multiplication, thus saving resources. Therefore, the filter coefficients in formula (4) can be expressed as

[0064]

[0065] where c m (j,n) represents the symbol on the n-th bit from low to high of the j-th coefficient of the m-th sub-filter, and its value range is (-1, 0, 1). If the bit width after coding exceeds N, the highest bit is discarded.

[0066] For the m-th sub-filter, substituting equation (5) into formula (3), its convolution operation process can be expressed as:

[0067]

[0068] where C represents the symbol matrix of the L filter coefficients of a single sub-filter on the bit positions after coding, X represents the data to be calculated input to a single sub-filter, and E represents the shift vector of N bits; it can be seen that each row in matrix C represents the symbol of each bit position after the CSD coding of a single filter coefficient. Since c m (j,n) has a value range of (-1, 0, 1), the calculation process of y(m) can be carried out in two steps. First, sum the L input data according to the non-zero symbols c m (j,n) on the n-th bit of all filter coefficients of the sub-filter, that is, X*C, to obtain the summation results of N columns, and then perform shift addition on the summation results of each bit position. Therefore, the convolution operation of the sub-filter is transformed into a series of addition or subtraction and shift operations, saving a large amount of DSP resources.

[0069] In the fully parallel pipeline mode, it is necessary to sum the input data of the sub-filter simultaneously according to the non-zero symbol bits of each column in matrix C. In the FPGA implementation, in order to reduce the logic complexity, the summation process of multiple data adopts hierarchical addition or subtraction, and only two data are added or subtracted at each level. The number of levels of addition or subtraction is determined by the number d of non-zero symbols in each column of matrix Cm (n) Determine and take its logarithm Denote ceiling function, then the maximum number of operation levels for the entire process of X*C is L max = max(L n ), if L max > 1, multi-level operations are required.

[0070] Assume that a certain column in matrix C contains non-zero terms c m (j 1 , n) and c m (j 2 , n). If there are identical non-zero terms between different columns, the sum of the input data corresponding to these two terms can be obtained using the same adder or subtractor x m (j 1 ) ± x m (j 2 ); if there are non-zero terms with opposite signs -c m (j 1 , n) and -c m (j 2 , n) between different columns, the sum of the input data corresponding to these two terms can be obtained using an adder (or subtractor) and a negation operation -(x m (j 1 ) ± x m (j 2 )); then this adder or subtractor can be reused and only calculated once. This reused adder or subtractor is the shared operation unit. Therefore, eliminating the shared operation units between the column vectors in C can reduce the consumption of hardware resources.

[0071] Based on the relationship between the non-zero terms in the sign matrix C in the expression after encoding the sub-filter coefficients, find the shared operation units and perform addition or subtraction until all operation levels are completed to obtain the sum results on N bits; finally, for the N sum results, first perform corresponding shifts according to the positions of the bits, and then further perform summation to obtain the convolution result of the sub-filter. The execution flow of the multiplication-free sub-filter operation rule designed in this step is as Figure 5 shown, and each operation level includes: finding the shared operation units and single-level addition or subtraction.

[0072] Among them, the first-level operation process is as follows:

[0073] The steps for finding the shared operation units include: First, find all the shared operation units between any two filter coefficients according to the non-zero elements in the sign matrix C, and the number b ij of the corresponding shared operation units, obtaining a set of b ijThe formed matrix B; then select a group in matrix B to maximize the sum. The adder or subtractor composed of the non-zero sign bits corresponding to the selected elements and the input data is the required shared operation unit.

[0074] Here, b ij is obtained by calculating the number of columns in which the signs of the sub-filter coefficients h m (i) and h m (j) are the same or opposite in different columns of the sign matrix C. This value essentially refers to the maximum number of pairs of adders or subtractors that can be shared between two sub-filter coefficients.

[0075] Assume that in the CSD coding expressions of the i-th filter coefficient and the j-th filter coefficient in matrix C, the number of shared operation units is b ij . For L filter coefficients, find the number of shared operation units between any two filter coefficients to obtain an L×L matrix B, and there is b ij = b ji . Let b ii = 0, then matrix B can be expressed as:

[0076]

[0077] Then select a group from this matrix to maximize the sum, and j 0 , j 1 ,..., j l-1 are all different. The process is as follows:

[0078] (1) Start from finding the largest element in matrix B, and remove the j 0 -th row, j 0 -th column and the j 1 -th row, j 1 -th column respectively;

[0079] (2) Find the largest element among the remaining elements in matrix B, and then remove the j 2 -th row, j 2 -th column and the j 3 -th row, j 3 -th column;

[0080] (3) Continue to find the largest element in the remaining elements of B until the elements in the matrix are 0. The adder or subtractor composed of the non-zero sign bits corresponding to the element numbers obtained each time and the input data is the required shared operation unit. For example, {x m (j 0 ) ± x m (j 1), x m (j 2 ) ± x m (j 3 ),... x m (j l-2 ) ± x m (j l-1 )}。

[0081] If multiple elements are the largest simultaneously, start from each of them respectively to search for other elements, and then select the group of elements with the largest sum. The largest sum represents the largest number of shared operation units obtained and the least adder resources used.

[0082] Record the result of the first-level operation as matrix A 0 , as shown in formula (8). Among them, A(0) to A(T 0 - 1) used to calculate matrix A 1 represent the results of adding or subtracting two input data in the T 1 found shared operation units; A(T 1 ) to A(T 2 ) represent the elements required for calculating the sum of each column except for the shared operation units. For example, the first-column elements of the symbol matrix C are [0, 1, 0, -1, 0, 1, 0] T , and for the sum of the data on the first-column bit positions x m (1) - x m (3) + x m (5), where x m (1) - x m (3) is the shared operation unit, and the remaining x m (5) is A(T 1 ), which needs to be cached for the next-level summation. Use a ij to represent the sign bit of the operation result. If the j 2 -th column and the j 3 -th column of the symbol matrix C contain the same shared operation unit A(i), and the sign bits corresponding to the shared operation unit are the same, then the sign bit of the i-th row has If the sign bits corresponding to the shared operation unit are opposite, then there is If the result of this column operation does not include the result of this shared operation unit, then there is

[0083]

[0084] Second-level operation:

[0085] For the result A 0 of the first-level operation, according to the sign bit a ij, find the shared operation units required for the second-level operation. Similar to the first level, first find the number of shared operation units, and then obtain a T 2 ×T 2 upper triangular matrix B 1 , and select the largest element from it and delete the corresponding row and column of the element. Then select the second-largest element, the second-second-largest element, etc. from the remaining matrix, and so on until the elements in the matrix are 0, to obtain the maximum sum of all selected elements. According to the sign bits corresponding to the selected elements and the results of the first-level shared operation units, form the second-level adder or subtractor, which is the shared operation unit required for the second-level operation, and obtain the result matrix A of the second-level operation 1 , and matrix A 0 is similar

[0086] And so on, perform the third-level and fourth-level operations until the maximum L max level operation ends, and obtain N parallel summation results of matrix X*C

[0087] Then perform N-1-n bit shifts on the N summation results respectively, and perform additions to obtain the convolution result of the mth sub-filter

[0088] Step 2: Store the D-channel data input in parallel into the shift register, and select I*L data to be calculated from the shift register according to the selected phase number of the polyphase filtering and the length of the sub-filter

[0089] In this step, the length of the shift register is D+L-1. In each clock cycle, D data are shifted out from the low address of the shift register, and the newly input D data are stored in the high address, as Figure 6 shown

[0090] For sub-filter m, when the polyphase extraction phase number l is fixed, the jth input data to be calculated is

[0091] x m (j) = x(p m -j), 0≤j<L (9)

[0092] where 0≤m<I, then the data to be calculated for sub-filter m are the L consecutive data starting from x(p m -j). For the I-channel parallel sub-filters of the present invention, it is necessary to simultaneously select I consecutive data blocks with a length of L according to the starting positions of I different sub-filter data, that is, the total length of the data to be calculated is I*L, as Figure 7 shown, and input them into the I sub-filters for filtering respectively

[0093] Step 3: Input the I*L data to be calculated obtained in the above Step 2 into I sub-filters respectively. Each sub-filter then performs multi-stage operations on the L data to be operated according to the multiplication-free sub-filter operation rules designed in Step 1, and obtains the filtering result of this sub-filter. The I sub-filters finally obtain I-way parallel output data.

[0094] In a specific implementation of the present invention, assume that the parallel input path number D = 5, the output path number I = 4, the length of the sub-filter L = 4, and the total length of the filter W = I*L = 16. The length of the shift register is D + L - 1 = 8, and each clock cycle includes D = 5 new data and 3 old data from the previous clock cycle, such as x(-3), x(-2), …, x(4); if the polyphase decimation phase number l = 1 is selected, the data to be calculated for each sub-filter (m = 0, 1, 2, … I - 1) at the starting position p of the shift register m are respectively: 0, 1, 2, 4, and the initial positions q of the sub-filter coefficients m are respectively: 1, 2, 3, 0. It can be seen from formula (3) that the output of each sub-filter can be obtained from the following convolution results:

[0095] y(0) = x(0)h(1) + x(-1)h(5) + x(-2)h(9) + x(-3)h(13)

[0096] y(1) = x(1)h(2) + x(0)h(6) + x(-1)h(10) + x(-2)h(14)

[0097] y(2) = x(2)h(3) + x(1)h(7) + x(0)h(11) + x(-1)h(15)

[0098] y(3) = x(4)h(0) + x(3)h(4) + x(2)h(8) + x(1)h(12)

[0099] Among them, the coefficients and input data of each sub-filter are respectively:

[0100]

[0101] A total of I*L = 16 data to be calculated are generated. Assume that the four coefficients of the first sub-filter h 0 after 8-bit quantization are [-3, 63, 99, -4] respectively, and are converted into binary signed numbers and subjected to CSD coding, as shown in Table 1. If the number of bits after CSD coding is greater than 8, the highest bit is discarded.

[0102] Table 1 Filter coefficient coding of sub-filter h 0 of the filter

[0103] Coefficient Two's complement After CSD encoding -3 1111_1101 1_0000_0(-1)01 63 0011_1111 0100_000(-1) 99 0110_0011 10(-1)0_010(-1) -4 1111_1100 1_0000_0(-1)00

[0104] Then the symbol matrix C of this sub-filter is as follows:

[0105]

[0106] Among them, the number of non-zero symbol bits in each column is {1, 1, 1, 0, 0, 3, 0, 3} respectively. Then the maximum number of operation levels Two levels of operations are required. Search for shared operation units from matrix C. For example, the symbols in the 6th column of the 1st row and the 3rd row are (-1, 1), and the symbols in the 8th column are (1, -1). These two columns have a common operation unit x 0 (0) - x 0 (2). Therefore, b 02 = 2; the symbols in the 8th column of the 1st row and the 2nd row are only (1, -1). Therefore, b 01 = 1; the symbols in the 6th column of the 1st row and the 4th row are only (-1, -1). Therefore, b 03 = 1; the symbols in the 8th column of the 2nd row and the 3rd row are only (-1, -1). Therefore, b 12 = 1; the symbols in the 6th column of the 3rd row and the 4th row are only (1, -1). Therefore, b 23 = 1. Search for all possible shared operation units to form matrix B.

[0107]

[0108] Find the largest element 2 from B in turn to obtain the shared operation unit A(0) = x 0 (0) - x 0 (2) = x(0) + x(-2). Therefore, the result of the first-level operation of this sub-filter is as follows:

[0109]

[0110] Among them, in the symbol matrix of A 0 , there are at most two non-zero elements in each column. Therefore, addition and subtraction can be directly performed according to the symbols. Then the sum result X*C of each column is: A 1 = {x 0 (2), x 0 (1), -x 0 (2), 0, 0, -A(0) - x 0 (3), 0, A(0) - x 0 (1)}.

[0111] Then for each non-zero element A 1 in 0(n) Perform an N - 1 - n bit left shift, and then perform a summation to obtain the filtering result y(0) of the third sub - filter as shown in the following formula, where "<< " represents a left shift.

[0112]

[0113] The processing procedures of the other phase sub - filters y(1), y(2), y(3) are similar to the above. For a typical FIR filter with linear phase, due to the symmetry characteristics of its coefficients, the coefficients of h 0 and h 1 are symmetric, and the coefficients of h 2 and h 3 are symmetric. Therefore, only the coefficients of h 0 and h 2 need to be pre - processed. The other two sub - filters share the processing procedures of these two sub - filters, but the input data x 1 and x 3 of the sub - filters need to be reversed.

[0114] The above - described embodiments only represent the embodiments of the present application that are described more specifically and in detail, but should not be construed as limiting the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for multiplication-free fractional sampling rate conversion based on polyphase filtering, used in a multi-channel parallel transmission mode, wherein the number of input parallel channels is D, the number of output parallel channels is I, and I and D are mutually prime numbers; characterized in that: The method comprises the following steps: Preprocessing the coefficients of each sub-filter to obtain I-channel sub-filters without multiplication; The parallel input D-channel data is stored in the shift register, and the selected phase number l and the length L of the sub-filter are extracted according to the preset multi-phase filtering to obtain I*L data to be calculated; By utilizing the I-way non-multiplication sub-filter operation rule, the non-multiplication convolution operation is performed on the data to be calculated respectively to obtain I-way parallel output data.

2. The method for multiplication-free fractional sampling rate conversion based on polyphase filtering according to claim 1, characterized in that: The preprocessing of the coefficients of each sub-filter includes: According to the preset polyphase filter, the selected phase number l and sub-filter number m are extracted, where m = 1, 2, ..., I-1, 0 ≤ l < D, and the sub-filter coefficient h of length L is obtained. m (j) = h(jI + q m ), where q m =(mD+l)%I represents the initial position of the sub-filter coefficients, h(jI+q m ) represents the complete filter coefficients, j = 0, 1, ..., L-1; The sub-filter coefficients are subjected to N-bit fixed-point quantization and CSD encoding to obtain an encoded sub-filter coefficient expression and a symbol matrix C, wherein the symbol matrix C is composed of the symbol bits c of the sub-filter coefficient expression at the bit position m (j,n); where c m (j,n) represents the sign bit of the nth bit of the jth coefficient of subfilter m; According to the non-zero sign bits in the expressions of different sub-filter coefficients, the shared operation unit is found and the operation series is determined, and a set of operation rules of sub-filters without multiplication are designed.

3. The method for multiplication-free fractional sampling rate conversion based on polyphase filtering according to claim 2, characterized in that: The operation rules of the sub-filter without multiplication include: For sub-filter m, the convolution formula to be calculated is: Where C represents the symbol matrix of the L filter coefficients of a single sub-filter after encoding on the bit position, X represents the length of the calculated data of the single sub-filter input of L, E represents the shift vector of N bits, y(m) represents the convolution result of sub-filter m, x m (L-1) represents the Lth input data of sub-filter m, c m (L-1, N-1) represents the sign bit at the Nth bit position of the Lth coefficient of subfilter m; The steps of calculating the above convolution formula are divided into two steps. The first step is a multi-level operation based on a shared operation unit, and the second step is a shift operation. In the multi-stage operation based on the shared operation unit, the maximum number of sub-filter hierarchical operations is determined according to the number of non-zero symbols in each column of the symbol matrix C. If the maximum number is greater than 1, multi-stage operations are required, otherwise only the first-stage operation is performed.

4. The method for multiplication-free fractional sampling rate conversion based on polyphase filtering according to claim 1 or 3, characterized in that: The input data in the shift register is used to obtain the data to be calculated for the sub-filter through the following formula: x m (j)=x(p m -j) Among them, x m (j) represents the j-th input data of sub-filter m, x(p m -j) indicates the pth position in the shift register m -j input data, p m Indicates the starting position of the data to be calculated in the shift register.

5. The method for multiplication-free fractional sampling rate conversion based on polyphase filtering according to claim 3, characterized in that: The first-level operation process is: In the symbol matrix C, all shared operation units between any two filter coefficients are obtained according to the non-zero sign bits, and a matrix consisting of b ij The matrix B is composed of ij represents the sub-filter coefficient h m (i) and h m (j) The number of shared computing units between the two, which is calculated by calculating the sub-filter coefficient h m (i) and h m (j) the number of columns with the same or opposite signs on different columns of the symbol matrix C is obtained, and the adder or subtractor composed of the non-zero sign bits of the corresponding columns and the input data constitutes a shared operation unit; the adders or subtractors corresponding to the same or opposite non-zero sign bits in different columns can be reused; Select a group b with the largest sum in matrix B ij combination, in which b ij The row and column coordinates of b are not repeated; the selected ij The adder or subtractor composed of the non-zero sign bit corresponding to the element and the input data is the first-level shared operation unit; the addition or subtraction calculation is performed according to the selected first-level shared operation unit to obtain the expression of the first-level operation result A0; the expression of the first-level operation result A0 is as follows: Wherein, A(0) to A(T1-1) is a group of results after addition or subtraction calculation by T1 selected first-level shared operation units, A(T1) to A(T2) is a group of elements required for calculating the sum of each column except the first-level shared operation units, and the calculation of the sum of each column refers to the multiplication and accumulation operation of the non-zero sign bits in the sign matrix C and the input data, and the calculation results of the shared operation unit part in the multiplication and accumulation operation are listed in the corresponding A(0) to A(T1-1), and the data to be calculated of the non-shared operation unit part are listed in A(T1) to A(T2); is the symbolic matrix of the result of the first-level operation; In the symbol matrix C, if the j2th column and the j3th column contain the same shared operation unit A(i), and the sign bits corresponding to the shared operation units are the same, then the sign bits of the i-th row in the symbol matrix of the first-level operation result have If the sign bits corresponding to the shared arithmetic units are opposite, then If the result of this column operation does not include the result of the shared operation unit, then 6. The method for multiplication-free fractional sampling rate conversion based on polyphase filtering according to claim 3, characterized in that: The multi-level operation process is: The symbol matrix of the first-level operation result is regarded as a new symbol matrix, and the second-level shared operation unit required for the second-level operation is obtained by the same method as the first-level operation process, and the second-level operation result A1 is calculated, and so on, until the maximum series of operations are completed, and N parallel summation results of the matrix X*C are obtained, and then the N summation results are shifted respectively, and Additions are performed to obtain the convolution result of sub-filter m.

7. The method for multiplication-free fractional sampling rate conversion based on polyphase filtering according to claim 6, characterized in that: The convolution result of the sub-filter m is: Among them, y(m) represents the convolution result of sub-filter m, N represents the number of bits, and A Lmax-1 (n) represents the nth parallel summation result obtained by multi-level operation; By summing the N non-zero results in parallel A Lmax-1 (n) Perform N-1-n bit left shift and then sum to get the final convolution result.

8. The method for multiplication-free fractional sampling rate conversion based on polyphase filtering according to claim 3, characterized in that: The maximum number of stages of the sub-filter hierarchical operation is expressed as: L max =max(L n ) Among them, L max Indicates the maximum number of operations, L n Represents the number of non-zero symbols in each column of the non-zero symbol matrix C m The rounded value of the logarithm result of (n), where n represents the nth bit and corresponds to the nth column in the non-zero symbol matrix C.

9. The method for multiplication-free fractional sampling rate conversion based on polyphase filtering according to claim 1, characterized in that: The length of the shift register is D+L-1. In each clock cycle, D data are shifted out from the low address of the shift register, and the newly input D data are stored in the high address.

10. The method for multiplication-free fractional sampling rate conversion based on polyphase filtering according to claim 1, characterized in that: If there are symmetrical sub-filter coefficients, only one of the sub-filter coefficients is preprocessed, and the other symmetrical sub-filter coefficient uses the same preprocessing result and processes the input data in reverse order.

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