Encoder calibration circuit, calibration method and integrated circuit chip

Abstract

The present application relates to the technical field of encoder calibration, and especially relates to an encoder calibration circuit, a calibration method and an integrated circuit chip. The circuit comprises: an input end of an analog signal comparison circuit is connected with a signal source and a reference signal output end of a processor respectively, which is used for comparing the size of a reference signal output by the processor and an original sine signal output by the signal source, and outputting a first comparison result through an output end; and comparing the size of the reference signal and an original cosine signal output by the signal source, and outputting a second comparison result through the output end; the processor acquires the first comparison result and the second comparison result, and outputs a first difference value between an original sine signal offset and an original cosine signal offset to an offset adjustment circuit; the offset adjustment circuit adjusts the offset of the original sine signal and the original cosine signal based on the first difference value, and outputs the sine signal after offset adjustment and the cosine signal after offset adjustment.

Description

Technical Field

[0001] This invention relates to the field of encoder calibration technology, and in particular to an encoder calibration circuit, calibration method, and integrated circuit chip. Background Technology

[0002] An encoder is a rotary sensor that converts rotary displacement into digital pulse signals in the form of sine or cosine waves. During use, structural deformation, component aging, and environmental interference can cause deviations in the offset and gain of the output sine and cosine signals. To ensure the accuracy of the encoder angle, it needs to be calibrated by mounting the encoder onto a platform. However, disassembling the encoder after it has been installed in the system is complex, and sometimes impossible. Therefore, in practical scenarios, removing the encoder from the system and then reinstalling it on a platform for calibration is quite difficult. Summary of the Invention

[0003] In view of this, the present invention provides an encoder calibration circuit, calibration method and integrated circuit chip, which can calibrate the encoder without disassembling the encoder.

[0004] In a first aspect, embodiments of the present invention provide an encoder calibration circuit, comprising:

[0005] Analog signal comparison circuit and offset adjustment circuit;

[0006] The input terminals of the analog signal comparison circuit are respectively connected to the reference signal output terminals of the signal source and the processor, and are used to compare the magnitude of the reference signal output by the processor with the magnitude of the original sine signal output by the signal source, and output a first comparison result through the output terminal; and compare the magnitude of the reference signal with the magnitude of the original cosine signal output by the signal source, and output a second comparison result through the output terminal.

[0007] The processor's input terminal is connected to the output terminal of the analog signal comparison circuit, and is used to acquire the first comparison result and the second comparison result, and to obtain the maximum value, minimum value, maximum value, and minimum value of the original sine signal based on the first comparison result and the second comparison result; and to obtain the first difference between the offset of the original sine signal and the offset of the original cosine signal based on the maximum value, minimum value, maximum value, and minimum value of the original cosine signal.

[0008] The processor's output terminal is connected to the input terminal of the offset adjustment circuit, and is used to output the first difference to the offset adjustment circuit;

[0009] The offset adjustment circuit adjusts the offset of the original sine signal and the original cosine signal based on the first difference, and outputs the offset-adjusted sine signal and the offset-adjusted cosine signal.

[0010] In one possible implementation, the analog signal comparison circuit specifically includes a raw sine signal comparison circuit and a raw cosine signal comparison circuit, and the signal source includes a raw sine signal output terminal and a raw cosine signal output terminal;

[0011] The original sine wave signal comparison circuit includes a first comparator; the non-inverting input of the first comparator is connected to the original sine wave signal output of the signal source, and the inverting input of the first comparator is connected to the reference signal output of the processor.

[0012] The original cosine signal comparison circuit includes a second comparator; the non-inverting input of the second comparator is connected to the original cosine signal output of the signal source, and the inverting input of the second comparator is connected to the reference signal output of the processor.

[0013] In one possible implementation, the offset adjustment circuit is an original sine signal offset adjustment circuit, which adjusts the offset of the original sine signal according to the first difference and outputs the offset-adjusted sine signal.

[0014] In one possible implementation, the processor's output terminal specifically includes a first output port and a second output port, and the signal source includes an original sine signal output terminal and an original cosine signal output terminal;

[0015] The original sinusoidal signal offset adjustment circuit includes a first operational amplifier;

[0016] The processor's first output port is connected to the non-inverting input of the first operational amplifier, and a first resistor is connected in series between the first output port and the non-inverting input of the first operational amplifier.

[0017] The non-inverting input terminal of the first operational amplifier is also connected to the original sinusoidal signal output terminal of the signal source, and a second resistor is connected in series between the original sinusoidal signal output terminal and the non-inverting input terminal of the first operational amplifier.

[0018] The processor's second output port is connected to the inverting input of the first operational amplifier, and a third resistor is connected in series between the second output port and the non-inverting input of the first operational amplifier.

[0019] The inverting input terminal of the first operational amplifier is also connected to the output terminal of the first operational amplifier through a fourth resistor;

[0020] When the offset of the original sine signal is less than the offset of the original cosine signal, the processor outputs the first difference at its first output port, outputs a low-level signal at its second output port, and the output of the first operational amplifier is the sum of the original sine signal and the first difference.

[0021] When the offset of the original sine signal is greater than the offset of the original cosine signal, the processor outputs a low-level signal at its first output port, outputs the first difference at its second output port, and the output of the first operational amplifier is the difference between the original sine signal and the first difference.

[0022] In one possible implementation, the offset adjustment circuit is an original cosine signal offset adjustment circuit, which adjusts the offset of the original cosine signal according to the first difference and outputs the offset-adjusted cosine signal.

[0023] In one possible implementation, the processor is provided with a first output port and a second output port, and the signal source includes a raw sine signal output terminal and a raw cosine signal output terminal;

[0024] The original cosine signal offset adjustment circuit includes a first operational amplifier;

[0025] The processor's first output port is connected to the non-inverting input of the first operational amplifier, and a first resistor is connected in series between the first output port and the non-inverting input of the first operational amplifier.

[0026] The non-inverting input of the first operational amplifier is also connected to the original cosine signal output of the signal source, and a second resistor is connected in series between the original cosine signal and the non-inverting input of the first operational amplifier.

[0027] The processor's second output port is connected to the inverting input of the first operational amplifier, and a third resistor is connected in series between the second output port and the non-inverting input of the first operational amplifier.

[0028] The inverting input terminal of the first operational amplifier is also connected to the output terminal of the first operational amplifier through a fourth resistor;

[0029] When the offset of the original cosine signal is less than the offset of the original sine signal, the processor outputs the first difference at its first output port, outputs a low-level signal at its second output port, and the output of the first operational amplifier is the sum of the original cosine signal and the first difference.

[0030] When the offset of the original cosine signal is greater than the offset of the original sine signal, the processor outputs a low-level signal at its first output port, outputs the first difference at its second output port, and the output of the first operational amplifier is the difference between the original cosine signal and the first difference.

[0031] One possible implementation also includes: a signal gain correction circuit;

[0032] The input terminal of the signal gain correction circuit is connected to the output terminal of the offset adjustment circuit, and is used to obtain the offset-adjusted sine signal and offset-adjusted cosine signal output by the offset adjustment circuit.

[0033] The signal gain correction circuit specifically includes a sine signal gain correction circuit and a cosine signal gain correction circuit;

[0034] The sinusoidal signal gain correction circuit is used to correct the gain of the sinusoidal signal after the offset adjustment;

[0035] The cosine signal gain correction circuit is used to correct the gain of the cosine signal after the offset adjustment.

[0036] In one possible implementation, the sine signal gain correction circuit includes a second operational amplifier, and the cosine signal gain correction circuit includes a third operational amplifier; the output terminal of the offset adjustment circuit specifically includes a sine signal output terminal and a cosine signal output terminal.

[0037] The non-inverting input of the second operational amplifier is connected to the sinusoidal signal output of the offset adjustment circuit to obtain the gain-corrected sinusoidal signal output by the offset adjustment circuit. A fifth resistor is connected in series between the sinusoidal signal output and the non-inverting input of the second operational amplifier. The inverting input of the second operational amplifier is connected to the ground terminal through a sixth resistor. n sub-circuits are connected in parallel between the inverting input and the output of the second operational amplifier.

[0038] The non-inverting input of the third operational amplifier is connected to the cosine signal output of the offset adjustment circuit to obtain the gain-corrected cosine signal output by the offset adjustment circuit. A seventh resistor is connected in series between the cosine signal output and the non-inverting input of the third operational amplifier. The inverting input of the third operational amplifier is connected to the ground terminal through an eighth resistor. n sub-circuits are connected in parallel between the inverting input and the output of the third operational amplifier.

[0039] Each of the sub-circuits includes an amplifying resistor and a switch connected in series; the processor controls the conduction and disconnection of each sub-circuit by controlling the closing and opening of the switch of each sub-circuit, thereby controlling the amplification factor of the second operational amplifier and the amplification factor of the third operational amplifier.

[0040] Secondly, embodiments of the present invention provide an integrated circuit chip, the integrated circuit chip including an encoder and the encoder calibration circuit described in the first aspect.

[0041] In one possible implementation, the encoder calibration circuit is an on-chip integrated circuit; the encoder calibration circuit is connected to the integrated circuit chip through an internal chip interface.

[0042] In one possible implementation, the encoder calibration circuit is an off-chip integrated circuit; the encoder calibration circuit is connected to the integrated circuit chip through an external chip interface.

[0043] Thirdly, embodiments of the present invention provide an encoder calibration method, applied to the encoder calibration circuit described in the first aspect, comprising:

[0044] The analog signal comparison circuit outputs a reference signal.

[0045] Obtain the first comparison result and the second comparison result output by the analog signal comparison circuit;

[0046] The maximum value, minimum value, maximum value, and minimum value of the original sine signal are obtained based on the first comparison result and the second comparison result.

[0047] Based on the maximum value and the minimum value of the original sine signal, a first offset of the original sine signal is obtained, and based on the maximum value and the minimum value of the original cosine signal, a second offset of the cosine signal is obtained.

[0048] Determine the first difference between the first offset and the second offset;

[0049] The first difference is output to the offset adjustment circuit;

[0050] Obtain the offset-adjusted sine signal and offset-adjusted cosine signal output by the offset adjustment circuit.

[0051] In one possible implementation, obtaining the maximum value of the original sinusoidal signal based on the first comparison result includes:

[0052] Determine whether the first comparison result output by the first comparator is a continuous low level;

[0053] If the first comparison result output by the first comparator is not a continuous low level, the reference signal output is increased successively until the first comparison result output by the first comparator is a continuous low level.

[0054] The enhanced reference signal is determined as the maximum value of the original sine signal.

[0055] In one possible implementation, obtaining the minimum value of the original sinusoidal signal based on the first comparison result includes:

[0056] Determine whether the first comparison result output by the first comparator is a continuous high level;

[0057] If the first comparison result output by the first comparator is not a continuous high level, then the reference signal output is successively decreased until the first comparison result output by the first comparator becomes a continuous low level.

[0058] The reduced reference signal is determined as the minimum value of the original sine signal.

[0059] In one possible implementation, the method further includes:

[0060] The offset-adjusted sine signal and the offset-adjusted cosine signal are input into the signal gain correction circuit to correct the gain of the offset-adjusted sine signal and the offset-adjusted cosine signal.

[0061] Obtain the gain-corrected sine signal and the gain-corrected cosine signal output by the signal gain correction circuit.

[0062] In one possible implementation, adjusting the gain of the offset-adjusted sinusoidal signal includes:

[0063] By sequentially controlling the conduction of n sub-circuits of the second operational amplifier, n sinusoidal signals with different amplification factors are obtained;

[0064] The sinusoidal signal with the largest amplification among the n sinusoidal signals with different amplification factors that are within the gain recognition range is determined as the target sinusoidal signal;

[0065] The target sinusoidal signal is determined to be the gain-corrected sinusoidal signal.

[0066] In one possible implementation, the method further includes:

[0067] Determine the first peak-to-peak value of the gain-corrected sine signal output by the gain correction circuit and the second peak-to-peak value of the gain-corrected cosine signal output by the gain correction circuit;

[0068] Determine whether the value of the first peak and the value of the second peak are equal;

[0069] If the first peak-to-peak value and the second peak-to-peak value are not equal, then the gain-corrected sine signal or the gain-corrected cosine signal output by the gain correction circuit is calibrated a second time to obtain a target sine signal and a target cosine signal with equal peak-to-peak values.

[0070] In this embodiment of the invention, the offset of the sine and cosine signals output by the encoder is adjusted by a calibration circuit to obtain sine and cosine signals with the same offset. This achieves encoder calibration without disassembling the encoder. Attached Figure Description

[0071] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0072] Figure 1 This is a schematic diagram of an encoder calibration circuit provided in an embodiment of the present invention;

[0073] Figure 2 This is a schematic diagram of an analog signal comparison circuit provided in an embodiment of the present invention;

[0074] Figure 3 This is a schematic diagram of the original sine wave signal offset adjustment circuit provided in an embodiment of the present invention;

[0075] Figure 4 This is a schematic diagram of the original cosine signal offset adjustment circuit provided in an embodiment of the present invention;

[0076] Figure 5This is a schematic diagram of the gain correction circuit provided in an embodiment of the present invention;

[0077] Figure 6 A flowchart of an encoder calibration method provided in an embodiment of the present invention;

[0078] Figure 7 A schematic diagram illustrating the maximum and minimum values ​​of a raw analog signal provided in an embodiment of the present invention;

[0079] Figure 8 This invention provides a hardware block diagram of an encoder calibration circuit. Detailed Implementation

[0080] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0081] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0082] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0083] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0084] In this embodiment of the invention, the maximum and minimum values ​​of the original analog signal output by the encoder are obtained through an analog signal comparison circuit. Based on these maximum and minimum values, the original analog signal is adjusted by an offset to obtain an original analog signal with the same offset. This allows calibration to be achieved without disassembling the encoder. Specifically, Figure 1 This is a schematic diagram of an encoder calibration circuit provided in an embodiment of the present invention. Figure 1 As shown, the encoder calibration circuit includes an analog signal comparison circuit 101 and an offset adjustment circuit 102.

[0085] The input terminals of the analog signal comparison circuit 101 are connected to the signal source 103 and the reference signal output terminal of the processor 104, respectively. It compares the magnitude of the reference signal Vref output by the processor 104 with the magnitude of the original sine signal Vsin output by the signal source 103, and outputs a first comparison result to the processor 104 through its output terminal. It also compares the magnitude of the reference signal Vref with the magnitude of the original cosine signal Vcos output by the signal source 103, and outputs a second comparison result to the processor through its output terminal. The signal source 103 can be implemented in the form of an encoder.

[0086] The input terminal of processor 104 is connected to the output terminal of analog signal comparison circuit 101, and is used to acquire a first comparison result and a second comparison result. Based on the first comparison result and the second comparison result, processor 104 obtains the maximum value Vsmax, the minimum value Vsmin, the maximum value Vcmax, and the minimum value Vcmin of the original sine signal Vsin, the original cosine signal Vcos, and the original cosine signal Vcos. Furthermore, based on the maximum value Vsmax, the minimum value Vsmin, the maximum value Vcmax, and the minimum value Vcmin of the original sine signal, processor 104 obtains the first difference between the offset of the original sine signal and the offset of the original cosine signal.

[0087] The output of processor 104 is connected to the input of offset adjustment circuit 102, and is used to output the first difference to offset adjustment circuit 102.

[0088] The offset adjustment circuit 102 adjusts the offset of the original sine signal Vsin and the original cosine signal Vcos based on the first difference, and outputs the offset-adjusted sine signal Vosin and the offset-adjusted cosine signal Vocos.

[0089] Specifically, the analog signal comparison circuit 101 includes a raw sine signal comparison circuit and a raw cosine signal comparison circuit. Correspondingly, the signal source 103 includes a raw sine signal output terminal and a raw cosine signal output terminal. The raw sine signal output terminal of the signal source 103 outputs the raw sine signal Vsin. The raw cosine signal output terminal of the signal source 103 outputs the raw cosine signal Vcos. Figure 2 This is a schematic diagram of an analog signal comparison circuit provided in an embodiment of the present invention. Figure 2 As shown, the analog signal comparison circuit 101 includes a raw sine signal comparison circuit 1011 and a raw cosine signal comparison circuit 1012.

[0090] The original sine wave signal comparison circuit 1011 includes a first comparator. The non-inverting input of the first comparator is connected to the original sine wave signal output of the signal source 101, and the inverting input of the first comparator is connected to the reference signal output of the processor 104. The first comparator outputs the comparison result of Vsin and Vref, i.e., the first comparison result OUT1.

[0091] The original cosine signal comparison circuit 1012 includes a second comparator. The non-inverting input of the second comparator is connected to the original cosine signal output of the signal source, and the inverting input is connected to the reference signal output of the processor. The second comparator outputs the comparison result between Vcos and Vref, i.e., the second comparison result OUT2.

[0092] When Vsin is greater than Vref, the first comparator outputs OUT1 at a high level. When Vsin is less than Vref, the first comparator outputs OUT1 at a low level. Similarly, when Vcos is greater than Vref, the second comparator outputs OUT2 at a high level. When Vcos is less than Vref, the second comparator outputs OUT2 at a low level.

[0093] When correcting the original analog signal, the offsets of Vsin and Vcos need to be adjusted to be the same. This can be done by adjusting only the offset of Vsin so that the adjusted offset of Vosin is the same as the offset of Vcos. Alternatively, only the offset of Vcos can be adjusted so that the adjusted offset of Vocos is the same as the offset of Vsin.

[0094] In one specific embodiment, the offset adjustment circuit 102 is implemented as an original sine signal offset adjustment circuit. The original sine signal offset adjustment circuit adjusts the offset of the original sine signal Vsin according to a first difference and outputs an offset-adjusted sine signal Vosin. Specifically, the original sine signal offset adjustment circuit compensates for the original sine signal according to the first difference, so that the offset of the compensated Vosin is the same as the offset of the original cosine signal Vcos.

[0095] Figure 3 This is a schematic diagram of a circuit for adjusting the offset of a raw sine wave signal, provided as an embodiment of the present invention. Figure 3 As shown, the core of the original sine wave signal offset adjustment circuit consists of a first operational amplifier. The processor's first output port DACout2 is connected to the non-inverting input of the first operational amplifier, and a first resistor R1 is connected in series between the first output port DACout2 and the non-inverting input of the first operational amplifier.

[0096] The non-inverting input of the first operational amplifier is also connected to the original sinusoidal signal output of the signal source, and a second resistor R2 is connected in series between the original sinusoidal signal output and the non-inverting input of the first operational amplifier.

[0097] The processor's second output port DACout3 is connected to the inverting input of the first operational amplifier, and a third resistor R3 is connected in series between the second output port and the non-inverting input of the first operational amplifier.

[0098] The inverting input of the first operational amplifier is also connected to its output via a fourth resistor, R4. Where R1 = R2 = R3 = R4.

[0099] When the offset of the original sine signal Vsin is less than the offset of the original cosine signal Vcos, the processor's first output port outputs the first difference, and the second output port outputs a low-level signal (i.e., 0V). At this time, the first operational amplifier forms an adder, and the final output of the first operational amplifier is the sum of the original sine signal and the first difference (i.e., Vosin = Vsin + ΔV0, where ΔV0 is the first difference). At this point, the offset of Vosin is equal to the offset of Vcos.

[0100] When the offset of the original sine signal Vsin is greater than the offset of the original cosine signal Vcos, the processor's first output port outputs a low-level signal, and the second output port outputs the first difference. At this time, the first operational amplifier forms a subtractor, and the final output of the first operational amplifier is the difference between the original sine signal and the first difference (i.e., Vosin = Vsin - ΔV0). At this point, the offset of Vosin is equal to the offset of Vcos.

[0101] In another specific embodiment, the offset adjustment circuit can also be implemented as an original cosine signal offset adjustment circuit. The original cosine signal offset adjustment circuit adjusts the offset of the original cosine signal Vcos based on the first difference and outputs the offset-adjusted cosine signal Vocos. Specifically, the original cosine signal offset adjustment circuit compensates the original cosine signal based on the first difference, so that the offset of the compensated Vocos is the same as the offset of the original cosine signal Vsin.

[0102] Figure 4 This is a schematic diagram of a raw cosine signal offset adjustment circuit provided in an embodiment of the present invention. Figure 4 As shown, the processor's first output port DACout2 is connected to the non-inverting input of the first operational amplifier, and a first resistor R1 is connected in series between the first output port and the non-inverting input of the first operational amplifier.

[0103] The non-inverting input of the first operational amplifier is also connected to the original cosine signal output of the signal source, and a second resistor R2 is connected in series between the original cosine signal and the non-inverting input of the first operational amplifier.

[0104] The processor's second output port DACout3 is connected to the inverting input of the first operational amplifier, and a third resistor R3 is connected in series between the second output port and the non-inverting input of the first operational amplifier.

[0105] The inverting input of the first operational amplifier is also connected to the output of the first operational amplifier through a fourth resistor R4.

[0106] When the offset of the original cosine signal is less than the offset of the original sine signal, the processor's first output port DACout2 outputs the first difference, and the second output port DACout3 outputs a low-level signal. At this time, the first operational amplifier forms an adder, and its output is the sum of the original cosine signal and the first difference. That is, Vocos = Vcos + ΔV0. The offset of Vocos at this point is equal to the offset of Vsin.

[0107] When the offset of the original cosine signal is greater than the offset of the original sine signal, the processor's first output port DACout2 outputs a low-level signal, and the second output port DACout3 outputs the first difference. At this time, the first operational amplifier forms a subtractor, and its output is the difference between the original cosine signal and the first difference. That is, Vocos = Vcos - ΔV0. The offset of Vocos at this time is equal to the offset of Vsin.

[0108] In some embodiments, in addition to correcting the offset of the analog signal output by the encoder, the gain of the analog signal output by the encoder can also be corrected. Specifically, the encoder calibration circuit described above also includes a signal gain correction circuit. The input terminal of the signal gain correction circuit is connected to the output terminal of the offset adjustment circuit, and is used to obtain the offset-adjusted sine signal and offset-adjusted cosine signal output by the offset adjustment circuit.

[0109] The signal gain correction circuit specifically includes a sine signal gain correction circuit and a cosine signal gain correction circuit. The sine signal gain correction circuit is used to correct the gain of the sine signal after offset adjustment. The cosine signal gain correction circuit is used to correct the gain of the cosine signal after offset adjustment.

[0110] Taking the offset adjustment circuit as an example of the original cosine signal adjustment circuit, the output of the offset adjustment circuit is the offset-adjusted cosine signal Vocos and the original sine signal Vsin. The sine signal gain correction circuit corrects the signal gain of Vsin and outputs the corrected sine signal Vgsin. The cosine signal gain correction circuit corrects the signal gain of Vocos and outputs the corrected cosine signal Vgcos.

[0111] The offset adjustment circuit performs coarse adjustment on the signal through circuit amplification, thereby amplifying the analog signal to near the maximum sampling range of the processor's AD acquisition port. The closer the analog signal is to the maximum sampling range of the AD acquisition port, the more accurate the AD sampling result. The processor then fine-tunes the Vgsin and Vgcos values ​​obtained after coarse adjustment to obtain a more accurate analog signal.

[0112] Figure 5 This is a schematic diagram of the gain correction circuit provided in an embodiment of the present invention. This gain correction circuit is implemented as a gain correction circuit based on the offset adjustment circuit when it is used as an original cosine signal adjustment circuit. Figure 5 As shown, the gain correction circuit comprises a sine signal gain correction circuit 501 and a cosine signal gain correction circuit 502. The sine signal gain correction circuit 501 includes a second operational amplifier, and the cosine signal gain correction circuit 503 includes a third operational amplifier. The output terminals of the offset adjustment circuit specifically include a sine signal output terminal and a cosine signal output terminal.

[0113] The non-inverting input of the second operational amplifier is connected to the sinusoidal signal output of the offset adjustment circuit to obtain the gain-corrected sinusoidal signal (Vsin) output by the offset adjustment circuit. A fifth resistor R5 is connected in series between the sinusoidal signal output and the non-inverting input of the second operational amplifier. The inverting input of the second operational amplifier is connected to ground (GND) through a sixth resistor R6. n sub-circuits are connected in parallel between the inverting input and the output of the second operational amplifier.

[0114] The non-inverting input of the third operational amplifier is connected to the cosine signal output of the offset adjustment circuit to obtain the gain-corrected cosine signal (Vocos) output by the offset adjustment circuit. A seventh resistor R7 is connected in series between the cosine signal output and the non-inverting input of the third operational amplifier. The inverting input of the third operational amplifier is connected to ground (GND) through an eighth resistor R8. n sub-circuits are connected in parallel between the inverting input and the output of the third operational amplifier.

[0115] Each sub-circuit includes an amplifying resistor and a switch connected in series. Figure 5The switches in the sub-circuits shown in the Chinese diagram are specifically implemented using NMOS transistors. The n sub-circuits in the sinusoidal signal gain correction circuit 501 are D(1) to D(n). Sub-circuit D(1) consists of an amplifying resistor R7 and an NMOS transistor Cont(1), sub-circuit D(2) consists of an amplifying resistor R8 and an NMOS transistor Cont(2), and so on. Sub-circuit D(n) consists of an amplifying resistor R(6+n) and an NMOS transistor Cont(n). The resistance values ​​of each resistor from R7 to R(6+n) are all different.

[0116] Similarly, in the cosine signal gain correction circuit 502, the n sub-circuits are D(n+1) to D(2n). Sub-circuit D(n+1) consists of an amplifying resistor R(9+n) and an NMOS transistor Cont(n+1), sub-circuit D(n+2) consists of an amplifying resistor R(10+n) and an NMOS transistor Cont(n+2), and so on, sub-circuit D(2n) consists of an amplifying resistor R(8+2n) and an NMOS transistor Cont(2n). The resistance values ​​of each resistor in R(9+n) to R(8+2n) are different.

[0117] The processor controls the conduction and disconnection of each sub-circuit by controlling the opening and closing of the switches of each sub-circuit, thereby controlling the amplification factor of the second operational amplifier and the third operational amplifier. Specifically, in the sine signal gain correction circuit 501, only one of the n sub-circuits can be active at any given time. Similarly, in the cosine signal gain correction circuit 502, only one of the n sub-circuits can be active at any given time.

[0118] Corresponding to the encoder calibration circuit described above, this embodiment of the invention provides an integrated circuit chip. The integrated circuit chip includes an encoder and the aforementioned encoder calibration circuit. In some embodiments, the encoder calibration circuit is an off-chip integrated circuit. The encoder calibration circuit is connected to the integrated circuit chip via an external chip interface. When the encoder calibration circuit is implemented as an off-chip integrated circuit, performance and storage capacity can be improved by selecting a more suitable chip, thereby enabling the chip to be applied in more complex application scenarios.

[0119] In another embodiment, the encoder calibration circuit can also be an on-chip integrated circuit. The encoder calibration circuit is connected to the integrated circuit chip through an internal chip interface. When the encoder calibration circuit is implemented as an on-chip integrated circuit, it occupies less board space, consumes less power, and is cheaper and easier to integrate, which can meet the requirements of encoder miniaturization.

[0120] Corresponding to the encoder calibration circuit described above, this embodiment of the invention provides an encoder calibration method. Through...

[0121] The encoder calibration is achieved through analog signal comparison circuits, offset adjustment circuits, and the processor's native built-in digital-to-analog conversion function and general purpose input / output (GPIO). Figure 6 This is a flowchart illustrating an encoder calibration method provided in an embodiment of the present invention. Figure 6 As shown, the method includes:

[0122] Step 601: Output a reference signal to the analog signal comparison circuit.

[0123] Specifically, the encoder servo motor can be controlled to rotate at speed n first, and then encoder self-calibration can begin. During constant speed rotation, the encoder servo motor outputs the original sine signal Vsin and the original cosine signal Vcos.

[0124] Then, the processor outputs a reference signal Vref to the analog signal comparison circuit.

[0125] Step 602: Obtain the first comparison result and the second comparison result output by the analog signal comparison circuit.

[0126] Since the angles of Vsin and Vcos are constantly changing, the first comparison result and the second comparison result output by the analog signal comparison circuit are both constantly changing high and low level signals.

[0127] Step 603: Based on the first comparison result and the second comparison result, obtain the maximum value of the original sine signal, the minimum value of the original sine signal, the maximum value of the original cosine signal, and the minimum value of the original cosine signal.

[0128] Among these methods, multiple periods of Vsin and Vcos signals can be acquired to calculate the maximum and minimum values, thereby increasing the accuracy of the measurement results. Figure 7 This is a schematic diagram illustrating the maximum and minimum values ​​of a raw analog signal, provided as an embodiment of the present invention. Figure 7 As shown in the diagram, the horizontal axis represents the angle of the analog signal, and the vertical axis represents the voltage of the analog signal. The reference voltage Vref is a constant signal, and its voltage does not change with the angle. Figure 7 The peaks shown are the maximum values, and the troughs are the minimum values.

[0129] In step 601, while the processor outputs the reference signal Vref to the analog signal comparison circuit, it simultaneously starts Timer 1. The delay of Timer 1 is set to Tn. Tn is related to the speed n of the encoder servo motor. Within Tn time, the encoder needs to output multiple cycles of Vsin and Vcos signals. Assuming the encoder rotates one revolution and outputs y cycles of Vsin or Vcos signals, and 3 cycles of Vsin and Vcos signals need to be acquired within Tn time to measure the maximum and minimum values, then Tn = 3 / (n y).

[0130] During the measurement of the maximum value, the reference signal Vref can be gradually increased until Vref exceeds the peak of the Vsin or Vcos signal, thus obtaining the maximum value of the Vsin or Vcos signal. Specifically, taking the acquisition of the maximum value of the original sine signal as an example, firstly, it is determined whether the first comparison result output by the first comparator is a continuous low level. If the first comparison result output by the first comparator is not a continuous low level, the reference signal output is gradually increased until the first comparison result output by the first comparator is a continuous low level. The increased reference signal is then determined as the maximum value of the original sine signal.

[0131] When the first comparison result is not a continuous low level, it indicates that the reference signal Vref is still between the maximum and minimum values ​​of the analog signal. Since the analog signal is constantly changing, the first comparison result also changes. At the end of the aforementioned Timer 1, the processor determines whether the maximum value has been obtained based on the first comparison result corresponding to the waveforms of the original analog signal over multiple cycles within time Tn. When it is determined that the first comparison result is not a continuous low level, the output Vref is increased by one unit, and Timer 1 is restarted. If a continuous low level is detected in the first comparison result, it indicates that Vref is equal to or slightly higher than the peak of the original analog signal. At this point, it is determined whether Timer 1 has ended. If Timer 1 has not ended, the processor waits for Timer 1 to finish. If Timer 1 has ended, it records that the maximum value of the original analog signal is equal to the current value of the reference signal.

[0132] The process of obtaining the minimum value of an analog signal is the reverse of the process of obtaining the maximum value. It requires gradually decreasing Vref until Vref falls below the trough of the original analog signal. Specifically, taking the process of obtaining the minimum value of the original sine wave as an example: First, the processor determines whether the first comparison result output by the first comparator is a continuous high level. If the first comparison result output by the first comparator is not a continuous high level, the reference signal output is gradually decreased until the first comparison result output by the first comparator becomes a continuous low level. The decreased reference signal is then determined as the minimum value of the original sine wave signal.

[0133] Based on the above steps, obtain the maximum value Vsmax and the minimum value Vsmin of Vsin. Also obtain the maximum value Vcmax and the minimum value Vcmin of Vcos.

[0134] Step 604: Based on the maximum value and minimum value of the original sine signal, obtain the first offset of the original sine signal, and based on the maximum value and minimum value of the original cosine signal, obtain the second offset of the cosine signal.

[0135] Step 605: Determine the first difference between the first offset and the second offset.

[0136] The first difference ΔVo is calculated as follows: ΔVo = (Vsmax - Vsmin) / 2 - (Vcmax - Vcmin) / 2.

[0137] Step 606: Output the first difference to the offset adjustment circuit.

[0138] When ΔVo > 0, it means that the offset of Vsin is greater than the offset of Vcos. Taking the offset adjustment circuit implemented as the original sine signal offset adjustment circuit as an example, the processor's first output port outputs a low-level signal, and the second output port outputs ΔVo, so that the first operational amplifier forms a subtractor, thereby outputting the offset-adjusted Vosin. Wherein, Vosin = Vsin - ΔVo.

[0139] When ΔVo < 0, it means the offset of Vsin is less than the offset of Vcos. Taking the offset adjustment circuit implemented as the original sine signal offset adjustment circuit as an example, the processor's first output port outputs ΔVo, and the second output port outputs a low-level signal, so that the first operational amplifier forms an adder, thereby outputting the offset-adjusted Vosin. Here, Vosin = Vsin + ΔVo. This ensures that the offsets between the sine and cosine signals remain consistent.

[0140] Step 607: Obtain the offset-adjusted sine signal and offset-adjusted cosine signal output by the offset adjustment circuit.

[0141] When the offset adjustment circuit is the original sine signal adjustment circuit, the final obtained sine and cosine signals with equal offsets are Vosin and Vcos. When the offset adjustment circuit is the original cosine signal adjustment circuit, the final obtained sine and cosine signals with equal offsets are Vsin and Vocos.

[0142] In some embodiments, after adjusting the offsets of the original sine and cosine signals using an offset adjustment circuit, gain correction can also be performed. Specifically, the output signal gain correction circuit of the offset-adjusted sine and cosine signals can be used to correct the gain of the offset-adjusted sine and cosine signals. Finally, the gain-corrected sine and cosine signals output by the signal gain correction circuit are obtained.

[0143] Specifically, the signal gain correction circuit adjusts the gain of the offset-adjusted sinusoidal signal by: the processor sequentially controlling the conduction of n sub-circuits of the second operational amplifier to obtain n sinusoidal signals with different amplification factors. Then, the sinusoidal signal with the highest amplification factor among the n sinusoidal signals with different amplification factors, which falls within the gain recognition range, is determined as the target sinusoidal signal. The target sinusoidal signal is then determined as the gain-corrected sinusoidal signal.

[0144] The signal gain correction circuit adjusts the gain of the cosine signal after offset adjustment by: the processor sequentially controlling the conduction of n sub-circuits of the third operational amplifier to obtain n cosine signals with different amplification factors. Then, the sine signal with the highest amplification factor among the n cosine signals with different amplification factors, which falls within the gain recognition range, is selected as the target sine signal. This target sine signal is then determined as the gain-corrected sine signal.

[0145] The processor's ADC accepts input voltages from 0 to VCC. That is, the analog signal sampling range is 0 to VCC. The ADC has a fixed resolution and a fixed sampling voltage accuracy; for example, a 12-bit ADC has a sampling voltage accuracy of VCC. 1 / 2 12 Therefore, in order to obtain a more accurate analog signal voltage, the analog signal needs to be amplified to the maximum extent within the sampling range.

[0146] Specifically, the processor controls the conduction of each sub-circuit sequentially according to its amplification factor, from smallest to largest. After each sub-circuit is activated, the processor determines whether the amplified analog signal exceeds the processor's sampling range. For a cosine signal, this can be determined by checking whether Vref + m × (Vcmax - Vcmin) / 2 is greater than Vcc, and whether Vref - m × (Vcmax - Vcmin) / 2 is less than 0. Here, m is the amplification factor of the currently activated a-th sub-circuit. Vcmax is the peak value of the amplified analog signal, and Vcmin is the trough value of the amplified analog signal. When neither of the above two conditions is met, it means that the amplified analog signal does not exceed the processor's sampling range. Therefore, the a-th sub-circuit is deactivated, and the (a+1)-th sub-circuit is activated.

[0147] When the a-th sub-circuit is turned on, if the peak value of the amplified analog signal just exceeds Vcc (i.e., Vref+m×(Vcmax-Vcmin) / 2 is greater than Vcc), or if the trough value of the amplified analog signal is just less than 0 (i.e., Vref-m×(Vcmax-Vcmin) / 2 is less than 0), it indicates that the amplified analog signal exceeds the processor's sampling range. Therefore, the amplification factor corresponding to the (a-1)-th sub-circuit is the maximum amplification factor within the processor's sampling range. Therefore, the processor controls the NMOS transistor corresponding to the (a-1)-th sub-circuit to be turned on, and the NMOS transistors corresponding to the other sub-circuits are turned off. Specifically, the processor's Cont(1) pin to Cont(n) pins correspond one-to-one with the 1st to nth sub-circuits. The processor controls the Cont(a-1) pin to output a high-level signal. All other pins from the Cont(1) pin to the Cont(n) pin except for the Cont(a-1) pin output a low level. Thus, the analog signal with the highest amplification factor within the processor's sampling range can be obtained.

[0148] Specifically, Figure 8 This invention provides a hardware block diagram of an encoder calibration circuit. Figure 8 The hardware block diagram of the encoder calibration circuit shown is a hardware block diagram of a scenario where the offset adjustment circuit is implemented as an offset adjustment circuit for the original cosine signal. Figure 8 As shown, the encoder outputs the original sine signal Vsin and the original cosine signal Vcos to the analog signal comparison circuit 801. The processor's DAC outputs the reference signal Vref to the analog signal comparison circuit through DACout1. The analog signal comparison circuit outputs the first comparison result OUT1 between Vsin and Vref to the processor's GPIO (1) port. It also outputs the second comparison result OUT2 between Vcos and Vref to the processor's GPIO (2) port.

[0149] The processor obtains a first difference ΔV0 between the offsets of Vsin and Vcos based on the first comparison result and the second comparison result, and outputs the first difference ΔV0 to the original cosine signal offset adjustment circuit 802 through the first output port DACout2 and the second output port DACout3. The original cosine signal offset adjustment circuit 802 adjusts the offset of Vcos according to the ΔV0 output by the processor, and outputs the offset-adjusted cosine signal Vocos to the cosine signal gain correction circuit 803. The cosine signal gain correction circuit 803 amplifies the signal gain of Vocos based on one of the n sub-circuits, and outputs Vgcos to the processor. The processor controls the on and off of the n sub-circuits in the cosine signal gain correction circuit 803 through the GPIO (3) to GPIO (3+n) ports.

[0150] The sinusoidal signal gain correction circuit 804 amplifies the signal gain of the encoder output Vsin based on one of the n sub-circuits, and then outputs Vgsin to the processor. The processor controls the on and off of the n sub-circuits in the sinusoidal signal gain correction circuit 804 through GPIO (4+n) to GPIO (4+2n) ports.

[0151] Finally, the processor obtains the coarsely adjusted Vgcos output by the cosine signal gain correction circuit 803 and the coarsely adjusted Vgsin output by the sine signal gain correction circuit 804 through the ADC port.

[0152] In some embodiments, since the encoder angle is calculated using the arctangent ATAN(Vgsin / Vgcos), if the ratio Φg=(Vsmax-Vsmin) / (Vcmax-Vcmin) between the peak-to-peak values ​​of the sine signal Vsmax-Vsmin and the cosine signal Vcmax-Vcmin is not equal to 1, then the angle value ATAN(Vgsin / Vgcos) will have a deviation. If the peak-to-peak ratio adjustment only uses the aforementioned analog operational amplifier circuit (signal gain correction circuit), it requires resistors with appropriate resistance ratios and high precision, as well as a larger number of sub-circuits. Pure circuit adjustment is costly. Therefore, the peak-to-peak ratio Φg needs to be adjusted via software.

[0153] Specifically, the first peak-to-peak value of the gain-corrected sine signal output by the gain correction circuit and the second peak-to-peak value of the gain-corrected cosine signal output by the gain correction circuit are determined. It is then determined whether the first and second peak-to-peak values ​​are equal. If they are not equal, a secondary calibration is performed on either the gain-corrected sine signal or the gain-corrected cosine signal output by the gain correction circuit to obtain target sine and cosine signals with equal peak-to-peak values. Taking Vgsin adjustment as an example, the processor takes the Vgsin signal sampled by the ADC and output by the gain correction circuit, and uses the formula Vgsin × Φg to obtain the final secondary-corrected signal Vggsin.

[0154] This specification provides a computer program product, which includes a computer program that, when executed by a processor, performs the functions described in this specification. Figure 6 The encoder calibration method provided in the illustrated embodiment.

[0155] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0156] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0157] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this specification, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0158] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this specification includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which the embodiments of this specification pertain.

[0159] Depending on the context, the word "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if detection (of the stated condition or event)" can be interpreted as "when determination," "in response to determination," "when detection (of the stated condition or event)," or "in response to detection (of the stated condition or event)."

[0160] It should be noted that the devices involved in the embodiments of this specification may include, but are not limited to, personal computers (PCs), personal digital assistants (PDAs), wireless handheld devices, tablet computers, mobile phones, MP3 displays, MP4 displays, etc.

[0161] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0162] Furthermore, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.

[0163] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, a connector, or a network device, etc.) or a processor to execute some steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0164] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

[0165] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the device embodiments and terminal embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

Claims

1. An encoder calibration circuit, comprising: include: Analog signal comparison circuit and offset adjustment circuit; The input terminals of the analog signal comparison circuit are respectively connected to the reference signal output terminals of the signal source and the processor, and are used to compare the magnitude of the reference signal output by the processor with the magnitude of the original sine signal output by the signal source, and output a first comparison result through the output terminal; and compare the magnitude of the reference signal with the magnitude of the original cosine signal output by the signal source, and output a second comparison result through the output terminal. The processor's input terminal is connected to the output terminal of the analog signal comparison circuit, and is used to obtain the first comparison result and the second comparison result, and to obtain the maximum value, minimum value, maximum value, and minimum value of the original sine signal based on the first comparison result and the second comparison result. And, based on the maximum value of the original sine signal, the minimum value of the original sine signal, the maximum value of the original cosine signal, and the minimum value of the original cosine signal, a first difference between the offset of the original sine signal and the offset of the original cosine signal is obtained; The processor's output terminal is connected to the input terminal of the offset adjustment circuit, and is used to output the first difference to the offset adjustment circuit; The offset adjustment circuit adjusts the offset of the original sine signal and the original cosine signal based on the first difference, and outputs the offset-adjusted sine signal and the offset-adjusted cosine signal. The analog signal comparison circuit specifically includes a raw sine signal comparison circuit and a raw cosine signal comparison circuit, and the signal source includes a raw sine signal output terminal and a raw cosine signal output terminal. The original sine wave signal comparison circuit includes a first comparator; the non-inverting input of the first comparator is connected to the original sine wave signal output of the signal source, and the inverting input of the first comparator is connected to the reference signal output of the processor. The original cosine signal comparison circuit includes a second comparator; the non-inverting input of the second comparator is connected to the original cosine signal output of the signal source, and the inverting input of the second comparator is connected to the reference signal output of the processor.

2. The circuit of claim 1, wherein, The offset adjustment circuit is an original sine wave signal offset adjustment circuit. The original sine wave signal offset adjustment circuit adjusts the offset of the original sine wave signal according to the first difference and outputs the offset-adjusted sine wave signal.

3. The circuit of claim 2, wherein, The processor's output terminals specifically include a first output port and a second output port, and the signal source includes an original sine signal output terminal and an original cosine signal output terminal. The original sinusoidal signal offset adjustment circuit includes a first operational amplifier; The processor's first output port is connected to the non-inverting input of the first operational amplifier, and a first resistor is connected in series between the first output port and the non-inverting input of the first operational amplifier. The noninverted input end of the first operational amplifier is also connected with the original sine signal output end of the signal source, and a second resistor is connected in series between the original sine signal output end and the noninverted input end of the first operational amplifier; The second output port of the processor is connected with the inverted input end of the first operational amplifier, and a third resistor is connected in series between the second output port and the noninverted input end of the first operational amplifier; The inverted input end of the first operational amplifier is also connected with the output end of the first operational amplifier through a fourth resistor; When the offset of the original sine signal is less than the offset of the original cosine signal, the first output port of the processor outputs the first difference value, the second output port outputs a low-level signal, and the output of the first operational amplifier is the sum of the original sine signal and the first difference value; When the offset of the original sine signal is greater than the offset of the original cosine signal, the first output port of the processor outputs a low-level signal, the second output port outputs the first difference value, and the output of the first operational amplifier is the difference between the original sine signal and the first difference value.

4. The circuit of claim 1, wherein, The offset adjustment circuit is an original cosine signal offset adjustment circuit, which adjusts the offset of the original cosine signal according to the first difference value and outputs the cosine signal after the offset is adjusted.

5. The circuit of claim 4, wherein, The processor is provided with a first output port and a second output port, and the signal source includes an original sine signal output end and an original cosine signal output end; The original cosine signal offset adjustment circuit includes a first operational amplifier; The first output port of the processor is connected with the noninverted input end of the first operational amplifier, and a first resistor is connected in series between the first output port and the noninverted input end of the first operational amplifier; The noninverted input end of the first operational amplifier is also connected with the original cosine signal output end of the signal source, and a second resistor is connected in series between the original cosine signal and the noninverted input end of the first operational amplifier; The second output port of the processor is connected with the inverted input end of the first operational amplifier, and a third resistor is connected in series between the second output port and the noninverted input end of the first operational amplifier; The inverted input end of the first operational amplifier is also connected with the output end of the first operational amplifier through a fourth resistor; When the offset of the original cosine signal is less than the offset of the original sine signal, the first output port of the processor outputs the first difference value, the second output port outputs a low-level signal, and the output of the first operational amplifier is the sum of the original cosine signal and the first difference value; When the offset of the original cosine signal is greater than the offset of the original sine signal, the first output port of the processor outputs a low-level signal, the second output port outputs the first difference value, and the output of the first operational amplifier is the difference between the original cosine signal and the first difference value.

6. The circuit of claim 1, wherein Further comprising: a signal gain correction circuit; An input end of the signal gain correction circuit is connected with an output end of the offset adjustment circuit, for obtaining the offset-adjusted sine signal and the offset-adjusted cosine signal output by the offset adjustment circuit; The signal gain correction circuit specifically comprises a sine signal gain correction circuit and a cosine signal gain correction circuit; The sine signal gain correction circuit is used for correcting the gain of the offset-adjusted sine signal; The cosine signal gain correction circuit is used for correcting the gain of the offset-adjusted cosine signal.

7. The circuit of claim 6, wherein, The sine signal gain correction circuit comprises a second operational amplifier, and the cosine signal gain correction circuit comprises a third operational amplifier; the output end of the offset adjustment circuit specifically comprises a sine signal output end and a cosine signal output end; The noninverting input end of the second operational amplifier is connected with the sine signal output end of the offset adjustment circuit, for obtaining the gain-corrected sine signal output by the offset adjustment circuit, and a fifth resistor is connected in series between the sine signal output end and the noninverting input end of the second operational amplifier; the inverting input end of the second operational amplifier is connected with a grounding end through a sixth resistor; n sub-circuits are connected in parallel between the inverting input end of the second operational amplifier and the output end of the second operational amplifier; The noninverting input end of the third operational amplifier is connected with the cosine signal output end of the offset adjustment circuit, for obtaining the gain-corrected cosine signal output by the offset adjustment circuit, and a seventh resistor is connected in series between the cosine signal output end and the noninverting input end of the third operational amplifier; the inverting input end of the third operational amplifier is connected with a grounding end through an eighth resistor; n sub-circuits are connected in parallel between the inverting input end of the third operational amplifier and the output end of the third operational amplifier; Each of the sub-circuits comprises an amplification resistor and a switch connected in series; the processor controls the on and off of each sub-circuit by controlling the closing and opening of the switch of each sub-circuit, thereby controlling the amplification multiple of the second operational amplifier and the amplification multiple of the third operational amplifier.

8. An integrated circuit chip, characterized by The integrated circuit chip comprises an encoder and the encoder calibration circuit according to any one of claims 1 to 7.

9. The integrated circuit chip of claim 8, wherein, The encoder calibration circuit is an on-chip integrated circuit; the encoder calibration circuit is connected with the integrated circuit chip through an on-chip interface.

10. The integrated circuit chip of claim 8, wherein, The encoder calibration circuit is an off-chip integrated circuit; the encoder calibration circuit is connected with the integrated circuit chip through an off-chip interface.

11. An encoder calibration method, characterized by, The encoder calibration circuit according to any one of claims 1 to 7 comprises: outputting a reference signal to the analog signal comparison circuit; obtaining a first comparison result and a second comparison result output by the analog signal comparison circuit; obtaining a maximum value of the original sine signal, a minimum value of the original sine signal, a maximum value of the original cosine signal and a minimum value of the original cosine signal according to the first comparison result and the second comparison result; obtaining a first offset of the original sine signal based on the maximum value of the original sine signal and the minimum value of the original sine signal, and obtaining a second offset of the original cosine signal based on the maximum value of the original cosine signal and the minimum value of the original cosine signal; determining a first difference between the first offset and the second offset; outputting the first difference to the offset adjustment circuit; obtaining the offset-adjusted sine signal and the offset-adjusted cosine signal output by the offset adjustment circuit.

12. The method of claim 11, wherein, obtaining the maximum value of the original sine signal according to the first comparison result, comprising: determining whether the first comparison result output by the first comparator is a persistent low level; if the first comparison result output by the first comparator is not a persistent low level, gradually increasing the output reference signal until the first comparison result output by the first comparator becomes a persistent low level; determining the increased reference signal as the maximum value of the original sine signal.

13. The method of claim 11, wherein, obtaining the minimum value of the original sine signal according to the first comparison result, comprising: determining whether the first comparison result output by the first comparator is a persistent high level; if the first comparison result output by the first comparator is not a persistent high level, gradually decreasing the output reference signal until the first comparison result output by the first comparator becomes a persistent low level; determining the decreased reference signal as the minimum value of the original sine signal.

14. The method of claim 11, wherein, The method further comprises: inputting the offset-adjusted sine signal and the offset-adjusted cosine signal into a signal gain correction circuit to correct the gain of the offset-adjusted sine signal and the gain of the offset-adjusted cosine signal; obtaining the gain-corrected sine signal and the gain-corrected cosine signal output by the signal gain correction circuit.

15. The method of claim 14, wherein, adjusting the gain of the offset-adjusted sine signal, comprising: controlling n sub-circuits of the signal gain correction circuit to be turned on in sequence to obtain n sine signals with different amplification multiples; determining a sine signal with the largest amplification multiple in a gain identification range from the n sine signals with different amplification multiples as a target sine signal; determining the target sine signal as the gain-corrected sine signal.

16. The method of claim 14, wherein, The method further comprises: determining a first peak-to-peak value of the gain-corrected sine signal output by the gain correction circuit and a second peak-to-peak value of the gain-corrected cosine signal output by the gain correction circuit; determining whether the first peak-to-peak value and the second peak-to-peak value are equal; if the first peak-to-peak value and the second peak-to-peak value are not equal, performing secondary calibration on the gain-corrected sine signal output by the gain correction circuit or the gain-corrected cosine signal output by the gain correction circuit to obtain target sine signal and target cosine signal with equal first peak-to-peak value and second peak-to-peak value.

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