Signal generation circuit, signal generation method, electronic apparatus, and storage medium

Abstract

The embodiment of the invention provides a signal generation circuit, a signal generation method, electronic equipment and a storage medium. The signal generation circuit comprises a clock module, a control module and a frequency division module, the clock module is used for generating a first clock signal based on an input reference clock signal, and the first clock signal is at least used for generating a working clock signal of the control module; the control module is used for sending a first frequency division reset signal to the frequency division module and triggering starting of a timer associated with the first frequency division reset signal in the control module, and the timer carries out timing based on the work clock signal; the frequency division module is used for performing frequency division on an input clock signal based on the first frequency division reset signal so as to output a frequency division signal, and the input clock signal is generated based on the first clock signal; and the first frequency division reset signal is used for controlling the interval between the starting moment of the frequency division signal output by the frequency division module and the starting moment of the timer for a first preset duration.

Description

Technical Field

[0001] The present invention relates to the technical field of signal measurement, and particularly to a signal generation circuit, a signal generation method, an electronic device, and a storage medium. Background Art

[0002] In some application scenarios, devices usually need to perform time delay calibration, multi-channel synchronization calibration, etc. every time they are powered on. Usually, after the device is powered on, through a series of calibrations, the time relationships between various channels and between various modules of the device can meet the corresponding index requirements of the device. For example, for a signal source device, after each power-on, it is required that the time delay from trigger to output remains a fixed value, and the deviation of the time delay change is less than 10 ps. Calibration signals are usually used for calibration between various channels and / or between various modules. How to generate a calibration signal having a fixed phase relationship with the working clock of the control module and improve the calibration accuracy is an urgent problem to be solved. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a signal generation circuit, a signal generation method, an electronic device, and a storage medium.

[0004] According to a first aspect of the embodiments of the present disclosure, a signal generation circuit is proposed. The signal generation circuit includes: a clock module, a control module, and a frequency division module, where

[0005] The clock module is configured to generate a first clock signal based on an input reference clock signal, where the first clock signal is at least used to generate the working clock signal of the control module;

[0006] The control module is configured to send a first frequency division reset signal to the frequency division module and trigger the start of a timer associated with the first frequency division reset signal in the control module, where the timer counts based on the working clock signal;

[0007] The frequency division module is configured to divide the input clock signal based on the first frequency division reset signal to output a frequency division signal, where the input clock signal is generated based on the first clock signal; the first frequency division reset signal is used to control the start time of the output of the frequency division signal by the frequency division module and the start time of the timer to be separated by a first predetermined duration.

[0008] In some embodiments, the signal generation circuit further includes: a low-pass filter, configured to perform low-pass filtering on the frequency division signal to obtain a calibration signal, where the start time of the calibration signal and the start time of the timer are separated by a second predetermined duration.

[0009] In some embodiments, the signal generation circuit further includes: a first clock buffer; the control module includes: a first synchronous reset control module and a signal delay sub-module; the frequency division module includes a first frequency divider;

[0010] The first clock buffer is configured to generate the working clock signal and the input clock signal based on the first clock signal;

[0011] The first synchronous reset control module is configured to send the first frequency division reset signal to the frequency division module;

[0012] The signal delay sub-module is configured to delay the first frequency division reset signal by a predetermined delay duration to obtain a second frequency division reset signal, so that the second frequency division reset signal meets the setup time of a predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0013] The first frequency divider is configured to be triggered by the second frequency division reset signal at the predetermined trigger edge and generate the frequency division signal based on the input clock signal.

[0014] In some embodiments, the signal generation circuit further includes: a second clock buffer; the control module includes: a phase adjustment module and a second synchronous reset control module; the frequency division module includes a second frequency divider;

[0015] The second clock buffer is configured to generate a second clock signal and the input clock signal based on the first clock signal;

[0016] The second synchronous reset control module is configured to generate a first frequency division reset signal based on the working clock signal;

[0017] The phase adjustment module is configured to adjust the phase of the second clock signal to obtain the working clock signal, so that the first frequency division reset signal triggered based on the working clock signal meets the setup time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0018] The second frequency divider is configured to be triggered by the first frequency division reset signal at the predetermined trigger edge and generate the frequency division signal based on the input clock signal.

[0019] In some embodiments, the first clock signal includes the working clock signal; the frequency division module includes a counting frequency divider; the control module includes: a third synchronous reset control module and the counting frequency divider; the working clock signal is used to be input into the counting frequency divider as the input clock signal;

[0020] The third synchronous reset control module is configured to generate a first divided-frequency reset signal based on the working clock signal;

[0021] The start time includes a predetermined edge of the working clock signal after the generation time of the first divided-frequency reset signal;

[0022] The counting frequency divider is configured to be triggered by the first divided-frequency reset signal at the predetermined edge, count the working clock signal from the predetermined edge, and generate the divided-frequency signal based on the counting result of the counting.

[0023] According to a second aspect of the embodiments of the present disclosure, a signal generation method is provided, which is applied to a signal generation circuit. The signal generation circuit includes: a clock module, a control module, and a frequency division module. The method includes:

[0024] Generating, by the clock module, a first clock signal based on an input reference clock signal, where the first clock signal is at least used to generate the working clock signal of the control module;

[0025] Sending, by the control module, a first divided-frequency reset signal to the frequency division module, and triggering the start of a timer associated with the first divided-frequency reset signal in the control module, where the timer is timed based on the working clock signal;

[0026] Dividing, by the frequency division module, an input clock signal based on the first divided-frequency reset signal to output a divided-frequency signal, where the input clock signal is generated based on the first clock signal; the first divided-frequency reset signal is used to control that the start time of the divided-frequency signal output by the frequency division module and the start time of the timer are separated by a first predetermined duration.

[0027] In some embodiments, the signal generation circuit further includes: a low-pass filter;

[0028] The method further includes: performing low-pass filtering on the divided-frequency signal by the low-pass filter to obtain a calibration signal, where the start time of the calibration signal and the start time of the timer are separated by a second predetermined duration.

[0029] In some embodiments, the signal generation circuit further includes: a first clock buffer; the control module includes: a first synchronous reset control module and a signal delay sub-module; the frequency division module includes a first frequency divider; the method further includes:

[0030] Generating, by the first clock buffer, the working clock signal and the input clock signal based on the first clock signal;

[0031] Send the first frequency division reset signal to the frequency division module through the first synchronous reset control module;

[0032] Delay the first frequency division reset signal by a predetermined duration through the signal delay sub-module to obtain a second frequency division reset signal, so that the second frequency division reset signal meets the setup time of a predetermined trigger edge of the input clock signal, where the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0033] Trigger the first frequency divider at the predetermined trigger edge by the second frequency division reset signal to generate the frequency division signal based on the input clock signal.

[0034] In some embodiments, the signal generation circuit further includes: a second clock buffer; the control module includes: a phase adjustment module and a second synchronous reset control module; the frequency division module includes a second frequency divider;

[0035] The method further includes:

[0036] Generate a second clock signal and the input clock signal based on the first clock signal through the second clock buffer;

[0037] Generate a first frequency division reset signal based on the working clock signal through the second synchronous reset control module;

[0038] Adjust the phase of the second clock signal through the phase adjustment module to obtain the working clock signal, so that the first frequency division reset signal triggered based on the working clock signal meets the setup time of a predetermined trigger edge of the input clock signal, where the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0039] Trigger the second frequency divider at the predetermined trigger edge by the first frequency division reset signal to generate the frequency division signal based on the input clock signal.

[0040] In some embodiments, the first clock signal includes the working clock signal; the frequency division module includes a counting frequency divider; the control module includes: a third synchronous reset control module and the counting frequency divider; the working clock signal is used to input the counting frequency divider as the input clock signal;

[0041] The method further includes:

[0042] Generate a first frequency division reset signal based on the working clock signal through the third synchronous reset control module; the start time includes a predetermined edge of the working clock signal after the generation time of the first frequency division reset signal;

[0043] Triggered by the first frequency division reset signal at the predetermined edge through the counting frequency divider, the working clock signal is counted starting from the predetermined edge, and the frequency division signal is generated based on the counting result of the counting.

[0044] According to the third aspect of the embodiments of the present disclosure, an electronic device is provided, including the signal generation circuit as described in the first aspect.

[0045] According to the fourth aspect of the embodiments of the present disclosure, an electronic device is provided, including a processor, a memory, and an executable program stored on the memory and capable of being run by the processor. When the processor runs the executable program, it executes the steps of the signal generation method as described in the second aspect.

[0046] According to the fifth aspect of the embodiments of the present disclosure, a storage medium is provided, on which an executable program is stored. When the executable program is executed by a processor, it implements the steps of the signal generation method as described in the second aspect.

[0047] The embodiments of the present disclosure provide a signal generation circuit, a signal generation method, an electronic device, and a storage medium. The signal generation circuit includes: a clock module, a control module, and a frequency division module. Among them, the clock module is used to generate a first clock signal based on an input reference clock signal, where the first clock signal is at least used to generate the working clock signal of the control module; the control module is used to send a first frequency division reset signal to the frequency division module and trigger the start of a timer associated with the first frequency division reset signal in the control module, where the timer is timed based on the working clock signal; the frequency division module is used to divide the input clock signal based on the first frequency division reset signal to output a frequency division signal, where the input clock signal is generated based on the first clock signal; the first frequency division reset signal is used to control the start time of the frequency division signal output by the frequency division module and the start time of the timer to be separated by a first predetermined duration. In this way, based on the first frequency division reset signal, the adjustment of the start time of the frequency division signal is realized, and the corresponding relationship between the first frequency division reset signal and the start time of the timer is used to determine the control of the duration between the start time of the frequency division signal and the start time of the timer, so that the frequency division signal can be used for time delay calibration comparison, and further the calibration of the signal to be calibrated is realized. Description of the Drawings

[0048] Figure 1 is a schematic structural diagram of a signal generation device shown according to an exemplary embodiment;

[0049] Figure 2 is a schematic signal generation timing diagram shown according to an exemplary embodiment;

[0050] Figure 3It is a schematic structural diagram of another signal generation device shown according to an exemplary embodiment;

[0051] Figure 4 It is a schematic timing diagram of another signal generation shown according to an exemplary embodiment;

[0052] Figure 5 It is a schematic flowchart of a signal generation method shown according to an exemplary embodiment;

[0053] Figure 6 It is a schematic structural diagram of yet another signal generation device shown according to an exemplary embodiment;

[0054] Figure 7 It is a schematic timing diagram of yet another signal generation shown according to an exemplary embodiment;

[0055] Figure 8 It is a schematic flowchart of another signal generation method shown according to an exemplary embodiment;

[0056] Figure 9 It is a schematic structural diagram of still another signal generation device shown according to an exemplary embodiment;

[0057] Figure 10 It is a schematic timing diagram of still another signal generation shown according to an exemplary embodiment;

[0058] Figure 11 It is a schematic flowchart of yet another signal generation method shown according to an exemplary embodiment;

[0059] Figure 12 It is a schematic flowchart of still another signal generation method shown according to an exemplary embodiment. Detailed implementation manners

[0060] To make the technical solutions and beneficial effects of the present invention more obvious and understandable, the following will be described in detail by listing specific embodiments. Among them, the drawings are not necessarily drawn to scale, and local features can be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical and scientific fields to which this application belongs.

[0061] The embodiments of the present disclosure are not exhaustive. They are only schematic illustrations of some embodiments and do not specifically limit the protection scope of the present disclosure. Without contradiction, each step in an embodiment can be implemented as an independent embodiment, and the steps can be combined arbitrarily. For example, the solution after removing some steps in an embodiment can also be implemented as an independent embodiment, and the order of the steps in an embodiment can be exchanged arbitrarily. Additionally, the optional implementation manners in an embodiment can be combined arbitrarily; moreover, the embodiments can be combined arbitrarily. For example, some or all of the steps of different embodiments can be combined arbitrarily, and an embodiment can be combined arbitrarily with the optional implementation manners of other embodiments.

[0062] In each embodiment of the present disclosure, without special instructions and logical conflicts, the terms and / or descriptions among the embodiments are consistent and can be cited mutually. The technical features in different embodiments can be combined to form new embodiments according to their internal logical relationships.

[0063] The terms used in the embodiments of the present disclosure are only for the purpose of describing specific embodiments and are not intended as a limitation on the present disclosure.

[0064] In the embodiments of the present disclosure, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above-mentioned", "the foregoing", "this", etc., can mean "one and only one", or can also mean "one or more", "at least one", etc. For example, in the case of using articles such as "a", "an", "the" in English translation, the noun after the article can be understood as a singular expression form or a plural expression form.

[0065] In the embodiments of the present disclosure, "a plurality of" means two or more.

[0066] In some embodiments, terms such as "at least one (at least one, at least one item, at least one)", "one or more", "a plurality of", "multiple", etc. can be replaced with each other.

[0067] In some embodiments, notations such as "at least one of A and B", "A and / or B", "in one case A, in another case B", "one case A, another case B", etc. may, depending on the circumstances, include the following technical solutions: In some embodiments, A (A is executed independently of B); in some embodiments, B (B is executed independently of A); in some embodiments, one is selected from A and B for execution (A and B are selectively executed); in some embodiments, both A and B (both A and B are executed). The same applies when there are more branches such as A, B, C, etc.

[0068] In some embodiments, notations such as "A or B" may, depending on the circumstances, include the following technical solutions: In some embodiments, A (A is executed independently of B); in some embodiments, B (B is executed independently of A); in some embodiments, one is selected from A and B for execution (A and B are selectively executed). The same applies when there are more branches such as A, B, C, etc.

[0069] Prefix words such as "first", "second", etc. in the embodiments of the present disclosure are only used to distinguish different described objects, and do not constitute limitations on the position, order, priority, value, or content of the described objects. For the statements of the described objects, refer to the descriptions in the claims or the context of the embodiments. There should be no redundant limitations due to the use of prefix words. For example, if the described object is "field", the ordinal numbers before "field" in "first field" and "second field" do not limit the position or order between the "fields", and "first" and "second" do not limit whether the "fields" they modify are in the same message, nor do they limit the order of "first field" and "second field". Another example, if the described object is "level", the ordinal numbers before "level" in "first level" and "second level" do not limit the priority between the "levels". Another example, the value of the described object is not limited by the ordinal number and can be one or more. Taking "first device" as an example, the value of "device" can be one or more. In addition, the objects modified by different prefix words can be the same or different. For example, if the described object is "device", "first device" and "second device" can be the same device or different devices, and their types can be the same or different; another example, if the described object is "information", "first information" and "second information" can be the same information or different information, and their contents can be the same or different.

[0070] In some embodiments, "including A", "containing A", "for indicating A", "carrying A" can be interpreted as directly carrying A or as indirectly indicating A.

[0071] In some embodiments, terms such as "...", "determining...", "in the case of...", "when...", "when...", "if...", "if..." can be mutually replaced.

[0072] In some embodiments, terms such as "greater than", "greater than or equal to", "not less than", "more than", "more than or equal to", "not less than", "higher than", "higher than or equal to", "not lower than", "above", etc. may be interchangeable, and terms such as "less than", "less than or equal to", "not greater than", "less than", "less than or equal to", "not more than", "lower than", "lower than or equal to", "not higher than", "below", etc. may be interchangeable.

[0073] In some embodiments, a device or the like may be interpreted as physical or virtual, and its name is not limited to the name described in the embodiments. Terms such as "device", "equipment", "device", "circuit", "network element", "node", "function", "unit", "section", "system", "network", "chip", "chip system", "entity", "subject", etc. may be interchangeable.

[0074] In addition, each element, each row, or each column in the table of the embodiments of the present disclosure may be implemented as an independent embodiment, and any combination of any element, any row, or any column may also be implemented as an independent embodiment.

[0075] Figure 1 A signal generation circuit shown according to an embodiment of the present disclosure, the signal generation circuit includes: a clock module, a control module, and a frequency division module, wherein,

[0076] The clock module is configured to generate a first clock signal based on an input reference clock signal, wherein the first clock signal is at least used to generate a working clock signal of the control module;

[0077] The control module is configured to send a first frequency division reset signal to the frequency division module and trigger the start of a timer associated with the first frequency division reset signal in the control module, wherein the timer counts based on the working clock signal;

[0078] The frequency division module is configured to divide an input clock signal based on the first frequency division reset signal to output a frequency division signal, wherein the input clock signal is generated based on the first clock signal; the first frequency division reset signal is used to control that the start time of the frequency division signal output by the frequency division module and the start time of the timer are separated by a first predetermined duration.

[0079] In a possible implementation manner, the signal generation circuit may be implemented by an integrated circuit or may be implemented by a combination of at least one integrated circuit and at least one discrete component.

[0080] Here, the signal generation circuit can be applied to signal source electronic devices such as arbitrary waveform generators (AWGs), arbitrary waveform / function generators (AFGs), i.e., signal sources, RF signal sources, vector signal sources, etc., and can also be applied to electronic devices such as oscilloscopes and spectrum analyzers. The signal generation circuit can exist in the form of an independent functional module, such as an independent functional module in a PXIe architecture; it can also be combined with other functional circuits to achieve composite functions. For example, the signal generation circuit and an analog-to-digital converter (ADC) circuit are located on the same board to provide a specific signal to the ADC circuit.

[0081] Here, the reference clock signal can be a clock signal generated by a reference clock signal source. For example, the reference clock signal can be a crystal oscillator clock signal or a clock signal sent from the main board to each functional module board in a PXIe architecture.

[0082] The control module can be implemented by components with signal processing capabilities and / or data calculation and processing capabilities such as field programmable gate arrays (FPGAs). The control module can also be implemented by a micro processing unit (MCU), etc.

[0083] The clock module is used to perform at least one of buffering and frequency dividing the reference clock to generate clock signals with frequencies required for the operation of each module.

[0084] In a possible implementation, the first clock signal is used to generate at least one of a working clock signal and an input clock signal. For example, the first clock signal can generate a working clock signal and an input clock signal through fan-out or other means.

[0085] Here, the control module can control the reset and / or frequency division operation of the frequency division module through a reset signal. For example, the control module can control the frequency division module to enter the reset state and perform the frequency division operation through the two level states of the reset signal. The first frequency division reset signal can be a level that triggers the frequency division module to perform frequency division on the input clock signal. As Figure 2 shown, the first frequency division reset signal is Figure 2 the low level state of the reset signal in

[0086] In a possible implementation, the frequency division module is in a reset state before performing frequency division on the input clock signal.

[0087] In a possible implementation, the first frequency division reset signal is edge-triggered based on the working level.

[0088] In a possible implementation, the control module triggering the start of the timer associated with the first frequency division reset signal in the control module may include: the control module triggering the timer at a predetermined edge (rising edge or falling edge) of the working clock signal after the first frequency division reset signal is generated.

[0089] In a possible implementation, the predetermined edge is the first rising edge after the starting moment of the first frequency division reset signal (as Figure 2 indicated by arrow A).

[0090] In a possible implementation, the starting moment of the timer (as Figure 2 indicated by arrow B) is the edge moment of the predetermined edge of the working clock signal.

[0091] Since the timer counts time based on the working clock signal, the timing result of the timer is synchronized with the working clock signal. For example, for each cycle of the working clock signal, the timer counts once.

[0092] The working clock signal and the input clock signal are both generated from the first clock signal, so the working clock signal and the input clock signal have an associated relationship. In a possible implementation, the working clock signal and the input clock signal have a fixed phase difference.

[0093] In a possible implementation, the starting moment of the frequency division signal output by the frequency division module can be adjusted by adjusting the time domain position of the starting moment of the first frequency division reset signal. For example, the frequency division module can be triggered by the first frequency division reset signal at the edge of the input clock signal to output the frequency division signal. Therefore, based on the time domain position of the starting moment of the first frequency division reset signal and the time domain position of the edge of the input clock signal, the starting moment when the frequency division module triggers and outputs the frequency division signal based on the first frequency division reset signal can be determined. Since the working clock signal and the input clock signal have a fixed phase difference, the time interval between the starting moment of the frequency division signal triggered based on the input clock signal and the starting moment of the timer is fixed, that is, the time interval between the starting moment of the frequency division signal and the starting moment of the timer can be determined, that is, the first predetermined duration (as Figure 2 shown as T1).

[0094] Since the time interval between the start time of the divided-frequency signal and the start time of the timer, i.e., the first predetermined duration, is known, that is, the phase difference between the start time of the divided-frequency signal and the working clock is known (for example, the phase difference between the start time of the divided-frequency signal and the predetermined edge of the working clock is known), therefore, the divided-frequency signal can be used for time-delay comparison. For example, by comparing the signal to be calibrated with the divided-frequency signal to determine the time interval between the signal to be calibrated and the start time of the timer, and then determining the time delay of the signal to be calibrated relative to the start time of the timer.

[0095] In a possible implementation, the frequency division module can be used to divide the input clock signal by N to output a divided-frequency signal. Wherein, N is a positive integer greater than or equal to 1.

[0096] In this way, based on the first frequency division reset signal to adjust the start time of the divided-frequency signal and the corresponding relationship between the first frequency division reset signal and the start time of the timer, determine the control of the time interval between the start time of the divided-frequency signal and the start time of the timer, so that the divided-frequency signal can be used for time-delay calibration comparison, and then realize the calibration of the signal to be calibrated.

[0097] In some embodiments, as Figure 1 shown, the signal generation circuit further includes: a low-pass filter for performing low-pass filtering on the divided-frequency signal to obtain a calibration signal, wherein the start time of the calibration signal is separated from the start time of the timer by a second predetermined duration.

[0098] As Figure 2 shown, the divided-frequency signal obtained after passing through the frequency division module is approximately a square wave and has high-frequency harmonic components. Here, filtering can be performed through a low-pass filter to obtain a smooth calibration signal, thereby improving the accuracy of phase calculation. The low-pass filter can be set based on the frequency of the divided-frequency signal to filter out harmonic components with frequencies higher than that of the divided-frequency signal.

[0099] As Figure 2 shown, there is a filtering time delay when the low-pass filter performs filtering ( Figure 2 shown as T2 in Figure 2 ), so the second predetermined duration ( shown as T in

[0100]

[0101] In some embodiments, as Figure 3As shown, the signal generation circuit further includes: a first clock buffer; the control module includes: a first synchronous reset control module and a signal delay sub-module; the frequency division module includes a first frequency divider;

[0102] The first clock buffer is configured to generate the working clock signal and the input clock signal based on the first clock signal;

[0103] The first synchronous reset control module is configured to send the first frequency division reset signal to the frequency division module;

[0104] The signal delay sub-module is configured to delay the first frequency division reset signal by a predetermined delay duration to obtain a second frequency division reset signal, so that the second frequency division reset signal meets the setup time of a predetermined trigger edge of the input clock signal, where the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0105] The first frequency divider is configured to be triggered by the second frequency division reset signal at the predetermined trigger edge and generate the frequency division signal based on the input clock signal.

[0106] The first clock buffer is configured to generate two clock signals, namely the working clock signal and the input clock signal, by means of frequency replication or the like from one path of the first clock signal. The phase of the working clock signal when it is input to the control module can be determined based on the transmission path of the control module that can transmit based on the working clock signal, and the phase of the input clock signal when it is input to the first frequency divider can be determined based on the path of the input clock signal transmitted to the first frequency divider. That is, since the line for converting the first clock signal into the working clock signal and the input clock signal is fixed, the phase difference between the input clock signal and the working clock signal is known.

[0107] Here, the first synchronous reset control module in the control module can send the first frequency division reset signal to the frequency division module. The timer in the control module can start timing after the first frequency division reset signal.

[0108] Figure 4 For Figure 3 the timing diagram of the signal generation circuit shown. The timer can be triggered and started at a predetermined edge of the working clock signal after the first frequency division reset signal. As Figure 4 shown, the predetermined edge after the first frequency division reset signal can include the first rising edge after the first frequency division reset signal

[0109] In a possible implementation, the predetermined trigger edge of the input clock signal ( Figure 4 shown as C in) can include the Mth trigger edge (such as a rising edge) after the start time of the timer. M is a positive integer greater than or equal to 1. As Figure 4As shown, the predetermined trigger edge can be the first rising edge after the start time of the timer. Since the phase difference between the input clock signal and the working clock signal is known, the time interval between the predetermined trigger edge and the start time of the timer can be determined.

[0110] In a possible implementation, the predetermined delay duration can be determined based on the time interval between the start time of the first frequency division reset signal and the predetermined trigger edge. The predetermined delay duration can be determined based on at least one of the following: the second frequency division reset signal after the delay satisfies the setup time of the predetermined trigger edge (as Figure 4 described in t above); the second frequency division reset signal does not trigger the edge before the predetermined trigger edge in the input clock signal.

[0111] In a possible implementation, the predetermined delay duration can be pre-written into the signal delay sub-module. In an FPGA, the signal delay sub-module can be implemented by an input / output delay (IOdelay) circuit.

[0112] Through the second frequency division reset signal, the first frequency divider can be triggered to perform frequency division at the predetermined trigger edge and output a frequency division signal. Figure 4 Among them, the time interval T1 between the start time of the frequency division signal and the start time of the timer can include the response duration of the first frequency divider.

[0113] In summary, the time interval between the predetermined trigger edge and the start time of the timer is known, and the response duration of the first frequency divider can be determined based on the first frequency divider. Therefore, the time interval, the first predetermined duration, between the start time of the frequency division signal and the start time of the timer is fixed.

[0114] By filtering the frequency division signal to obtain a calibration signal, the filter delay duration is T2 (T2 is a performance parameter of the filter module and can be a fixed value). Therefore, the time interval, the second predetermined duration T, between the start time of the calibration signal and the start time of the timer is also fixed. In this way, the phase difference between the signal to be calibrated and the start time of the timer can be determined by comparing the phases of the calibration signal and the signal to be calibrated, and then the calibration of the signal to be calibrated can be realized.

[0115] In practical applications, the start time of the timer, the start time of the frequency division signal, and the time when the first frequency divider is triggered at a predetermined trigger edge are all related to the release time of the second frequency division reset signal. That is, the falling edge of the second reset signal needs to be sampled by the working clock signal and the input clock signal respectively, which requires that the falling edge of the second reset signal and the sampling time of the second reset signal have sufficient setup and hold time. The start time of the timer is triggered by the edge of the working clock signal, the start time of the frequency division signal and the first frequency divider are triggered by the input clock signal, and the working clock signal and the input clock signal have a fixed phase relationship. Therefore, the deviations between the start time of the above-mentioned timer, the start time of the frequency division signal, and the time when the first frequency divider is triggered at a predetermined trigger edge are fixed, so that high-precision calibration can be achieved.

[0116] Exemplarily, as Figure 5 shown, the specific steps of the calibration signal generation method include:

[0117] Step 501: Power on and initialize each module in the signal generation.

[0118] Step 502: Configure the clock module to generate the input clock signal of the first frequency divider and the working clock signal of the FPGA (control module).

[0119] Step 503: Synchronize the first synchronous reset control module to control the first frequency divider to be in the reset state and the timer to be in the reset state.

[0120] Step 504: Configure the delay value (predetermined delay duration) of the signal delay sub-module. The delay value can be a factory calibration value used to control the setup / hold time of the second frequency division reset signal and the input clock signal.

[0121] Step 505: The control module determines whether a calibration signal needs to be generated. If so, execute Step 506; otherwise, execute Step 505.

[0122] Step 506: Send out the second frequency division reset signal to release the first frequency divider.

[0123] Step 507: Start the internal timer of the FPGA. (Counting as the starting reference time of the calibration signal).

[0124] Step 508: The frequency division signal passes through a low-pass filter.

[0125] Step 509: The output signal of the low-pass filter is the calibration signal.

[0126] In the above steps, the signal delay sub-module obtains the delay value during factory calibration. This delay value is used to control the second divided-frequency reset signal output by the FPGA and the input clock signal to have sufficient setup / hold timing, ensuring that each time power is applied, there is a fixed delay relationship between the divided-frequency signal output by the first divider and the start time of the internal timer of the FPGA. In this way, it can be ensured that the calibration signal output by the low-pass filter has a fixed delay relationship with the start time of the internal timer of the FPGA.

[0127] In some embodiments, as Figure 6 shown, the signal generation circuit further includes: a second clock buffer; the control module includes: a phase adjustment module and a second synchronous reset control module; the frequency division module includes a second frequency divider;

[0128] The second clock buffer is used to generate a second clock signal and the input clock signal based on the first clock signal;

[0129] The second synchronous reset control module is used to generate a first divided-frequency reset signal based on the working clock signal;

[0130] The phase adjustment module is used to adjust the phase of the second clock signal to obtain the working clock signal, so that the first divided-frequency reset signal triggered based on the working clock signal meets the setup time of the predetermined trigger edge of the input clock signal, where the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0131] The second frequency divider is used to be triggered by the first divided-frequency reset signal at the predetermined trigger edge and generate the divided-frequency signal based on the input clock signal.

[0132] The first clock buffer is used to generate two clock signals: a second clock signal and an input clock signal by means of frequency replication or the like from one path of the first clock signal.

[0133] Here, there is a corresponding relationship between the first divided-frequency reset signal and the timer. The corresponding relationship between the first divided-frequency reset signal and the timer includes one of the following: there is a predetermined interval between the start time of the first divided-frequency reset signal and the start time of the timer; the first divided-frequency reset signal and the timer are triggered based on a predetermined edge of the same working clock signal.

[0134] The phase adjustment module can be used to adjust the phase of the second clock signal to obtain a working clock signal. The phase adjustment module can be implemented by at least one of the following to achieve the adjustment of the clock signal phase: Phase Locked Loop (PLL), Delay Locked Loop (DLL), Digital Clock Manager (DCM).

[0135] In a possible implementation, the amount of phase adjustment that the phase adjustment module can be used to adjust the second clock signal can be preset.

[0136] The phase of the second clock signal can be determined based on the transmission path of the control module through which the second clock signal is transmitted, and the phase of the input clock signal can be determined based on the path through which the input clock signal is transmitted to the first frequency divider. That is, the phase difference between the second clock signal and the input clock signal is known. Therefore, the phase difference between the working clock signal and the input clock signal can be determined based on the amount of phase adjustment of the phase adjustment module.

[0137] Figure 7 For Figure 6 the timing diagram of the signal generation circuit shown. The predetermined trigger edge ( Figure 7 shown as C in Figure 7 ) can include the Mth trigger edge (such as a rising edge) after the start time of the timer. M is a positive integer greater than or equal to 1. As shown, the predetermined trigger edge can be the first rising edge after the start time of the timer. Since the phase difference between the input clock signal and the working clock signal is known, the time interval between the predetermined trigger edge and the start time of the timer can be determined.

[0138] Figure 7 Here, the amount of phase adjustment can be determined based on at least one of the following: the setup time (such as

[0139] shown as t in Figure 7 ) that the first frequency division reset signal satisfies the predetermined trigger edge; the second frequency division reset signal does not trigger the edge before the predetermined trigger edge in the input clock signal.

[0140] In summary, the time interval between the predetermined trigger edge and the start time of the timer is known, and the response duration of the second frequency divider can be determined based on the second frequency divider. Therefore, the time interval (the first predetermined duration T1) between the start time of the frequency division signal and the start time of the timer is fixed.

[0141] The calibration signal is obtained by filtering the frequency-divided signal, and the filtering delay duration is T2 (T2 is a performance parameter of the filtering module and can be a fixed value). Therefore, the time interval, i.e., the second predetermined duration T, between the start time of the calibration signal and the start time of the timer is also fixed. In this way, the phase difference between the signal to be calibrated and the start time of the timer can be determined by comparing the phases of the calibration signal and the signal to be calibrated, and further the calibration of the signal to be calibrated can be achieved.

[0142] In practical applications, the start time of the timer is determined by the edge (such as the rising edge) of the working clock signal, and the start time of the frequency-divided signal is determined by the edge (such as the rising edge) of the input clock signal. The working clock signal and the input clock signal have a fixed phase relationship. Therefore, the deviation between the start time of the above-mentioned timer and the start time of the frequency-divided signal is fixed, so that high-precision calibration can be achieved.

[0143] Exemplarily, as Figure 8 shown, the specific steps of the calibration signal generation method include:

[0144] Step 801: Power on and initialize each module in the signal generation.

[0145] Step 802: Configure the clock module to generate the input clock signal of the frequency divider and the second clock signal.

[0146] Step 803: Synchronously reset the control module to control the second frequency divider to be in the reset state and the timer to be in the reset state.

[0147] Step 804: Configure the parameters of the phase adjustment module in the FPGA (control module) to adjust the phase of the second clock signal. The phase adjustment amount can be a factory calibration value, which is used to control the setup / hold time of the first frequency division reset signal and the input clock of the second frequency divider.

[0148] Step 805: The control module determines whether a calibration signal needs to be generated. If yes, execute Step 806; otherwise, execute Step 805.

[0149] Step 806: Send out the first frequency division reset signal to release the second frequency divider.

[0150] Step 807: Start the internal timer of the FPGA to count as the starting reference time of the calibration signal.

[0151] Step 808: The frequency-divided signal passes through a low-pass filter.

[0152] Step 809: The output signal of the low-pass filter is the calibration signal.

[0153] In the above steps, the internal clock unit of the FPGA, namely the phase adjustment module (such as PLL, DLL, DCM, etc.), is used to adjust the phase of the working clock signal of the FPGA, so as to control the first divided-frequency reset signal given by the FPGA to the second frequency divider and the input clock of the second frequency divider to have sufficient setup / hold timing. Thus, when powered on each time, the output signal of the second frequency divider and the start time of the internal timer of the FPGA have a fixed time delay relationship.

[0154] In some embodiments, as Figure 9 shown, the first clock signal includes the working clock signal; the frequency division module includes a counting frequency divider; the control module includes: a third synchronous reset control module and the counting frequency divider; the working clock signal is used to be input into the counting frequency divider as the input clock signal;

[0155] The third synchronous reset control module is used to generate a first divided-frequency reset signal based on the working clock signal;

[0156] The start time includes a predetermined edge of the working clock signal after the generation time of the first divided-frequency reset signal;

[0157] The counting frequency divider is used to be triggered by the first divided-frequency reset signal at the predetermined edge, count the working clock signal from the predetermined edge, and generate the divided-frequency signal based on the counting result of the counting.

[0158] Here, the clock module outputs a first clock signal based on the reference clock signal as the working clock signal of the control module. Inside the control module, the working clock signal is transmitted to the counting frequency divider as the input clock signal.

[0159] In a possible implementation, the counting frequency divider is used to count the input clock signal, and when the count value reaches the counting threshold, the level is inverted, so as to generate a periodic divided-frequency signal.

[0160] For example, the required divided-frequency signal is an N-divided-frequency signal of the working clock signal. Then the counting threshold can be set to N / 2. When the counting frequency divider counts the working clock signal, when the count value reaches N / 2, the level is inverted, so as to generate an N-divided-frequency signal.

[0161] Figure 10 For Figure 9 the timing diagram of the signal generation circuit shown. As Figure 10 shown, the first divided-frequency reset signal and the timer have a corresponding relationship. The start time of the timer is located at the predetermined edge of the working clock signal after the generation time of the first divided-frequency reset signal.

[0162] In a possible implementation, the predetermined edge may include the first edge (rising edge or falling edge) of the working clock signal after the generation time of the first divided-frequency reset signal.

[0163] The counting frequency divider counts based on the trigger of the first divided-frequency reset signal, so as to output a divided-frequency signal.

[0164] Here, the counting frequency divider is triggered at the start time of the timer. Therefore, the time interval between the start time of the divided-frequency signal and the start time of the timer is fixed. For example, the start time of the divided-frequency signal is the same as the start time of the timer. The filtering delay of the low-pass filter is fixed. Therefore, the interval T between the start time of the calibration signal generated by the divided-frequency signal and the start time of the timer is a fixed value.

[0165] Exemplarily, as Figure 11 shown, the specific steps of the calibration signal generation method include:

[0166] Step 1101: Power on and initialize each module in the signal generation.

[0167] Step 1102: The third synchronous reset control module controls the counting frequency divider to be in the reset state and the timer to be in the reset state.

[0168] Step 1103: The control module determines whether a calibration signal needs to be generated. If so, execute Step 1104; otherwise, execute Step 1103.

[0169] Step 1104: Send out the first divided-frequency reset signal to release the counting frequency divider.

[0170] Step 1105: Start the internal timer of the FPGA (control module) to count as the starting reference time of the calibration signal.

[0171] Step 1106: The divided-frequency signal passes through a low-pass filter.

[0172] Step 1107: The output signal of the low-pass filter is the calibration signal.

[0173] In the above steps, this solution does not use an external frequency divider, nor does it need to adjust the phase of the input clock signal of the third synchronous reset control module and the external frequency divider. This solution directly starts the internal frequency division counter based on the FPGA working clock signal, realizes the N-fold divided-frequency signal, and outputs the signal through a low-pass filter to obtain the calibration signal, which is simple and easy to implement.

[0174] Figure 12 is a signal generation method shown according to an embodiment of the present disclosure. The signal generation circuit is as Figure 1 shown and includes: a clock module, a control module, and a frequency division module, wherein,

[0175] The method includes:

[0176] Step 1201: Generate a first clock signal by the clock module based on an input reference clock signal, where the first clock signal is at least used to generate the working clock signal of the control module;

[0177] Step 1202: Send a first frequency division reset signal to the frequency division module by the control module, and trigger the start of a timer associated with the first frequency division reset signal in the control module, where the timer counts based on the working clock signal;

[0178] Step 1203: Divide an input clock signal by the frequency division module based on the first frequency division reset signal to output a divided signal, where the input clock signal is generated based on the first clock signal; the first frequency division reset signal is used to control the start time of the divided signal output by the frequency division module and the start time of the timer to be separated by a first predetermined duration.

[0179] In a possible implementation, the signal generation circuit can be implemented by an integrated circuit, or can be implemented by a combination of at least one integrated circuit and at least one discrete component.

[0180] Here, the signal generation circuit can be applied to signal source electronic devices such as an arbitrary waveform generator (AWG) signal source, an arbitrary waveform / function generator (AFG) signal source, i.e., a signal source, a radio frequency signal source, a vector signal source, etc., and can also be applied to electronic devices such as an oscilloscope and a spectrum analyzer. The signal generation circuit can exist in the form of an independent functional module, such as an independent functional module in a PXIe architecture; it can also be combined with other functional circuits to implement a composite function. For example, the signal generation circuit and an analog-to-digital converter (ADC) circuit are located on the same board to provide a specific signal to the ADC circuit.

[0181] In a possible implementation, the signal generation method can be executed by a controller in an electronic device.

[0182] Here, the reference clock signal can be a clock signal generated by a reference clock signal source. For example, the reference clock signal can be a crystal oscillator clock signal, or can be a clock signal sent by the main board to each functional module board in a PXIe architecture.

[0183] The control module can be implemented by components with signal processing capabilities and / or data calculation and processing capabilities, such as a Field Programmable Gate Array (FPGA). The control module can also be implemented by a Micro Processing Unit (MCU), etc.

[0184] The clock module is used for at least one of buffering and frequency dividing the reference clock to generate a clock signal with a frequency required for the operation of each module.

[0185] In a possible implementation, the first clock signal is used for generating at least one of the working clock signal and the input clock signal. For example, the first clock signal can generate the working clock signal and the input clock signal through fan-out or other means.

[0186] Here, the control module can control the reset of the frequency division module and / or perform frequency division work through a reset signal. For example, the control module can control the frequency division module to enter the reset state and perform frequency division work through two level states of the reset signal respectively. The first frequency division reset signal can be a level that triggers the frequency division of the input clock signal by the frequency division module. As Figure 2 shown, the first frequency division reset signal is Figure 2 the low level state of the reset signal in

[0187] In a possible implementation, the frequency division module is in a reset state before dividing the input clock signal.

[0188] In a possible implementation, the first frequency division reset signal is edge-triggered based on the working level.

[0189] In a possible implementation, the control module triggering the start of a timer associated with the first frequency division reset signal in the control module can include: the control module triggering the timer at a predetermined edge (rising edge or falling edge) of the working clock signal after the first frequency division reset signal is generated.

[0190] In a possible implementation, the predetermined edge is the first rising edge after the starting moment of the first frequency division reset signal (as Figure 2 indicated by arrow A).

[0191] In a possible implementation, the starting moment of the timer (as Figure 2 indicated by arrow B) is the edge moment of the predetermined edge of the working clock signal.

[0192] Since the timer counts time based on the working clock signal, the timing result of the timer is synchronized with the working clock signal. For example, for each cycle of the working clock signal, the timer counts once.

[0193] Both the working clock signal and the input clock signal are generated from the first clock signal, so there is a correlation between the working clock signal and the input clock signal. In a possible implementation, the working clock signal and the input clock signal have a fixed phase difference.

[0194] In a possible implementation, the starting time domain position of the first frequency division reset signal can be adjusted to adjust the starting time of the frequency division signal output by the frequency division module. For example, the frequency division module can be triggered by the first frequency division reset signal at the edge of the input clock signal to output the frequency division signal. Therefore, based on the time domain position of the starting time of the first frequency division reset signal and the time domain position of the edge of the input clock signal, the starting time of the frequency division signal output by the frequency division module triggered by the first frequency division reset signal can be determined. Since the working clock signal and the input clock signal have a fixed phase difference, the time interval between the starting time of the frequency division signal triggered by the input clock signal and the starting time of the timer is fixed, that is, the time interval between the starting time of the frequency division signal and the starting time of the timer can be determined, that is, the first predetermined duration (such as Figure 2 shown as T1 in

[0195] Since the time interval between the starting time of the frequency division signal and the starting time of the timer, that is, the first predetermined duration, is known, that is, the phase difference between the starting time of the frequency division signal and the working clock is known (for example, the phase difference between the starting time of the frequency division signal and the predetermined edge of the working clock is known), the frequency division signal can be used for time delay comparison. For example, by comparing the signal to be calibrated with the frequency division signal to determine the time interval between the signal to be calibrated and the starting time of the timer, and then determining the time delay of the signal to be calibrated relative to the starting time of the timer.

[0196] In a possible implementation, the frequency division module can be used to perform N-frequency division on the input clock signal to output a frequency division signal. Wherein, N is a positive integer greater than or equal to 1.

[0197] In this way, based on the first frequency division reset signal to realize the adjustment of the starting time of the frequency division signal, and the corresponding relationship between the first frequency division reset signal and the starting time of the timer, the control of the time interval between the starting time of the frequency division signal and the starting time of the timer is determined, so that the frequency division signal can be used for time delay calibration comparison, and then the calibration of the signal to be calibrated is realized.

[0198] In some embodiments, as Figure 1 shown, the signal generation circuit further includes: a low-pass filter;

[0199] The method further includes: performing low-pass filtering on the frequency division signal through the low-pass filter to obtain a calibration signal, wherein the starting time of the calibration signal is separated from the starting time of the timer by a second predetermined duration.

[0200] As Figure 2 shown, the frequency-divided signal obtained after the frequency division module is approximately a square wave and has high-frequency harmonic components. Here, a low-pass filter can be used for filtering to obtain a smooth calibration signal, thereby improving the accuracy of phase calculation. The low-pass filter can be set based on the frequency of the frequency-divided signal to filter out harmonic components with frequencies greater than that of the frequency-divided signal.

[0201] As Figure 2 shown, there is a filtering time delay (shown as T2 in Figure 2 ) when the low-pass filter performs filtering. Therefore, the second predetermined duration (shown as T in Figure 2 ) between the calibration signal obtained after filtering and the start time of the timer is the sum of the first predetermined duration and the filtering time delay.

[0202] Therefore, when comparing the calibration signal with the signal to be calibrated, the phase difference between the signal to be calibrated and the start time of the timer can be determined based on the phase difference T3 between the signal to be calibrated and the calibration signal and the second predetermined duration.

[0203] In some embodiments, as Figure 3 shown, the signal generation circuit further includes: a first clock buffer; the control module includes: a first synchronous reset control module and a signal delay sub-module; the frequency division module includes a first frequency divider; the method further includes:

[0204] generating the working clock signal and the input clock signal based on the first clock signal through the first clock buffer;

[0205] sending the first frequency division reset signal to the frequency division module through the first synchronous reset control module;

[0206] delaying the first frequency division reset signal by a predetermined duration through the signal delay sub-module to obtain a second frequency division reset signal, so that the second frequency division reset signal meets the setup time of the predetermined trigger edge of the input clock signal, where the predetermined trigger edge is at a predetermined time domain position after the start time;

[0207] generating the frequency-divided signal based on the input clock signal by triggering the first frequency divider with the second frequency division reset signal at the predetermined trigger edge.

[0208] The first clock buffer is used to generate two clock signals, namely a working clock signal and an input clock signal, from a first clock signal through frequency replication or other means. The phase of the working clock signal when it is input to the control module can be determined based on the transmission path of the control module that transmits the working clock signal, and the phase of the input clock signal when it is input to the first frequency divider can be determined based on the path of the input clock signal transmitted to the first frequency divider. That is, since the circuit for converting the first clock signal into the working clock signal and the input clock signal is fixed, the phase difference between the input clock signal and the working clock signal is known.

[0209] Here, the first synchronization reset control module in the control module can send the first frequency division reset signal to the frequency division module. The timer in the control module can start timing after the first frequency division reset signal.

[0210] Figure 4 For Figure 3 the timing diagram of the signal generation circuit shown. The timer can be triggered and started at a predetermined edge of the working clock signal after the first frequency division reset signal. As Figure 4 shown, the predetermined edge after the first frequency division reset signal can include the first rising edge after the first frequency division reset signal

[0211] In a possible implementation, the predetermined trigger edge of the input clock signal ( Figure 4 shown as C in Figure 4 ) can include the Mth trigger edge (such as a rising edge) after the start time of the timer. M is a positive integer greater than or equal to 1. As

[0212] shown, the predetermined trigger edge can be the first rising edge after the start time of the timer. Since the phase difference between the input clock signal and the working clock signal is known, the time interval between the predetermined trigger edge and the start time of the timer can be determined. Figure 4 In a possible implementation, the predetermined delay duration can be determined based on the time interval between the start time of the first frequency division reset signal and the predetermined trigger edge. The predetermined delay duration can be determined based on at least one of the following: the setup time (such as

[0213] shown as t in

[0214] ) of the second frequency division reset signal after the delay to satisfy the predetermined trigger edge; the second frequency division reset signal does not trigger the edge before the predetermined trigger edge in the input clock signal. Figure 4Among them, the time interval T1 between the start time of the frequency-divided signal and the start time of the timer may include the response duration of the first frequency divider.

[0215] In summary, the time interval between the predetermined trigger edge and the start time of the timer is known, and the response duration of the first frequency divider can be determined based on the first frequency divider. Therefore, the time interval, i.e., the first predetermined duration, between the start time of the frequency-divided signal and the start time of the timer is fixed.

[0216] By filtering the frequency-divided signal to obtain a calibration signal, the filtering delay duration is T2 (T2 is a performance parameter of the filtering module and can be a fixed value). Therefore, the time interval, i.e., the second predetermined duration T, between the start time of the calibration signal and the start time of the timer is also fixed. In this way, the phase difference between the signal to be calibrated and the start time of the timer can be determined by comparing the phases of the calibration signal and the signal to be calibrated, thereby realizing the calibration of the signal to be calibrated.

[0217] In practical applications, the start time of the timer, the start time of the frequency-divided signal, and the time when the first frequency divider is triggered at the predetermined trigger edge are all related to the release time of the second frequency division reset signal. That is, the falling edge of the second reset signal needs to be sampled by the working clock signal and the input clock signal respectively, which requires that the falling edge of the second reset signal and the sampling time of the second reset signal have sufficient setup and hold time. The start time of the timer is triggered by the edge of the working clock signal, the start time of the frequency-divided signal and the first frequency divider are triggered by the input clock signal, and the working clock signal and the input clock signal have a fixed phase relationship. Therefore, the deviations between the above-mentioned start time of the timer, the start time of the frequency-divided signal, and the time when the first frequency divider is triggered at the predetermined trigger edge are fixed relative to each other, thus enabling high-precision calibration.

[0218] In some embodiments, as Figure 6 shown, the signal generation circuit further includes: a second clock buffer; the control module includes: a phase adjustment module and a second synchronous reset control module; the frequency division module includes a second frequency divider;

[0219] The method further includes:

[0220] generating a second clock signal and the input clock signal based on the first clock signal through the second clock buffer;

[0221] generating a first frequency division reset signal based on the working clock signal through the second synchronous reset control module;

[0222] The phase of the second clock signal is adjusted by the phase adjustment module to obtain the working clock signal, so that the first divided-frequency reset signal triggered based on the working clock signal meets the setup time of the predetermined trigger edge of the input clock signal, where the predetermined trigger edge is located at a predetermined time domain position after the start time;

[0223] The second divider is triggered by the first divided-frequency reset signal at the predetermined trigger edge, and the divided-frequency signal is generated based on the input clock signal.

[0224] The first clock buffer is used to generate two clock signals, namely the second clock signal and the input clock signal, from one first clock signal through frequency replication or the like.

[0225] Here, there is a corresponding relationship between the first divided-frequency reset signal and the timer. The corresponding relationship between the first divided-frequency reset signal and the timer includes one of the following: there is a predetermined interval between the start time of the first divided-frequency reset signal and the start time of the timer; the first divided-frequency reset signal and the timer are triggered based on a predetermined edge of the same working clock signal.

[0226] The phase adjustment module can be used to adjust the phase of the second clock signal to obtain the working clock signal. The phase adjustment module can be implemented by at least one of the following to achieve the adjustment of the phase of the clock signal: Phase Locked Loop (PLL), Delay Locked Loop (DLL), Digital Clock Manager (DCM).

[0227] In a possible implementation manner, the amount of phase adjustment that the phase adjustment module can be used to adjust the second clock signal can be preset.

[0228] The phase of the second clock signal can be determined based on the transmission path of the control module through which the second clock signal is transmitted, and the phase of the input clock signal can be determined based on the path through which the input clock signal is transmitted to the first divider. That is, the phase difference between the second clock signal and the input clock signal is known. Therefore, the phase difference between the working clock signal and the input clock signal can be determined based on the amount of phase adjustment of the phase adjustment module.

[0229] Figure 7 For Figure 6 The timing diagram of the signal generation circuit shown. The predetermined trigger edge ( Figure 7 shown as C) can include the Mth trigger edge (such as the rising edge) after the start time of the timer. M is a positive integer greater than or equal to 1. For example, Figure 7As shown, the predetermined trigger edge can be the first rising edge after the start time of the timer. Since the phase difference between the input clock signal and the working clock signal is known, the time interval between the predetermined trigger edge and the start time of the timer can be determined.

[0230] Here, the phase adjustment amount can be determined based on at least one of the following: the first divided-frequency reset signal satisfies the setup time of the predetermined trigger edge (such as Figure 7 shown as t); the second divided-frequency reset signal does not trigger the edge before the predetermined trigger edge in the input clock signal.

[0231] Through the first divided-frequency reset signal, the second divider can trigger at the predetermined trigger edge, perform frequency division, and output a divided-frequency signal. Figure 7 Among them, the time interval between the divided-frequency signal and the start time of the timer, the first predetermined duration T1, can include the response duration of the first divider.

[0232] In summary, the time interval between the predetermined trigger edge and the start time of the timer is known, and the response duration of the second divider can be determined based on the second divider. Therefore, the time interval between the start time of the divided-frequency signal and the start time of the timer, the first predetermined duration T1, is fixed.

[0233] By filtering the divided-frequency signal to obtain a calibration signal, the filtering delay duration is T2 (T2 is a performance parameter of the filtering module and can be a fixed value). Therefore, the time interval between the start time of the calibration signal and the start time of the timer, the second predetermined duration T, is also fixed. In this way, the phase difference between the calibration signal and the signal to be calibrated can be determined by comparing the phases of the calibration signal and the signal to be calibrated, and then the calibration of the signal to be calibrated can be realized.

[0234] In practical applications, the deviations of the start time of the timer, the start time of the divided-frequency signal, and the time when the second divider is triggered at the predetermined trigger edge come from the edge setup times of the working clock signal and the input clock signal. Since the edge setup times themselves are short, the above-mentioned deviations of the start time of the timer, the start time of the divided-frequency signal, and the time when the second divider is triggered at the predetermined trigger edge are small, so high-precision calibration can be achieved. The start time of the timer is determined by the edge (such as the rising edge) of the working clock signal, and the start time of the divided-frequency signal is determined by the edge (such as the rising edge) of the input clock signal. The working clock signal and the input clock signal have a fixed phase relationship. Therefore, the deviations between the start time of the above-mentioned timer and the start time of the divided-frequency signal are fixed to each other, so high-precision calibration can be achieved.

[0235] In some embodiments, such as Figure 9As shown, the first clock signal includes the working clock signal; the frequency division module includes a counting frequency divider; the control module includes, for example: a third synchronous bit control module and the counting frequency divider; the working clock is used to input to the counting frequency divider as the input clock;

[0236] The method further includes:

[0237] generating a first frequency division reset signal by the third synchronous reset control module based on the working clock signal; the start moment includes a predetermined edge of the working clock signal after the generation moment of the first frequency division reset signal;

[0238] triggering the counting frequency divider by the first frequency division reset signal at the predetermined edge, counting the working clock signal from the predetermined edge, and generating the frequency division signal based on the counting result of the counting.

[0239] Here, the clock module outputs a first clock signal based on a reference clock signal as the working clock signal of the control module. Inside the control module, the working clock signal is transmitted to the counting frequency divider as the input clock signal.

[0240] In a possible implementation, the counting frequency divider is used to count the input clock signal, and when the count value reaches the counting threshold, the level is inverted, thereby generating a periodic frequency division signal.

[0241] For example, the required frequency division signal is an N - division signal of the working clock signal. Then the counting threshold can be set to N / 2. When the counting frequency divider counts the working clock signal, when the count value reaches N / 2, the level is inverted, thereby generating an N - division signal.

[0242] Figure 10 For Figure 9 the timing diagram of the signal generation circuit shown. As Figure 10 shown, there is a corresponding relationship between the first frequency division reset signal and the timer. The start moment of the timer is located at a predetermined edge of the working clock signal after the generation moment of the first frequency division reset signal.

[0243] In a possible implementation, the predetermined edge may include the first edge (rising edge or falling edge) of the working clock signal after the generation moment of the first frequency division reset signal.

[0244] The counting frequency divider counts based on the trigger of the first frequency division reset signal, thereby outputting the frequency division signal.

[0245] Here, the counting frequency divider is triggered at the start moment of the timer. Therefore, the time interval between the start moment of the frequency-divided signal and the start moment of the timer is fixed. For example, the start moment of the frequency-divided signal is the same as the start moment of the timer. The filtering delay of the low-pass filter is fixed. Therefore, the interval T between the start moment of the calibration signal generated by the frequency-divided signal and the start moment of the timer is a fixed value.

[0246] An embodiment of the present disclosure also provides an electronic device, including a processor, a memory, and an executable program stored in the memory and capable of running by the processor. When the processor runs the executable program, it executes the steps of the signal generation method described in any of the above embodiments.

[0247] In the embodiments of the present disclosure, the processor is a circuit with signal processing capabilities. In one implementation, the processor can be a circuit with instruction reading and running capabilities, such as a central processing unit (CPU), a microprocessor, a graphics processing unit (GPU) (which can be understood as a type of microprocessor), or a digital signal processing circuit (DSP), etc.; in another implementation, the processor can implement certain functions through the logical relationship of hardware circuits, and the logical relationship of the above hardware circuits is fixed or can be reconfigured. For example, the processor is a hardware circuit implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD), such as an FPGA. In a reconfigurable hardware circuit, the process of the processor loading a configuration document to implement the configuration of the hardware circuit can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units or modules. In addition, it can also be a hardware circuit designed for artificial intelligence, which can be understood as a type of ASIC, such as a neural network processing unit (NPU), a tensor processing unit (TPU), a deep learning processing unit (DPU), etc.

[0248] The computer-readable storage medium provided in this embodiment can execute the signal generation method of the above embodiment. Its implementation principle and technical effects are similar to those of the above embodiment, and will not be elaborated here.

[0249] The above-mentioned computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium accessible by a general-purpose or special-purpose computer.

[0250] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (ASIC). Of course, the processor and the readable storage medium can also exist as discrete components in an electronic device or a master device.

[0251] Those of ordinary skill in the art can understand that all or part of the steps for implementing the above method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps including those of the above method embodiments; and the foregoing storage medium includes various media that can store program codes, such as ROM, RAM, magnetic disk or optical disk.

[0252] The embodiments or implementation manners in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other.

[0253] In the description of this specification, the descriptions referring to "one implementation manner", "some implementation manners", "illustrative implementation manners", "examples", "specific examples", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of this application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples.

[0254] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A signal generating circuit, characterized in that: The signal generating circuit comprises: a clock module, a control module and a frequency dividing module, wherein: The clock module is used to generate a first clock signal based on an input reference clock signal, wherein the first clock signal is at least used to generate a working clock signal of the control module; The control module is used to send a first frequency division reset signal to the frequency division module, and trigger the start of a timer associated with the first frequency division reset signal in the control module, wherein the timer is timed based on the working clock signal; The frequency division module is used to divide the input clock signal based on a first frequency division reset signal to output a frequency division signal, wherein the input clock signal is generated based on the first clock signal; the first frequency division reset signal is used to control the start time of the frequency division module outputting the frequency division signal and the start time of the timer to be separated by a first predetermined time length.

2. The signal generating circuit according to claim 1, characterized in that: The signal generating circuit further includes: a low-pass filter, configured to perform low-pass filtering on the frequency-divided signal to obtain a calibration signal, wherein a start time of the calibration signal and a start time of the timer are separated by a second predetermined time length.

3. The signal generating circuit according to claim 1 or 2, characterized in that: The signal generating circuit further comprises: a first clock buffer; the control module comprises: a first synchronous reset control module and a signal delay submodule; the frequency dividing module comprises a first frequency divider; The first clock buffer is used to generate the working clock signal and the input clock signal based on the first clock signal; The first synchronous reset control module is used to send the first frequency division reset signal to the frequency division module; The signal delay submodule is used to delay the first frequency-divided reset signal by a predetermined delay time to obtain a second frequency-divided reset signal, so that the second frequency-divided reset signal meets the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time; The first frequency divider is configured to be triggered by the second frequency division reset signal at the predetermined trigger edge and to generate the frequency division signal based on the input clock signal.

4. The signal generating circuit according to claim 1 or 2, characterized in that: The signal generating circuit further comprises: a second clock buffer; the control module comprises: a phase adjustment module and a second synchronous reset control module; the frequency dividing module comprises a second frequency divider; The second clock buffer is used to generate a second clock signal and the input clock signal based on the first clock signal; The second synchronous reset control module is used to generate a first frequency-divided reset signal based on the working clock signal; The phase adjustment module is used to adjust the phase of the second clock signal to obtain the working clock signal, so that the first frequency-divided reset signal triggered by the working clock signal meets the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time; The second frequency divider is configured to be triggered by the first frequency division reset signal at the predetermined trigger edge and to generate the frequency division signal based on the input clock signal.

5. The signal generating circuit according to claim 1 or 2, characterized in that: The first clock signal includes the working clock signal; the frequency division module includes a counting frequency divider; the control module includes: a third synchronous reset control module and the counting frequency divider; the working clock signal is used to input the counting frequency divider as the input clock signal; The third synchronous reset control module is used to generate a first frequency-divided reset signal based on the working clock signal; The start-up time includes a predetermined edge of the working clock signal after the first frequency-divided reset signal is generated; The counting frequency divider is used to be triggered by the first frequency division reset signal at the predetermined edge, count the working clock signal from the predetermined edge, and generate the frequency division signal based on the counting result.

6. A signal generation method, characterized in that: Applied to a signal generating circuit, the signal generating circuit comprises: a clock module, a control module and a frequency dividing module, wherein the method comprises: Generate a first clock signal based on an input reference clock signal by the clock module, wherein the first clock signal is at least used to generate a working clock signal of the control module; Sending a first frequency division reset signal to the frequency division module through the control module, and triggering the start of a timer associated with the first frequency division reset signal in the control module, wherein the timer performs timing based on the working clock signal; The frequency division module divides the input clock signal based on a first frequency division reset signal to output a frequency division signal, wherein the input clock signal is generated based on the first clock signal; the first frequency division reset signal is used to control the start time of the frequency division module outputting the frequency division signal and the start time of the timer to be spaced by a first predetermined time length.

7. The signal generating method according to claim 6, characterized in that: The signal generating circuit further comprises: a low pass filter; The method further includes: performing low-pass filtering on the frequency-divided signal through the low-pass filter to obtain a calibration signal, wherein a start time of the calibration signal and a start time of the timer are separated by a second predetermined time length.

8. The signal generating method according to claim 6 or 7, characterized in that: The signal generating circuit further comprises: a first clock buffer; the control module comprises: a first synchronous reset control module and a signal delay submodule; the frequency dividing module comprises a first frequency divider; the method further comprises: generating the working clock signal and the input clock signal based on the first clock signal by the first clock buffer; Sending the first frequency division reset signal to the frequency division module through the first synchronous reset control module; Delaying the first frequency-divided reset signal by a predetermined time length through the signal delay submodule to obtain a second frequency-divided reset signal, so that the second frequency-divided reset signal meets the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time; The first frequency divider is triggered by the second frequency division reset signal at the predetermined trigger edge to generate the frequency division signal based on the input clock signal.

9. The signal generating method according to claim 6 or 7, characterized in that: The signal generating circuit further comprises: a second clock buffer; the control module comprises: a phase adjustment module and a second synchronous reset control module; the frequency dividing module comprises a second frequency divider; The method further comprises: generating a second clock signal and the input clock signal based on the first clock signal by the second clock buffer; Generate a first frequency-divided reset signal based on the working clock signal by the second synchronous reset control module; The working clock signal is obtained by adjusting the phase of the second clock signal through the phase adjustment module, so that the first frequency-divided reset signal triggered by the working clock signal meets the establishment time of the predetermined trigger edge of the input clock signal, wherein the predetermined trigger edge is located at a predetermined time domain position after the start time; The second frequency divider is triggered by the first frequency division reset signal at the predetermined trigger edge to generate the frequency division signal based on the input clock signal.

10. The signal generating method according to claim 6 or 7, characterized in that: The first clock signal includes the working clock signal; the frequency division module includes a counting frequency divider; the control module includes: a third synchronous reset control module and the counting frequency divider; the working clock signal is used to input the counting frequency divider as the input clock signal; The method further comprises: generating a first frequency-divided reset signal based on the working clock signal by the third synchronous reset control module; the start-up time includes a predetermined edge of the working clock signal after the time when the first frequency-divided reset signal is generated; The counting frequency divider is triggered by the first frequency division reset signal at the predetermined edge, the working clock signal is counted from the predetermined edge, and the frequency division signal is generated based on the counting result.

11. An electronic device, characterized in that: The method comprises the signal generating circuit as claimed in any one of claims 1 to 5.

12. An electronic device comprising a processor, a memory, and an executable program stored in the memory and capable of being run by the processor, characterized in that: When the processor runs the executable program, the processor performs the steps of the signal generating method according to any one of claims 6 to 10.

13. A storage medium having an executable program stored thereon, characterized in that: When the executable program is executed by a processor, the steps of the signal generating method according to any one of claims 6 to 10 are implemented.

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