Low-voltage differential signal receiving end circuit with clock and data matching function
By designing a first phase lock loop coupled to the clock receiving buffer and a second phase lock loop coupled to the data receiving buffer in the LVDS receiving terminal circuit, the delay time of the second phase lock loop is equal to the circuit delay time of the first phase lock loop, hardware delay compensation is realized, and the timing offset problem caused by signal delay in the prior art is solved, reducing the need for external corrections and correction problems caused by hardware or process differences.
Patent Information
- Application Number
- CN202311727162.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-29
- Filing Date
- 2023-12-15
- Publication Date
- 2025-05-30
AI Technical Summary
When the clock matches the data, the existing LVDS receivers have signal delays caused by transistor gate and layout traces, resulting in timing offsets. The prior art requires external corrections, and the correction effect is poor due to hardware or process differences.
A low voltage differential signal receiving terminal circuit is designed, including a data reception buffer, a clock reception buffer, a first phase lock loop coupled to the clock reception buffer, and a second phase lock loop coupled to the data reception buffer. The delay time of the second phase lock loop is equal to the circuit delay time of the first phase lock loop, and delay compensation is realized through hardware design.
The LVDS receiver circuit without external timing correction is realized, which reduces the problem of poor timing correction caused by hardware or process differences, improves chip testing efficiency and reduces time cost.
Smart Images
Figure CN120074470A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a Low-Voltage Differential Signaling (LVDS) receiver circuit, and more particularly to an LVDS receiver circuit with clock and data matching. Background Art
[0002] As the data transmission speed becomes faster and faster, the signal delay generated by the transistor gate and the signal delay generated by the layout routing will affect the correctness of the LVDS receiver clock and data reception timing. As Figure 1 shown, the LVDS receiver (LVDSR) has a data reception buffer (DB) for receiving a data differential signal pair (DP, DN) and a clock reception buffer (CB) for receiving a clock differential signal pair (CP, CN). There is a delay between the signals (DATA, CLK) output from the data reception buffer (DB) and the clock reception buffer (CB) to the shift register (SR) due to reasons such as transistor gates, layout routing, or other circuit modules (e.g., a delay locked loop DLL).
[0003] As Figure 2 shown, there will be a timing offset (TS) between the data signal (DATA) and the phase-locked clock signal (TCK) of the data signal (DATA) passing through the delay locked loop DLL. Although a delay unit as Figure 1 shown can be used for regulation to make the data signal (DATA) and the phase-locked clock signal (TCK) achieve the delay elimination effect as Figure 3 shown. However, the current method is to use external correction means. More specifically, when there is a timing offset (TS) between the LVDS clock and data due to delay, after obtaining the degree of the timing offset (TS) during the chip test process, the external delay compensator (DC) as Figure 1 shown is set with correction parameters (EXT) to correct the timing offset (TS). However, when performing timing correction from outside the chip, each chip needs to be independently processed, resulting in a long chip test time. If the same delay compensation parameters are used for each chip, it is also easy to cause poor correction effects due to process or hardware differences.
[0004] As can be seen from the above, there are still many problems in the clock and data matching of the LVDS receiver that need to be overcome and solved in the prior art. Summary of the Invention
[0005] Therefore, the present invention proposes an LVDS receiver circuit with clock and data matching to effectively solve the problems encountered in the prior art.
[0006] More specifically, one of the objectives of the present invention is to provide an LVDS receiver circuit that does not require external timing correction.
[0007] One of the objectives of the present invention is to provide an LVDS receiving-end circuit that is not easily affected by hardware or process differences to cause poor timing correction.
[0008] A preferred specific embodiment according to the present invention is a low-voltage differential signal receiving-end circuit. In this embodiment, the low-voltage differential signal receiving-end circuit includes a data receiving buffer, a clock receiving buffer, a first phase-locked loop coupled to the clock receiving buffer, and a second phase-locked loop coupled to the data receiving buffer. The data receiving buffer is used to receive a data differential signal pair and convert it into a full-scale data signal. The clock receiving buffer is used to receive a clock differential signal pair and convert it into a full-scale clock signal. The first phase-locked loop is used to receive the full-scale clock signal and output at least one phase-locked clock signal. The second phase-locked loop is used to receive the full-scale data signal and output the full-scale data signal after a delay time, where the delay time is equal to the circuit delay time of the first phase-locked loop.
[0009] In one embodiment, the first phase-locked loop is a delay-locked loop.
[0010] In one embodiment, the signal line length from the data receiving buffer to the second phase-locked loop is equal to the signal line length from the clock receiving buffer to the first phase-locked loop.
[0011] In one embodiment, it further includes a shift register coupled to the first phase-locked loop and the second phase-locked loop. The shift register is used to receive the full-scale data signal and at least one phase-locked clock signal to output a parallel data signal.
[0012] In one embodiment, the shift register is a serial-in parallel-out register.
[0013] In one embodiment, the signal line length from the first phase-locked loop to the shift register is equal to the signal line length from the second phase-locked loop to the shift register.
[0014] Another preferred specific embodiment according to the present invention is a low-voltage differential signal receiving-end circuit. In this embodiment, the low-voltage differential signal receiving-end circuit includes a data receiving buffer, a clock receiving buffer, a phase-locked loop coupled to the clock receiving buffer, and a delay buffer coupled to the data receiving buffer. The data receiving buffer is used to receive a data differential signal pair and convert it into a full-scale data signal. The clock receiving buffer is used to receive a clock differential signal pair and convert it into a full-scale clock signal. The phase-locked loop is used to receive the full-scale clock signal and output at least one phase-locked clock signal. The delay buffer is used to receive the full-scale data signal and output the full-scale data signal after a delay time, where the delay time is equal to the circuit delay time of the phase-locked loop.
[0015] In one embodiment, the delay buffer has at least the same delay unit and buffer unit as the phase-locked loop.
[0016] In one embodiment, the phase-locked loop is a delay-locked loop.
[0017] In one embodiment, the low voltage differential signal receiving end circuit further includes a shift register coupled to the phase-locked loop and the delay buffer. The shift register is used to receive a full-width data signal and at least one phase-locked clock signal to output a parallel data signal.
[0018] In one embodiment, the shift register is a serial-in parallel-out register.
[0019] In one embodiment, the signal line length from the data receiving buffer to the delay buffer is equal to the signal line length from the clock receiving buffer to the phase-locked loop.
[0020] In one embodiment, the signal line length from the delay buffer to the shift register is equal to the signal line length from the phase-locked loop to the shift register.
[0021] Compared with the prior art, the low voltage differential signal receiving end circuit of the present invention uses a second phase-locked loop or a delay buffer with the same hardware delay time as the phase-locked loop coupled to the clock receiving buffer as the delay compensation for the data receiving buffer. Therefore, a relatively uniform and consistent delay compensation effect can be achieved in terms of hardware or process. Moreover, the setting of the second phase-locked loop or the delay buffer is designed and integrated into the hardware during the hardware design and manufacturing process, so no additional external calibration is required, reducing the time cost of testing and setting compensation parameters for individual chips. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The drawings presented in the present invention are for helping to describe various embodiments of the present invention. However, in order to simplify the drawings and / or highlight the content to be presented by the drawings, the existing structures and / or elements in the drawings may be drawn in a simple schematic manner or presented in an omitted manner. On the other hand, the number of elements in the drawings can be singular or plural. The drawings presented in the present invention are only for explaining these embodiments and not for limiting them.
[0023] Figure 1 It is a schematic diagram of a conventional LVDS receiver architecture.
[0024] Figure 2 It is a schematic diagram of the clock and data timing offset in a conventional LVDS receiver.
[0025] Figure 3 It is a schematic diagram of the clock and data timing offset correction in a conventional LVDS receiver.
[0026] Figure 4 It is a schematic diagram of the LVDS receiver architecture in the first specific embodiment of the present invention.
[0027] Figure 5 Schematic diagram of an LVDS receiver architecture with a shift register as the output stage according to the first specific embodiment.
[0028] Figure 6 Schematic diagram of the LVDS receiver architecture in the second specific embodiment of the present invention.
[0029] Figure 7 Schematic diagram of an LVDS receiver architecture taking a delay locked loop as an example according to the second specific embodiment. Description of main component symbols:
[0030] 10, 20 Low-voltage differential signal receiving end circuits
[0031] 110 Data receiving buffer
[0032] 120 Clock receiving buffer
[0033] 130 First phase-locked loop
[0034] 140 Second phase-locked loop
[0035] 150 Shift register
[0036] 210 Data receiving buffer
[0037] 220 Clock receiving buffer
[0038] 230 First phase-locked loop
[0039] 231 Buffer unit
[0040] 232 Delay unit
[0041] 233 Phase detection unit
[0042] 234 Feedback buffer unit
[0043] 240 Delay buffer
[0044] 241 Buffer unit
[0045] 242 Delay unit
[0046] CB Clock receiving buffer
[0047] CP Positive clock differential signal
[0048] CN Negative clock differential signal
[0049] CLK Full-scale clock signal
[0050] DATA Full-scale data signal
[0051] DB Data receiving buffer
[0052] DC Delay Compensator
[0053] DP Positive Data Differential Signal
[0054] DN Negative Data Differential Signal
[0055] DLL Delay Locked Loop
[0056] EXT Calibration Parameter
[0057] TCK Phase - Locked Clock Signal
[0058] TS Timing Shift
[0059] SR Shift Register
[0060] LVDSR Low - Voltage Differential Signal Receiver Detailed Implementation Manner
[0061] Any reference to elements using names such as "first", "second", etc. in this document generally does not limit the number or order of these elements. On the contrary, these names are used herein as a convenient way to distinguish two or more elements or element instances. Therefore, it should be understood that the names "first", "second", etc. in the claims do not necessarily correspond to the same names in the written description. In addition, it should be understood that the reference to the first and second elements does not mean that only two elements can be used or that the first element must precede the second element. Regarding the terms "comprising", "including", "having", "containing", etc. used in this document, they are all open - ended terms, that is, they are intended to mean including but not limited to.
[0062] The term "coupled" is used herein to refer to a direct or indirect electrical coupling between two structures. For example, in an example of indirect electrical coupling, one structure can be coupled to another structure via passive elements such as resistors, capacitors, or inductors.
[0063] In the present invention, the words "exemplary", "for example" are used to mean "serving as an example, instance, or illustration". Any implementation or aspect described as "exemplary", "for example" in this document is not necessarily to be construed as being more preferred or advantageous than other aspects of the present invention. As used herein, the terms "about", "substantially" with respect to a specified value or characteristic are intended to mean within a certain numerical value (e.g., 10%) of the specified value or characteristic.
[0064] A first specific embodiment according to the present invention is a low-voltage differential signal receiving-end circuit. In this embodiment, the low-voltage differential signal receiving-end circuit includes a first phase-locked loop coupled to a clock receiving buffer and a second phase-locked loop coupled to a data receiving buffer. The delay time of the second phase-locked loop is equal to the circuit delay time of the first phase-locked loop. Therefore, a relatively uniform and consistent delay compensation effect can be achieved in terms of hardware or process, and the time cost of testing and setting compensation parameters for individual chips is reduced, but not limited thereto.
[0065] Please refer to Figure 4 , Figure 4 to draw a schematic diagram of the low-voltage differential signal receiving-end circuit 10 in the first embodiment of the present invention. As Figure 4 shown, the low-voltage differential signal receiving-end circuit 10 includes a data receiving buffer 110, a clock receiving buffer 120, a first phase-locked loop 130 coupled to the clock receiving buffer 120, and a second phase-locked loop 140 coupled to the data receiving buffer 110.
[0066] The data receiving buffer 110 is used to receive a data differential signal pair and convert it into a full-scale data signal (DATA). The data receiving buffer 110 can be, for example, a differential amplifier or an operational amplifier and other circuit elements with the function of receiving data differential signals. The data differential signal pair can be the positive data differential signal (DP) and the negative data differential signal (DN) with the same amplitude and opposite phases output from any low-voltage differential signal driver or low-voltage differential signal output device and other components. By receiving the positive data differential signal (DP) and the negative data differential signal (DN) through the data receiving buffer 110 and comparing the difference between the positive data differential signal (DP) and the negative data differential signal (DN), the logic state of the original signal sent by the sending end of the data differential signal pair is judged.
[0067] The clock receiving buffer 120 is used to receive a clock differential signal pair and convert it into a full-scale clock signal (CLK). Similar to the data receiving buffer 110, the clock receiving buffer 120 can also be, for example, a differential amplifier or an operational amplifier and other circuit elements with the function of receiving data differential signals. The clock differential signal pair can also be from any low-voltage differential signal driver or low-voltage differential signal output device and other components, which convert the original clock signal into the positive clock differential signal (CP) and the negative clock differential signal (CN) with the same amplitude and opposite phases. By receiving the positive clock differential signal (CP) and the negative clock differential signal (CN) through the clock receiving buffer 120 and comparing the difference between the positive clock differential signal (CP) and the negative clock differential signal (CN), the original clock signal sent by the sending end of the clock differential signal pair is judged.
[0068] The first phase-locked loop 130 is used to receive a full-frame clock signal (CLK) and output at least one phase-locked clock signal (TCK). The second phase-locked loop 140 is used to receive the full-frame data signal (DATA), and after a delay time, output the full-frame data signal (DATA), where the delay time is equal to the circuit delay time of the first phase-locked loop 130. Specifically, the first phase-locked loop 130 and the second phase-locked loop 140 are, for example, a delay-locked loop (DLL) or a phase-locked loop (PLL). The first phase-locked loop 130 and the second phase-locked loop 140 can be arranged in the same or similar manner in the circuit layout or chip layout. In the chip process, the first phase-locked loop 130 and the second phase-locked loop 140 with the same or similar layout can undergo the same process, so that the problem of different delay times caused by process differences or differences between process batches can be greatly reduced. By using the second phase-locked loop 140 as the delay compensation for the full-frame data signal (DATA), the time when the full-frame data signal (DATA) is transmitted to the backend can be exactly the same or approximate to the time when the full-frame clock signal (CLK) is transmitted to the backend in hardware. Therefore, a more uniform and consistent delay compensation effect can be achieved in terms of hardware or process. Compared with the prior art that must test and adjust the delay compensation parameters for individual chips or circuits, this embodiment can reduce the time cost of testing and setting the compensation parameters for individual chips.
[0069] In a preferred embodiment, the signal line length from the data receiving buffer 110 to the second phase-locked loop 140 is equal to the signal line length from the clock receiving buffer 120 to the first phase-locked loop 130. Specifically, in the circuit layout or chip layout, the signal line responsible for transmitting the full-frame clock signal (CLK) and the signal line responsible for transmitting the full-frame data signal (DATA) are preferably set to be of equal length. In this way, the time taken for the full-frame clock signal (CLK) and the full-frame data signal (DATA) to be transmitted on the signal line can be more consistent, making the compensation of the delay time more accurate. If the straight-line distance between the signal lines cannot be equal due to component configuration or other factors, the physical lengths of the signal lines can be made the same by means of bending and detouring.
[0070] In a preferred embodiment, please refer to Figure 5, the low-voltage differential signal receiving end circuit 10 further includes a shift register 150 coupled to the first phase-locked loop 130 and the second phase-locked loop 140. The shift register 150 is used to receive a full-scale data signal (DATA) and at least one phase-locked clock signal (TCK) to output a parallel data signal (DOUT). Specifically, the present invention does not limit the type of the shift register 150. The shift register 150 of the present invention can be selected as a serial-in parallel-out (SIPO) register, a parallel-in serial-out (PISO) register or other existing shift register 150 configurations according to requirements. The shift register 150 can be used, for example, to convert a high-speed / high-frequency data signal connected in series at the front end into a low-speed / low-frequency data signal. For example, the shift register 150 can rearrange the full-scale data signal (DATA) and output it to a backend circuit (for example, a timing control circuit (Tcon)), but is not limited thereto. In this embodiment, the problem of mismatch caused by the transmission delay of physical signal lines in signal transmission can be further reduced by means of equal-length transmission lines. Specifically, the signal line length from the first phase-locked loop 130 to the shift register 150 can be set to be equal to the signal line length from the second phase-locked loop 140 to the shift register 150. However, it should be noted that Figure 5 This is only an example and does not limit the outputs to which the first phase-locked loop 130 and the second phase-locked loop 140 are coupled. In other words, it is not necessary for the first phase-locked loop 130 and the second phase-locked loop 140 of the present invention to be coupled to the shift register 150 and output via the shift register 150. The first phase-locked loop 130 and the second phase-locked loop 140 of the present invention can be coupled to any suitable output stage and then output.
[0071] According to the second specific embodiment of the present invention, there is provided a low-voltage differential signal receiving end circuit. In this embodiment, the low-voltage differential signal receiving end circuit includes a phase-locked loop coupled to a clock receiving buffer and a delay buffer coupled to a data receiving buffer. The delay time of the delay buffer is equal to the circuit delay time of the first phase-locked loop. Therefore, a more uniform and consistent delay compensation effect can be achieved in terms of hardware or process, and the time cost of testing and setting compensation parameters for individual chips is reduced, but it is not limited thereto.
[0072] Please refer to Figure 6 , Figure 6 is a schematic diagram of the low-voltage differential signal receiving end circuit 20 in the second embodiment of the present invention. As Figure 6As shown, the low-voltage differential signal receiving end circuit 20 includes a data receiving buffer 210, a clock receiving buffer 220, a first phase-locked loop 230 coupled to the clock receiving buffer 220, and a delay buffer 240 coupled to the data receiving buffer 210. Compared with the first embodiment, in this embodiment, the delay buffer 240 is coupled to the data receiving buffer 210. Specifically, the delay buffer 240 is set according to the circuit delay time of the first phase-locked loop 230. For example, the delay buffer 240 can be the same as the components, logic gates, or transistors passed between the input and output of the first phase-locked loop 230 in terms of quantity or structure. Therefore, the delay buffer 240 can have the same circuit delay time as the first phase-locked loop 230. And because both the delay buffer 240 and the first phase-locked loop 230 are manufactured by the same process method, the differences or errors between different processes can be effectively reduced. Compared with the prior art that requires testing and adjusting delay compensation parameters for individual chips or circuits, this embodiment can reduce the time cost of testing and setting compensation parameters for individual chips.
[0073] Taking the first phase-locked loop 230 as a delay-locked loop as an example, please refer to Figure 7 , there is at least a buffer unit 231 and a delay unit 232 between the input and output of the delay-locked loop. It should be noted that Figure 7 only the components of a conventional delay-locked loop such as a phase detection unit 233 and a feedback buffer unit 234 are drawn, and it is not limited thereto. Any adjustment of the delay-locked loop in the present invention according to the prior art shall fall within the scope of the present invention. According to the configuration of the delay-locked loop DLL, the delay buffer 240 can be designed according to the transistors or other hardware components required by the buffer unit 231 and the delay unit 232 of the first phase-locked loop 230. So that the delay buffer 240 has the same buffer unit 241 and delay unit 242 as the first phase-locked loop 230. Therefore, the delay buffer 240 and the first phase-locked loop 230 can have the same delay time. The time when the full data signal (DATA) and the phase-locked clock signal (TCK) in the low-voltage differential signal receiving end circuit 20 are transmitted to the backend will be the same, and the problem of timing offset can be effectively reduced. And in this embodiment, only the hardware part that causes delay in the first phase-locked loop 230 is designed for the delay buffer 240, and the layout area required for timing offset compensation of the chip or circuit layout can be reduced without affecting the timing matching effect.
[0074] The present description of the invention is provided to enable a person skilled in the art to make or practice the invention. Various modifications to the invention will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations or the embodiments may be combined with each other or implemented separately without departing from the spirit or scope of the invention. Accordingly, the invention is not intended to be limited to the examples described herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.
Claims
1. A low-voltage differential signal receiving end circuit, characterized in that, it includes: A data receiving buffer for receiving a data differential signal pair and converting it into a full-scale data signal; A clock receiving buffer for receiving a clock differential signal pair and converting it into a full-scale clock signal; A phase-locked loop coupled to the clock receiving buffer, the phase-locked loop for receiving the full-scale clock signal and outputting at least one phase-locked clock signal; and A delay buffer coupled to the data receiving buffer, the delay buffer for receiving the full-scale data signal and outputting the full-scale data signal after a delay time, where the delay time is equal to the circuit delay time of the phase-locked loop.
2. The low-voltage differential signal receiving end circuit according to claim 1, characterized in that, the delay buffer has at least the same delay units and buffer units as the phase-locked loop.
3. The low-voltage differential signal receiving end circuit according to claim 1, characterized in that, the phase-locked loop is a delay-locked loop.
4. The low-voltage differential signal receiving end circuit according to claim 1, characterized in that, the signal line length from the data receiving buffer to the delay buffer is equal to the signal line length from the clock receiving buffer to the phase-locked loop.
5. The low-voltage differential signal receiving end circuit according to claim 1, characterized in that, further includes a shift register coupled to the phase-locked loop and the delay buffer, the shift register for receiving the full-scale data signal and the at least one phase-locked clock signal to output a parallel data signal.
6. The low-voltage differential signal receiving end circuit according to claim 5, characterized in that, the shift register is a serial-in parallel-out register.
7. The low-voltage differential signal receiving end circuit according to claim 5, characterized in that, the signal line length from the delay buffer to the shift register is equal to the signal line length from the phase-locked loop to the shift register.
8. A low-voltage differential signal receiving end circuit, characterized in that, it includes: A data receiving buffer for receiving a data differential signal pair and converting it into a full-scale data signal; A clock receiving buffer for receiving a clock differential signal pair and converting it into a full-scale clock signal; A first phase-locked loop coupled to the clock receiving buffer, the first phase-locked loop for receiving the full-scale clock signal and outputting at least one phase-locked clock signal; and A second phase-locked loop coupled to the data receiving buffer, the second phase-locked loop for receiving the full-scale data signal and outputting the full-scale data signal after a delay time, where the delay time is equal to the circuit delay time of the first phase-locked loop.
9. The low-voltage differential signal receiving end circuit according to claim 8, characterized in that, the first phase-locked loop is a delay-locked loop.
10. The low-voltage differential signal receiving end circuit according to claim 8, characterized in that, the signal line length from the data receiving buffer to the second phase-locked loop is equal to the signal line length from the clock receiving buffer to the first phase-locked loop.
11. The low-voltage differential signal receiving end circuit according to claim 8, characterized in that, Further includes a shift register coupled to the first phase-locked loop and the second phase-locked loop, the shift register is used to receive the full-frame data signal and the at least one phase-locked clock signal to output a parallel data signal.
12. The low voltage differential signal receiving end circuit as claimed in claim 11, wherein, the shift register is a serial-in parallel-out register.
13. The low voltage differential signal receiving end circuit as claimed in claim 11, wherein, the signal line length from the first phase-locked loop to the shift register is equal to the signal line length from the second phase-locked loop to the shift register.