Comparison circuit, decision feedback equalizer and communication interface

Abstract

The embodiment of the invention discloses a comparison circuit, a decision feedback equalizer and a communication interface, the comparison circuit comprises a first-stage comparator and a second-stage comparator, the first-stage comparator carries out comparison sampling on an input signal and a reference signal, obtains and amplifies a potential difference between the input signal and the reference signal, and outputs the potential difference between the input signal and the reference signal; and the secondary comparator receives the pre-amplified potential difference and performs secondary comparison sampling on the pre-amplified potential difference to obtain a target signal. Therefore, according to the comparison circuit provided by the embodiment of the invention, the first-stage comparator can work at a relatively low conversion rate through a biphase sampling principle, the comparison efficiency of the second-stage comparator is improved through pre-amplification of the first-stage comparator, and meanwhile, physical separation of input and output of the comparison circuit is realized; according to the embodiment, direct coupling paths between input and output are reduced, input end interference caused by output changes is reduced, meanwhile, biphase sampling is based on discrete time type sampling, the bandwidth and gain requirements are reduced, and eye pattern distortion is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic power, and more specifically, to a comparison circuit, a decision feedback equalizer, and a communication interface. Background Art

[0002] In a comparator, when switching from the pre-charge phase to the evaluation phase, a rapidly changing clock signal will bring a large transient current, causing kickback noise, which may lead to unstable comparator input or incorrect decision-making. Therefore, how to reduce the interference caused by kickback noise is crucial. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a comparison circuit, a decision feedback equalizer, and a communication interface. Among them, the comparison circuit enables a first-stage comparator to operate at a lower conversion rate through the principle of two-phase sampling, and improves the comparison efficiency of the second-stage comparator through the pre-amplification of the first-stage comparator. At the same time, the physical separation of the input and output of the comparison circuit is realized, reducing the direct coupling path between the input and output, thereby reducing the interference at the input end caused by output changes. At the same time, the two-phase sampling in this embodiment is based on discrete-time sampling, reducing the bandwidth and gain requirements and avoiding eye diagram distortion.

[0004] In a first aspect, an embodiment of the present invention provides a comparison circuit, the comparison circuit includes:

[0005] A first-stage comparator, including a first input terminal, a second input terminal, and a first output terminal, the first input terminal is configured to receive an input signal, the second input terminal is configured to receive a reference signal, and the first-stage comparator is configured to compare and sample the input signal and the reference signal, and output the potential difference between the pre-amplified input signal and the reference signal through the first output terminal;

[0006] An energy storage module, connected to the first output terminal, and configured to store the potential difference output by the first-stage comparator;

[0007] A second-stage comparator, including a third input terminal, a fourth input terminal, and a second output terminal, the third input terminal and the fourth input terminal are configured to receive the pre-amplified potential difference, and the second-stage comparator is configured to perform secondary comparison and sampling on the potential difference to obtain a target signal.

[0008] Further, the energy storage module further includes:

[0009] A first energy storage element, connected between the first output terminal and the third input terminal of the second-stage comparator;

[0010] A second energy storage element, connected between the first output terminal and the fourth input terminal of the secondary comparator;

[0011] The first energy storage element and the second energy storage element are configured to store the potential difference.

[0012] Further, the comparison circuit further includes:

[0013] A buffer;

[0014] Wherein, the input terminal of the buffer is connected to the first output terminal, and the output terminal of the buffer is respectively connected to the third input terminal and the fourth input terminal.

[0015] Further, the control clock of the buffer is the same as the sampling clock of the primary comparator.

[0016] Further, the buffer is a tri-state buffer.

[0017] Further, the primary comparator includes:

[0018] A current source, connected to the virtual ground of the primary comparator;

[0019] A resistor isolation module, connected to the first input terminal and the second input terminal, and configured to isolate the kickback noise generated during the pre-charging and evaluation of the first output terminal;

[0020] A clock-controlled cross-coupling module, connected to the resistor isolation module, and the common node between the two is the first output terminal, and is configured to amplify the difference between the input signal and the reference signal and control the switching between the pre-charging stage and the evaluation stage of the output by using a clock signal. The clock-controlled cross-coupling module includes at least one clock control circuit.

[0021] Further, the resistor isolation module includes:

[0022] A first resistor, connected between the first regeneration node of the primary comparator and the corresponding first clock control circuit;

[0023] A second resistor, connected between the second regeneration node of the primary comparator and the corresponding second clock control circuit;

[0024] A third resistor, connected between the first regeneration node and the second regeneration node;

[0025] The first regeneration node is the common node of the first input terminal and the first resistor, and the second regeneration node is the common node of the second input terminal and the second resistor.

[0026] Second aspect, an embodiment of the present invention provides a decision feedback equalizer, and the decision feedback equalizer includes:

[0027] A feedback module, configured to determine an inter-symbol interference parameter based on a decoded symbol;

[0028] A calculation circuit, configured to combine an initial signal and the inter-symbol interference parameter and output an equalized signal;

[0029] The comparison circuit as described above, configured to compare the difference between the sampled equalized signal and a preset reference signal and output a current symbol value.

[0030] Further, the feedback module includes:

[0031] A delay unit, connected to the output end of the comparison circuit;

[0032] A feedback filter, connected between the delay unit and the calculation circuit, configured to receive the decoded symbol at the correct time point based on the delay unit and determine the inter-symbol interference parameter based on the decoded symbol.

[0033] Further, the decision feedback equalizer further includes:

[0034] A feed-forward equalizer, configured to compensate for the influence of a channel on a signal to be processed and obtain the initial signal.

[0035] Third aspect, an embodiment of the present invention provides a communication interface, and a physical layer of the communication interface employs the decision feedback equalizer as described above.

[0036] The comparison circuit of the embodiment of the present invention includes a first-level comparator and a second-level comparator. Among them, the first-level comparator performs comparison sampling on an input signal and a reference signal, obtains and amplifies the potential difference between the input signal and the reference signal, and the second-level comparator receives and performs secondary comparison sampling on the pre-amplified potential difference to obtain a target signal. Thus, the comparison circuit of this embodiment enables the first-level comparator to operate at a lower conversion rate through the principle of two-phase sampling, and improves the comparison efficiency of the second-level comparator through the pre-amplification of the first-level comparator. At the same time, physical separation between the input and output of the comparison circuit is achieved, the direct coupling path between the input and output is reduced, and further, interference at the input end caused by output changes is reduced. At the same time, the two-phase sampling of this embodiment is based on discrete-time sampling, reducing bandwidth and gain requirements and avoiding eye diagram distortion. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0038] Figure 1It is a schematic diagram of a pre-amplification stage comparison circuit of a related comparative example;

[0039] Figure 2 It is a schematic diagram of the comparison circuit of the embodiment of the present invention;

[0040] Figure 3 It is a schematic diagram of a first-stage comparator of the embodiment of the present invention;

[0041] Figure 4 It is a timing diagram of the comparison circuit of the embodiment of the present invention;

[0042] Figure 5 and Figure 6 It is a simulation schematic diagram of the comparison circuit of the embodiment of the present invention and a traditional comparison circuit;

[0043] Figure 7 It is a schematic diagram of the decision feedback equalizer of the embodiment of the present invention. Detailed implementation manners

[0044] The following describes the present application based on embodiments, but the present application is not limited to these embodiments. In the following detailed description of the present application, some specific details are described in detail. Those skilled in the art can fully understand the present application without the description of these details. In order to avoid obscuring the essence of the present application, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0045] In addition, those of ordinary skill in the art should understand that the drawings provided herein are all for illustrative purposes and are not necessarily drawn to scale.

[0046] Unless the context clearly requires otherwise, the words such as "including" and "comprising" in the entire application document should be interpreted as the meaning of including rather than exclusive or exhaustive; that is, it is the meaning of "including but not limited to".

[0047] In the description of the present application, it should be understood that the terms "first", "second", etc. are only configured for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0048] For the solutions described in this specification and the embodiments, if they involve personal information processing, they will all be processed on the premise of having a legal basis (such as obtaining the consent of the personal information subject, or being necessary for performing a contract, etc.), and will only be processed within the specified or agreed scope. If the user refuses to process personal information other than the necessary information required for the basic functions, it will not affect the user's use of the basic functions.

[0049] When designing the comparison circuit of relevant circuit modules, it is very important to fully consider and minimize kickback noise. For example, the design of the comparison circuit in a Decision Feedback Equalizer (DFE). It should be understood that this embodiment does not limit the circuit modules to which the comparison circuit is applied, and it can also be other circuit modules using a comparison circuit. This embodiment mainly takes the DFE as an example for detailed description.

[0050] Kickback noise generally refers to the negative impact on other parts of the circuit caused by transient voltage or current changes due to switching operations. Traditional means of reducing kickback noise include: (1) Slowing down the conversion speed of the sampling clock, but its disadvantage is that it is very sensitive to power supply noise. (2) Increasing the positive-phase gate-drain capacitance to compensate for the kickback noise introduced by the gate-drain capacitance of the input pair transistors, but its disadvantage is that in the application scenario of single-ended data input of the high-speed interface physical layer PHY, there is a large difference in the RC time constants of the two input terminals of the comparator, resulting in a very poor actual compensation effect. (3) Using a continuous-time comparator, but its disadvantage is that in high-speed scenarios, there are high requirements for the bandwidth of the comparator, resulting in a large power consumption of the comparator and being not suitable for the integration of multi-bit wide parallel ports.

[0051] Figure 1 is a schematic diagram of a pre-amplification stage comparison circuit of a related comparative example, as Figure 1 shown, in the comparison circuit of the related comparative example, a pre-amplifier 11 (Pre-amplifier, Pre-amp) is inserted before the comparator 12 (such as Strong-Arm, SA) to isolate the influence of the kickback noise of the comparator 12 on the input terminals (DQ signal and reference signal Vref). Among them, the pre-amplifier 11 uses continuous time to pre-amplify the signal, and the comparator 12 samples and compares the input signal based on the corresponding sampling clock CLK to obtain the target signal. In this comparative example, since the pre-amplifier 11 uses continuous time, there are relatively large requirements for the corresponding bandwidth, gain, and slew rate. And the bandwidth limitation in actual applications will bring phase shift and affect the actual amplification ability of the output signal. Also, too small a gain will result in too large a kickback noise at the equivalent input terminal. The slew rate will affect the conversion speed under large signals. Therefore, to meet the requirements of the pre-amplifier 11, a large power consumption needs to be paid. At the same time, the pre-amplifier 11 will cause distortion when processing large signals, resulting in a certain degree of distortion of the actual sampled eye diagram. Moreover, the pre-amplifier 11 may also be relatively sensitive to external environmental conditions (such as temperature changes, etc.), which requires corresponding measures to be taken in actual applications to ensure its performance stability and not be affected, increasing the cost and implementation complexity.

[0052] Based on this, the embodiments of the present invention provide a comparison circuit, a decision feedback equalizer, and a communication interface. Among them, the comparison circuit enables the first-stage comparator to operate at a lower conversion rate through the principle of two-phase sampling, and improves the comparison efficiency of the second-stage comparator through the pre-amplification of the first-stage comparator. At the same time, the physical separation of the input and output of the comparison circuit is realized, reducing the direct coupling path between the input and output, thereby reducing the interference at the input end caused by the output change. At the same time, the two-phase sampling in this embodiment is based on discrete-time sampling, reducing the bandwidth and gain requirements and avoiding eye diagram distortion.

[0053] Figure 2 FIG. is a schematic diagram of the comparison circuit according to the embodiment of the present invention. The comparison circuit of this embodiment includes a first-stage comparator and a second-stage comparator. The first-stage comparator is used to compare and sample and pre-amplify the input signal and a preset reference signal. The second-stage comparator is used to perform secondary comparison sampling and amplification on the output of the first-stage comparator to obtain the target signal. The first-stage comparator and the second-stage comparator in the comparison circuit are designed based on the principle of two-phase sampling in this embodiment, so that the first-stage comparator can operate at a lower conversion rate, and the comparison efficiency of the second-stage comparator is improved through the pre-amplification of the first-stage comparator. Moreover, both the first-stage comparator and the second-stage comparator adopt the discrete-time sampling principle, reducing the bandwidth and gain requirements and avoiding eye diagram distortion. At the same time, the comparison circuit of this embodiment realizes the physical separation of the input and output, reducing the direct coupling path between the input and output, thereby reducing the interference at the input end caused by the output change.

[0054] As Figure 2 shown, the comparison circuit of this embodiment includes a first-stage comparator 21 and a second-stage comparator 22. Among them, the first-stage comparator 21 includes a first input terminal p1, a second input terminal p2, and a first output terminal. The first output terminal includes output terminals p3 and p4. Among them, the input terminal p1 is configured to receive the input signal DQ, and the input terminal p2 is configured to receive the reference signal Vref. The first-stage comparator 21 is configured to compare and sample the input signal DQ and the reference signal Vref, and output the potential difference between the pre-amplified input signal DQ and the reference signal Vref through the output terminals p3 and p4. Optionally, the reference signal Vref is pre-determined based on the ideal signal and the estimated corresponding interference, or can be dynamically updated based on the actual operating conditions of the circuit (such as interference corresponding to channel conditions and / or environmental factors, etc.). This embodiment does not limit this.

[0055] Furthermore, the first-stage comparator 21 can compare and sample and differentially amplify the input signal DQ and the reference signal Vref at the falling edge φ1 of the sampling clock CLK, and output the corresponding potential difference.

[0056] Figure 3Schematic diagram of the first-stage comparator according to an embodiment of the present invention. Further, as Figure 3 shown, the first-stage comparator 21 of this embodiment includes a first input terminal p1, a second input terminal p2, a current source I1 connected to the virtual ground of the first-stage comparator, a resistor isolation module 31, and a clock-controlled cross-coupling module 32. Among them, the first input terminal p1 and the second input terminal p2 are respectively used to receive an input signal DQ and a reference signal Vref. Among them, the first input terminal p1 and the second input terminal p2 can be implemented by transistors, such as MOS transistors, bipolar transistors, etc., and this embodiment does not limit this.

[0057] Among them, the virtual ground refers to a node in a circuit where the voltage is stabilized at a predetermined value, which can be the common source or common emitter of the first input terminal p1 and the second input terminal p2. Further, in order to ensure that the virtual ground can work effectively in this embodiment, a low-impedance return path to the actual ground wire is provided. The first-stage comparator 21 of this embodiment realizes the virtual ground through the current source I1 to reduce the kickback noise generated due to the introduction of the virtual ground. It should be understood that in other alternative implementation manners, a cascode structure can also be used to realize the virtual ground, and this embodiment does not limit this.

[0058] The resistor isolation module 31 is connected to the first input terminal p1 and the second input terminal p2, and is configured to isolate the kickback noise generated during the pre-charge and evaluation of the first-stage comparator 21. The clock-controlled cross-coupling module 32 is connected to the resistor isolation module 31, and is configured to amplify the difference between the input signal DQ and the reference signal Vref and control the switching of the pre-charge stage and the evaluation stage of the output by using the clock signals CLK1 / CLK2. Among them, the clock-controlled cross-coupling module 32 includes at least one clock control circuit. The common node of the resistor isolation module 31 and the clock-controlled cross-coupling module 32 is the output terminal of the first-stage comparator 21.

[0059] Further, the clock control cross-coupling module 32 is used to control the operation period of the first-stage comparator 21 to ensure the precise switching between the precharge and evaluation phases of the first-stage comparator 21. Among them, CLK1 and CLK2 are in-phase clocks. When the CLK1 / CLK2 signal is at a high level, the first-stage comparator 21 enters the precharge phase, and the internal node signals of the first-stage comparator 21 enter a fully reset state. When the CLK1 / CLK2 signal is at a low level, the first-stage comparator 21 enters the evaluation phase and starts to sample and pre-amplify the difference between the input signal DQ and the reference signal Vref. In this embodiment, the clock control cross-coupling module 32 is composed of N-type MOS transistors, and it can also be composed of P-type MOS transistors. Correspondingly, when the CLK1 / CLK2 signal is at a high level, the first-stage comparator 21 is in the evaluation phase, and when the CLK1 / CLK2 signal is at a low level, the first-stage comparator 21 is in the precharge phase. This embodiment does not limit this.

[0060] Further, in this embodiment, the resistor isolation module 31 is implemented by multiple resistors. The resistor isolation module 31 includes a first resistor R1, a second resistor R2, and a third resistor R3. The first resistor R1 is connected between the first regeneration node X of the first-stage comparator 21 and the corresponding first clock control circuit CLK1. The second resistor R2 is connected between the second regeneration node Y of the first-stage comparator 21 and the corresponding second clock control circuit CLK2. The third resistor R3 is connected between the first regeneration node X and the second regeneration node Y. Among them, the first regeneration node X is the common node of the first input terminal p1 and the first resistor R1, the second regeneration node Y is the common node of the second input terminal p2 and the second resistor R2, the output terminal p3 is the common node of the first resistor R1 and the first clock control circuit CLK1, and the output terminal p4 is the common node of the second resistor R2 and the second clock control circuit CLK2. Further, the implementation manner of the circuit structure of the resistor isolation module 31 in this embodiment is only exemplary. Other types of circuit structures that can achieve the function of the resistor isolation module 31, such as those based on other circuit elements (such as transistors, etc.), can be applied to this embodiment, and will not be described in detail one by one here.

[0061] Among them, the first resistor R1 and the second resistor R2 are used to isolate the rapid changes at the output terminals p3 and p4 during the precharge and evaluation phases of the first-stage comparator 21. The third resistor R3 further reduces the kickback effect on the input signal DQ and the reference signal Vref caused by the swing of the internal nodes by reducing the differential-mode output impedance between the first regeneration node X and the second regeneration node Y.

[0062] Further, the first regeneration node X and the second regeneration node Y also introduce a kind of kickback noise. However, since the embodiment of the present invention adopts the principle of bipolar sampling, the requirement for the comparison speed of the first-stage comparator 21 is relatively low, and at the same time, the requirement for the amplitude of the output signal is also relatively low. Therefore, the kickback noise introduced by the first regeneration node X and the second regeneration node Y is very limited. At the same time, since this embodiment uses multiple resistors to implement the resistor isolation module 31, further increasing the series circuit (i.e., the first resistor R1 and the second resistor R2), and / or reducing the bridging resistor (i.e., the third resistor R3) can further reduce the kickback noise introduced by the first regeneration node X and the second regeneration node Y. Thus, this embodiment can reduce the internal kickback noise of the first-stage comparator by design, improving the output accuracy.

[0063] This embodiment will elaborate on a hybrid architecture dynamic comparator for the first-stage comparator 21. It should be understood that other types of discrete-time comparators (such as Strong-Arm type comparators, etc.) can be applied to this embodiment, and no further examples will be given here.

[0064] Further, as Figure 2 shown, the second-stage comparator 22 of this embodiment includes a third input terminal p5, a fourth input terminal p6, and a second output terminal. The second output terminal includes output terminals p7 and p8. Among them, the third input terminal p5 and the fourth input terminal p6 are configured to receive the output of the first-stage comparator 21 to prevent a large potential difference, perform secondary sampling on this potential difference, and perform secondary comparison on the sampled potential difference to obtain the target signals {vop, von}. Among them, the second-stage comparator 22 receives two electrical signals op1 and on1 output by the first-stage comparator 21 through the two input terminals p5 and p6 respectively. The difference between these two electrical signals op1 and on1 is used to represent the potential difference output by the first-stage comparator 21, that is, to represent the difference between the pre-amplified input signal DQ and the reference signal Vref.

[0065] The second-stage comparator of this embodiment can adopt any existing discrete-time comparator, such as a Strong-Arm type dynamic comparator, etc. No further examples will be given here in this embodiment.

[0066] In an optional implementation manner, for the convenience of sampling by the second-stage comparator 22, the comparison circuit of this embodiment further includes an energy storage module 23, which is connected to the output terminal of the first-stage comparator 21 and is used to store the potential difference output by the first-stage comparator 21.

[0067] Further, the energy storage module 23 includes a first energy storage element and a second energy storage element. Among them, the first energy storage element and the second energy storage element are respectively used to store two electrical signals op1 and on1 output by the first-level comparator 21. Further, the energy storage module 23 is implemented by a capacitive element. It should be understood that this embodiment does not limit the electrical components used for the energy storage element, as long as it can play the corresponding energy storage role, and no further examples will be given here.

[0068] As Figure 2 shown, the energy storage module 23 includes a capacitive element C1 and a capacitive element C2. Among them, the capacitive element C1 is connected to the third input terminal p5, and the capacitive element C2 is connected to the fourth input terminal p6.

[0069] Further, the output terminal of the first-level comparator 21 in this embodiment is connected to the input terminal of the second-level comparator 22 through a buffer 24 to further isolate the first-level comparator 21 and the second-level comparator 22 and avoid the interference of the change of the second-level comparator 22 on the first-level comparator 21. Specifically, as Figure 2 shown, the input terminals of the buffer 24 are respectively connected to the output terminal p3 and the output terminal p4 of the first-level comparator 21, and the output terminals of the buffer 24 are respectively connected to the third input terminal p5 and the fourth input terminal p6 of the second-level comparator 22. The buffer 24 is a tri-state buffer (TBUF), and its function is to hold the potential difference on the energy storage module 23 during the second sampling comparison of the second-level comparator 22. It should be understood that this embodiment does not limit the type of the buffer, as long as it can implement the corresponding function.

[0070] Further, the control clock of the buffer 24 is the same as the sampling clock of the first-level comparator 21, so that while the first-level comparator 21 performs sampling comparison, the enable of the buffer 24 is at a high level to store the potential difference output by the first-level comparator 21 into the energy storage module 23, and when the first-level comparator 21 enters the pre-charge state, the potential difference stored in the energy storage module 23 remains unchanged. Thus, the comparison circuit in this embodiment controls the enable of the buffer 24 to be at a low level during the non-sampling comparison time of the first-level comparator 21 to further control the physical isolation between the first-level comparator and the second-level comparator, and controls the enable of the buffer 24 to be at a high level while the first-level comparator 21 performs sampling comparison to store the potential difference output by the first-level comparator 21 into the energy storage module 23, achieving the acquisition of the target signal.

[0071] Figure 4 is the timing diagram of the comparison circuit of the embodiment of the present invention. As Figure 2 and Figure 4As shown, the first-stage comparator 21 receives the input signal DQ and the reference signal Vref through the input terminals p1 and p2. The first-stage comparator 21 is controlled by the falling edge φ1 of the clock signal CLK for comparison and sampling. At the same time, the buffer 24 is controlled by the low level of the clock signal CLK to store the potential differences {op1, on1} obtained by the first-stage comparator 21 through sampling and comparison on the capacitive elements C1 and C2. The second-stage comparator 22 is controlled by the rising edge φ2 of the clock signal CLK to perform secondary comparison and sampling on the potential differences {op1, on1} stored on the capacitive elements C1 and C2 to obtain the target signal {vop, von}.

[0072] Optionally, in this embodiment, the first-stage comparator 21 can use a discrete-time Half-Latch dynamic comparator to pre-amplify the input signal DQ and the reference signal Vref. Compared with the traditional continuous-time pre-amplifier (such as Figure 1 the comparative example shown), due to the intervention of the positive feedback Latch, its output swing is larger and it is less affected by the kickback noise of the second-stage comparator 22. At the same time, the comparison circuit in this embodiment reduces the bandwidth requirement by adopting a discrete-time sampling method. The first-stage comparator 21 only needs to complete comparison and sampling within one unit interval (UI), and the power consumption is relatively low. Moreover, the two-phase sampling essentially belongs to the discrete-time sampling of the input signal DQ, and there is no pre-processing and modulation of the signal during the conversion process, so the distortion on the sampling eye diagram can be avoided. At the same time, the comparison circuit in this embodiment is less sensitive to the changes of Process / Voltage / Temperature (PVT), and there is no need to adopt additional measures to ensure the stability of performance, reducing the cost.

[0073] It should be understood that since a unidirectional charge storage path needs to be established between the first-stage comparator 21 and the second-stage comparator 22 in this embodiment, the first-stage comparator 21 and the second-stage comparator 22 may not be connected through the buffer 24. The specific structure can be configured based on the cost and accuracy requirements in actual applications.

[0074] In this embodiment, although the second-stage comparator 22 operates in a fast sampling state and its kickback noise is relatively large, since the input signal DQ has been isolated by the first-stage comparator 21 and the buffer 24 (or the first-stage comparator 21), it is difficult for the second-stage comparator 22 to cause interference of kickback noise to the input signal DQ. Further, since the first-stage comparator 21 pre-amplifies the input signal DQ and the reference signal Vref, the potential difference maintained on the energy storage element in the energy storage module 23 is large enough. Therefore, the kickback noise of the second-stage comparator 22 will not affect its own sampling accuracy either.

[0075] Figure 5 and Figure 6 are the simulation schematic diagrams of the comparison circuit of the embodiment of the present invention and the traditional comparison circuit. As Figure 5 shown, the simulation schematic Figure 5 of the comparison circuit of the embodiment of the present invention includes an input signal DQ, a reference signal Vref, a positive-phase output v1 and an inverting output v2 of the comparison circuit. The simulation schematic Figure 6 of the traditional comparison circuit includes an input signal DQ', a reference signal Vref', a positive-phase output v1' and an inverting output v2' of the comparison circuit. As Figure 5 and Figure 6 shown, by comparing the simulation schematic Figure 5 of the embodiment of the present invention and the simulation schematic Figure 6 of the traditional comparison circuit, it can be known that compared with the traditional comparison circuit, the comparison circuit of the embodiment of the present invention realizes the physical separation of the input and output of the comparison circuit through the isolation of a first-stage comparator (or through a first-stage comparator and a buffer), reduces the direct coupling path between the input and output, so that the kickback noise at the output end can hardly cause interference, and ensures the output stability and decision accuracy of the comparison circuit.

[0076] The comparison circuit of the embodiment of the present invention includes a first-stage comparator and a second-stage comparator. Among them, the first-stage comparator compares and samples the input signal and the reference signal, obtains and amplifies the potential difference between the input signal and the reference signal, and the second-stage comparator receives and performs secondary comparison sampling on the potential difference to obtain the target signal. Thus, the comparison circuit of this embodiment enables the first-stage comparator to operate at a lower conversion rate through the double-phase sampling principle, and improves the comparison efficiency of the second-stage comparator through the pre-amplification of the first-stage comparator. At the same time, the physical separation of the input and output of the comparison circuit is realized, the direct coupling path between the input and output is reduced, and further, the interference at the input end caused by the output change is reduced. At the same time, the double-phase sampling of this embodiment is based on discrete-time sampling, which reduces the bandwidth and gain requirements and avoids eye diagram distortion.

[0077] Furthermore, the comparison circuit of the embodiment of the present invention can be applied to various circuit modules that require signal comparison sampling. This embodiment takes its application in a decision feedback equalizer (DFE) as an example for detailed description. It should be understood that the application of the above comparison circuit is not limited to the decision feedback equalizer DFE. In other application scenarios, such as high-precision measurement systems, high-performance data converters, etc., the comparison circuit of this embodiment can be used, and no further detailed examples will be given here one by one.

[0078] In the design of the physical layer PHY of a high-speed interface, the decision feedback equalizer (DFE) is a crucial part, mainly used to compensate for inter-symbol interference (ISI) caused by the channel. The comparator in the decision feedback equalizer DFE is one of the key components for making the final data decision. For the comparator in the decision feedback equalizer DFE, kickback noise may lead to problems such as a decrease in comparison accuracy, an increase in latency, an increase in power consumption, and an impact on the reliability of the entire communication link. The embodiment of the present invention ensures the sampling accuracy of the decision feedback equalizer DFE through the comparison circuit in the above embodiment. That is, the decision feedback equalizer DFE in this embodiment uses the comparison circuit based on the dual-phase sampling principle described above, samples using two consecutive non-overlapping windows during the signal processing, greatly reducing the impact of kickback noise on the sampling accuracy and avoiding the problem of eye diagram distortion.

[0079] Figure 7 is a schematic diagram of the decision feedback equalizer according to an embodiment of the present invention. As Figure 7 shown, the decision feedback equalizer in this embodiment includes a feedback module 71, a calculation circuit 72, and a comparison circuit 73.

[0080] Among them, the feedback module 71 is configured to determine the inter-symbol interference parameter based on the decoded symbol. The calculation circuit 72 is configured to combine the initial signal s1 and the inter-symbol interference ISI parameter and output an equalized signal DQ (i.e., the input signal of the comparison circuit 73). The comparison circuit 73 is configured to compare the difference between the sampled equalized signal DQ and a preset reference signal Vref and output the current symbol value sign. Optionally, in this embodiment, the calculation circuit 72 is implemented using an adder. It should be understood that other calculation circuits capable of combining the initial signal s1 and the inter-symbol interference ISI parameter can also be applied to this embodiment.

[0081] Furthermore, the feedback module 71 in this embodiment includes a delay unit 711 and a feedback filter 712. Among them, the delay unit 711 is connected to the output end of the comparison circuit 73 and is configured to enable the decoded symbol sign to be applied to the feedback filter 712 at the correct time point. The feedback filter 712 is connected between the delay unit 711 and the calculation circuit 72 and is configured to determine the inter-symbol interference ISI parameter based on the decoded symbol received by the delay unit 711 at the correct time point.

[0082] It should be understood that the comparison circuit 73 in the decision feedback equalizer of this embodiment adopts the comparison circuit of any of the above implementation manners, and will not be described in detail here. Further, the feedback module 71 and the calculation circuit 72 of this embodiment can both be implemented by using the relevant implementation manners adopted by the decision feedback equalizer in the prior art or the relevant implementation manners generated during the future technological development, and the internal circuit structures thereof will not be described in detail one by one in this embodiment.

[0083] In an alternative implementation manner, the decision feedback equalizer of this embodiment further includes a feedforward equalizer 74. The output end of the feedforward equalizer 74 is connected to the input end of the calculation circuit 72 and is configured to compensate for the influence of the channel on the signal s0 to be processed and obtain an initial signal s1.

[0084] In an alternative implementation manner, the decision feedback equalizer of this embodiment further includes an output module ( Figure 7 not shown in the figure), which is configured to store the symbol decision result (i.e., the current symbol value sign) and provide the symbol decision result to the feedback module 71 and the output end. Optionally, the output module of this embodiment can be implemented by a latch or a flip-flop, and the implementation manner of the output module is not limited in this embodiment.

[0085] It should be understood that the feedforward equalizer 74 and the output module of this embodiment can both be implemented by using the relevant implementation manners adopted by the decision feedback equalizer in the prior art or the relevant implementation manners generated during the future technological development, and the internal circuit structures thereof will not be described in detail one by one in this embodiment.

[0086] In the decision feedback equalizer according to the embodiment of the present invention, the feedback module determines the inter-symbol interference parameter based on the decoded symbol, the calculation circuit combines the initial signal and the inter-symbol interference parameter to output an equalized signal, and the comparison circuit compares the difference between the sampled equalized signal and a preset reference signal to output the current symbol value. The comparison circuit includes a first-level comparator and a second-level comparator. The first-level comparator compares and samples the input signal and the reference signal to obtain and amplify the potential difference between the input signal and the reference signal. The second-level comparator receives and performs a second comparison sampling on the potential difference to obtain the target signal. Thus, the comparison circuit according to this embodiment enables the first-level comparator to operate at a lower conversion rate through the double-phase sampling principle, improves the comparison efficiency of the second-level comparator through the pre-amplification of the first-level comparator, physically separates the input and output of the comparison circuit, reduces the direct coupling path between the input and output, and further reduces the interference at the input end caused by the output change. At the same time, the double-phase sampling according to this embodiment is based on discrete-time sampling, reduces the bandwidth and gain requirements, and avoids eye diagram distortion. Thus, by adopting the comparison circuit based on the double-phase sampling principle as described above, the decision feedback equalizer (DFE) according to this embodiment uses two consecutive non-overlapping windows for sampling during the signal processing process, greatly reducing the influence of kickback noise on the sampling accuracy, avoiding the problem of eye diagram distortion, ensuring the comparison sampling accuracy, reducing the delay and power consumption, and ensuring the reliability of the communication link.

[0087] Furthermore, this embodiment also provides a communication interface. In the physical layer design of this communication interface, the decision feedback equalizer described in the above embodiment is adopted, so that by using the comparison circuit based on the double-phase sampling principle as described above, two consecutive non-overlapping windows are used for sampling during the signal processing process, greatly reducing the influence of kickback noise on the sampling accuracy, avoiding the problem of eye diagram distortion, ensuring the comparison sampling accuracy, reducing the delay and power consumption, and ensuring the reliability of the communication link. The above is only the preferred embodiment of the present application and is not configured to limit the present application. For those skilled in the art, various modifications and changes can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A comparison circuit, characterized in that: The comparison circuit comprises: A primary comparator, comprising a first input terminal, a second input terminal and a first output terminal, wherein the first input terminal is configured to receive an input signal, the second input terminal is configured to receive a reference signal, the primary comparator is configured to compare and sample the input signal with the reference signal, and output a potential difference between the pre-amplified input signal and the reference signal through the first output terminal; an energy storage module, connected to the first output terminal, configured to store the potential difference output by the primary comparator; The secondary comparator comprises a third input terminal, a fourth input terminal and a second output terminal, wherein the third input terminal and the fourth input terminal are configured to receive the pre-amplified potential difference, and the secondary comparator is configured to perform secondary comparison sampling on the potential difference to obtain a target signal.

2. The comparison circuit according to claim 1, characterized in that: The energy storage module comprises: A first energy storage element, connected between the first output terminal and the third input terminal of the secondary comparator; A second energy storage element, connected between the first output terminal and the fourth input terminal of the secondary comparator; The first energy storage element and the second energy storage element are configured to store the potential difference.

3. The comparison circuit according to claim 1, characterized in that: The comparison circuit further comprises: buffer; The input end of the buffer is connected to the first output end, and the output end of the buffer is connected to the third input end and the fourth input end respectively.

4. The comparison circuit according to claim 3, characterized in that: The control clock of the buffer is the same as the sampling clock of the first-level comparator.

5. The comparison circuit according to claim 3, characterized in that: The buffer is a tri-state buffer.

6. The comparison circuit according to claim 1, characterized in that: The primary comparator comprises: A current source connected to the virtual ground point of the first-level comparator; a resistive isolation module connected to the first input terminal and the second input terminal, and configured to isolate kickback noise generated when the first output terminal is pre-charged and evaluated; A clock-controlled cross-coupling module is connected to the resistance isolation module, and the common node between the two is the first output terminal. The module is configured to amplify the difference between the input signal and the reference signal and to use a clock signal to control the switching of the pre-charging phase and the evaluation phase of the output. The clock-controlled cross-coupling module includes at least one clock control circuit.

7. The comparison circuit according to claim 6, characterized in that: The resistance isolation module comprises: A first resistor connected between the first regeneration node of the first-level comparator and the corresponding first clock control circuit; A second resistor connected between the second regeneration node of the first-level comparator and the corresponding second clock control circuit; a third resistor connected between the first regeneration node and the second regeneration node; The first regeneration node is a common node of the first input terminal and the first resistor, and the second regeneration node is a common node of the second input terminal and the second resistor.

8. A decision feedback equalizer, characterized in that: The decision feedback equalizer comprises: A feedback module configured to determine an intersymbol interference parameter based on the decoded symbols; A calculation circuit configured to combine the initial signal and the inter-symbol interference parameter to output an equalized signal; The comparison circuit according to any one of claims 1 to 7 is configured to compare the difference between the sampled equalized signal and a preset reference signal and output a current symbol value.

9. The decision feedback equalizer according to claim 8, characterized in that: The feedback module comprises: A delay unit connected to the output end of the comparison circuit; A feedback filter is connected between the delay unit and the calculation circuit, and is configured to determine the inter-symbol interference parameter based on the decoded symbol based on the delay unit receiving the decoded symbol at a correct time point.

10. The decision feedback equalizer according to claim 8, characterized in that: The decision feedback equalizer also includes: The feedforward equalizer is configured to compensate for the influence of the channel on the signal to be processed and obtain the initial signal.

11. A communication interface, characterized in that: The physical layer of the communication interface adopts the decision feedback equalizer as described in any one of claims 8-10.

Images