Femtosecond time comparator

Abstract

The invention discloses a femtosecond time comparator, which comprises a time comparison front end, a first voltage-controlled delay line, a second voltage-controlled delay line and a time comparator, signals START and STOP are input to a time comparison front end, corresponding voltages V1 and V2 are generated, V1 is connected to a first voltage-controlled delay line, V2 is connected to a second voltage-controlled delay line, the two voltage-controlled delay lines are triggered by an external sampling clock signal CLK, the first voltage-controlled delay line generates a signal T1, the second voltage-controlled delay line generates a signal T2, and the first voltage-controlled delay line and the second voltage-controlled delay line are triggered by an external sampling clock signal CLK. The time comparator detects the sequence of the time T1 and the time T2 reaching the high level and outputs a digital signal. Compared with an existing time comparator structure, the time comparator has the advantage that the discriminable time precision is within 10fs.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a femtosecond-level time comparator. Background Art

[0002] With the development of semiconductor technology and the iteration of integrated circuit processes, the scale, integration level, and operating frequency of circuit systems are constantly increasing, which poses higher requirements for the positioning of system time-domain signals. For example, in circuits such as digital phase-locked loops, clock generators, timing regulators, and time-domain voltage comparators, time-to-digital conversion technology can effectively quantify the time of the clock or signal therein and output it in digital form and send it back to the feedback loop.

[0003] Similar to the voltage comparator in an analog-to-digital converter, a time comparator compares a signal to be measured with a time reference to generate valid digital bits, and then encodes them to obtain the output of the time-to-digital converter. Therefore, the time comparator is the core module of the time-to-digital converter, and its comparison accuracy determines the quality of the final conversion result.

[0004] Most of the existing time comparators adopt a latch (logic gate) scheme. The comparison accuracy of the latch can only be at the picosecond level. For input signals with smaller time differences, the latch will enter the subthreshold region and cannot provide an effective digital output, and the discrimination accuracy even fluctuates by ten picoseconds at different process corners.

[0005] However, in application scenarios such as timing adjustment and phase locking, a time adjustment accuracy of one picosecond requires a time comparison accuracy at the sub-picosecond level. Therefore, there is an urgent need for a time comparator with a comparison accuracy at the femtosecond level. Summary of the Invention

[0006] Object of the Invention: To solve the problems existing in the above-mentioned prior art, the present invention provides a time comparator.

[0007] Technical Solution: The present invention discloses a femtosecond-level time comparator, including: a time comparison front end, first and second voltage-controlled delay lines, and a time comparator; inputting signals START and STOP to the time comparison front end to generate corresponding voltages V 1 and V 2 , and connecting V 1 to the first voltage-controlled delay line, connecting V 2 to the second voltage-controlled delay line. The two voltage-controlled delay lines are triggered by an external sampling clock signal CLK. The first voltage-controlled delay line generates a signal T 1 , the second voltage-controlled delay line generates a signal T 2 , and the time comparator detects the order of the arrival times of T 1 and T 2 at the high level and outputs a digital signal.

[0008] Further, the time comparison front end includes a first OR gate and first to sixth MOS transistors; signals START and STOP are respectively input to the first input terminal and the second input terminal of the first OR gate, and the output terminal of the first OR gate is connected to the gates of the fifth MOS transistor and the sixth MOS transistor; the sources of the fifth MOS transistor and the sixth MOS transistor are connected to the power supply AVDD, and the drain of the fifth MOS transistor serves as the first output terminal of the time comparison front end to output signal V 1 , and is connected to the gate of the fourth MOS transistor and the drain of the third MOS transistor; the drain of the sixth MOS transistor serves as the second output terminal of the time comparison front end to output signal V 2 , and is connected to the gate of the third MOS transistor and the drain of the fourth MOS transistor; the source of the third MOS transistor is connected to the drain of the first MOS transistor, the gate of the first MOS transistor is connected to signal START, the source of the first MOS transistor is connected to the source of the second MOS transistor, the gate of the second MOS transistor is connected to signal STOP, and the drain of the second MOS transistor is connected to the source of the fourth MOS transistor.

[0009] Further, the first to fourth MOS transistors are NMOS transistors, and the fifth and sixth MOS transistors are both PMOS transistors.

[0010] Further, the structures of the first and second voltage-controlled delay lines are the same, and both include a plurality of cascaded voltage-controlled delay units.

[0011] Further, the voltage-controlled delay unit includes seventh to twelfth MOS transistors; the sources of the seventh MOS transistor and the eighth MOS transistor are connected to the power supply AVDD, the gate of the seventh MOS transistor is connected to the control voltage VC; the gate of the eighth MOS transistor is grounded, the drain of the seventh MOS transistor is connected to the source of the ninth MOS transistor, the gate of the ninth MOS transistor serves as the input terminal of the voltage-controlled delay unit and is connected to the gate of the eleventh MOS transistor, the drain of the ninth MOS transistor is connected to the drain of the eleventh MOS transistor, the gate of the tenth MOS transistor and the gate of the twelfth MOS transistor; the sources of the eleventh MOS transistor and the twelfth MOS transistor are both grounded, the drain of the twelfth MOS transistor serves as the output terminal of the voltage-controlled delay unit and is connected to the drain of the tenth MOS transistor, and the source of the tenth MOS transistor is connected to the drain of the eighth MOS transistor.

[0012] Further, the eleventh and twelfth MOS transistors are both NMOS transistors, and the seventh to tenth MOS transistors are all PMOS transistors.

[0013] Further, the time comparator includes a second OR gate, thirteenth to eighteenth MOS transistors, and an SR latch, signal T 1 and signal T 2They are respectively input to the first input terminal and the second input terminal of the second OR gate; the output terminal of the second OR gate is connected to the gate of the seventeenth MOS transistor and the gate of the eighteenth MOS transistor. The source electrodes of the seventeenth MOS transistor and the eighteenth MOS transistor are both connected to the power supply AVDD. The drain electrode of the seventeenth MOS transistor is connected to the S terminal of the SR latch, the drain electrode of the fifteenth MOS transistor, and the gate of the sixteenth MOS transistor; the gate of the fifteenth MOS transistor is connected to the drain electrode of the eighteenth MOS transistor, the R terminal of the SR latch, and the drain electrode of the sixteenth MOS transistor. The source electrode of the fifteenth transistor is connected to the drain electrode of the thirteenth MOS transistor, and the gate of the thirteenth MOS transistor is connected to the signal T 1 , the source electrodes of the thirteenth MOS transistor and the fourteenth MOS transistor are both grounded, and the gate of the fourteenth MOS transistor is connected to the signal T 2 , the drain electrode of the fourteenth MOS transistor is connected to the source electrode of the sixteenth MOS transistor, and the output terminal of the SR latch serves as the output terminal of the time comparator.

[0014] Furthermore, the fifteenth to eighteenth MOS transistors are all NMOS transistors, and the thirteenth and fourteenth MOS transistors are all PMOS transistors.

[0015] Beneficial effects: The present invention designs a high-sensitivity time pre-amplification scheme. By means of a time comparison front end and a voltage-controlled delay line, an input signal with a femtosecond-level time difference is amplified and converted into a signal with a picosecond-level time difference, and then sent to the time comparator to output the result, rather than directly connecting the input signal to the time comparator. The present invention thereby obtains higher time discrimination accuracy, reaching the femtosecond level. Description of the Drawings

[0016] Figure 1 is the main block diagram of a femtosecond-level high-precision time comparator designed by the present invention;

[0017] Figure 2 is the structural diagram of the time comparison front end of the present invention;

[0018] Figure 3 is the structural diagram of the voltage-controlled delay unit of the present invention;

[0019] Figure 4 is the structural diagram of the time comparator of the present invention;

[0020] Figure 5 is the waveform simulation diagram of the existing time comparator;

[0021] Figure 6 is the waveform simulation diagram of a femtosecond-level high-precision time comparator designed by the present invention. Detailed Embodiments

[0022] The accompanying drawings, which form a part of the present invention, are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention.

[0023] As Figure 1 shown, a femtosecond-level high-precision time comparator designed by the present invention includes a time comparison front end, two voltage-controlled delay lines, and a time comparator. Among them: Signals START and STOP are input to the time comparison front end to generate two voltages V 1 and V 2 , converting the time polarity into a voltage polarity. If START reaches the high level before STOP, then V 2 >V 1 ; if STOP reaches the high level before START, then V 1 >V 2 . Then V 1 and V 2 are respectively connected to two identical voltage-controlled delay lines VCDL1 and VCDL2, triggered by the sampling clock CLK, to generate delay signals T 1 and T 2 with a picosecond-level time difference, and their polarities are determined by V 2 , V 1 . Finally, the subsequent time comparator Arbiter detects the sequence of the high-level arrival times of T 1 and T 2 and outputs digitally. If V 2 >V 1 , then T 1 <T 2 , and Arbiter outputs a high level; if V 1 >V 2 , then T 2 <T 1 , and Arbiter outputs a low level. Therefore, overall, if START reaches the high level before STOP, a high level is output; if STOP reaches the high level before START, a low level is output.

[0024] In the actual application process of the femtosecond-level high-precision time comparator designed by the present invention, a specific circuit structure is designed for the time comparison front end. As Figure 2 shown, it includes NMOS transistor M 1 , NMOS transistor M 2 , NMOS transistor M 3 , NMOS transistor M 4 , PMOS transistor M 5 , PMOS transistor M 6, and an OR logic gate. Wherein: the input signals START and STOP are connected to the inputs of the OR logic gate; the output START||STOP of the OR logic gate is connected to the gate of M 5 's gate, M 6 's gate; the power supply AVDD is connected to the source of M 5 's source, M 6 's source; the ground AVSS is connected to the source of M 1 's source, M 2 's source; the input signal START is connected to the gate of M 1 ; the input signal STOP is connected to the gate of M 2 ; the drain of M 1 is connected to the source of M 3 ; the drain of M 2 is connected to the source of M 4 ; the output V 1 terminal of the time comparison front end is connected to the drain of M 3 , the drain of M 5 , the drain of M 4 's gate; the output V 2 terminal of the time comparison front end is connected to the drain of M 4 , the drain of M 6 , the drain of M 3 's gate;

[0025] As Figure 3 shown, a voltage-controlled delay cell adopted by the present invention includes NMOS transistors MN 1 , NMOS transistors MN 2 , PMOS transistors MP 1 , PMOS transistors MP 2 , PMOS transistors MP 3 , PMOS transistors MP 4 . Wherein: the source of MN 1 , the source of MN 2 are connected to the ground AVSS; the input control voltage VC is connected to the gate of MP 3 ; the power supply ground AVSS is connected to the gate of MP 4 ; the source of MP 3 , the source of MP 4 are connected to the power supply AVDD; the source of MP 1 is connected to the source of MP 2 , the drain of MP 3 , the drain of MP 4 ; the input terminal IN is connected to the gate of MP 1 , the gate of MN 1 ; the drain of MP 1 is connected to MN1 The drain of 2 and the gate of MP, 2 the gate of 2 and the gate of MN are connected; the output terminal OUT is connected to the drain of MP 2 and the drain of MN; the voltage-controlled delay line is cascaded by the delay units, and the specific number of cascades is adjusted according to the design requirements.

[0026] As Figure 4 shown, a time comparator adopted by the present invention includes NMOS transistors M 1 , NMOS transistors M 2 , NMOS transistors M 3 , NMOS transistors M 4 , PMOS transistors M 5 , PMOS transistors M 6 , an OR logic gate OR, and an SR latch. Among them: the input signals T 1 and T 2 are connected to the input of the OR logic gate OR; the output START||STOP of the OR logic gate OR is connected to the gate of M 5 and the gate of M 6 ; the power supply AVDD is connected to the source of M 5 and the source of M 6 ; the ground AVSS is connected to the source of M 1 and the source of M 2 ; the input signal START is connected to the gate of M 1 ; the input signal STOP is connected to the gate of M 2 ; the drain of M 1 is connected to the source of M 3 ; the drain of M 2 is connected to the source of M 4 ; the input S terminal of the SR latch is connected to the drain of M 3 , the drain of M 5 , and the gate of M 4 ; the input R terminal of the SR latch is connected to the drain of M 4 , the drain of M 6 , and the gate of M 3 ; the output Q terminal of the SR latch is used as the output of the time comparator.

[0027] Figure 5 is the simulation waveform diagram of an existing time comparator. Figure 5 In Figure 5In (b), the level of the Q output terminal of the existing time comparator is shown, which is 457 mV. This indicates that when the existing time comparator discriminates input signals with a 200 fs time difference, the output level is in the subthreshold region, resulting in an invalid output.

[0028] Figure 6 is the waveform diagram of a femtosecond-level high-precision time comparator. Figure 6 In (a), the time difference between the input signals START and STOP is shown, which is 10 fs. This indicates that the discrimination accuracy of this high-precision time comparator can reach 10 fs. Figure 6 In (b), the output voltage V 1 and V 2 of the voltage difference is shown, which is 42.5 mV. This indicates that the time comparison front-end can effectively convert the polarity of time into the polarity of voltage. Figure 6 In (c), the time difference between the outputs T 1 and T 2 of the voltage-controlled delay line is shown, which is 4.23 ps. This indicates that the 10 fs time difference of the input signal is converted into a 4.23 ps time difference. Figure 6 In (d), the level of the Q output terminal of the high-precision time comparator is shown. It flips from low level to high level at the simulation time of 2.49 ns, indicating that this design effectively outputs high and low levels after detecting the input signal.

[0029] The present invention designs a high-precision time comparator, adopting a designed high-sensitivity time pre-amplification scheme. That is, through the time comparison front-end and the voltage-controlled delay line, an input signal with a femtosecond-level time difference is amplified and converted into a picosecond-level time difference signal, and then sent to the time comparator to output the result, improving the discrimination accuracy of time comparison.

[0030] The present invention operates at a power supply voltage of 1.1 V, and the input time difference is 10 fs. Compared with the existing time comparator structure, the discriminable time accuracy can reach within 10 fs.

[0031] In addition, it should be noted that in the above specific embodiments, the various specific technical features described can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the present invention does not separately describe all possible combination methods.

Claims

1. A femtosecond time comparator, characterized in that: include: Time comparison front end, first and second voltage-controlled delay lines and time comparator; input signals START and STOP to the time comparison front end to generate corresponding voltages V1 and V2, and connect V1 to the first voltage-controlled delay line, and connect V2 to the second voltage-controlled delay line. The two voltage-controlled delay lines are triggered by an external sampling clock signal CLK, the first voltage-controlled delay line generates a signal T1, and the second voltage-controlled delay line generates a signal T2. The time comparator detects the order of when T1 and T2 reach a high level and outputs a digital signal.

2. A femtosecond time comparator according to claim 1, characterized in that: The time comparison front end includes a first OR gate and first to sixth MOS tubes; signals START and STOP are respectively input to the first input end and the second input end of the first OR gate, and the output end of the first OR gate is connected to the gate of the fifth MOS tube and the gate of the sixth MOS tube; the source of the fifth MOS tube and the source of the sixth MOS tube are connected to the power supply AVDD, the drain of the fifth MOS tube outputs the signal V1 as the first output end of the time comparison front end, and is connected to the gate of the fourth MOS tube and the drain of the third MOS tube; the drain of the sixth MOS tube outputs the signal V2 as the second output end of the time comparison front end, and is connected to the gate of the third MOS tube and the drain of the fourth MOS tube; the source of the third MOS tube is connected to the drain of the first MOS tube, the gate of the first MOS tube is connected to the signal START, the source of the first MOS tube is connected to the source of the second MOS tube, the gate of the second MOS tube is connected to the signal STOP, and the drain of the second MOS tube is connected to the source of the fourth MOS tube.

3. A femtosecond time comparator according to claim 2, characterized in that: The first to fourth MOS tubes are NMOS tubes, and the fifth and sixth MOS tubes are PMOS tubes.

4. A femtosecond time comparator according to claim 1, characterized in that: The first and second voltage-controlled delay lines have the same structure, and both include a plurality of cascaded voltage-controlled delay units.

5. A femtosecond time comparator according to claim 4, characterized in that: The voltage-controlled delay unit includes seventh to twelfth MOS tubes; the source of the seventh MOS tube and the source of the eighth MOS tube are connected to the power supply AVDD, and the gate of the seventh MOS tube is connected to the control voltage VC; the gate of the eighth MOS tube is grounded, the drain of the seventh MOS tube is connected to the source of the ninth MOS tube, the gate of the ninth MOS tube is used as the input end of the voltage-controlled delay unit, connected to the gate of the eleventh MOS tube, the drain of the ninth MOS tube is connected to the drain of the eleventh MOS tube, the gate of the tenth MOS tube and the gate of the twelfth MOS tube; the source of the eleventh MOS tube and the source of the twelfth MOS tube are both grounded, the drain of the twelfth MOS tube is used as the output end of the voltage-controlled delay unit, connected to the drain of the tenth MOS tube, and the source of the tenth MOS tube is connected to the drain of the eighth MOS tube.

6. A femtosecond time comparator according to claim 5, characterized in that: The eleventh and twelfth MOS tubes are both NMOS tubes, and the seventh to tenth MOS tubes are all PMOS tubes.

7. The femtosecond time comparator according to claim 1, characterized in that: The time comparator includes a second OR gate, thirteenth to eighteenth MOS tubes and an SR latch, and a signal T1 and a signal T2 are respectively input to a first input terminal and a second input terminal of the second OR gate; the output terminal of the second OR gate is connected to the gate of the seventeenth MOS tube and the gate of the eighteenth MOS tube, the source of the seventeenth MOS tube and the source of the eighteenth MOS tube are both connected to the power supply AVDD, the drain of the seventeenth MOS tube is connected to the S terminal of the SR latch, the drain of the fifteenth MOS tube and the gate of the sixteenth MOS tube; the gate of the fifteenth MOS tube is connected to the drain of the eighteenth MOS tube, the R terminal of the SR latch and the drain of the sixteenth MOS tube, the source of the fifteenth tube is connected to the drain of the thirteenth MOS tube, the gate of the thirteenth MOS tube is connected to the signal T1, the source of the thirteenth MOS tube and the source of the fourteenth MOS tube are both grounded, the gate of the fourteenth MOS tube is connected to the signal T2, the drain of the fourteenth MOS tube is connected to the source of the sixteenth MOS tube, and the output terminal of the SR latch serves as the output terminal of the time comparator.

8. A femtosecond time comparator according to claim 7, characterized in that: The fifteenth to eighteenth MOS tubes are all NMOS tubes, and the thirteenth and fourteenth MOS tubes are all PMOS tubes.

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